Hybrid deployment method for heterogeneous multi-core chip application program

Abstract

The invention discloses a hybrid deployment method for heterogeneous multi-core chip application programs, and relates to the technical field of heterogeneous multi-core chips. In order to realize hybrid deployment of heterogeneous multi-core chip application programs, the adopted scheme comprises the following steps: performing function identification and performance demand analysis on the application programs; performing task decomposition and evaluation according to the performance demand analysis result of the application program and the hardware characteristics of the heterogeneous multi-core chip; generating a task scheduling schedule according to sub-tasks contained in the task decomposition result and hardware characteristics of the heterogeneous multi-core chip; based on the task scheduling schedule, evaluating the performance of the subtasks contained in the task decomposition result; adjusting and optimizing distribution of subtasks contained in the task decomposition result according to the evaluation result, and generating a new task scheduling plan table; and performing task execution based on the new task scheduling schedule. The method is applied to the field of heterogeneous multi-core chips, and the resource utilization rate of the heterogeneous multi-core chips and the execution efficiency of the application programs can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of heterogeneous multi-core chips, and in particular to a hybrid deployment method of heterogeneous multi-core chip applications. Background Art

[0002] A heterogeneous multi-core system is a complete system that integrates multiple types of processing units and completes various complex computing tasks through specific interconnection and coordination mechanisms, with the support of operating systems and software platforms. It aims to make full use of the unique advantages of different processing units to achieve optimization in computing performance, energy efficiency and other aspects to meet the growing and diverse computing needs.

[0003] Heterogeneous multi-core systems usually include heterogeneous multi-core chips, other hardware components, operating systems, and software platforms. Among them: Heterogeneous multi-core chips are the core hardware foundation of heterogeneous multi-core systems. Heterogeneous multi-core chips are integrated circuit chips that integrate multiple different types of processing cores. These different types of cores have their own unique architectures, functions and performance characteristics. They are integrated on the same chip, connected and coordinated through high-speed Internet networks to meet the computing power, energy efficiency and other requirements of different application scenarios. Different types of processing cores specifically include: ① General-purpose processor core: such as the common central processing unit (CPU) core, which has strong versatility and can execute various complex instruction sets. It is suitable for processing various types of tasks, such as operating system management, general data processing, logic control, etc. ② Graphics processing unit core: that is, GPU core, which is good at processing graphics data and parallel computing, and has excellent performance in graphics rendering, image and video processing, deep learning and other fields. ③ Digital signal processor core: referred to as DSP core, mainly used for fast processing of digital signals, such as audio signal processing, communication signal processing, etc., with efficient digital signal processing capabilities and specialized instruction sets. ④Other dedicated cores: may also include encryption cores for encryption and decryption, sensor processing cores for processing sensor data, dedicated neural network processing units (NPUs) for artificial intelligence computing, etc. These dedicated cores are optimized for specific tasks or algorithms and can provide higher performance and energy efficiency in the corresponding fields. Heterogeneous multi-core chip applications refer to software programs designed and developed specifically to run on heterogeneous multi-core chips. It can make full use of the advantages of different types of cores in heterogeneous multi-core chips, and achieve more efficient computing and function realization by reasonably allocating tasks and working together.

[0004] Other hardware components specifically include memory, storage devices, network interfaces and other hardware components. Memory provides data storage and temporary cache space for heterogeneous multi-core chips, storage devices are used to store data and programs for a long time, and network interfaces are responsible for the communication between the system and the external environment. These hardware components work together with heterogeneous multi-core chips to form a complete computing platform. For example, in a server-level heterogeneous multi-core system, large-capacity memory and high-speed storage devices can provide sufficient data support for heterogeneous multi-core chips, enabling them to efficiently process large-scale data sets, while high-speed network interfaces can achieve fast data transmission between servers to meet the needs of distributed computing and cloud computing.

[0005] The operating system and software platform are responsible for the management and coordination of the various hardware components of the heterogeneous multi-core system. The operating system is responsible for identifying and managing the different processing cores in the heterogeneous multi-core chip, reasonably assigning tasks to the corresponding cores for execution based on the characteristics of the tasks and resource requirements, and handling issues such as communication, synchronization, and resource competition between cores. The software platform provides developers with development tools, programming models, and runtime environments, making it easier for developers to develop various applications using the performance advantages of heterogeneous multi-core systems. For example, in a heterogeneous multi-core system on a mobile device, the operating system will dynamically assign graphics rendering tasks to the GPU and other general computing tasks to the CPU based on the type of application and the current system load, in order to achieve the best user experience and energy efficiency.

[0006] In heterogeneous multi-core systems, in order to meet the diverse computing needs of users, different types of processor cores need to run applications that are adapted to them. For example, the CPU core can run operating system management, complex logic operations and other related applications due to its strong versatility; the GPU core is suitable for running graphics rendering, deep learning model training and other applications due to its parallel computing characteristics; the DSP core plays an advantage in running applications such as audio processing and communication signal processing.

[0007] Given that users' computing needs are in dynamic change, this requires that applications running on the processor cores of heterogeneous multi-core systems be flexible and adaptable. When user needs change, for example, from daily office document processing to video editing, the office software originally running on the CPU core may need to be updated or replaced with video editing-related applications; if user needs further change to inference calculations of deep learning models, the applications running on the GPU core also need to be updated accordingly to deep learning inference frameworks and related tools. In other words, in order to meet users' ever-changing computing needs, applications running on heterogeneous cores must be able to be updated and flexibly adjusted in a timely manner to ensure that the system always provides services to users efficiently and stably.

[0008] Based on this, a hybrid deployment method is designed to quickly deploy different applications running on processor cores in heterogeneous multi-core systems to meet users' computing needs. Summary of the invention

[0009] In order to achieve flexibility and adaptability of running applications on processor cores of a heterogeneous multi-core system, the present invention provides a hybrid deployment method for heterogeneous multi-core chip applications to improve resource utilization of the heterogeneous multi-core chips and execution efficiency of applications.

[0010] A hybrid deployment method of heterogeneous multi-core chip applications of the present invention solves the above technical problems using the following technical solutions: A hybrid deployment method for heterogeneous multi-core chip applications comprises the following steps: S1. Perform application function identification and performance requirement analysis; S2. Perform task decomposition and evaluation based on the application's performance requirement analysis results and the hardware characteristics of heterogeneous multi-core chips; S3, generating a task scheduling plan table according to the subtasks included in the task decomposition result and the hardware characteristics of the heterogeneous multi-core chip; S4. Based on the task scheduling plan, the performance of the subtasks included in the task decomposition result is evaluated; S5. According to the evaluation result of step S4, the allocation of subtasks included in the task decomposition result is adjusted and optimized to generate a new task scheduling plan table; S6. Execute the task based on the new task scheduling plan.

[0011] Optionally, executing step S1 to perform function identification of the application program refers to analyzing the processing flow of the application program to clarify its various components and corresponding functions, and finally identifying various different functional modules; Performing performance requirement analysis on an application refers to performing performance requirement analysis on the identified functional modules, including analysis of computing demand, computing real-time demand, data throughput, and data dependency.

[0012] Optionally, step S2 specifically includes: Decompose tasks based on the performance requirements of the identified functional modules and the hardware characteristics of heterogeneous multi-core chips; Taking the independence of tasks as the evaluation principle, the subtasks included in the task decomposition results are evaluated to determine the execution process of the subtasks and the interdependencies between the subtasks.

[0013] Optionally, the task scheduling plan table specifies the execution logic relationship of the subtasks included in the task decomposition result, the computing resource attributes and the number of computing resources required for the subtask execution, and specifically includes the name, number, attribute, computing resource configuration and dependency relationship of the subtasks included in the task decomposition result.

[0014] Optionally, execute step S4, and according to the task scheduling plan, directly deploy the subtasks included in the task decomposition result to the heterogeneous multi-core chip to run the test, view the actual running results of the subtasks, and generate a performance evaluation report containing the following indicators: the overall execution time of the task, the execution time of a single subtask included in the task decomposition result, the loss time of data flowing between subtasks, and the utilization and power consumption of the computing core.

[0015] Optionally, execute step S4, use evaluation software to perform simulation test on the scheduling plan, measure the performance indicators of the subtask operation included in the task decomposition result, and generate a performance evaluation report; wherein the performance evaluation report includes the following indicators: the overall execution time of the task, the execution time of a single subtask included in the task decomposition result, the loss time of data flowing between subtasks, and the utilization and power consumption of the computing core.

[0016] Optionally, step S6 specifically includes: S6.1. Read the source programs of all subtasks in the new task scheduling table, and compile the source programs into executable programs of the architecture supported by the corresponding computing cores in the heterogeneous multi-core chip; S6.2, numbering the executable programs according to the new task scheduling table, and storing the executable programs in the program cache area in sequence; S6.3, read the computing resource configuration parameters, send the executable program to the computing core corresponding to the heterogeneous multi-core chip, and store the collected data in the data cache area; S6.4, after the computing core completes the computation, it stores the data in the area specified by the data buffer, and notifies the main core of the heterogeneous multi-core chip that the computation is complete; S6.5, the main core continues to read the next subtask and sends it to the computing core for calculation; S6.6. The main core repeats steps S6.3 to S6.5 until all subtasks are completed.

[0017] Preferably, the heterogeneous multi-core chip includes a CPU main core and 32 computing cores, wherein the CPU main core has logic processing and control capabilities, and is responsible for task decomposition and scheduling schedule formulation, and the computing core has large-scale parallel computing capabilities, and is responsible for the execution of the assigned computing tasks; A performance model is established based on the different characteristics of the CPU main core and computing core, as well as the specific requirements of the subtasks included in the task decomposition results. The performance model aims to predict the execution time and resource consumption of each subtask on different cores.

[0018] Compared with the prior art, the hybrid deployment method of heterogeneous multi-core chip applications of the present invention has the following beneficial effects: The present invention can effectively improve the resource utilization of heterogeneous multi-core chips and the execution efficiency of applications, and quickly complete the mixed deployment of different applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Attached Figure 1 It is a flowchart of the method of the present invention. DETAILED DESCRIPTION

[0020] In order to make the technical solution, the technical problem solved and the technical effect of the present invention more clearly understood, the technical solution of the present invention is clearly and completely described below in conjunction with specific embodiments.

[0021] Example: Refer to the attached Figure 1 This embodiment proposes a hybrid deployment method for heterogeneous multi-core chip applications, which includes the following steps: S1. Perform application identification and analysis, including application function identification and performance requirement analysis.

[0022] Identifying the functions of an application refers to analyzing the processing flow of the application to clarify its various components and corresponding functions, and finally identifying the different functional modules; Performing performance requirement analysis on an application refers to performing performance requirement analysis on the identified functional modules, including analysis of computing demand, computing real-time demand, data throughput, and data dependency.

[0023] For example, when performing functional identification of an application, the application is divided into a data acquisition module, a data primary calculation module, a data secondary calculation module, a behavior analysis module, and a calculation result storage module. Then, the performance requirements of the application are analyzed: the data acquisition module has high real-time requirements and needs to obtain data continuously and stably; the data primary calculation module and the data secondary calculation module are computationally intensive tasks and need to perform computations on a large amount of collected data; the behavior analysis module needs to comprehensively process the detection results and has high requirements for logical processing capabilities; the calculation result storage module is mainly responsible for data storage and has certain requirements for the external I / O access performance of the chip.

[0024] S2. Task decomposition and evaluation. Specifically, the tasks are decomposed according to the performance requirements of the identified functional modules and the hardware characteristics of heterogeneous multi-core chips. Then, the subtasks included in the task decomposition results are evaluated based on the principle of maintaining task independence, and the execution process of the subtasks and the interdependencies between the subtasks are determined.

[0025] The heterogeneous multi-core chip described in this embodiment includes a CPU main core and 32 computing cores, wherein the CPU main core has logical processing and control capabilities, and is responsible for task decomposition and scheduling schedule formulation, and the computing core has large-scale parallel computing capabilities, and is responsible for the execution of the assigned computing tasks. Based on the different characteristics of the CPU main core and the computing core, and the specific requirements of the subtasks included in the task decomposition results, a performance model is established, and the performance model is intended to predict the execution time and resource consumption of each subtask on different cores.

[0026] For example, taking the data computing task as an example, when decomposing it, the convolutional neural network calculation in the computing task is decomposed into smaller computing subtasks, including data loading, convolution calculation, pooling calculation, full connection calculation, and data output. Convolution calculation can be further decomposed into three subtasks: sliding window calculation, sliding window calculation, and sliding window calculation. Pooling calculation can be decomposed into maximum pooling or average pooling, and data downsampling subtasks. Full connection calculation can be decomposed into multiplication of weight matrix and input vector, and bias addition subtasks.

[0027] Evaluate the decomposed data loading, convolution calculation, pooling calculation, full connection calculation, and data output subtasks, including computational complexity, resource usage, and parallelization potential. In terms of computational complexity: convolution has high computational complexity, including a large number of multiplication and addition operations; pooling has medium computational complexity, mainly comparison or summation operations; full connection has high computational complexity, involving large-scale matrix operations. In terms of resource usage: convolution calculation occupies a large number of computing units; pooling calculation occupies fewer computing resources; full connection calculation occupies a large number of computing units and storage resources. In terms of parallelization potential: convolution calculation has high parallelization potential and can be decomposed into multiple independent computing windows. Pooling calculation has medium parallelization potential and can be decomposed into multiple independent regional calculations. Fully connected layer calculation has high parallelization potential and can be decomposed into multiple independent vector multiplications.

[0028] S3. Generate a task scheduling plan based on the subtasks included in the task decomposition results (such as the five smaller computing subtasks of data loading, convolution computing, pooling computing, fully connected computing and data output decomposed from the data computing task) and the hardware characteristics of the heterogeneous multi-core chip. The task scheduling plan specifies the execution logic relationship of the subtasks included in the task decomposition results, the computing resource attributes and the number of computing resources required for the execution of the subtasks, and specifically includes the names, numbers, attributes, computing resource configurations and dependencies of the subtasks included in the task decomposition results. See Table 1 below.

[0029] Table 1:

[0030] S4. Based on the task scheduling plan, the performance of the subtasks included in the task decomposition result is evaluated by any of the following methods: a) According to the task scheduling table, the subtasks included in the task decomposition results are directly deployed to the heterogeneous multi-core chip for running tests, the actual running results of the subtasks are checked, and a performance evaluation report containing the following indicators is generated: the overall execution time of the task, the execution time of a single subtask included in the task decomposition results, the loss time of data flowing between subtasks, and the utilization and power consumption of the computing core; b) Use the evaluation software to simulate the scheduling schedule, measure the performance indicators of the subtasks included in the task decomposition results, and generate a performance evaluation report; the performance evaluation report includes the following indicators: the overall execution time of the task, the execution time of a single subtask included in the task decomposition results, the loss time of data flowing between subtasks, the utilization rate of the computing core, and the power consumption. See Table 2 below.

[0031] Table 2:

[0032] S5, that is, according to the evaluation result of step S4, the allocation of subtasks included in the task decomposition result is adjusted and optimized to generate a new task scheduling plan, as shown in Table 3 below.

[0033] Table 3:

[0034] S6. Execute the task based on the new task scheduling schedule, specifically including: S6.1. Read the source programs of all subtasks in the new task scheduling table, and compile the source programs into executable programs of the architecture supported by the corresponding computing cores in the heterogeneous multi-core chip. For example, three executable programs are generated for convolution calculation, pooling calculation, and fully connected layer calculation in the new task scheduling table, which can be named 01.bin, 02.bin, and 03.bin respectively; S6.2, number the executable programs according to the new task scheduling table, and store the executable programs in the program cache area in sequence, that is, store the three executable programs 01.bin, 02.bin, and 03.bin in the program storage area in sequence; S6.3, read the computing resource configuration parameters, send the executable program to the computing core corresponding to the heterogeneous multi-core chip, store the collected data in the data cache area, such as before performing convolution calculation, read the 01.bin program in the program storage area, and write it to the instruction storage area of ​​the specified computing core, send the start calculation instruction after the data transfer is completed, and the computing core reads the instruction from the instruction cache area to perform data calculation; S6.4, after the computing core completes the computation, it stores the data in the area specified by the data buffer, and notifies the main core of the heterogeneous multi-core chip that the computation is complete; S6.5, the main core continues to read the next subtask and sends it to the computing core for calculation; for example, after the execution of the 01.bin program is completed, the main core is notified that the pooling calculation has been completed, and the main core immediately re-sends the 02.bin execution program to the computing core, and performs subsequent calculation subtasks after the data is ready. After the 02.bin program is executed, the 03.bin execution program is written into the instruction cache area of ​​the computing core to execute the calculation subtask of the fully connected layer; S6.6. The main core repeats steps S6.3 to S6.5 until all subtasks included in the task decomposition are executed.

[0035] In summary, the hybrid deployment method of heterogeneous multi-core chip applications of the present invention can effectively improve the resource utilization of heterogeneous multi-core chips and the execution efficiency of applications, and quickly complete the hybrid deployment of different applications.

[0036] The above specific examples are used to explain the principles and implementation methods of the present invention in detail. These examples are only used to help understand the core technical content of the present invention. Based on the above specific embodiments of the present invention, any improvements and modifications made by technicians in this technical field without departing from the principles of the present invention should fall within the scope of patent protection of the present invention.

Claims

1. A hybrid deployment method for heterogeneous multi-core chip applications, characterized in that: The steps include: S1. Perform application function identification and performance requirement analysis; S2. Perform task decomposition and evaluation based on the application's performance requirement analysis results and the hardware characteristics of heterogeneous multi-core chips; S3, generating a task scheduling plan table according to the subtasks included in the task decomposition result and the hardware characteristics of the heterogeneous multi-core chip; S4. Based on the task scheduling plan, the performance of the subtasks included in the task decomposition result is evaluated; S5. According to the evaluation result of step S4, the allocation of subtasks included in the task decomposition result is adjusted and optimized to generate a new task scheduling plan table; S6. Execute the task based on the new task scheduling plan.

2. A hybrid deployment method for heterogeneous multi-core chip applications according to claim 1, characterized in that: Executing step S1 to perform function identification of the application program refers to analyzing the processing flow of the application program to clarify its various components and corresponding functions, and finally identifying various different functional modules; Performing performance requirement analysis on an application refers to performing performance requirement analysis on the identified functional modules, including analysis of computing demand, computing real-time demand, data throughput, and data dependency.

3. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 2, characterized in that: The step S2 specifically includes: Decompose tasks based on the performance requirements of the identified functional modules and the hardware characteristics of heterogeneous multi-core chips; Taking the independence of tasks as the evaluation principle, the subtasks included in the task decomposition results are evaluated to determine the execution process of the subtasks and the interdependencies between the subtasks.

4. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 1, characterized in that: The task scheduling plan table specifies the execution logic relationship of the subtasks included in the task decomposition result, the computing resource attributes and the number of computing resources required for the subtask execution, and specifically includes the name, number, attribute, computing resource configuration and dependency relationship of the subtasks included in the task decomposition result.

5. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 1, characterized in that: Execute step S4, according to the task scheduling plan, directly deploy the subtasks included in the task decomposition result to the heterogeneous multi-core chip to run the test, check the actual running results of the subtasks, and generate a performance evaluation report containing the following indicators: the overall execution time of the task, the execution time of a single subtask included in the task decomposition result, the loss time of data flowing between subtasks, and the utilization and power consumption of the computing core.

6. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 1, characterized in that: Execute step S4, use the evaluation software to simulate the scheduling plan, measure the performance indicators of the subtasks included in the task decomposition results, and generate a performance evaluation report; wherein the performance evaluation report includes the following indicators: the overall execution time of the task, the execution time of a single subtask included in the task decomposition results, the loss time of data flowing between subtasks, and the utilization and power consumption of the computing core.

7. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 1, characterized in that: The step S6 specifically includes: S6.

1. Read the source programs of all subtasks in the new task scheduling table, and compile the source programs into executable programs of the architecture supported by the corresponding computing cores in the heterogeneous multi-core chip; S6.2, numbering the executable programs according to the new task scheduling table, and storing the executable programs in the program cache area in sequence; S6.3, read the computing resource configuration parameters, send the executable program to the computing core corresponding to the heterogeneous multi-core chip, and store the collected data in the data cache area; S6.4, after the computing core completes the computation, it stores the data in the area specified by the data buffer, and notifies the main core of the heterogeneous multi-core chip that the computation is complete; S6.5, the main core continues to read the next subtask and sends it to the computing core for calculation; S6.

6. The main core repeats steps S6.3 to S6.5 until all subtasks are completed.

8. The hybrid deployment method of heterogeneous multi-core chip applications according to claim 1, characterized in that: The heterogeneous multi-core chip includes a CPU main core and 32 computing cores, wherein the CPU main core has logical processing and control capabilities, and is responsible for task decomposition and scheduling schedule formulation, and the computing core has large-scale parallel computing capabilities, and is responsible for the execution of the assigned computing tasks; A performance model is established based on the different characteristics of the CPU main core and computing core, as well as the specific requirements of the subtasks included in the task decomposition results. The performance model aims to predict the execution time and resource consumption of each subtask on different cores.

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