Multiplexer address conflict processing method and device

Abstract

The invention provides a multiplexer address conflict processing method which is executed by a baseboard management controller. A plurality of output pins of the substrate management controller are electrically connected with reset pins of the multiplexers respectively, and each output pin can be switched between a high potential and a low potential and is preset to be the low potential. The method comprises the following steps: (A) switching a target output pin of the output pins to the high potential, and sending a reset signal by a target reset pin of a target multiplexer electrically connected with the output pin, so that the target multiplexer is started; (B) reading at least one target integrated body wiring circuit device of the target multiplexer; (C) the target output pin is switched to the low potential, so that the target multiplexer is turned off; and (D) repeating step (A) until all the output pins have been switched to the high potential.

Description

Technical Field

[0001] The present invention relates to the technical field of computing devices, and in particular to a method and device for handling multiplexer address conflicts. Background Art

[0002] See also Figure 1 The existing computing device capable of multitasking includes a baseboard management controller (BMC) 11, and a plurality of multiplexers (MUX) 13 electrically connected to the baseboard management controller 11 via a system management bus (SMBus) 12. The multiplexer 13 is used to switch between slots of an integrated circuit (IC). Due to the design of the multiplexer 13 integrated circuit (IC), the address of the multiplexer 13 can only be changed between 3 positions (A0, A1, A2), so only 8 addresses (0xE0-0xEE) can be selected.

[0003] However, once the number of the multiplexers 13 exceeds 8, the addresses of some multiplexers 13 will be repeated, that is, address conflicts will occur. When the baseboard management controller 11 reads at least one integrated bus circuit device 14 electrically connected to the multiplexer 13 via the system management bus 12, the baseboard management controller 11 cannot correctly distinguish the multiplexers 13 with repeated addresses, so that the baseboard management controller 11 cannot correctly determine which multiplexer 13 the read information belongs to. Summary of the invention

[0004] Therefore, an object of the present invention is to provide a method and device for handling multiplexer address conflicts.

[0005] In order to solve the above technical problems, as a preferred embodiment, the present invention provides a multiplexer address conflict processing method, which is executed by a device, wherein the device includes a baseboard management controller, and a plurality of multiplexers electrically connected to the baseboard management controller, the baseboard management controller includes a plurality of output pins, each multiplexer is electrically connected to at least one integrated bus circuit device, and each multiplexer includes a reset pin, the reset pin is electrically connected to one of the output pins, each output pin can be switched between a high potential and a low potential, each output pin is preset to the low potential, for each output pin, when the output pin is switched to the high potential, the reset pin of the multiplexer electrically connected to the output pin sends a reset signal, so that the reset pin of the multiplexer electrically connected to the output pin is reset. The multiplexer is started, and when the output pin is switched to the low potential, the multiplexer electrically connected to the output pin is turned off. The method includes the following steps: (A) the baseboard management controller switches one of the target output pins of the output pin to the high potential, and a target reset pin of a target multiplexer electrically connected to the target output pin sends the reset signal, so that the target multiplexer is started; (B) the baseboard management controller reads at least one target integrated bus circuit device of the target multiplexer; (C) the baseboard management controller switches the target output pin to the low potential, so that the target multiplexer is turned off; and (D) repeating step (A) until the baseboard management controller has switched the output pin to the high potential.

[0006] Preferably, after step (A), the following steps are also included: (E) the baseboard management controller generates and transmits at least one inquiry message to the at least one target integrated circuit bus circuit device of the target multiplexer; wherein, when the baseboard management controller receives at least one reply message corresponding to the at least one inquiry message, step (B) is executed.

[0007] Preferably, when the baseboard management controller does not receive the at least one reply message, the baseboard management controller determines that the at least one target integrated circuit bus circuit device is damaged, does not execute step (B) and step (C), and executes step (D).

[0008] In order to further achieve the above-mentioned object, the present invention also provides a device with a multiplexer address conflict processing function, comprising: a plurality of multiplexers, each multiplexer is electrically connected to at least one integrated bus circuit device, and each multiplexer includes a reset pin; and a baseboard management controller, electrically connected to the multiplexers, including a plurality of output pins, respectively electrically connected to the reset pins of the multiplexers, each output pin can be switched between a high potential and a low potential, each output pin is preset to the low potential, for each output pin, when the output pin is switched to the high potential, the reset pin of the multiplexer to which the output pin is electrically connected sends a reset signal, so that the output pin The multiplexer to which the pin is electrically connected is started, and when the output pin is switched to the low potential, the multiplexer to which the output pin is electrically connected is turned off, and a control unit is electrically connected to the output pin, and switches one of the target output pins of the output pin to the high potential, and a target reset pin of a target multiplexer to which the target output pin is electrically connected sends a reset signal, so that the target multiplexer is started, and at least one target integrated bus circuit device of the target multiplexer is read, and then the target output pin is switched to the low potential, so that the target multiplexer is turned off, and the above actions are repeated until the output pins have been switched to the high potential.

[0009] Preferably, after switching the target output pin to the high voltage, the control unit generates and transmits at least one inquiry message to the at least one target integrated bus circuit device of the target multiplexer respectively, and when receiving at least one reply message corresponding to the at least one inquiry message respectively, the control unit reads the at least one target integrated bus circuit device of the target multiplexer.

[0010] Preferably, when the at least one reply message is not received, the control unit determines that the at least one target integrated circuit bus circuit device is damaged and does not perform reading. The control unit switches another target output pin of the output pin to the high potential and repeats the above actions until the output pin has been switched to the high potential.

[0011] The effect of the present invention is that without adding any hardware, the control unit controls the output pins to switch to the high potential one by one to start the multiplexers one by one, and after the control unit reads all the integrated bus circuit devices of the multiplexer, the output pins are controlled to switch to the low potential to shut down the multiplexer to avoid address conflicts. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1is a block diagram illustrating an existing computing device capable of multitasking;

[0014] Figure 2 is a block diagram illustrating an embodiment of an apparatus having a multiplexer address conflict handling function according to the present invention; and

[0015] Figure 3 is a flow chart illustrating an embodiment of a multiplexer address conflict handling method of the present invention. DETAILED DESCRIPTION

[0016] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.

[0017] See also Figure 2 , an embodiment of a device with a multiplexer address conflict processing function of the present invention, the device includes a plurality of multiplexers 21, and a baseboard management controller 22 electrically connected to the multiplexers 21 via a system management bus 3.

[0018] Each multiplexer 21 is electrically connected to at least one integrated bus circuit device 23 , and each multiplexer 21 includes a reset pin 211 .

[0019] The baseboard management controller 22 includes a plurality of output pins 221 and a control unit 222 electrically connected to the output pins 221 .

[0020] Each output pin 221 is electrically connected to a reset pin 211 of one of the multiplexers 21. Each output pin 221 can be switched between a high potential and a low potential and is preset to the low potential. For each output pin 221, when the output pin 221 is switched to the high potential, the reset pin 211 of the multiplexer 21 to which the output pin 221 is electrically connected sends a reset signal to start the multiplexer 21 to which the output pin 221 is electrically connected; when the output pin 221 is switched to the low potential, the multiplexer 21 to which the output pin 221 is electrically connected is turned off.

[0021] It should be noted that in this embodiment, the output pin 221 is, for example, a general-purpose input / output (GPIO) pin, and the number of the output pin 221 and the number of the multiplexer 21 are both N, where N>8, but not limited thereto.

[0022] See also Figure 2 , 3 , an embodiment of the multiplexer address conflict processing method of the present invention, the steps included in the embodiment will be described below.

[0023] In step 41 , the control unit 222 sets i=1 for the first output pin 221 .

[0024] In step 42 , the control unit 222 switches an i-th output pin 221 to the high potential, so that an i-th multiplexer 21 electrically connected to the i-th output pin 221 is activated.

[0025] In step 43 , the control unit 222 transmits at least one inquiry message to the at least one integrated bus circuit device 23 of the i-th multiplexer 21 via the system management bus 3 .

[0026] In step 44, the control unit 222 determines whether at least one reply message corresponding to the at least one inquiry message is received. When it is determined that the at least one reply message is received, the process proceeds to step 45; and when it is determined that the at least one reply message is not received, the control unit 222 determines that the at least one integrated bus circuit device 23 of the i-th multiplexer 21 is damaged, and the process proceeds to step 47.

[0027] It should be noted that in this embodiment, after the control unit 222 sends the inquiry message, if the control unit 222 does not receive the at least one reply message within a set period of time, it determines that the at least one reply message has not been received, but the present invention is not limited thereto.

[0028] In step 45 , the control unit 222 reads the at least one integrated bus circuit device 23 of the i-th multiplexer 21 .

[0029] It is worth noting that in the present embodiment, the control unit 222 will first send out the at least one inquiry message, and then determine whether the at least one integrated bus circuit device 23 of the i-th multiplexer 21 is damaged based on whether the at least one reply message is received. If the at least one reply message is not received, it is determined to be damaged and no reading is performed to avoid errors when the control unit 222 reads the damaged integrated bus circuit device 23. However, in other implementations, steps 43 and 44 may not be performed, that is, step 45 may be performed directly after step 42, but this is not limited to it.

[0030] In step 46 , the control unit 222 switches the i-th output pin 221 to the low potential, so that the i-th multiplexer 21 is turned off.

[0031] In step 47, the control unit 222 determines whether the output pin 221 has been switched to the high potential, that is, whether i = N. When it is determined that the control unit 222 has not switched one of the output pins 221 to the high potential, that is, i≠N, the process proceeds to step 48; and when it is determined that the control unit 222 has switched the output pin 221 to the high potential, that is, i = N, the process ends.

[0032] In step 48 , the control unit 222 sets i=i+1 for the (i+1)th output pin 221 , and repeats step 42 .

[0033] In summary, the multiplexer address conflict processing method and the device with the multiplexer address conflict processing function of the present invention, without adding any hardware, controls the output pins 221 to switch to the high potential one by one by the control unit 222 to start the multiplexers 21 one by one, and after the control unit 222 reads all the integrated bus circuit devices 23 of the multiplexer 21, controls the output pins 221 to switch to the low potential to shut down the multiplexer 21 to avoid address conflicts, so the purpose of the present invention can be achieved.

[0034] However, the above is only an embodiment of the present invention and should not be used to limit the scope of the present invention. All simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still within the scope of the patent of the present invention.

Claims

1. A method for handling multiplexer address conflicts, performed by a device, the device comprising a baseboard management controller, and a plurality of multiplexers electrically connected to the baseboard management controller, the baseboard management controller comprising a plurality of output pins, each multiplexer electrically connected to at least one integrated bus circuit device, and each multiplexer comprising a reset pin, the reset pin electrically connected to one of the output pins, each output pin can be switched between a high potential and a low potential, each output pin is preset to the low potential, for each output pin, when the output pin is switched to the high potential, the reset pin of the multiplexer electrically connected to the output pin sends a reset signal to start the multiplexer electrically connected to the output pin, and when the output pin is switched to the low potential, the multiplexer electrically connected to the output pin is turned off, characterized in that The method comprises the following steps: (A) the baseboard management controller switches one of the target output pins of the output pins to the high potential, and a target reset pin of a target multiplexer electrically connected to the target output pin sends the reset signal, so that the target multiplexer is activated; (B) the baseboard management controller reads at least one target integrated bus circuit device of the target multiplexer; (C) the baseboard management controller switches the target output pin to the low voltage level, so that the target multiplexer is turned off; and (D) Repeat step (A) until the baseboard management controller has switched the output pin to the high potential.

2. The method for handling multiplexer address conflicts according to claim 1, wherein: After step (A), the method further comprises the following steps: (E) the baseboard management controller generates and transmits at least one inquiry message to the at least one target integrated bus circuit device of the target multiplexer respectively; When the baseboard management controller receives at least one reply message corresponding to the at least one inquiry message, step (B) is executed.

3. The multiplexer address conflict handling method according to claim 1, wherein: When the baseboard management controller does not receive the at least one reply message, the baseboard management controller determines that the at least one target integrated circuit bus circuit device is damaged, does not execute step (B) and step (C), and executes step (D).

4. A device with a multiplexer address conflict handling function, characterized in that: Include: A plurality of multiplexers, each multiplexer is electrically connected to at least one integrated bus circuit device, and each multiplexer includes a reset pin; and a baseboard management controller is electrically connected to the multiplexer, including a plurality of output pins, each electrically connected to a reset pin of the multiplexer, each output pin being switchable between a high potential and a low potential, each output pin being preset to the low potential, and for each output pin, when the output pin is switched to the high potential, the reset pin of the multiplexer to which the output pin is electrically connected sends a reset signal to start the multiplexer to which the output pin is electrically connected, and when the output pin is switched to the low potential, the multiplexer to which the output pin is electrically connected is shut down, and A control unit is electrically connected to the output pins, switches one of the target output pins of the output pins to the high potential, and a target reset pin of a target multiplexer electrically connected to the target output pin sends a reset signal, so that the target multiplexer is started, and reads at least one target integrated bus circuit device of the target multiplexer, and then switches the target output pin to the low potential, so that the target multiplexer is turned off, and repeats the above actions until the output pins have been switched to the high potential.

5. The device with multiplexer address conflict handling function according to claim 4, characterized in that: After switching the target output pin to the high voltage, the control unit generates and transmits at least one inquiry message to the at least one target integrated circuit bus circuit device of the target multiplexer respectively. When receiving at least one reply message corresponding to the at least one inquiry message respectively, the control unit reads the at least one target integrated circuit bus circuit device of the target multiplexer.

6. The device with multiplexer address conflict handling function according to claim 5, characterized in that: When the at least one reply message is not received, the control unit determines that the at least one target integrated circuit bus circuit device is damaged and does not read it. The control unit switches another target output pin of the output pin to the high potential and repeats the above actions until the output pin has been switched to the high potential.

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