Equipment debugging method and device, equipment and medium

Abstract

The invention discloses an equipment debugging method and device, equipment and a medium, and relates to the technical field of chips, and the method comprises the steps: determining whether a target time parameter is pre-configured in a first preset device or not after a target event is monitored; if the target time parameter is pre-configured, triggering a waiting operation of a corresponding duration based on the target time parameter, and triggering a data sampling operation after the waiting operation is ended, so as to sample interaction data between the target controller and a corresponding port physical layer, and obtain a sampling data packet; determining a target device from a plurality of second preset devices on the basis of the device priorities of the plurality of preset second preset devices and on the basis of whether corresponding sampling ending conditions are pre-configured in the second preset devices or not; and on the basis of a sampling ending condition in the target device, ending control is carried out on the data sampling operation, and the obtained sampling data packet is utilized to carry out equipment debugging on the peripheral component interconnection fast bus equipment. Therefore, the equipment problem can be quickly and conveniently positioned and debugged.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a device debugging method, device, equipment and medium. Background Art

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard that provides higher bandwidth, faster data transfer rates and lower latency. More and more main control chip data interfaces of expansion cards such as graphics cards, network cards and solid-state drives use PCIe interfaces. It has become the most widely used high-speed data transmission interconnection technology in modern computers, servers and SOC (System on Chip) chips. When debugging SOC chips with PCIe interfaces, one method is to use a PCIe protocol analyzer. This method requires a special fixture to connect the SOC chip PCIe interface to the analyzer. If the chip or board is not considered at the beginning of design, it is difficult to debug the interface using this method; another method is to use registers to record various states of the PCIe interface, and then read these registers through software for analysis. This method can obtain relatively few states, and it is difficult to accurately analyze the cause of the problem based on limited state information.

[0003] It can be seen that how to analyze the problem and debug the PCIe device when a problem occurs in the PCIe device is a problem that technical personnel in this field need to solve. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a device debugging method, apparatus, device and medium, which can easily and quickly locate the problem of the PCIe device so as to debug the PCIe device.

[0005] In a first aspect, the present invention provides a device debugging method, comprising:

[0006] After the target event is detected, determining whether the target time parameter is pre-configured in the first preset device;

[0007] If the first preset device is pre-configured with a target time parameter, a waiting operation of a corresponding duration is triggered based on the target time parameter, and a data sampling operation is triggered after the waiting operation ends, so as to sample the interactive data between the target controller and the corresponding port physical layer to obtain a corresponding sampled data packet; the target controller is a controller based on the Peripheral Component Interconnect Express bus standard;

[0008] Based on the device priorities of the plurality of preset second preset devices and based on whether the corresponding sampling end condition is pre-configured in each second preset device, determining a target device from the plurality of second preset devices;

[0009] Based on the sampling end condition in the target device, the data sampling operation is terminated and controlled, and the peripheral component interconnect fast bus device corresponding to the target controller is debugged using the sampling data packet obtained during the data sampling operation.

[0010] Optionally, the preset plurality of second preset devices include a first register, a second register and a third register, and the first preset device is a fourth register;

[0011] Correspondingly, the device debugging method also includes:

[0012] Based on the sampling start and end time requirements, configure the data sampling start time and the data sampling end time through the first register;

[0013] and / or, based on an event-active trigger requirement, configuring a first event for triggering the start of data sampling and a second event for triggering the end of data sampling through a second register;

[0014] and / or, based on the requirement of the number of sampled data packets, configuring the number of data packets to be sampled through a third register;

[0015] And / or, based on the sampling waiting time requirement and configuring the target parameter time through a fourth register.

[0016] Optionally, determining whether the target time parameter is pre-configured in the first preset device includes:

[0017] After detecting that the current time is the data sampling start time pre-configured in the first register, determining whether the target parameter time is configured in the fourth register;

[0018] Or, after detecting the occurrence of the first event pre-configured in the second register, it is determined whether the target parameter time is configured in the fourth register.

[0019] Optionally, the device priority of the third register is higher than the device priority of the first register and the second register;

[0020] Accordingly, based on the device priorities of the preset plurality of second preset devices and based on whether the corresponding sampling end condition is pre-configured in each second preset device, determining the target device from the plurality of second preset devices includes:

[0021] Monitoring whether the third register is pre-configured with the number of data packets that need to be sampled;

[0022] If the third register is pre-configured with the number of data packets to be sampled, the third register is directly determined as the target device;

[0023] If the number of data packets to be sampled is not pre-configured in the third register, monitoring whether the data sampling end time is configured in the first register and whether the second event is configured in the second register, and determining the target device from the first register and the second register based on the monitoring result;

[0024] Among them, if the data sampling end time is configured in the first register and the second event is not configured in the second register, the first register is determined as the target device; if the data sampling end time is not configured in the first register and the second event is configured in the second register, the second register is determined as the target device; if the data sampling end time is configured in the first register and the second event is configured in the second register, a register is randomly selected from the first register and the second register as the target device.

[0025] Optionally, based on a sampling end condition in the target device, the data sampling operation is terminated, including:

[0026] If the target device is the third register, the data sampling operation is terminated based on the number of data packets to be sampled that is preconfigured in the third register;

[0027] If the target device is the first register, the data sampling operation is terminated according to the data sampling termination time configured based on the first register;

[0028] If the target device is the second register, the data sampling operation is ended by controlling the second event configured by the second register.

[0029] Optionally, if a target time parameter is pre-configured in the first preset device, triggering a waiting operation of a corresponding duration based on the target time parameter includes:

[0030] If the fourth register is pre-configured with a target time parameter, a waiting operation of a corresponding duration is triggered based on the target time parameter;

[0031] Correspondingly, the device debugging method also includes:

[0032] If the target time parameter is not pre-configured in the fourth register, the data sampling operation is directly triggered to sample the interactive data between the target controller and the corresponding port physical layer to obtain a corresponding sampled data packet.

[0033] Optionally, using the sampled data packets obtained during the data sampling operation to perform device debugging on a peripheral component interconnect fast bus device corresponding to the target controller includes:

[0034] Determine the data packet encapsulation format based on the bit width of the physical layer interface of the peripheral component interconnect express bus device and the system bus occupancy efficiency;

[0035] Encapsulating the sampled data packets obtained during the data sampling operation according to the data encapsulation format, and writing the corresponding encapsulated data packets into the double rate synchronous dynamic random access memory;

[0036] Read the encapsulated data packet in the double rate synchronous dynamic random access memory, write the encapsulated data packet to a local storage device or transmit the encapsulated data packet to a remote device through a network port;

[0037] Parsing the encapsulated data packet through a storable device or a remote device based on a physical layer interface standard of a peripheral component interconnect express bus device to obtain corresponding parsed data;

[0038] The peripheral component interconnect express bus device corresponding to the target controller is debugged according to the parsed data.

[0039] Optionally, after obtaining the corresponding parsed data, it also includes:

[0040] If there is no error in the data after parsing, the third register is used to reconfigure the number of data packets to be sampled or the fourth register is used to reconfigure the target time parameters, and the process jumps again to the step of determining whether the target time parameters are pre-configured in the first preset device after the target event is monitored.

[0041] In a second aspect, the present invention provides a device debugging apparatus, comprising:

[0042] A time parameter determination module, used to determine whether a target time parameter is pre-configured in the first preset device after a target event is detected;

[0043] A sampling data packet acquisition module is used for triggering a waiting operation of a corresponding duration based on the target time parameter if a target time parameter is pre-configured in the first preset device, and triggering a data sampling operation after the waiting operation ends, so as to sample the interactive data between the target controller and the corresponding port physical layer to obtain a corresponding sampling data packet; the target controller is a controller based on the Peripheral Component Interconnect Express bus standard;

[0044] A target device determination module, configured to determine a target device from a plurality of second preset devices based on device priorities of the plurality of second preset devices and based on whether a corresponding sampling end condition is pre-configured in each second preset device;

[0045] The device debugging module is used to control the end of the data sampling operation based on the sampling end condition in the target device, and use the sampling data packet obtained during the data sampling operation to debug the peripheral component interconnect fast bus device corresponding to the target controller.

[0046] In a third aspect, the present invention provides an electronic device, comprising:

[0047] Memory for storing computer programs;

[0048] The processor is used to execute the computer program to implement the above-mentioned device debugging method.

[0049] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the aforementioned device debugging method when executed by a processor.

[0050] In the present invention, after monitoring a target event, it is determined whether a target time parameter is pre-configured in a first preset device; if the target time parameter is pre-configured in the first preset device, a waiting operation of a corresponding duration is triggered based on the target time parameter, and a data sampling operation is triggered after the waiting operation ends, so as to sample the interaction data between the target controller and the corresponding port physical layer to obtain a corresponding sampling data packet; the target controller is a controller based on the peripheral component interconnect fast bus standard; based on the device priority of a plurality of preset second preset devices, and based on whether a corresponding sampling end condition is pre-configured in each second preset device, a target device is determined from a plurality of second preset devices; based on the sampling end condition in the target device, the data sampling operation is terminated, and the sampling data packet obtained during the data sampling operation is used to perform device debugging on the peripheral component interconnect fast bus device corresponding to the target controller.

[0051] Beneficial effects: The present invention samples the interactive data between the controller and the corresponding port physical layer by pre-configuring the waiting time, sampling start condition and sampling end condition through a preset device, and then debugs the peripheral component interconnection fast bus device through the sampling data packet obtained during the data sampling operation. In this way, the sampling conditions of the interactive data can be flexibly configured, so as to conveniently and quickly locate the problems of the peripheral component interconnection fast bus device, and then realize the debugging of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 A flow chart of a device debugging method provided by an embodiment of the present invention.

[0054] Figure 2 A schematic diagram of the structure of a device debugging method provided by an embodiment of the present invention;

[0055] Figure 3 A schematic diagram of implementing a device debugging module provided by an embodiment of the present invention;

[0056] Figure 4 A flow chart of a specific device debugging method provided by an embodiment of the present invention;

[0057] Figure 5 A schematic diagram of register definition provided by an embodiment of the present invention;

[0058] Figure 6 A schematic diagram of register definition provided by an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of the structure of a device debugging apparatus provided by an embodiment of the present invention;

[0060] Figure 8 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0063] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0064] When debugging a SOC chip with a PCIe interface, one method is to use a PCIe protocol analyzer. This method requires a special fixture to connect the PCIe interface of the SOC chip to the analyzer. If the chip or board is not considered at the beginning of design, it is difficult to use this method to debug the interface; another method is to use registers to record the various states of the PCIe interface, and then read these registers through software for analysis. This method can obtain relatively few states, and it is difficult to accurately analyze the cause of the problem based on limited state information. In order to solve the above technical problems, the present invention provides a device debugging method, device, equipment and medium, which can easily and quickly locate the problem of PCIe equipment to debug the PCIe equipment.

[0065] See also Figure 1 As shown, an embodiment of the present invention provides a device debugging method, including:

[0066] Step S11: after detecting a target event, determining whether a target time parameter is pre-configured in the first preset device.

[0067] In an embodiment of the present invention, firstly, it is necessary to configure the data sampling start time and the data sampling end time based on the sampling start and end time requirements and through the first register; and / or, based on the event active triggering requirements, configure the first event for triggering the start of data sampling and the second event for triggering the end of data sampling through the second register; and / or, based on the sampling data packet number requirements, configure the number of data packets to be sampled through the third register; and / or, based on the sampling waiting time requirements, configure the target parameter time through the fourth register. At the same time, the first preset device is the fourth register. Specifically, the structural block diagram of the present invention is as follows: Figure 2As shown, it mainly includes debug control registers, packaging modules, and interrupt generation modules. The debug control registers include sampling control register group, manual sampling registers, and automatic sampling register group. The sampling control register group controls sampling wait, sampling channel, and data packet number settings; the manual sampling register includes manual sampling start and stop settings; the automatic sampling register group includes the start event register group, the start event enable register, the end event register group, and the end event enable register. Sampling wait is used to determine how long to wait before actually starting to sample data after configuring the manual sampling start or automatic sampling start event trigger. The sampling channel is used to select whether to sample received data or sent data, or to sample sent and received data at the same time. The data packet number setting is used to configure the sampling depth. If the number of data packets is not 0, sampling stops after completing the configured number of data packets; if the data packet is configured to be 0, sampling stops when the configuration manual sampling ends or the automatic sampling ends event is triggered. Manual sampling control is used by software to control the capture of sampled data according to the PCIe module status or business status. However, sometimes when the control is performed according to the business status, it may be too far away from the time when the problem occurs, or the software control itself may be affected by other processes, resulting in uncontrollable time points, resulting in missed data capture moments. Automatic sampling control is used to solve the above problems. Users can configure some events to the start event register or end event register according to their own business. These events can be a certain type of data packet, a data packet accessing a certain address, a certain error indication, etc. When the automatic sampling start event or stop event is triggered, the internal circuit automatically starts or stops capturing data packets.

[0068] Therefore, the present invention determines whether the target parameter time is configured in the fourth register after monitoring that the current time is the data sampling start time pre-configured in the first register; or, after monitoring that the first event pre-configured in the second register currently occurs, determines whether the target parameter time is configured in the fourth register. That is, if it is monitored that the current time is the sampling start time or the sampling start event is triggered, it is first determined according to the sampling wait register how long to wait before actually starting to sample data.

[0069] Step S12: If the target time parameter is pre-configured in the first preset device, a waiting operation of a corresponding duration is triggered based on the target time parameter, and a data sampling operation is triggered after the waiting operation ends to sample the interaction data between the target controller and the corresponding port physical layer to obtain a corresponding sampling data packet; the target controller is a controller based on the Peripheral Component Interconnect Express bus standard.

[0070] In an embodiment of the present invention, if the fourth register, i.e., the sampling wait register, is pre-configured with a target time parameter, it indicates that although the signal to start sampling has been triggered, it is still necessary to wait for the target time before actually performing sampling, rather than starting sampling immediately when the current moment is detected to be the time to start sampling or when the start sampling event is triggered. Then the present invention will trigger a waiting operation of a corresponding duration based on the target time parameter, and trigger a data sampling operation after the waiting operation ends. That is, sampling will start after waiting for a period of time. In this way, the data for a certain time period can be customized according to the user's settings, and the desired data can be captured more accurately.

[0071] On the contrary, if the target time parameter is not pre-configured in the fourth register, the data sampling operation is directly triggered to sample the interactive data between the target controller and the corresponding port physical layer to obtain the corresponding sampling data packet. That is, if the target time parameter is not configured in the sampling wait register or the target time parameter is 0, when the current moment is detected as the time to start sampling or the start sampling event is triggered, sampling can be started immediately without waiting. This reflects the personalized customization of data sampling events, and data within any time period can be obtained.

[0072] In addition, since the present invention triggers a waiting operation of corresponding duration based on the target time parameter when sampling data, and triggers the data sampling operation after the waiting operation ends, that is, it is necessary to first determine whether the waiting time is set. If it is set, wait for a while before collecting, and if not, collect immediately. Therefore, for the setting of this target time parameter, the time can be pre-set in the register, or the type of sampled data can be determined first, and different target time parameters can be determined according to the types of different data and historical experience. The urgency of the collected data can also be determined first, and the waiting time with a high urgency can be set shorter, while the waiting time with a relatively low urgency can be set longer. In the process of collection, a corresponding adjustment interface can be set, and the waiting time can be set in real time through the adjustment interface, so as to adapt to the occurrence of various situations and flexibly obtain sampled data of different time periods.

[0073] It should be pointed out that, in the process of sampling the interactive data between the target controller and the corresponding port physical layer to obtain the corresponding sampled data packet, the present invention determines the interactive data by configuring the sampling channel register, and the sampling channel is used to select whether to sample the received data or the sent data, or to sample the sent and received data at the same time. Therefore, if the sampled sending channel data is configured through the sampling channel, the sampled data at this time is the data sent to the port physical layer by the controller based on the peripheral component interconnection express bus standard. Similarly, if the sampled receiving channel data is configured through the sampling channel, the sampled interactive data at this time is the data sent by the port physical layer received by the controller based on the peripheral component interconnection express bus standard. If the sampled sending and receiving channel data are configured through the sampling channel, the sampled data at this time is the data sent and received by the controller based on the peripheral component interconnection express bus standard to the port physical layer.

[0074] Step S13: based on the device priorities of the plurality of second preset devices and based on whether the corresponding sampling end condition is pre-configured in each second preset device, determine the target device from the plurality of second preset devices.

[0075] In an embodiment of the present invention, the preset second preset devices include a first register, a second register and a third register, and the first preset device is a fourth register; the present invention can configure the data sampling start time and the data sampling end time based on the sampling start and end time requirements and through the first register; and / or, based on the event active triggering requirements and through the second register to configure the first event for triggering the start sampling of data and the second event for triggering the end sampling of data; and / or, based on the sampling data packet number requirements and through the third register to configure the number of data packets to be sampled. Therefore, in the process of sampling the interactive data between the controller based on the peripheral component interconnection express bus standard and the corresponding port physical layer, the device priority of the third register is higher than the device priority of the first register and the second register. The third register here is the data packet number register, that is, it is used to configure the sampling depth; the first register is a manual sampling register, and the second register is an automatic sampling register. That is, it is necessary to first look at the setting of the data packet number register.

[0076] Specifically, monitor whether the third register is pre-configured with the number of data packets to be sampled; if the third register is pre-configured with the number of data packets to be sampled, directly determine the third register as the target device; if the third register is not pre-configured with the number of data packets to be sampled, monitor whether the first register is configured with the data sampling end time and whether the second register is configured with the second event, and determine the target device from the first register and the second register based on the monitoring results; wherein, if the first register is configured with the data sampling end time and the second register is not configured with the second event, the first register is determined as the target device; if the first register is not configured with the data sampling end time and the second register is configured with the second event, the second register is determined as the target device; if the first register is configured with the data sampling end time and the second register is configured with the second event, a register is randomly selected from the first register and the second register as the target device. In other words, if the number of data packets is configured as non-0, the third register is the one that can determine the end of sampling at this time. If the number of data packets to be sampled is not pre-configured in the third register, or the number of data packets is configured to 0, then the second register and the first register can determine the end of sampling. When determining between the two registers, it is necessary to further determine whether the data sampling conditions are configured in the second register and the first register. If both are configured, then one of the two registers can be selected as the register for determining the end. If only one is configured, then the register configured with the end condition is selected as the register for determining the end of sampling.

[0077] Step S14: Based on the sampling end condition in the target device, the data sampling operation is terminated, and the sampling data packet obtained during the data sampling operation is used to perform device debugging on the PCI Express bus device corresponding to the target controller.

[0078] In an embodiment of the present invention, after determining the register that can control the sampling control, the data sampling operation is terminated according to the sampling end condition in the register. Specifically, if the target device is the third register, the data sampling operation is terminated based on the number of data packets that need to be sampled pre-configured in the third register; if the target device is the first register, the data sampling operation is terminated according to the data sampling end time configured based on the first register; if the target device is the second register, the data sampling operation is terminated through the second event configured by the second register. In short, if the number of data packets is configured to be non-0, sampling stops after the configured number of data packets is completed; if the data packet is configured to be 0, sampling stops when the manual sampling end or automatic sampling end event is triggered.

[0079] After the sampling is finished, the present invention determines the data packet encapsulation format based on the bit width of the physical layer interface of the peripheral component interconnection fast bus device and the system bus occupancy efficiency; encapsulates the sampled data packet obtained during the data sampling operation according to the data encapsulation format, and writes the corresponding encapsulated data packet into the double-rate synchronous dynamic random access memory; reads the encapsulated data packet in the double-rate synchronous dynamic random access memory, writes the encapsulated data packet into a local storable device or transmits the encapsulated data packet to a remote device through a network port; parses the encapsulated data packet based on the physical layer interface standard of the peripheral component interconnection fast bus device through the storable device or the remote device to obtain the corresponding parsed data; debugs the peripheral component interconnection fast bus device corresponding to the target controller according to the parsed data. In other words, after the sampling is completed, the present invention writes the sampled data from DDR (Double Data Rate, double-rate synchronous dynamic random access memory) into a local SD card, a U disk or transmits it to the remote end through a network port. After obtaining the sampled data, the user first writes a script to unpack the obtained data according to the package format, and then uses the script to parse the data according to the PCIe PIPE (Physical Interface for PCI Express) interface standard to obtain the business data packet and analyze the cause of the problem, or import the data into the RTL (Register-Transfer Level) simulation platform to observe whether the processing process of the data packet in the actual circuit is consistent with expectations. It should also be pointed out that when the sampling is completed, an indication signal will be generated to the interrupt module to notify the software that the sampling is completed.

[0080] In an embodiment of the present invention, if the currently acquired data packet has an error in the result analysis or simulation, the cause of the error can be determined, and the peripheral component interconnect fast bus device can be debugged according to the cause of the error. However, if the acquired sampled data packet is parsed and the parsed data does not have an error, the number of data packets to be sampled is reconfigured using the third register or the target time parameter is reconfigured using the fourth register, and the process jumps again to the step of determining whether the target time parameter is pre-configured in the first preset device after the target event is detected. That is, if there is no error in the result analysis or simulation of the captured data, the sampling wait register or the data packet number register can be adjusted to capture more data later for analysis.

[0081] Beneficial effects: The present invention samples the interactive data between the controller and the corresponding port physical layer by pre-configuring the waiting time, sampling start condition and sampling end condition through a preset device, and then debugs the peripheral component interconnection fast bus device through the sampling data packet obtained during the data sampling operation. In this way, the sampling conditions of the interactive data can be flexibly configured, so as to conveniently and quickly locate the problems of the peripheral component interconnection fast bus device, and then realize the debugging of the device.

[0082] Based on the above embodiment, it can be known that the device debugging method of the present invention mainly includes a debugging control register, a packaging module, and an interrupt generation module. Next, the implementation process of device debugging will be specifically described based on these modules.

[0083] One way to implement PCIe device debugging is to Figure 3 As shown, it includes a manual sampling register, a sampling wait register, a data packet number register, an automatic sampling start event / enable register, an automatic sampling end event / enable register, a timer, a packaging module and an interrupt module.

[0084] In a specific embodiment, suppose a PCIe device has a problem and needs to be debugged. It is known that the last normal access before the problem was a memory write data packet request received at address 0x12345678. Now it is necessary to capture the data interaction between devices after the last normal access. The process is as follows: Figure 4 As shown, first configure the sampling channel register, configure the sampling wait register, configure the data packet number register, configure the automatic sampling start event register, and configure the automatic sampling start event enable register. The definition of each register is as follows Figure 5 and Figure 6 shown.

[0085] The manual sampling register is used for software to flexibly configure the start and end time of data sampling. The automatic sampling start event group defines N events. When the corresponding event detection is enabled and the event occurs or the manual sampling register is configured to start sampling, it indicates that it is necessary to start preparing to capture data. After waiting for the number of clocks configured in the sampling waiting register, it instructs the packaging module to start sampling and packaging the PIPE (Physical Interface for PCI Express, PCIe physical layer interface) data between the PCIe controller and the PHY (Physical Layer, port physical layer). If the data packet number register is configured to be non-0, the packaging module will automatically stop data sampling after sampling the number of data packets; if the data packet number register is 0, the packaging module will stop data sampling when the automatic sampling end event detection is enabled and the event occurs or the manual sampling register configuration ends. The sampling module can choose to sample only the receiving channel or the transmitting channel according to the sampling channel configuration, and encapsulate the data in a certain data packet format and write it to DDR. When packing data, the data format of the packing module can be considered according to factors such as the bit width of the PIPE interface and the system bus occupancy efficiency, and then the data packet encapsulation format is determined based on the bit width of the physical layer interface of the peripheral component interconnect fast bus device and the system bus occupancy efficiency; the sampled data packets obtained during the data sampling operation are encapsulated according to the data encapsulation format, and the corresponding encapsulated data packets are written into the double rate synchronous dynamic random access memory. When the sampling is completed, an indication is generated to the interrupt module to notify the software that the sampling is completed.

[0086] Then wait for the sampling completion interrupt. Since the sampled data are all packaged and written into DDR, after the sampling completion interrupt, the data can be read from DDR and written into SD card, USB flash drive or remotely transmitted back through the network for subsequent analysis. Then parse these PCIe physical layer interface data according to the format, and then use the script to parse the data according to the PCIe PIPE interface standard to obtain the business data packet and analyze the cause of the problem as needed, or import the data into the RTL simulation platform to observe whether the processing process of the data packet in the actual circuit is consistent with expectations. Finally, the debugging is completed. At the same time, in this process, designers can add automatic sampling start events, add automatic sampling end events, adjust the packaged data format, etc. These can all be customized.

[0087] Beneficial effects: The present invention flexibly configures various registers and parameters in the registers, flexibly configures manual or automatic capture of the final data sent by the PCIe device or the initial data received, and exports the captured data locally or remotely. According to the protocol, these original data are parsed or imported into the RTL platform for simulation, which can easily locate the problem of the PCIe device.

[0088] See also Figure 7 As shown, an embodiment of the present invention provides a device debugging apparatus, including:

[0089] The time parameter determination module 11 is used to determine whether the target time parameter is pre-configured in the first preset device after the target event is detected;

[0090] The sampling data packet acquisition module 12 is used for triggering a waiting operation of a corresponding duration based on the target time parameter if the target time parameter is pre-configured in the first preset device, and triggering a data sampling operation after the waiting operation ends, so as to sample the interaction data between the target controller and the corresponding port physical layer to obtain a corresponding sampling data packet; the target controller is a controller based on the Peripheral Component Interconnect Express bus standard;

[0091] A target device determination module 13, configured to determine a target device from a plurality of second preset devices based on device priorities of the plurality of second preset devices and based on whether a corresponding sampling end condition is pre-configured in each second preset device;

[0092] The device debugging module 14 is used to control the end of the data sampling operation based on the sampling end condition in the target device, and use the sampling data packet obtained during the data sampling operation to perform device debugging on the PCI Express bus device corresponding to the target controller.

[0093] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0094] Beneficial effects: The present invention samples the interactive data between the controller and the corresponding port physical layer by pre-configuring the waiting time, sampling start condition and sampling end condition through a preset device, and then debugs the peripheral component interconnection fast bus device through the sampling data packet obtained during the data sampling operation. In this way, the sampling conditions of the interactive data can be flexibly configured, so as to conveniently and quickly locate the problems of the peripheral component interconnection fast bus device, and then realize the debugging of the device.

[0095] Furthermore, the present application also discloses an electronic device. Figure 8It is a structural diagram of an electronic device according to an exemplary embodiment, and the content in the figure cannot be regarded as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the device debugging method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0096] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0097] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0098] The operating system 221 is used to manage and control various hardware devices on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the device debugging method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0099] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the device debugging method disclosed above. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the above embodiments, and no further description will be given here.

[0100] Furthermore, the present application also discloses a computer program product, including a computer program / instruction; wherein the computer program / instruction, when executed by a processor, implements the aforementioned disclosed alarm aggregation method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0101] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0102] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0103] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0104] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0105] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A device debugging method, characterized in that: include: After the target event is detected, determining whether the target time parameter is pre-configured in the first preset device; If the first preset device is pre-configured with a target time parameter, a waiting operation of a corresponding duration is triggered based on the target time parameter, and a data sampling operation is triggered after the waiting operation ends, so as to sample the interaction data between the target controller and the corresponding port physical layer to obtain a corresponding sampled data packet; The target controller is a controller based on the Peripheral Component Interconnect Express bus standard; Based on the device priorities of the plurality of second preset devices and based on whether the corresponding sampling end condition is pre-configured in each of the second preset devices, determining a target device from the plurality of second preset devices; Based on the sampling end condition in the target device, the data sampling operation is controlled to end, and the peripheral component interconnect fast bus device corresponding to the target controller is debugged using the sampling data packet obtained during the data sampling operation.

2. The device debugging method according to claim 1, characterized in that: The preset plurality of second preset devices include a first register, a second register and a third register, and the first preset device is a fourth register; Accordingly, the device debugging method further includes: Based on the sampling start and end time requirements, configure the data sampling start time and the data sampling end time through the first register; and / or, based on an event-active triggering requirement, configuring a first event for triggering the start of data sampling and a second event for triggering the end of data sampling through the second register; and / or, based on the requirement of the number of sampled data packets, configuring the number of data packets to be sampled through the third register; And / or, the target parameter time is configured through a fourth register based on a sampling waiting time requirement.

3. The device debugging method according to claim 2, characterized in that: After the target event is detected, determining whether the target time parameter is pre-configured in the first preset device includes: After monitoring that the current time is the data sampling start time pre-configured in the first register, determining whether the target parameter time is configured in the fourth register; Or, after monitoring the current occurrence of the first event pre-configured in the second register, determining whether the target parameter time is configured in the fourth register.

4. The device debugging method according to claim 2, characterized in that: The device priority of the third register is higher than the device priorities of the first register and the second register; Accordingly, the device priorities of the preset plurality of second preset devices and determining the target device from the plurality of second preset devices based on whether the corresponding sampling end condition is pre-configured in each of the second preset devices include: Monitoring whether the third register is pre-configured with the number of data packets that need to be sampled; If the third register is pre-configured with the number of data packets to be sampled, the third register is directly determined as the target device; If the number of data packets to be sampled is not pre-configured in the third register, monitoring whether the data sampling end time is configured in the first register and whether the second event is configured in the second register, and determining the target device from the first register and the second register based on the monitoring result; Among them, if the data sampling end time is configured in the first register and the second event is not configured in the second register, the first register is determined as the target device; if the data sampling end time is not configured in the first register and the second event is configured in the second register, the second register is determined as the target device; if the data sampling end time is configured in the first register and the second event is configured in the second register, a register is randomly selected from the first register and the second register as the target device.

5. The device debugging method according to claim 4, characterized in that: The step of controlling the end of the data sampling operation based on the sampling end condition in the target device includes: If the target device is the third register, then the data sampling operation is terminated based on the number of data packets that need to be sampled that is pre-configured in the third register; If the target device is the first register, controlling the end of the data sampling operation according to the data sampling end time configured based on the first register; If the target device is the second register, the data sampling operation is terminated by controlling the second event configured by the second register.

6. The device debugging method according to claim 2, characterized in that: If the first preset device is pre-configured with a target time parameter, triggering a waiting operation of a corresponding duration based on the target time parameter includes: If the target time parameter is pre-configured in the fourth register, a waiting operation of a corresponding duration is triggered based on the target time parameter; Accordingly, the device debugging method further includes: If the target time parameter is not pre-configured in the fourth register, the data sampling operation is directly triggered to sample the interactive data between the target controller and the corresponding port physical layer to obtain a corresponding sampled data packet.

7. The device debugging method according to any one of claims 2 to 6, characterized in that: The method of using the sampled data packet obtained during the data sampling operation to debug a peripheral component interconnect fast bus device corresponding to the target controller includes: Determine a data packet encapsulation format based on the bit width of the physical layer interface of the PCI Express bus device and the system bus occupancy efficiency; Encapsulating the sampling data packets acquired during the data sampling operation according to the data encapsulation format, and writing the corresponding encapsulated data packets into a double rate synchronous dynamic random access memory; Reading the encapsulated data packet in the double rate synchronous dynamic random access memory, writing the encapsulated data packet to a local storable device or transmitting the encapsulated data packet to a remote device through a network port; Parsing the encapsulated data packet through the storable device or the remote device based on the physical layer interface standard of the peripheral component interconnect fast bus device to obtain corresponding parsed data; The PCI Express bus device corresponding to the target controller is debugged according to the parsed data.

8. The device debugging method according to claim 7, characterized in that: After obtaining the corresponding parsed data, the method further includes: If there is no error in the parsed data, the third register is used to reconfigure the number of data packets to be sampled or the fourth register is used to reconfigure the target time parameters, and the process jumps again to the step of determining whether the target time parameters are pre-configured in the first preset device after the target event is monitored.

9. A device debugging device, characterized in that: include: A time parameter determination module, used to determine whether a target time parameter is pre-configured in the first preset device after a target event is detected; a sampling data packet acquisition module, configured to trigger a waiting operation of a corresponding duration based on the target time parameter if the target time parameter is pre-configured in the first preset device, and trigger a data sampling operation after the waiting operation ends, so as to sample the interaction data between the target controller and the corresponding port physical layer to obtain a corresponding sampling data packet; The target controller is a controller based on the Peripheral Component Interconnect Express bus standard; A target device determination module, configured to determine a target device from among the plurality of second preset devices based on device priorities of the plurality of second preset devices and based on whether a corresponding sampling end condition is pre-configured in each of the second preset devices; A device debugging module is used to control the end of the data sampling operation based on the sampling end condition in the target device, and to use the sampling data packet obtained during the data sampling operation to perform device debugging on the peripheral component interconnect fast bus device corresponding to the target controller.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the device debugging method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the device debugging method according to any one of claims 1 to 8 are implemented.

Images