Verification method and device of chip register, equipment and medium

Abstract

The embodiment of the invention relates to a chip register verification method and device, equipment and a medium, and the method comprises the steps: determining a target verification case of a to-be-verified register in response to a verification instruction; the to-be-verified module obtains data from the address of the to-be-verified register based on the target verification case and sends the data to the target memory through the interaction function; the monitoring module obtains data from the target memory based on the interaction function, prints all read-write data of the register to be verified, generates a verification mark according to the obtained data, and sends the verification mark to the scoreboard module based on the event module; and the scoreboard module compares the verification mark sent by the monitoring module with the real mark sent by the reference model module to generate a verification result of the register to be verified. Therefore, all the registers in all the modules of the chip can be subjected to full-coverage detection, and the verification efficiency of the chip registers is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip register verification method, device, equipment and medium. Background Art

[0002] With the development of technology, the functions of chips will become more and more powerful and the scale will become larger and larger, resulting in more and more modules in a chip. The number of registers in different modules is also different. Some complex modules will have hundreds or thousands of registers. Therefore, the verification of the read and write functions of these registers will become more and more cumbersome and time-consuming. How to quickly verify all registers of all modules of a chip has become an urgent problem to be solved.

[0003] Most of the existing methods for detecting chip registers are to detect the registers in a certain module or a certain address range, which cannot achieve full coverage of chip register detection. In addition, the use of electronic equipment to verify the registers through software and hardware interaction increases the cost. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a chip register verification method, device, equipment and medium.

[0005] The present disclosure provides a chip register verification method, including:

[0006] In response to the verification instruction, determining a target verification case of the register to be verified;

[0007] The module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function;

[0008] The monitoring module obtains data from the target memory based on the interactive function, prints all read and write data of the register to be verified, generates a verification mark according to the obtained data, and sends the verification mark to the scoreboard module based on the event module;

[0009] The scoreboard module compares the verification flag with the real flag sent by the reference model module to generate a verification result of the register to be verified.

[0010] Optionally, the method further includes:

[0011] Generate all verification cases and verification files by reading register table information through script; wherein the verification file includes the monitoring module, the event module, the reference model module and the scoreboard module;

[0012] All the verification cases are stored in the module to be verified.

[0013] Optionally, the register table information is read through a script to generate all verification cases, including:

[0014] Acquire a worksheet name based on the register table information;

[0015] The worksheet corresponding to the worksheet name is read in a preset reading order to obtain register information, and all the verification use cases are generated based on the register information.

[0016] Optionally, the generating all the verification cases based on the register information includes:

[0017] determining a register attribute based on the register information;

[0018] Generate an application corresponding to each of the register attributes to obtain all the verification use cases.

[0019] Optionally, the method further includes:

[0020] acquiring a register table name based on the register table information;

[0021] Set the register table name to the verification environment name.

[0022] Optionally, before running the script, the method further includes:

[0023] Install the database for working with table files.

[0024] Optionally, the method further includes:

[0025] Run the move script to move all the verification cases and the verification files to the target file path and generate a verification environment.

[0026] The present disclosure also provides a chip register verification device, including:

[0027] A response module, configured to determine a target verification case of a register to be verified in response to a verification instruction;

[0028] A module to be verified, used for obtaining data from the address of the register to be verified based on the target verification case and sending it to the target memory through an interactive function;

[0029] A monitoring module, configured to obtain data from the target memory based on an interactive function, print all read and write data of the register to be verified, generate a verification mark according to the obtained data, and send the verification mark to the scoreboard module based on an event module;

[0030] The scoreboard module is used to generate a verification result of the register to be verified based on the comparison between the verification flag and the real flag sent by the reference model module.

[0031] An embodiment of the present disclosure also provides an electronic device, which includes: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the chip register verification method provided in the embodiment of the present disclosure.

[0032] An embodiment of the present disclosure further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the chip register verification method provided by the embodiment of the present disclosure.

[0033] An embodiment of the present disclosure further provides a computer program product, including a computer program, wherein the computer program implements the chip register verification method described in the aforementioned aspect when executed by a processor.

[0034] The technical solution provided by the embodiment of the present disclosure has the following advantages over the prior art: the verification solution for chip registers provided by the embodiment of the present disclosure includes: in response to the verification instruction, determining the target verification case of the register to be verified; the module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function; the monitoring module obtains data from the target memory based on the interactive function, and prints all read and write data of the register to be verified, generates a verification mark based on the obtained data, and sends the verification mark to the scoreboard module based on the event module; the scoreboard module compares the verification mark sent by the monitoring module with the real mark sent by the reference model module, and generates the verification result of the register to be verified. It solves the problem that the existing method cannot achieve full coverage of chip register detection technology, can save time and labor costs, generate verification cases and verification environments in one click, perform full coverage read and write verification on the registers of the entire chip, and improve the verification efficiency of chip registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0036] Figure 1 A schematic diagram of a flow chart of a chip register verification method provided by an embodiment of the present disclosure;

[0037] Figure 2 A flowchart of another chip register verification method provided by an embodiment of the present disclosure;

[0038] Figure 3 An example diagram of verification of a chip register provided in an embodiment of the present disclosure;

[0039] Figure 4 An example diagram of another chip register verification provided by an embodiment of the present disclosure;

[0040] Figure 5 An example diagram of a verification environment provided for an embodiment of the present disclosure;

[0041] Figure 6 A schematic diagram of the structure of a chip register verification device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0043] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0044] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0045] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0046] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0047] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0048] At present, most methods for detecting chip registers are to detect registers in a certain module or a certain address range, which cannot achieve full coverage of chip register detection. In addition, the use of electronic equipment to verify registers through software and hardware interaction increases costs.

[0049] In view of the above problems, the present disclosure implements a verification method for chip registers, which determines the target verification case of the register to be verified by responding to the verification instruction; the module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function; the monitoring module obtains data from the target memory based on the interactive function, prints all read and write data of the register to be verified, generates a verification mark based on the obtained data, and sends the verification mark to the scoreboard module based on the event module; the scoreboard module compares the verification mark sent by the monitoring module with the real mark sent by the reference model module, and generates the verification result of the register to be verified. In this way, all registers in all modules of the chip can be fully covered and tested, thereby improving the verification efficiency of the chip registers.

[0050] Figure 1 The following is a flow chart of a chip register verification method provided by an embodiment of the present disclosure. Figure 1 As shown, the method includes:

[0051] Step 101: In response to a verification instruction, determine a target verification case of a register to be verified.

[0052] In the disclosed embodiments, the verification instruction may be a verification instruction for any register function corresponding to any module of the chip, such as a verification instruction for the read and write functions of all registers of the timer module, a verification instruction for checking the reset values ​​of all registers of the timer module, and a verification instruction for the erase function of all registers of the timer module, etc. In other words, any module may be selected to perform verification of a register function according to the actual verification scenario needs, thereby further satisfying the flexibility of chip register verification.

[0053] It can be understood that after installing the database for processing table files, the script can be run to generate all verification cases and verification files by reading the register table information through the script; wherein, the verification file includes a monitoring module, an event module, a reference model module and a scoreboard module, and all verification cases are stored in the module to be verified, and the move script is run to move all verification cases and verification files to the target file path to generate a verification environment, so that the chip registers can be verified.

[0054] In an embodiment of the present disclosure, in response to a verification instruction, a module to be verified can be obtained, such as a module to be verified, and all registers corresponding to the module to be verified are taken as registers to be verified; it can be understood that each register to be verified has a corresponding verification case, so after determining the register to be verified, the target verification case of the register to be verified can be determined, that is, the target verification case refers to the verification case corresponding to the register to be verified, wherein different register attributes of all modules correspond to different verification cases.

[0055] Step 102: The module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function.

[0056] In the disclosed embodiment, all corresponding verification cases are generated for all registers corresponding to all modules of a chip and burned into the module to be verified. Therefore, the module to be verified can write, read or erase data to the address of the register to be verified through the target verification case. For example, write a data such as "55" to a module register address, and then obtain the data of the register address through the target verification case and send it to the target memory such as an idle SRAM (Static Random-Access Memory) memory of the chip through the interactive function.

[0057] Step 103: The monitoring module obtains data from the target memory based on the interactive function, prints all read and write data of the register to be verified, generates a verification mark according to the obtained data, and sends the verification mark to the scoreboard module based on the event module.

[0058] Among them, the monitoring module can obtain data from the target memory through interactive functions such as "word_from_c". If the data obtained is zero, it will fall into an infinite loop and will continue to obtain data from the target memory. If the data obtained is not zero, the target verification use case will continue to execute, and the data of the register to be verified of each module will be printed out until all the registers of this module are covered.

[0059] Among them, the verification flag in the monitoring module is obtained through the data obtained from the target memory. If the obtained data is correct, the verification flag will be the correct value, such as 1, otherwise the verification flag will be set to zero. The monitoring module transmits data with the scoreboard module through the event module, that is, the verification flag is sent to the scoreboard module based on the event module; in addition, the printing information can quickly locate which register has a problem, so as to correct and troubleshoot it.

[0060] Step 104: The scoreboard module compares the verification flag sent by the monitoring module with the real flag sent by the reference model module to generate a verification result of the register to be verified.

[0061] In the disclosed embodiment, the real flag in the reference model module can be the correct data generated by the script, and the real flag is sent to the scoreboard module, so that the scoreboard module compares the verification flag and the real flag sent by the monitoring module to generate a verification result of the register to be verified. That is to say, if the verification flag and the real flag are the same, it means that the reading and writing functions of the register to be verified are normal and no processing is required. If the verification flag and the real flag are not the same, it means that the reading and writing functions of the register to be verified are abnormal, and further correction and troubleshooting can be performed to further improve the chip register verification efficiency.

[0062] The chip register verification scheme provided by the disclosed embodiment determines the target verification case of the register to be verified by responding to the verification instruction; the module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function; the monitoring module obtains data from the target memory based on the interactive function, prints all read and write data of the register to be verified, generates a verification mark based on the obtained data, and sends the verification mark to the scoreboard module based on the event module; the scoreboard module compares the verification mark with the real mark sent by the reference model module to generate the verification result of the register to be verified. It solves the problem that the existing method cannot achieve full coverage of chip register detection technology, can save time and labor costs, generate verification cases and verification environments in one click, perform full coverage read and write verification on the registers of the entire chip, and improve the verification efficiency of chip registers.

[0063] Figure 2 The present invention provides a flow chart of a chip register verification method according to an embodiment of the present invention. This embodiment further optimizes the chip register verification method based on the above embodiment. Figure 2 As shown, the method includes:

[0064] Step 201: Install a database for processing table files.

[0065] Specifically, some python databases, such as pandas, openpyxl, etc., are installed in the test system to process table files, so that subsequent scripts can be run.

[0066] Step 202, read the register table information through the script to generate all verification cases and verification files; wherein the verification file includes a monitoring module, an event module, a reference model module and a scoreboard module, and stores all verification cases in the module to be verified.

[0067] Step 203: Run the move script to move all verification cases and verification files to the target file path and generate a verification environment.

[0068] In some embodiments, all verification cases are generated by reading register table information through a script, including: obtaining a worksheet name based on the register table information, reading a worksheet corresponding to the worksheet name according to a preset reading order, obtaining register information, and generating all verification cases based on the register information.

[0069] In some embodiments, all verification use cases are generated based on the register information, including: determining register attributes based on the register information, generating an application corresponding to each register attribute, and obtaining all verification use cases.

[0070] In some embodiments, a register table name is obtained based on the register table information, and the register table name is set as the verification environment name.

[0071] Specifically, you can obtain register table information, such as the filled register table. The name of the register table is the name of the final verification environment. The names of different worksheets are the names of each module in the chip. Even repeated modules such as TIM0, TIM1, and TIM2 require different worksheets. The table also needs to fill in six columns of information, namely register name, module address, register offset address, read and write attributes, written data (0 if there is no written data) and reset value; then run the script to generate all verification cases and verification files.

[0072] Specifically, when running the register script, the information of the register table is extracted as follows Figure 3 As shown, it includes: step 3.1 extracts the table name; step 3.2 scans row by row to obtain information (register name, address, offset address, read-write attributes, written data, reset value); step 3.3 determines whether the row is empty; if not, continues to execute step 3.2; if so, executes step 3.4 to determine whether there are other worksheets (sheet); if so, executes step 3.5 to obtain another worksheet name (sheet) and information, and then executes step 3.2; if not, executes step 3.6 to generate the "c\sv\josn" file; step 3.7 creates a folder and moves the generated file to the corresponding folder.

[0073] The first step is to extract the register table name and worksheet name. The register table name will be used as the final verification environment name (the verification environment name is standardized and isolated to ensure the stability and reliability of the verification platform; for example, UVM (Universal Verification Methodology) improves the reuse rate and portability of the verification platform through the characteristics of object-oriented programming and coverage components, making the verification environment more standardized and easy to manage). The worksheet name is the name of each module of the chip. After reading the worksheet name, the rows and columns of the current table will be scanned, and the information will be extracted and stored in the array. Then, the array where the information of the next row is stored will be read. Each read will determine whether it is empty. If it is empty, the information of another worksheet will be read until the entire register table is read. The read information will be converted into the required files for the subsequent generation of verification environments and verification cases. When all the generation is completed, some folders will be created and the generated files will be moved to the corresponding paths.

[0074] Finally, run the move script to move all the verification cases and verification files generated previously to the corresponding file path to generate the verification environment. After the verification environment is generated, you can go to the simulation path for verification. You can use the corresponding command to verify which module. For example, to verify the write function of the timer register, you can enter "run timer0_WR_test" to write a value to all the registers of the timer and then read them to see whether the value is written in for verification.

[0075] Among them, generating verification cases based on register attributes mainly includes three parts: if the register is readable and writable, the value will be written to the register and then read; if the register can only be read but not written, it will be reset through other modules first and then the reset value will be read; if the register has read-erase-write-erase functions, it will be erased first and then the value of the corresponding register will be read.

[0076] Step 204: In response to the verification instruction, a target verification case of the register to be verified is determined, and the module to be verified obtains data from the address of the register to be verified based on the target verification case and sends it to the target memory through the interactive function.

[0077] Step 205: The monitoring module obtains data from the target memory based on the interactive function, and prints all read and write data of the register to be verified, generates a verification mark according to the obtained data, and sends the verification mark to the scoreboard module based on the event module. The scoreboard module compares the verification mark sent by the monitoring module with the real mark sent by the reference model module to generate a verification result of the register to be verified.

[0078] In an embodiment of the present disclosure, after installing a database for processing table files, a script can be run to generate all verification cases and verification files by reading register table information through the script; wherein the verification file includes a monitoring module, an event module, a reference model module and a scoreboard module, and all verification cases are stored in the module to be verified, and a move script is run to move all verification cases and verification files to the target file path, thereby generating a verification environment, so that verification of chip registers can be performed.

[0079] In an embodiment of the present disclosure, in response to a verification instruction, a module to be verified can be obtained, such as a module to be verified, and all registers corresponding to the module to be verified are taken as registers to be verified; it can be understood that each register to be verified has a corresponding verification case, so after determining the register to be verified, the target verification case of the register to be verified can be determined, that is, the target verification case refers to the verification case corresponding to the register to be verified.

[0080] Furthermore, the module to be verified can write data to the address of the register to be verified according to the target verification case, and then obtain the data of the register address through the target verification case and send it to the target memory, such as an idle SRAM memory of the chip, and send it to the monitoring module through the interactive function.

[0081] Furthermore, the monitoring module can obtain data from the target memory through the interactive function. If the obtained data is zero, it will fall into an infinite loop and will continue to obtain data from the target memory. If the obtained data is not zero, the target verification use case will continue to execute. Each time the value of a register to be verified of a module is obtained, the value will be printed out until all registers of this module are covered. A verification flag is generated according to the obtained data, and the verification flag is sent to the scoreboard module based on the event module. The scoreboard module compares the verification flag sent by the monitoring module with the real flag sent by the reference model module to generate a verification result for the register to be verified.

[0082] Furthermore, the scoreboard module generates a verification result of the register to be verified based on the comparison between the verification mark and the real mark sent by the monitoring module. That is to say, if the verification mark and the real mark are the same, it means that the reading and writing functions of the register to be verified are normal and no processing is required. If the verification mark and the real mark are different, it means that the reading and writing functions of the register to be verified are abnormal, and further correction and troubleshooting can be performed to further improve the chip utilization efficiency.

[0083] As an example scenario, Figure 4 As shown, it includes step 4.1 installing the update library; step 4.2 filling in the form file; step 4.3 running the register script; step 4.4 running the move script, generating a verification environment, and running verification.

[0084] Specifically, Figure 5 As shown, the register table information "register.xlsx" is read through the script "practic.py" to generate C programs and various modules. The script first reads the information in the register table to generate C programs (verification use cases) and verification .sv files. Different C programs are generated according to the different register attributes of all modules of the chip. Each C program corresponds to a verification use case. The C program burned into the DUT (module to be verified) will interact with the rx_monitor module (monitoring module). The verification is mainly performed through this interactive function. First, the DUT writes or reads a data to the corresponding module register address through the C program, and then sends the data of the register for write or read operations to an SRAM address through the C program and sends it to the Rx_monitor module through the interactive function "word_to_sv". In the Rx_monitor module, the interactive function "word_from_c" is used to obtain the data in the SRAM address. If the data obtained is zero, it will fall into an infinite loop and will continue to obtain the data at this SRAM address. If the data obtained is not zero, the C program will continue to execute, and the value of each module register will be printed out until all registers of this module are covered.

[0085] The Refer_model module (reference model module) is also automatically generated by the script. The rx_monitor module and the Refer_model module will put the verification flag and the real flag into the scoreboard module (scoreboard module) for comparison. The real flag of the Refer_model module is generated by the script itself. The verification flag in the rx_monitor module is obtained by comparing the data given by the C program with the value actually read from the module's register. If the two values ​​are the same, the verification flag variable will be the correct value, otherwise the verification flag will be set to zero. The printed information can quickly help locate which register has a problem, so as to correct and debug it. Among them, the rx_monitor module and the Refer_model module can transmit signals through the transaction module.

[0086] It is understandable that if the module read and write functions are normal, then the data obtained by the monitoring module is the same as the data written by the C program. If the module register read and write functions are abnormal, then the data originally placed in the free SRAM memory will be different and may be 0 or other values. In the monitoring module, because different verification flags are detected, such as set to zero, the scoreboard module fails to compare the verification flag determined by the monitoring module with the real flag in the reference model module. In addition, the verification of register reset value, erase and other functions are also written by C program first, or read by C program. By setting the design document, it is determined which module register reset value is what, and which register data is erased. Finally, the data is read out and sent to the monitoring module through the interactive function for final comparison.

[0087] It should be noted that Figure 5 Some unnecessary modules are omitted to make the verification diagram direct and clear. Some cumbersome interface modules, driver modules, sequencer modules, etc. are not used. The modules that need to be modified are completely generated by scripts. Running the move script will replace the files in the verification environment, and there is no need to manually modify the program.

[0088] As a result, test cases and verification environments can be generated in one click, which is fast, convenient, and iterative. All registers in all modules of the chip can be fully covered. No professional electronic equipment is required for software and hardware interaction, which is low cost. It has strong reusability and can be applied to multiple different projects at the same time. Register read and write verification can be performed at the beginning of the project, which can find problems more quickly. It saves time and labor costs, generates verification cases and verification environments in one click, and performs full coverage read and write verification on the registers of the entire chip.

[0089] Figure 6 This is a schematic diagram of the structure of a chip register verification device provided by an embodiment of the present disclosure. The device can be implemented by software and / or hardware and can generally be integrated into an electronic device. Figure 6 As shown, the device comprises:

[0090] A response module 601 is used to determine a target verification case of a register to be verified in response to a verification instruction;

[0091] The module to be verified 602 is used to obtain data from the address of the register to be verified based on the target verification case and send it to the target memory through an interactive function;

[0092] The monitoring module 603 is used to obtain data from the target memory based on the interactive function, print all read and write data of the register to be verified, generate a verification mark according to the obtained data, and send the verification mark to the scoreboard module based on the event module;

[0093] The scoreboard module 604 is used to generate a verification result of the register to be verified based on the comparison between the verification flag and the real flag sent by the reference model module.

[0094] Optionally, the device further includes:

[0095] A generation module, used to generate all verification cases and verification files by reading register table information through a script; wherein the verification file includes the monitoring module, the event module, the reference model module and the scoreboard module;

[0096] A storage module is used to store all the verification use cases in the module to be verified.

[0097] Optionally, the generating module includes:

[0098] A first acquisition unit, configured to acquire a worksheet name based on the register table information;

[0099] A second acquisition unit is used to read the work table corresponding to the work table name according to a preset reading order to obtain register information;

[0100] A generating unit is used to generate all the verification use cases based on the register information.

[0101] Optionally, the generating unit is specifically used to:

[0102] determining a register attribute based on the register information;

[0103] Generate an application corresponding to each of the register attributes to obtain all the verification use cases.

[0104] Optionally, the generating module further includes:

[0105] a third acquiring unit, configured to acquire a register table name based on the register table information;

[0106] A setting unit is used to set the register table name as a verification environment name.

[0107] Optionally, the device further comprises:

[0108] Installation module for installing databases for processing table files.

[0109] Optionally, the device further comprises:

[0110] The moving module is used to run the moving script to move all the verification cases and the verification files to the target file path and generate a verification environment.

[0111] The chip register verification device provided in the embodiments of the present disclosure can execute the chip register verification method provided in any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0112] An embodiment of the present disclosure further provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the chip register verification method provided by any embodiment of the present disclosure.

[0113] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0114] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (Hyper Text Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0115] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0116] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0117] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0118] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0119] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0120] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0121] According to one or more embodiments of the present disclosure, the present disclosure provides an electronic device, including:

[0122] processor;

[0123] a memory for storing instructions executable by the processor;

[0124] The processor is used to read the executable instructions from the memory and execute the instructions to implement any chip register verification method provided in the present disclosure.

[0125] According to one or more embodiments of the present disclosure, the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute any chip register verification method as provided in the present disclosure.

[0126] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0127] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0128] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A chip register verification method, characterized in that: The method comprises: In response to the verification instruction, determining a target verification case of the register to be verified; The module to be verified obtains the data interaction function from the address of the register to be verified based on the target verification case and sends it to the target memory; The monitoring module obtains data from the target memory based on the interactive function, prints all read and write data of the register to be verified, generates a verification mark according to the obtained data, and sends the verification mark to the scoreboard module based on the event module; The scoreboard module compares the verification flag with the real flag sent by the reference model module to generate a verification result of the register to be verified.

2. The chip register verification method according to claim 1, characterized in that: The method further comprises: Generate all verification cases and verification files by reading register table information through script; wherein the verification file includes the monitoring module, the event module, the reference model module and the scoreboard module; All the verification cases are stored in the module to be verified.

3. The chip register verification method according to claim 2, characterized in that: The script reads the register table information to generate all verification cases, including: Acquire a worksheet name based on the register table information; The worksheet corresponding to the worksheet name is read in a preset reading order to obtain register information, and all the verification use cases are generated based on the register information.

4. The chip register verification method according to claim 3, characterized in that: The generating all the verification cases based on the register information includes: determining a register attribute based on the register information; Generate an application corresponding to each of the register attributes to obtain all the verification use cases.

5. The chip register verification method according to claim 3, characterized in that: The method further comprises: acquiring a register table name based on the register table information; Set the register table name to the verification environment name.

6. The chip register verification method according to claim 2, characterized in that: Before running the script, the method further includes: Install the database for working with table files.

7. The chip register verification method according to claim 2, further comprising: Run the move script to move all the verification cases and the verification files to the target file path and generate a verification environment.

8. A chip register verification device, characterized in that: include: A response module, configured to determine a target verification case of a register to be verified in response to a verification instruction; A module to be verified, used for obtaining data from the address of the register to be verified based on the target verification case and sending it to the target memory for sending through an interactive function; A monitoring module, used for acquiring data from the target memory based on an interactive function, and printing all read and write data of the register to be verified, generating a verification mark according to the acquired data, and sending the verification mark to a scoreboard module based on an event module; The scoreboard module is used to generate a verification result of the register to be verified based on the comparison between the verification flag and the real flag sent by the reference model module.

9. An electronic device, characterized in that: The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the chip register verification method described in any one of claims 1-7 above.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and the computer program is used to execute the chip register verification method described in claims 1-7 above.

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