Acceleration interrupt-driven real-time system time sequence verification method based on Parcel framework
Through the Parcel framework-based method, the interrupt-driven real-time system model is abstracted, eliminated and optimized, which solves the problem of inefficient verification caused by state space explosion in the existing technology, and achieves fast and accurate timing verification.
Patent Information
- Application Number
- CN202411484578.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-04-25
AI Technical Summary
When existing model detection tools deal with interrupt-driven real-time system timing models, the status space explosion leads to long verification time, high memory consumption, low efficiency and even fail to verify.
Using a Parcel framework-based method, the interrupt-driven real-time system model is abstracted, the unobservable Parcel fragments are eliminated, and the timing model is optimized through time zone truncation and Parcel sequence pruning technology is used to reduce the verification path and calculation complexity.
Through Parcel decomposition and optimization technology, the exploration of state space is reduced, verification speed is improved, and the accuracy of timing verification is ensured. It is suitable for timing verification of large-scale interrupts driven real-time systems.
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Figure CN119883854A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of model verification, and in particular to a timing verification method for an accelerated interrupt-driven real-time system based on a Parcel framework. Background Art
[0002] The mainstream methods currently used to verify the timing requirements of real-time systems are model checking and formal verification techniques. These methods verify timing properties by building models such as interrupt timed automata (IA) or sequence diagrams (SD). However, as the scale of the system increases, these methods face the problem of state space explosion, that is, the number of possible states and time sequences in the model increases dramatically, resulting in excessive verification time and even exceeding the limitations of computing resources. Model checking technology systematically checks the timing specifications under all possible states, but the frequent interrupts and complex interleaving behaviors in real-time systems cause the state space to expand rapidly, significantly increasing the verification complexity and computational cost. For example, the existing tool ISDChecker takes 2751 seconds to verify a model containing 13 messages and 9 timing properties, and when the number of messages increases to 46, the tool even has an out of memory error. In addition, although the SMT (Satisfiability Modulo Theories) solver based on symbolic computing and logical reasoning can exhaust all possible event sequences when verifying systems involving explicit clock constraints, it is still computationally inefficient when dealing with interrupt behaviors and timing variables, which can easily lead to long verification time or memory exhaustion.
[0003] The key challenges faced by these verification tools are: state space explosion. The interleaved behaviors in interrupt-driven systems generate a large number of event sequences, which are difficult for existing tools to deal with effectively, and the computational workload and time of the verification process have increased significantly; low verification efficiency. When dealing with systems with frequent and random interrupts, the SMT solver is inefficient in processing timing variables and is difficult to adapt to actual engineering needs; insufficient memory and computational timeouts. When the number of messages and timing fragments in the system increases, the tool may run out of memory or time out, resulting in the inability to complete verification. Although some studies have attempted to reduce state space and computational time, these methods have limited effectiveness when dealing with complex timing requirements in interrupt-driven systems. Summary of the invention
[0004] Purpose of the invention: The purpose of the present invention is to provide a method for accelerating interrupt-driven real-time system timing verification based on the Parcel framework, so as to solve the problem that when traditional model checking tools such as ISDChecker process timing models containing interrupts, the verification process is inefficient or even fails due to state space explosion, long verification time and large memory consumption.
[0005] Technical solution: The method for accelerating interrupt-driven real-time system timing verification based on the Parcel framework of the present invention comprises the following steps:
[0006] (1) Perform Parcel abstraction on the timing segments in the interrupt-driven real-time system model and generate Parcel units;
[0007] (2) Parcel elimination techniques are used to remove unobservable Parcel segments during the verification process;
[0008] (3) Through the time zone truncation technology, the timing segments in the timing model are optimized to reduce the verification path;
[0009] (4) Execute Parcel sequence pruning technology to prune unnecessary timing segments based on the reachability and importance of the Parcel sequence;
[0010] (5) Input the optimized model into the verification tool to verify the timing specifications.
[0011] Furthermore, step (1) is specifically as follows: abstracting the timing segments of the interrupt-driven system model into Parcel units; each Parcel corresponds to an event or multiple closely related event sequences.
[0012] Furthermore, step (2) is as follows: by analyzing the behavioral characteristics of each Parcel, determine whether it will affect the timing properties during the verification process; if some Parcels do not affect the timing properties, remove them from the verification path.
[0013] Furthermore, step (3) is specifically as follows: by analyzing the time series segments, determine which time intervals are critical to the verification results and which time segments can be ignored; then, only the time series segments in the important time zones are processed during the verification process, and the rest will be truncated.
[0014] Furthermore, step (4) is as follows: by analyzing the reachability of the Parcel sequence, determine which Parcels are necessary in the verification process of a specific timing attribute; then, prune the Parcel sequences that have no impact on the verification results.
[0015] Furthermore, step (5) is specifically as follows: the verification tool uses formal verification technology to check the timing specifications of the system based on the optimized timing model; the tool compares the time attributes in the verification model with the predefined timing requirements to ensure that the timing behavior of the system meets the real-time requirements.
[0016] Further, formal verification techniques include: model checking or SMT solvers
[0017] The present invention discloses a Parcel framework-based accelerated interrupt-driven real-time system timing verification system, comprising:
[0018] Parcel abstraction module: used to perform Parcel abstraction on interrupt-driven real-time system models;
[0019] Parcel elimination module: used to remove unobservable Parcel fragments during the verification process;
[0020] Time zone truncation module: used to divide and optimize the Parcel sequence within the time zone;
[0021] Parcel sequence pruning module: used to prune unnecessary Parcel segments during the verification process to improve verification efficiency;
[0022] Verification execution module: used to execute the optimized model and verify the timing specifications.
[0023] An electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, any one of the methods for accelerating interrupt-driven real-time system timing verification based on the Parcel framework is implemented.
[0024] A storage medium described in the present invention stores a computer program, and when the computer program is executed by a processor, any one of the methods for accelerating interrupt-driven real-time system timing verification based on a Parcel framework is implemented.
[0025] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: by Parcel decomposing the timing model of the interrupt-driven system, the exploration of the state space is reduced while ensuring the accuracy of the timing verification; the verification speed is improved, which is particularly suitable for the timing verification of large-scale interrupt-driven real-time systems. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a flow chart of the present invention;
[0027] Figure 2 An example diagram for modeling the present invention;
[0028] Figure 3 It is an exemplary diagram of the modularization of the present invention;
[0029] Figure 4 This is an example diagram of modularization of different fragments of the present invention.
[0030] Figure 5This is an example diagram of the time zone division of the present invention. DETAILED DESCRIPTION
[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.
[0032] Module or modularity used in the invention is synonymous with Parcel, which means that the interrupt model such as Figure 2 Some parts of the diagram are modularized into a whole, called Parcel, and the final effect is as follows Figure 3 .
[0033] like Figure 1 As shown, an embodiment of the present invention provides a method for accelerating interrupt-driven real-time system timing verification based on a Parcel framework, comprising the following steps:
[0034] S1. Obtain the input interrupt-driven real-time system model. The model can be represented by a UML sequence diagram or an interrupt sequence diagram (ISD). Figure 2 . The following steps are included:
[0035] S11. Model parsing: Parse the input model and identify the basic events and messages therein.
[0036] S12, Parcel generation: According to the timing fragments in the model, they are grouped into Parcel units. Each Parcel unit contains related events and corresponding timing constraints. Figure 4
[0037] S13, priority marking: Assign a priority to each Parcel unit to determine whether it can be interrupted by other Parcels in subsequent processing.
[0038] The syntax of the Interrupt Sequence Diagram (ISD) is represented as a four-tuple Among them: F is a non-interruption segment, which represents the system behavior when there is no interruption; is a finite set of interrupt fragments, representing various interrupt behaviors in the system. C is a finite set of timing specifications, representing the constraints in ISD; Ψ is a finite set of timing specifications, representing the properties of ISD. For a Parcel grammar, P = (p, B, C L ,Ψ L ), p represents the priority of Parcel; B is a basic fragment, which represents the core behavior or function of Parcel; C L is a finite set of timing specifications, representing the local constraints of Parcel; LIt is a finite set of timing specifications that represent the local properties of a Parcel. A Parcel describes a specific behavioral unit in the system by defining priorities, behavior fragments, initial and terminal events, and local timing constraints and properties.
[0039] S2. Analyze each Parcel unit to determine its impact on the verification results. This includes the following steps:
[0040] S21. Behavior analysis: Check whether the behavior of each Parcel is observable.
[0041] S22, Elimination strategy: For unobservable Parcels, directly delete them from the verification path to reduce the state space.
[0042] During modular construction, we often encounter components that lack timing specifications. This lack of information introduces uncertainty and complicates model definition. Specifically, when building a Parcel using basic fragments, if local specifications are not assigned, the Parcel will be excluded from the final Parcel graph. We give the following proof:
[0043] Let <Σ, <> be a partially ordered set. When verifying the temporal property Ψ of <Σ, <>, the following proposition holds:
[0044]
[0045] Consider the event sequence w = (e1 → e2 → ... → e n ), the sequence has no timing specification. For any adjacent events, the partial order relation < is satisfied, which simply specifies the order in which the events occur. Due to the lack of timing specification, the interval δ between events remains unspecified, so δ∈(0,∞). Therefore, for any Using the transitivity of partial order relations, δ(e i ,e j )=δ(e i ,e i+1 )+…+δ(e j-1 ,e j ). Therefore, w=δ(e1,e n ) expands to Σ - , that is, the aforementioned subset of events that lacks temporal specification, for any sequence t∈trace(<Σ - ,<>, with interval t=δ(x,y). Therefore, assuming that the timing specification is unknown, x and y can effectively represent Σ - This allows any interval between events to take on any value, representing a different point in time.
[0046] S3. Optimize the timing model and improve the verification efficiency by dividing the time interval. This includes the following steps: Figure 5 :
[0047] S31. Time division: Divide the time series model into multiple time zones and only operate on the time zones that need to be verified.
[0048] S32, path pruning: pruning the timing paths that are not in the valid time zone to avoid useless calculations.
[0049] S4, reducing computational complexity by identifying and deleting unnecessary Parcel sequences; comprising the following steps:
[0050] S41, Sequence Analysis: Analyze the accessibility and importance of Parcel sequences, and identify which sequences are insignificant to the final verification results.
[0051] S42, pruning operation: prune unnecessary Parcel sequences to ensure that only sequences that affect verification are retained.
[0052] Step S5, the system enters the verification phase, and uses formal verification tools to verify the timing specifications of the optimized model. The following steps are included:
[0053] S51. Input optimized model: Input the optimized Parcel model into the verification tool.
[0054] S52. Perform verification: The verification tool checks the model according to the timing specification to ensure that the timing behavior of the system meets the design requirements.
[0055] S53. Result output: Output the verification result, including the success or failure status and related error information (if any).
[0056] The invention discloses an accelerated interrupt-driven real-time system timing verification system based on a Parcel framework, comprising:
[0057] Parcel abstraction module: used to perform Parcel abstraction on interrupt-driven real-time system models;
[0058] Parcel elimination module: used to remove unobservable Parcel fragments during the verification process;
[0059] Time zone truncation module: used to divide and optimize the Parcel sequence within the time zone;
[0060] Parcel sequence pruning module: used to prune unnecessary Parcel segments during the verification process to improve verification efficiency;
[0061] Verification execution module: used to execute the optimized model and verify the timing specifications.
[0062] An electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, any one of the methods for accelerating interrupt-driven real-time system timing verification based on the Parcel framework is implemented.
[0063] A storage medium described in the present invention stores a computer program, and when the computer program is executed by a processor, any one of the methods for accelerating interrupt-driven real-time system timing verification based on a Parcel framework is implemented.
Claims
1. A method for accelerating interrupt-driven real-time system timing verification based on Parcel framework, characterized in that: The following steps are involved: (1) Perform Parcel abstraction on the timing segments in the interrupt-driven real-time system model and generate Parcel units; (2) Parcel elimination techniques are used to remove unobservable Parcel segments during the verification process; (3) Through the time zone truncation technology, the timing segments in the timing model are optimized to reduce the verification path; (4) Execute Parcel sequence pruning technology to prune unnecessary timing segments based on the reachability and importance of the Parcel sequence; (5) Input the optimized model into the verification tool to verify the timing specifications.
2. According to the method of claim 1, the method is characterized in that: Step (1) is as follows: abstract the timing segments of the interrupt-driven system model into Parcel units; each Parcel corresponds to an event or multiple closely related event sequences.
3. According to the method of claim 1, the method is characterized in that: Step (2) is as follows: By analyzing the behavioral characteristics of each Parcel, determine whether it will affect the timing properties during the verification process; if some Parcels do not affect the timing properties, remove them from the verification path.
4. According to the method of claim 1, the method is characterized in that: Step (3) is as follows: by analyzing the time segments, determine which time intervals are critical to the verification results and which time segments can be ignored; then, during the verification process, only the time segments within the important time zones are processed, and the rest will be truncated.
5. According to the method of claim 1, the method is characterized in that: Step (4) is as follows: by analyzing the reachability of the Parcel sequence, determine which Parcels are necessary in the verification process of specific timing properties; then, prune the Parcel sequences that have no impact on the verification results.
6. According to the method of claim 1, the method is characterized in that: Step (5) is as follows: the verification tool uses formal verification technology to check the timing specifications of the system based on the optimized timing model; the tool compares the time attributes in the verification model with the predefined timing requirements to ensure that the timing behavior of the system meets the real-time requirements.
7. The method for accelerating interrupt-driven real-time system timing verification based on Parcel framework according to claim 6 is characterized in that: Formal verification techniques include: model checking or SMT solvers.
8. An accelerated interrupt-driven real-time system timing verification system based on the Parcel framework, characterized in that: include: Parcel abstraction module: used to perform Parcel abstraction on interrupt-driven real-time system models; Parcel elimination module: used to remove unobservable Parcel fragments during the verification process; Time zone truncation module: used to divide and optimize the Parcel sequence within the time zone; Parcel sequence pruning module: used to prune unnecessary Parcel segments during the verification process to improve verification efficiency; Verification execution module: used to execute the optimized model and verify the timing specifications.
9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is loaded into the processor, the method for accelerating interrupt-driven real-time system timing verification based on the Parcel framework according to any one of claims 1 to 7 is implemented.
10. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, a method for accelerating interrupt-driven real-time system timing verification based on a Parcel framework according to any one of claims 1 to 7 is implemented.