Signal processing system, data transmission method, equipment and medium

Abstract

The invention relates to the technical field of signal processing, in particular to a signal processing system, a data transmission method, data transmission equipment and a medium, through the method provided by the invention, the method mainly comprises the following steps that: an operation DSP (Digital Signal Processor) group receives data required to be processed by the signal processing system through an input data interface; processing the data according to actual algorithm requirements to obtain a final result; and the algorithm result is transmitted to the master control DSP through a high-speed transmission link in the signal processing board, and the master control DSP sorts, classifies, packs and uniformly uploads the algorithm result to the final result output module through a control interface. According to the invention, the processing chip type of the signal processor is planned through working groups divided by different groups and different functions. And efficient sending and receiving processes are set. And high-performance information transmission is realized.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a signal processing system and a data transmission method, device and medium. Background Art

[0002] Signal processing is the process of processing, analyzing and interpreting signals, and is widely used in communications, audio, image processing and other fields. It includes digital signal processing (DSP), filter design, Fourier transform, signal sampling and quantization, and image processing algorithms. These technologies make signals easier to store, transmit and analyze, thereby improving the performance of multimedia and communication systems. With the development of machine learning and artificial intelligence, signal processing technology is also continuing to evolve, driving the development of smart devices and automated systems.

[0003] In the traditional signal processing field, data information interaction and aggregation rely on the operating system for scheduling and maintenance. The information integration method based on the operating system ensures a low bit error rate of information, but it is only suitable for scenarios with low real-time performance requirements. Summary of the invention

[0004] The purpose of the present invention is to provide a signal processing system and a data transmission method, device and medium to solve the above problems in the prior art.

[0005] The present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a data transmission method of a signal processing system, including core 0 and core 1 of a master control DSP:

[0007] Obtain result information sent by the operation DSP group, the core 1 reads the additional number in the result information, and determines the source of the result information through the additional number;

[0008] A storage space is set in a storage unit shared by multiple cores through the master control DSP, and a group of queues are set in the storage space, and the queues are used to store result information;

[0009] The core 1 stores the result to the corresponding position of the queue according to the information of the additional number, and the corresponding position is used for the user to allocate according to actual needs;

[0010] The core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue. If not, the core 1 continues to receive the result information from the operation DSP group. If yes, the core 0 is notified to read the queue information through the IPC inter-core interrupt.

[0011] After core 0 reads the queue information, it filters and processes the data that needs to be uploaded to the control module host computer and reassembles it into a new data structure;

[0012] Core 0 uploads the result information to the upper computer module that finally reads the data information through the network port;

[0013] After core 0 sends the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again.

[0014] Preferably, the main control DSP receives result information sent by the operation DSP group through a communication interface in the signal processing board.

[0015] Preferably, both core 0 and core 1 can access the queue, core 0 only has read permission for the queue, and core 1 only has write permission for the queue.

[0016] Preferably, the command issuing process is also included, including:

[0017] The master control DSP receives control commands from the control interface through the network port external interface;

[0018] The master control DSP reorganizes command instructions suitable for different DSPs according to the control command;

[0019] The master DSP sends commands to each DSP through the communication interface in the signal processing board.

[0020] Preferably, the master control DSP is used for external communication and normal operation of the control process.

[0021] In a second aspect, the present invention further provides a signal processing system, comprising:

[0022] The information acquisition module is configured as core 0 and core 1 of the main control DSP, obtains the result information sent by the operation DSP group, and the core 1 reads the additional number in the result information and determines the source of the result information through the additional number; the main control DSP sets a storage space in a storage unit shared by multiple cores, and a group of queues are set in the storage space, and the queues are used to store the result information;

[0023] The processing module is configured such that the core 1 stores the result in the corresponding position of the queue according to the information of the additional number, and the corresponding position is used for the user to allocate according to the actual needs; the core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue, if not, the core 1 continues to receive the result information from the operation DSP group, if yes, notifies the core 0 to read the queue information through the IPC inter-core interrupt; after reading the queue information, the core 0 screens and processes the data that needs to be uploaded to the control module host computer, and recombines it into a new data structure;

[0024] The upload module is configured so that core 0 uploads the result information to the upper computer module that finally reads the data information through the network port; after core 0 sends the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again;

[0025] The main control module, together with the information acquisition module, the processing module and the uploading module, is used to execute the above-mentioned data transmission method of the signal processing system.

[0026] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned data transmission method of a signal processing system when executing the computer program.

[0027] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the data transmission method of a signal processing system described above is implemented.

[0028] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0029] The above method provided by the present invention mainly includes that the operation DSP group receives the data required to be processed by the signal processing system through the input data interface; according to the actual algorithm requirements, the data is processed to obtain the final result; and the algorithm result is transmitted to the main control DSP through the high-speed transmission link in the signal processing board, and the main control DSP organizes and classifies the algorithm results, packages them and uploads them to the final result output module through the control interface. The present invention plans the processing chip type of the signal processor through different groups and working groups divided by different functions. Set up efficient sending and receiving processes. Realize high-performance information transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a system framework diagram of the present invention;

[0032] Figure 2 A flowchart of the master control DSP group implementing the result information uploading process of the present invention;

[0033] Figure 3The present invention is a flowchart of the master control DSP group implementing the command issuing process. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0035] The division of modules in this application is a logical division. There may be other division methods when implemented in actual applications. For example, multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0036] The modules or submodules described independently may be physically separated or not: they may be implemented by software or hardware, and some modules or submodules may be implemented by software, and the processor may call the software to implement the functions of these modules or submodules, and other modules or submodules may be implemented by hardware, such as by hardware circuits. In addition, some or all of the modules may be selected according to actual needs to achieve the purpose of the present application.

[0037] Please refer to Figure 1-Figure 3 , the present invention provides a data transmission method for a signal processing system.

[0038] In this embodiment, the hardware device used in the present invention is a multi-core DSP TMS320C6678 produced by TI. TMS320C6678 is an 8-core DSP processor of KeyStone architecture, and the frequency of each CorePac core is up to 1.25GHz, providing powerful fixed-point and floating-point computing capabilities. At the same time, the chip integrates peripherals such as Multi core Navigator, Rapid IO, Gigabit Ethernet and EDMA. Due to the strong processing capability of the chip, rich peripheral functions, and a large number of hardware accelerators such as Packet Accelerator and Multi core Navigator integrated in the chip, it can be widely used in the fields of communication, radar, sonar, fire control, electronic countermeasures, etc.

[0039] The entire hardware system architecture is shown in Figure 1The whole system is divided into two parts: the operation DSP group and the main control DSP. The operation DSP group is responsible for the algorithm processing module of the whole system, and the main control DSP is responsible for external communication and controlling the normal operation of the whole process. The operation DSP group can increase or decrease the number of DSPs according to the actual computing power requirements, that is, the actual needs of engineering. The communication process is divided into the result information upload process and the command instruction downlink process

[0040] Includes core 0 and core 1 of the main control DSP, where core 0 is the main core or control core, responsible for executing the main control logic and system management tasks. For example, it may be responsible for operating system scheduling, task allocation, and resource management. This core usually runs at a higher frequency to quickly respond to real-time tasks.

[0041] Core 1: Auxiliary core or data processing core, dedicated to performing complex signal processing operations and data processing tasks, such as filtering, transformation and calculation. The design of this core may pay more attention to parallel processing capabilities to improve computing efficiency.

[0042] By assigning different tasks to different cores, the master DSP can achieve higher performance and response speed, making it more efficient in real-time processing and complex calculations. This multi-core architecture is widely used in communications, audio processing, video processing, and embedded systems.

[0043] S101: Obtaining result information sent by the operation DSP group, the core 1 reads the additional number in the result information, and determines the source of the result information through the additional number;

[0044] This step is completed by core 1 of the master DSP to determine which computing DSP the result information comes from. The result information usually includes:

[0045] Processing result data: The output generated after the DSP executes a specific algorithm, such as a filtered signal, a transformed spectrum data, or a demodulated signal.

[0046] Status information: system operation status information, such as current processing progress, operation errors, normal operation instructions, etc.

[0047] Control signal: A control signal used to regulate and configure the system, such as starting and stopping processing, adjusting parameters, etc.

[0048] Clock and synchronization information: In a multi-core system, clock signals and synchronization information may be included to ensure coordination and data consistency between the various processing cores.

[0049] This information is transmitted to other system components or external devices through specified communication protocols (such as serial ports, Ethernet, SPI, etc.) for further processing or monitoring. This information transfer is usually critical for real-time processing systems to ensure that the various parts of the system can work together effectively.

[0050] S102: Setting a storage space in a storage unit shared by multiple cores through the master control DSP, wherein a group of queues are set in the storage space, and the queues are used to store result information;

[0051] S103: the core 1 stores the result in a corresponding position of the queue according to the information of the additional number, and the corresponding position is used for allocation by the user according to actual needs;

[0052] S104: the core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue. If not, the core 1 continues to receive the result information from the operation DSP group. If yes, the core 0 is notified to read the queue information through the IPC inter-core interrupt.

[0053] Among them, inter-core interrupts provide an effective communication mechanism that allows each processing core to send interrupt signals to each other to achieve synchronization and coordination, such as direct interrupts, shared memory, message queues, external interrupt controllers, etc.

[0054] S105: After core 0 reads the queue information, it filters and processes the data that needs to be uploaded to the control module host computer and reassembles it into a new data structure;

[0055] Among them, after core 0 reads the queue information, it can also perform secondary processing, for example, data parsing: the data read from the queue may be stored in a specific format, so it needs to be parsed first to extract useful information. Data cleaning: this stage may remove redundant, repeated or incomplete data to ensure the quality of data for subsequent processing. Data conversion: converting raw data into a format that is more suitable for further analysis or processing, such as through standardization, normalization, encoding, etc.

[0056] S106: Core 0 uploads the result information to the upper computer module that finally reads the data information through the network port;

[0057] S107: After core 0 has sent the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again.

[0058] The above method provided by the present invention mainly includes that the operation DSP group receives the data that needs to be processed by the signal processing system through the input data interface; processes the data according to the actual algorithm requirements to obtain the final result; and transmits the algorithm result to the main control DSP through the high-speed transmission link in the signal processing board. The main control DSP organizes and classifies the algorithm results, packages them and uploads them to the final result output module through the control interface. The specific implementation steps of the command instruction downlink process are as follows: First, the upper computer control module sends the control instruction to the main control DSP group through the network port. The main control DSP group decomposes the control command according to the actual workflow, and recombines it into commands suitable for DSPs with different numbers in the operation DSP group. Finally, the commands are distributed to different DSPs.

[0059] The present invention plans the processing chip type of the signal processor through different groups and working groups divided by different functions, sets up efficient sending and receiving processes, and realizes high-performance information transmission.

[0060] In an exemplary embodiment of the present invention, the main control DSP receives result information sent by the operation DSP group through a communication interface within the signal processing board.

[0061] Specifically, both core 0 and core 1 can access the queue, core 0 only has read permission for the queue, and core 1 only has write permission for the queue.

[0062] An exemplary implementation of the present invention further includes a command issuing process, including:

[0063] The master control DSP receives control commands from the control interface through the network port external interface;

[0064] The master control DSP reorganizes command instructions suitable for different DSPs according to the control command;

[0065] The master DSP sends commands to each DSP through the communication interface (SRIO / HyperLink, etc.) within the signal processing board.

[0066] The master DSP is used for external communication and normal operation of the control process.

[0067] In a second aspect, the present invention further provides a signal processing system, comprising:

[0068] The information acquisition module is configured as core 0 and core 1 of the main control DSP, obtains the result information sent by the operation DSP group, and the core 1 reads the additional number in the result information and determines the source of the result information through the additional number; the main control DSP sets a storage space in a storage unit shared by multiple cores, and a group of queues are set in the storage space, and the queues are used to store the result information;

[0069] The processing module is configured such that the core 1 stores the result in the corresponding position of the queue according to the information of the additional number, and the corresponding position is used for the user to allocate according to the actual needs; the core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue, if not, the core 1 continues to receive the result information from the operation DSP group, if yes, notifies the core 0 to read the queue information through the IPC inter-core interrupt; after reading the queue information, the core 0 screens and processes the data that needs to be uploaded to the control module host computer, and recombines it into a new data structure;

[0070] The upload module is configured so that core 0 uploads the result information to the upper computer module that finally reads the data information through the network port; after core 0 sends the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again;

[0071] The main control module, together with the information acquisition module, the processing module and the uploading module, is used to execute the above-mentioned data transmission method of the signal processing system.

[0072] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0073] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-On l yMemory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0074] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data transmission method of a signal processing system, characterized in that: Including core 0 and core 1 of the main control DSP: Obtain result information sent by the operation DSP group, the core 1 reads the additional number in the result information, and determines the source of the result information through the additional number; A storage space is set in a storage unit shared by multiple cores through the master control DSP, and a group of queues are set in the storage space, and the queues are used to store result information; The core 1 stores the result to the corresponding position of the queue according to the information of the additional number, and the corresponding position is used for the user to allocate according to actual needs; The core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue. If not, the core 1 continues to receive the result information from the operation DSP group. If yes, the core 0 is notified to read the queue information through the IPC inter-core interrupt. After core 0 reads the queue information, it filters and processes the data that needs to be uploaded to the control module host computer and reassembles it into a new data structure; Core 0 uploads the result information to the upper computer module that finally reads the data information through the network port; After core 0 sends the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again.

2. The data transmission method of a signal processing system according to claim 1, characterized in that: The main control DSP receives the result information sent by the operation DSP group through the communication interface in the signal processing board.

3. The data transmission method of a signal processing system according to claim 2, characterized in that: Both core 0 and core 1 can access the queue, core 0 only has read permission for the queue, and core 1 only has write permission for the queue.

4. The data transmission method of a signal processing system according to claim 3, characterized in that: It also includes the command issuance process, including: The master control DSP receives control commands from the control interface through the network port external interface; The master control DSP reorganizes command instructions suitable for different DSPs according to the control command; The master DSP sends commands to each DSP through the communication interface in the signal processing board.

5. The data transmission method of a signal processing system according to claim 1, characterized in that: The master DSP is used for external communication and normal operation of the control process.

6. A signal processing system, characterized in that: include: The information acquisition module is configured as core 0 and core 1 of the main control DSP, obtains the result information sent by the operation DSP group, and the core 1 reads the additional number in the result information and determines the source of the result information through the additional number; the main control DSP sets a storage space in a storage unit shared by multiple cores, and a group of queues are set in the storage space, and the queues are used to store the result information; The processing module is configured such that the core 1 stores the result in the corresponding position of the queue according to the information of the additional number, and the corresponding position is used for the user to allocate according to the actual needs; the core 1 determines whether the result information of all the operation DSP groups has entered the queue according to the result information stored in the queue, if not, the core 1 continues to receive the result information from the operation DSP group, if yes, notifies the core 0 to read the queue information through the IPC inter-core interrupt; after reading the queue information, the core 0 screens and processes the data that needs to be uploaded to the control module host computer, and recombines it into a new data structure; The upload module is configured as core 0 to upload the result information to the upper computer module that finally reads the data information through the network port; After core 0 sends the result information, it resets the result information queue shared by core 0 and core 1, and notifies core 1 to start receiving new data from the starting position again; The main control module, together with the information acquisition module, the processing module and the uploading module, is used to execute the data transmission method of a signal processing system as described in any one of claims 1-5.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the data transmission method of the signal processing system according to any one of claims 1 to 5 is implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the data transmission method of a signal processing system according to any one of claims 1 to 5 is implemented.

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