Method and system for sequencing test vectors of digital integrated circuit
In the test of integrated circuits, the simulation test is carried out by using logic gate injection faults, and the contribution of the test vector is established to calculate the contribution of the test vectors, and the loading order of the test vectors is optimized according to the contribution degree, which solves the problems of long test time and low efficiency in integrated circuit tests, and achieves more efficient fault detection and testing cost savings.
Patent Information
- Application Number
- CN202411745687.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-04-25
AI Technical Summary
In the productivity test of integrated circuits, the test data is large and the test time is long, resulting in low testing costs and efficiency. The fixed sorting of existing test vectors leads to low fault detection efficiency.
By injecting faults into logic gates for simulation testing, the evaluation model is established to calculate the contribution degree of the test vector, and the loading order of the test vector is optimized according to the contribution degree to improve the test efficiency.
By optimizing the sorting and combination of test vectors, faulty integrated circuits can be hit earlier, saving test time and maximizing test cost.
Smart Images
Figure CN119885983A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit testing, and in particular to a digital integrated circuit test vector sorting method and system. Background Art
[0002] As the scale of integrated circuits continues to increase, the large amount of test data and long test time have become key issues affecting test costs and test efficiency. At present, in the production test of integrated circuits, the "stop at first failure" test rule is often adopted, that is, if the chip fails the test on a certain test item or test vector, then the subsequent test items or test vectors will no longer be tested. On the one hand, this can avoid unnecessary testing of faulty chips and reduce test time; on the other hand, it can reduce the intensity of use of test machines and extend the service life and cost of equipment. Therefore, adjusting the test order of test items or test vectors and testing test items or test vectors with stronger fault detection capabilities first can help detect faulty chips as early as possible and save test costs.
[0003] Usually, a fault in a digital integrated circuit corresponds to one or more test vectors, and a collection of test vectors that can cover all fault combinations is called a test set. For a digital integrated circuit to be tested, the loading order of the test vectors in an unoptimized test set is usually fixed. This leads to low test efficiency and too many vectors that do not contribute much to the fault during the test process.
[0004] In order to overcome these defects, the present application proposes a digital integrated circuit test vector sorting method and system. Summary of the invention
[0005] The purpose of this application is to provide a digital integrated circuit test vector sorting method and system to solve the above-mentioned problems.
[0006] To achieve the above objectives, this application provides the following technical solutions:
[0007] In a first aspect, the present application provides a digital integrated circuit test vector sorting method, the specific steps of which are:
[0008] Get the test vector set;
[0009] Injecting faults into logic gates to perform fault simulation, performing simulation tests according to test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors;
[0010] Establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model;
[0011] According to the contribution, the test vectors are sorted to obtain a test vector combination with the highest node coverage;
[0012] The node coverage of the test vector combination and the preset test vector combination is calculated, and a reordered test vector set is obtained according to the screened node coverage.
[0013] Further, the step of injecting faults into logic gates to perform fault simulation, performing simulation tests according to the test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors specifically includes the following steps:
[0014] Inject faults into each logic gate to perform fault simulation, and use the test vector sets V1, V2, V3...V in sequence. i ,…,V m The test vectors in the program are used for simulation testing, and the number of logic gates hit by the test vectors and the corresponding faulty gate types are counted.
[0015] Furthermore, the step of establishing an evaluation model based on the faulty gate type and the number of logic gates and calculating the contribution of the test vector by using the evaluation model specifically includes the following steps:
[0016] The calculation formula of the evaluation model is:
[0017]
[0018] Among them, M i is the test vector V i The number of logic gates corresponding to the covered nodes, N i is the number of transistors corresponding to each logic gate, C i is the vector V i The test contribution.
[0019] Furthermore, in the step of sorting the test vectors according to the contribution to obtain the test vector combination with the highest node coverage, the following steps are specifically included:
[0020] The contribution is calculated by the evaluation model to obtain the contribution C1, C2, C3, ..., C corresponding to the test vector. i , ..., C m ;
[0021] The test vector with the highest contribution is taken as the first test vector in the sorted test vector set, denoted as VC1;
[0022] Calculate the contribution of the first test vector and the preset test vector in pairs, and select the combination with the highest node coverage, which is recorded as (VC1, VC2);
[0023] Calculate the node coverage of the combination (VC1, VC2) and the remaining test vectors in the test vector set, and select the three test vector combinations with the highest node coverage (VC1, VC2, VC3).
[0024] Furthermore, the step of calculating the node coverage of the test vector combination and the preset test vector combination, and obtaining the reordered test vector set according to the screened node coverage, specifically includes the following steps:
[0025] Calculate the node coverage of the measurement vector combination (VC1, VC2, VC3) and the preset test vector combination;
[0026] The node coverage of the screened test vector combinations is counted to obtain the final reordered test vector set (VC1, VC2, VC3, ..., VC n ).
[0027] Furthermore, the coverage of the test vector is the ratio of the number of faults covered by the test vector set to the total number of circuit faults.
[0028] Furthermore, the probability of occurrence of the fault is:
[0029]
[0030] Where x is the random variable of the number of failures and λ is the average failure rate.
[0031] In the second aspect, the present application proposes a digital integrated circuit test vector sorting system, the specific contents of which include:
[0032] Acquisition module: obtain the test vector set;
[0033] Testing module: injecting faults into logic gates to perform fault simulation, performing simulation tests according to the test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors;
[0034] Evaluation module: establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model;
[0035] Sorting module: sorting the test vectors according to the contribution to obtain the test vector combination with the highest node coverage;
[0036] Output module: Calculate the node coverage of the test vector combination and the preset test vector combination, and obtain a reordered test vector set according to the screened node coverage.
[0037] In a third aspect, the present application provides a device, comprising a processor and a memory coupled to the processor, wherein the memory stores program instructions for implementing a digital integrated circuit test vector sorting method; and the processor is used to execute the program instructions stored in the memory to implement a digital integrated circuit test vector sorting.
[0038] In a fourth aspect, the present application provides a storage medium storing program instructions executable by a processor, wherein the program instructions are used to execute a digital integrated circuit test vector sorting method.
[0039] The present application provides a digital integrated circuit test vector sorting method and system, which has the following beneficial effects:
[0040] (1) By optimizing the order and combination of test vectors in the test vector set, test vectors with relatively high test performance are loaded first, and the faulty IC under test is hit earlier, thereby saving test time;
[0041] (2) According to the constraints of coverage and test cost, the optimal test item combination is selected from the sorted test vector list, and the test vectors at the end that contribute less to the test are discarded, thereby maximizing the test cost savings;
[0042] (3) This application embodies the characteristics of multi-feature fusion through a multi-dimensional test vector contribution evaluation method, further improving the automation and intelligence level of integrated circuit test solution optimization design;
[0043] (4) Using the test vector generation tool Tessent, the circuit’s test point coverage is increased based on DFT testability design. The generated test vectors ensure that the test coverage is above 98%, thereby improving the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 A flowchart of a digital integrated circuit test vector sorting method according to Embodiment 1 of the present application;
[0045] Figure 2 A schematic diagram of digital integrated circuit test vector sorting based on Example 1 of the present application;
[0046] Figure 3 A schematic diagram of predicting coverage of test vectors generated in Example 1 of the present application;
[0047] Figure 4 This is a schematic diagram of a circuit unit list of Embodiment 1 of the present application;
[0048] Figure 5A schematic diagram of the structure of a digital integrated circuit test vector sorting system according to Embodiment 2 of the present application;
[0049] Figure 6 This is a schematic diagram of the device structure of Example 3 of the present application;
[0050] Figure 7 This is a schematic diagram of the storage medium structure of Example 4 of the present application. DETAILED DESCRIPTION
[0051] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0052] The following is an analysis of the solutions in the prior art in combination with related technologies.
[0053] Currently, the test vectors generated by EDA tools are usually generated based on fixed rules and algorithms, and most of these generated test vectors aim to achieve a high fault coverage rate. The generated test sets contain many repetitive test vectors with low test performance. Such generated test vectors have low test efficiency in actual testing, which greatly increases the production test cost of the chip.
[0054] This application optimizes the order and combination of test vectors or test items in the test set based on the feature correlation of test vectors and test items, and prioritizes the loading of test vectors with relatively high test performance, and places test vectors or test items with less contribution to the test at the end of the priority list. On the one hand, the optimized and sorted test vector set can hit the faulty integrated circuit under test earlier, thereby saving test time; on the other hand, according to the constraints of coverage and test cost, the optimal test item combination is selected from the sorted test vector list.
[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0056] Example 1
[0057] See also Figure 1 , is a flow chart of a digital integrated circuit test vector sorting method according to Embodiment 1 of the present application; the steps include:
[0058] S1: Get a test vector set.
[0059] S2: injecting faults into logic gates to perform fault simulation, and performing simulation tests according to the test vectors in the test vector set to obtain the fault gate type and the number of logic gates corresponding to the test vectors.
[0060] In this embodiment, a fault is injected into each logic gate to perform fault simulation, and the test vector sets V1, V2, V3 ... V are used in sequence. i ,…,V m The test vectors in the program are used for simulation testing, and the number of logic gates hit by the test vectors and the corresponding faulty gate types are counted.
[0061] In terms of the probability of failure, ignoring obvious defects in the circuit design or serious problems in the manufacturing process, circuit failure has the following characteristics: circuit failure is a low-probability event; failures are relatively independent; and the failure rate is relatively stable. The probability of failure is:
[0062]
[0063] Where x is the random variable of the number of failures and λ is the average failure rate.
[0064] Therefore, it is believed that the event of circuit failure is approximately in line with the Poisson distribution. The larger the area of the integrated circuit, the greater the probability of failure. The larger the area of the logic gate circuit, the greater the probability of failure.
[0065] S3: Establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model.
[0066] In this embodiment, the calculation formula of the evaluation model is:
[0067]
[0068] Among them, M i is the test vector V i The number of logic gates corresponding to the covered nodes, N i is the number of transistors corresponding to each logic gate, C i is the vector V i The test contribution.
[0069] It is understandable that in actual integrated circuits, the size of transistors mainly depends on the manufacturing process and the logic structure of the circuit. Under the same manufacturing process, the sizes of transistors in different logic gates are also different. This application mainly considers the number of transistors in the logic gate, thus simplifying the above problem.
[0070] S4: Sort the test vectors according to the contribution to obtain a test vector combination with the highest node coverage.
[0071] In this embodiment, the contribution is calculated by the evaluation model to obtain the contribution C1, C2, C3, ..., C corresponding to the test vector. i , ..., C m The test vector with the highest contribution is taken as the first test vector of the sorted test vector set, denoted as VC1.
[0072] Calculate the contribution of the first test vector and the preset test vector in pairs, and select the combination with the highest node coverage, which is recorded as (VC1, VC2). Calculate the node coverage of the combination (VC1, VC2) and the remaining test vectors in the test vector set, and select the three test vector combinations with the highest node coverage (VC1, VC2, VC3).
[0073] S5: Calculate the node coverage of the test vector combination and the preset test vector combination, and obtain a reordered test vector set according to the screened node coverage.
[0074] In this embodiment, the node coverage of the combination of the measurement vectors (VC1, VC2, VC3) and the preset test vectors is calculated. The node coverage of the selected test vector combinations is counted to obtain the final reordered test vector set (VC1, VC2, VC3, ..., VC n ). The coverage of the test vector is the ratio of the number of faults covered by the test vector set to the total number of circuit faults.
[0075] It can be understood that by optimizing the test vector set through combinatorial sorting, an efficient test set that hits the fault point earlier can be screened out. At the same time, in the case of test cost and time control, test vectors with large contribution rate are preferentially selected for testing according to coverage.
[0076] See also Figure 2 , which is a schematic diagram of the sorting of digital integrated circuit test vectors based on Example 1 of the present application. First, the test vector with the highest contribution is obtained by screening through the evaluation model, and then this test vector is combined with other test vectors one by one to calculate the coverage of each combination. The combination with the highest coverage is used as the combination determined in the first round, and the vector combination becomes two vectors. According to the combination of these two vectors and other vectors, a combination of three vectors is obtained. The combination with the largest coverage in the combination of the three vectors is screened out as the combination determined in the second round. One vector is added in each round, and so on, and finally the vector order of the entire combination is determined, and a reordered test vector set is generated.
[0077] See also Figure 3, which is a schematic diagram of the predicted coverage of the test vectors generated in Example 1 of the present application. Through the test vector generation tool Tessent, the test point coverage of the circuit is increased based on DFT testability design, and the generated test vectors ensure that the test coverage is above 98% and improve the test efficiency.
[0078] In summary, Example 1 of the present application optimizes the order and combination of test vectors or test items in a test vector set based on the feature correlation of test vectors and test items, and preferentially loads test vectors with relatively high test performance, and places test vectors or test items with less contribution to the test at the end of the priority list. The optimized and ordered test vector set can hit the faulty integrated circuit under test earlier, thereby saving test time, and at the same time, the optimal test item combination can be selected from the ordered test vector list according to the constraints of coverage and test cost.
[0079] Example 2
[0080] See also Figure 5 , is a structural diagram of a digital integrated circuit test vector sorting system according to Embodiment 2 of the present application; the specific contents include:
[0081] Acquisition module: obtain the test vector set;
[0082] Testing module: injecting faults into logic gates to perform fault simulation, performing simulation tests according to the test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors;
[0083] Evaluation module: establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model;
[0084] Sorting module: sorting the test vectors according to the contribution to obtain the test vector combination with the highest node coverage;
[0085] Output module: Calculate the node coverage of the test vector combination and the preset test vector combination, and obtain a reordered test vector set according to the screened node coverage.
[0086] Example 3
[0087] See also Figure 6 , is a schematic diagram of the device structure of Embodiment 3 of the present application. The device 50 includes a processor 51 and a memory 52 coupled to the processor 51 .
[0088] The memory 52 stores program instructions for implementing the above-mentioned digital integrated circuit test vector sorting method.
[0089] The processor 51 is used to execute program instructions stored in the memory 52 to implement a digital integrated circuit test vector sorting.
[0090] The processor 51 may also be referred to as a CPU (Central Processing Unit).
[0091] The processor 51 may be an integrated circuit chip with signal processing capabilities. The processor 51 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0092] Example 4
[0093] See also Figure 7 , which is a schematic diagram of the structure of the storage medium of Example 4 of the present application. The storage medium of the embodiment of the present application stores a program file 61 that can implement all the above methods, wherein the program file 61 can be stored in the above storage medium in the form of a software product, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or a computer, a server, a mobile phone, a tablet, and other devices.
[0094] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.
[0095] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.
[0096] Although the embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the appended claims and their equivalents.
[0097] Of course, the present invention may have many other implementations. Based on this implementation, other implementations obtained by ordinary technicians in this field without any creative work are all within the scope of protection of the present invention.
Claims
1. A digital integrated circuit test vector sorting method, characterized in that: include: Get the test vector set; Injecting faults into logic gates to perform fault simulation, performing simulation tests according to test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors; Establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model; According to the contribution, the test vectors are sorted to obtain a test vector combination with the highest node coverage; The node coverage of the test vector combination and the preset test vector combination is calculated, and a reordered test vector set is obtained according to the screened node coverage.
2. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The step of injecting faults into logic gates to perform fault simulation, performing simulation tests according to the test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors specifically includes the following steps: Inject faults into each logic gate to perform fault simulation, and use the test vector sets V1, V2, V3...V in sequence. i ,…,V m The test vectors in the program are used for simulation testing, and the number of logic gates hit by the test vectors and the corresponding faulty gate types are counted.
3. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The step of establishing an evaluation model based on the faulty gate type and the number of logic gates and calculating the contribution of the test vector by using the evaluation model specifically includes the following steps: The calculation formula of the evaluation model is: Among them, M i is the test vector V i The number of logic gates corresponding to the covered nodes, N i is the number of transistors corresponding to each logic gate, C i is the vector V i The test contribution.
4. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The step of sorting the test vectors according to the contribution to obtain the test vector combination with the highest node coverage specifically includes the following steps: The contribution is calculated by the evaluation model to obtain the contribution C1, C2, C3, ..., C corresponding to the test vector. i ,…,C m ; The test vector with the highest contribution is taken as the first test vector in the sorted test vector set, denoted as VC1; Calculate the contribution of the first test vector and the preset test vector in pairs, and select the combination with the highest node coverage, which is recorded as (VC1, VC2); Calculate the node coverage of the combination (VC1, VC2) and the remaining test vectors in the test vector set, and select the three test vector combinations with the highest node coverage (VC1, VC2, VC3).
5. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The step of calculating the node coverage of the test vector combination and the preset test vector combination, and obtaining the reordered test vector set according to the screened node coverage, specifically includes the following steps: Calculate the node coverage of the measurement vector combination (VC1, VC2, VC3) and the preset test vector combination; The node coverage of the screened test vector combinations is counted to obtain the final reordered test vector set (VC1, VC2, VC3, ..., VC n ).
6. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The coverage of the test vector is the ratio of the number of faults covered by the test vector set to the total number of circuit faults.
7. A digital integrated circuit test vector sorting method according to claim 1, characterized in that: The probability of occurrence of the fault is: Where x is the random variable of the number of failures and λ is the average failure rate.
8. A system for a digital integrated circuit test vector sorting method according to claim 1, characterized in that: include: Acquisition module: obtain the test vector set; Testing module: injecting faults into logic gates to perform fault simulation, performing simulation tests according to the test vectors in the test vector set, and obtaining the fault gate type and the number of logic gates corresponding to the test vectors; Evaluation module: establishing an evaluation model based on the faulty gate type and the number of logic gates, and calculating the contribution of the test vector through the evaluation model; Sorting module: sorting the test vectors according to the contribution to obtain the test vector combination with the highest node coverage; Output module: Calculate the node coverage of the test vector combination and the preset test vector combination, and obtain a reordered test vector set according to the screened node coverage.
9. A device, characterized in that: The device includes a processor and a memory coupled to the processor, wherein the memory stores program instructions for implementing a digital integrated circuit test vector sorting method as described in any one of claims 1-7; and the processor is used to execute the program instructions stored in the memory to implement a digital integrated circuit test vector sorting.
10. A storage medium, characterized in that: Program instructions executable by a processor are stored, and the program instructions are used to execute a digital integrated circuit test vector sorting method as described in any one of claims 1-7.