A method for extracting parasitic capacitance of integrated circuit interconnections

Abstract

The present invention belongs to the technical field related to integrated circuits, and particularly relates to a method for extracting parasitic capacitance of integrated circuit interconnections, including: constructing a set of sampling points on and inside the conductor surface; constructing a parasitic capacitance matrix with an initial value of zero for each pairwise interconnected capacitance; generating a set of ideal surface potential values corresponding to the surface sampling points of each conductor; constructing a neural network structure composed of an input layer, a single hidden layer, and an output layer, using the surface sampling points as the input, using the mean square error between the ideal surface potential value corresponding to the surface sampling points and the output of the neural network as the loss function, using the Green's function of the Poisson equation as the activation function of the hidden layer, and using all the equivalent point charge positions as the center coordinates of the activation function of the hidden layer; training the weight coefficients of each neuron in the hidden layer, corresponding to the equivalent charge values of each equivalent point charge, obtaining the equivalent charge values of all equivalent point charges of each conductor, and updating the parasitic capacitance matrix. The present invention can achieve the extraction of parasitic capacitance.

Description

Technical Field

[0001] The present invention belongs to the technical field related to integrated circuits, and more specifically, relates to a method for extracting parasitic capacitance of integrated circuit interconnects. Background Art

[0002] With the continuous progress of semiconductor manufacturing process technology, the size of integrated circuits has been continuously reduced accordingly. In this case, the integration density of the chip has increased significantly, resulting in a more dense arrangement of interconnects. The distance between interconnects has become smaller and smaller. At the same time, the process variations of the interconnects themselves have become more and more obvious. Therefore, the parasitic effects between interconnects are more serious, and the influence of parasitic parameters, especially parasitic capacitance, on the circuit has become more and more significant. How to accurately extract the parameters of these parasitic effects has become one of the key problems in the field of integrated circuits.

[0003] Currently, the mainstream parasitic capacitance field solvers for interconnects can be mainly divided into two categories according to the solving principle. One is the traditional discrete numerical method for solving physical field equations, such as the finite difference method and the boundary element method, etc.; the other is the method for solving integrals, such as the floating random walk method, which uses floating random walk to transform the calculation of conductor charges into Monte Carlo integration. The floating random walk method has relatively higher calculation efficiency and accuracy than several other traditional numerical methods, but the calculation results have variance, so the symmetry of the interconnect capacitance matrix is poor, and it often faces challenges when dealing with conductors with non-Manhattan shapes (process variability exists) and complex dielectric distributions; the accuracy of the traditional numerical discrete method is lower than that of the random shape method, and the division of discrete grids requires a large calculation cost (especially for non-Manhattan shape conductors).

[0004] The rapidly developing neural network plays an increasingly important role in the field of integrated circuit electronic design automation. Great progress has been made in the research on data-driven neural network parasitic capacitance prediction methods, but there are few related studies on the method of directly solving parasitic capacitance using neural networks, and no machine learning method for solving the parasitic capacitance field that is comparable to methods such as the boundary element method has been proposed. Summary of the Invention

[0005] In view of the above defects or improvement requirements of the prior art, the present invention provides a method for extracting parasitic capacitance of integrated circuit interconnects, aiming to organically combine artificial neural networks with the physical problem of solving parasitic capacitance, give full play to the flexible and efficient characteristics of neural networks, and achieve high-precision parasitic capacitance extraction.

[0006] To achieve the above object, according to one aspect of the present invention, there is provided a method for extracting parasitic capacitance of integrated circuit interconnects, including:

[0007] S1. Construct a set of position coordinates of surface sampling points and a set of position coordinates of internal sampling points for each conductor in the integrated circuit. Among them, each internal sampling point is used as the position of an equivalent point charge; construct a parasitic capacitance matrix with all-zero initial values composed of the mutual capacitance between all pairs of conductors.

[0008] S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values to 0; according to the ideal surface potential values of each conductor, generate a set of ideal surface potential values corresponding one-to-one to the surface sampling points of the conductor.

[0009] S3. Construct a neural network structure composed of an input layer, a single hidden layer, and an output layer. Among them, use the position coordinates of the surface sampling points as the input of the neural network, use the mean square error between the ideal surface potential values corresponding one-to-one to the surface sampling points and the output of the neural network as the loss function. The number of neurons is the same as the number of all equivalent point charges corresponding to all conductors. Use the Green's function of the Poisson equation in three-dimensional space as the activation function of the single hidden layer, and use the position coordinates of all equivalent point charges as the central coordinates of the hidden layer activation function; based on the set of position coordinates of the surface sampling points of all conductors and the corresponding set of ideal surface potential values, train the weight coefficients of each neuron in the single hidden layer of the neural network, corresponding to the equivalent charge values of each equivalent point charge, and obtain the equivalent charge values of all equivalent point charges in each conductor.

[0010] S4. Calculate the charge quantity of each conductor using the equivalent charge values of all equivalent point charges in the conductor, calculate the mutual capacitance between two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor has served as the main conductor.

[0011] Further, the construction method of the set of position coordinates of the surface sampling points is as follows:

[0012] Read the binary file describing the physical layout of the integrated circuit and the file recording the information of each process layer in the integrated circuit, and establish a three-dimensional space model of each conductor in the integrated circuit;

[0013] According to the three-dimensional space model of each conductor, sample a preset number of sampling points on the surface of the conductor by uniform random sampling or uniform grid sampling to obtain the set of position coordinates of the surface sampling points.

[0014] Further, the construction method of the set of position coordinates of the internal sampling points is as follows:

[0015] Read the binary file describing the physical layout of the integrated circuit and the file recording the information of each process layer in the integrated circuit, and establish a three-dimensional space model of each conductor in the integrated circuit;

[0016] According to the three-dimensional space model of each conductor, it is set that all internal sampling points are distributed on the surface of the three-dimensional closed solid structure obtained by equally scaling down each original side length of the conductor according to a preset sampling ratio parameter a to sample the interior of the conductor, and a set of position coordinates of the internal sampling points is obtained.

[0017] Furthermore, when there are conductors with irregular surfaces in the integrated circuit, each conductor with an irregular surface is regarded as a conductor with a regular surface, and the training described in S1 - S3 is performed; according to the real surface of the conductor with an irregular surface, the training described in S1 - S3 is performed, where the number of surface sampling points and the number of internal sampling points obtained by the two samplings are the same, and the initial values of the weight coefficients of each neuron in the neural network during the second training are the weight coefficients of each neuron in the neural network obtained after the first training; the equivalent charge values of all equivalent point charges in each conductor finally obtained are used to perform S4.

[0018] Furthermore, in S3, the gradient descent method or the least squares method is used to train the weight coefficients of each neuron in the single-layer hidden layer of the neural network.

[0019] Furthermore, when using the least squares method to train the weight coefficients of each neuron in the single-layer hidden layer of the neural network, after the least squares method training is completed, another set of position coordinates of internal sampling points is constructed for each conductor. According to the equivalent charge values of all equivalent point charges corresponding to each conductor obtained by the current training, the electrostatic potential jointly excited by all equivalent point charges on the conductor at the positions of each surface sampling point is calculated, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined. The mean square error between the difference corresponding to each surface sampling point one by one and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge values of all equivalent point charges determined by the two sets of position coordinates of internal sampling points for each conductor.

[0020] According to another aspect of the present invention, an electronic device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the method described above are implemented.

[0021] According to another aspect of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium includes a stored computer program, wherein when the computer program is run by a processor, the device where the storage medium is located is controlled to execute the steps of the method described above.

[0022] According to another aspect of the present invention, a computer program product is provided, including a computer program or instruction. When the computer program or instruction is executed by a processor, the steps of the method described above are implemented.

[0023] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the technical solutions provided by the present invention mainly have the following beneficial effects:

[0024] 1. The present invention proposes a method for extracting the parasitic capacitance of integrated circuit interconnections. The basic principle is to assume that there are a large number of equivalent point charges inside each conductor, and the combined action of all equivalent point charges makes the potential value on the surface of each conductor reach the expected value, and then calculate the parasitic capacitance matrix. The specific approach is to construct a neural network structure composed of an input layer, a single hidden layer, and an output layer, using the Green's function of the Poisson equation in three-dimensional space as the activation function (i.e., kernel function) of the single hidden layer, and using the position coordinates of all equivalent point charges as the center coordinates of the kernel function of the single hidden layer. In this way, the equivalent charge values of all equivalent point charges can be calculated, and then the capacitance matrix can be calculated. Therefore, as the first parasitic capacitance numerical calculation method completely driven by machine learning, this method has sufficient theoretical support, distinct physical significance, and interpretability, which ensures the reliability of the solution results. Compared with traditional algorithms such as random walk and finite element method, the accuracy of calculating capacitance by this method exceeds that of the finite element method, and is comparable to the calculation accuracy of the current highest-precision random walk method. Moreover, the variance of the calculation results is smaller than that of the random walk method, that is, the symmetry of the parasitic capacitance matrix calculated by this method is higher. In addition, due to the structural characteristics of this neural network, different training parameters can be selected, so it has higher calculation flexibility; the construction method and parameter training method of this neural network determine that when calculating the interconnection capacitance matrix, it will not be limited by the process deviation and random fluctuation of the interconnection conductor structure (for example, when dealing with an interconnection conductor structure with an irregular surface, first train it: train the neural network model for the interconnection line conductor in the ideal state, and make the distribution of its equivalent point charges geometrically similar, then change the position of the sampling points to map them to the actual surface of the conductor with process variations, keep its charge constant, and continue to make the distribution of the equivalent point charges and the sampling points geometrically approximate. Finally, use this as the initial state of the neural network for training to simulate the capacitance situation of the interconnection line conductor with process deviation, and the high-precision solution of the parasitic capacitance matrix of the interconnection conductor with an irregular surface can be quickly realized); this method organically combines the artificial neural network with the physical problem of parasitic capacitance solution, can give full play to the flexible and efficient characteristics of the neural network, and brings new ideas for the numerical solution of the physical problem of parasitic capacitance.

[0025] 2. The present invention proposes a sampling method for surface sampling points. By sampling on the surface of the interconnect conductor structure to obtain the set of position coordinates of the surface sampling points as the input of the constructed neural network model, compared with the traditional full-space discretization methods such as the finite element method, the dimension of the problem is reduced. At the same time, there is no need to perform mesh discretization on the interconnect conductor structure, thus saving the computational cost of mesh generation.

[0026] 3. In the training scheme proposed by the present invention, after the parameters are trained by the least squares method for the first time, another set of position coordinates of internal sampling points is constructed for each conductor. According to the equivalent charge values of all equivalent point charges corresponding to each conductor obtained from the current training, calculate the electrostatic potential jointly excited by all equivalent point charges on the conductor at the positions of each surface sampling point, and determine the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor. Taking the mean square error between the difference corresponding to each surface sampling point and the output of the neural network as the loss function, reconstruct the neural network structure and train again to obtain the equivalent charge values of all equivalent point charges determined by the two sets of position coordinates of internal sampling points for each conductor. This scheme reduces the error of the training result of the least squares method through multiple trainings, ensuring the accuracy of the calculation result of the final interconnect capacitance matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flowchart of a method for extracting parasitic capacitance of an integrated circuit interconnect line provided by an embodiment of the present invention.

[0028] Figure 2 It is a schematic diagram of the structure and training method of a physics-aware extreme learning machine provided by an embodiment of the present invention.

[0029] Figure 3 It is an overall flowchart of a parasitic capacitance extraction provided by an embodiment of the present invention.

[0030] Figure 4 It is a detailed flowchart of building a neural network model - physics-aware extreme learning machine and calculating the interconnect capacitance matrix of a conductor provided by an embodiment of the present invention.

[0031] Figure 5 It is a structural diagram of an interconnect conductor provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0033] Example 1

[0034] A method for extracting parasitic capacitance of interconnections in an integrated circuit, as Figure 1 shown, includes:

[0035] S1. Construct a set of position coordinates of surface sampling points and a set of position coordinates of internal sampling points for each conductor in the integrated circuit, where each internal sampling point is used as the position of an equivalent point charge; construct a parasitic capacitance matrix with all-zero initial values composed of the mutual capacitances between all pairs of conductors;

[0036] S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values to 0; generate a set of ideal surface potential values corresponding one-to-one to the surface sampling points of the conductor according to the ideal surface potential values of each conductor;

[0037] S3. Construct a neural network structure composed of an input layer, a single hidden layer, and an output layer, where the position coordinates of surface sampling points are used as the input of the neural network, the mean square error between the ideal surface potential values corresponding one-to-one to the surface sampling points and the output of the neural network is used as the loss function, the number of neurons is the same as the number of all equivalent point charges corresponding to all conductors, the Green's function of the Poisson equation in three-dimensional space is used as the kernel function of the single hidden layer, and the position coordinates of all equivalent point charges are used as the central coordinates of the kernel function of the single hidden layer; based on the set of position coordinates of surface sampling points of all conductors and the corresponding set of ideal surface potential values, train the weight coefficients of each neuron in the single hidden layer of the neural network, corresponding to the equivalent charge values of each equivalent point charge, and obtain the equivalent charge values of all equivalent point charges in each conductor;

[0038] S4. Calculate the charge amount of the conductor by using the equivalent charge values of all equivalent point charges in each conductor, calculate the mutual capacitance between two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor has served as the main conductor.

[0039] It should be noted that the mutual capacitance is the parasitic capacitance. The above Green's function is , and the position coordinates of all equivalent point charges are used as the central coordinates of the kernel function of the single hidden layer , represents the permittivity, represents the position coordinates of the surface sampling points. Using the set of position coordinates of the surface sampling points of the conductor obtained above as the input, using the positions of the equivalent point charges obtained above as the initial positions of the neurons in the hidden layer, and using the Green's function of the Poisson equation in three-dimensional space as the activation function of the hidden layer, where, is the Euclidean distance between each element in the input surface sampling coordinate set and all hidden layer neurons. This activation function maps the relationship between the input quantity and the output quantity to a linear space. The mean square error between the ideal surface potential value of the conductor set above and the output of the neural network is used as the loss function, and the equivalent charge value of the equivalent point charge is obtained by solving the coefficient matrix of the linear equation system of the input quantity and the output quantity in the linear space.

[0040] In S4, when calculating and updating the parasitic capacitance matrix of the conductor structure, since the electric fields excited by different point charges at the same position in space are linearly superposed, according to the relationship formula between the surface potential and the conductor charge capacitance , sum the equivalent charge values of the equivalent point charges inside each conductor obtained, to get the self-capacitance of the main conductor when the main conductor is the above-selected conductor and its mutual capacitance with the slave conductor, and write the result into the corresponding position in the interconnect capacitance matrix of the conductor.

[0041] In addition, in S4, determine whether all conductors have ever been set as the main conductor. If there is a conductor that has not been set as the main conductor, set it as the new main conductor, set its ideal surface potential value to 1, and set the remaining conductors as slave conductors, set their ideal surface potential values to 0, generate a set of potential values corresponding one-to-one to its surface sampling point set according to the ideal surface potential values of each conductor, and repeat the steps of neural network construction and training. If all conductors have been set as the main conductor, then calculate and output the interconnect capacitance matrix. The principle of selecting another main conductor is that the conductor has not been set as the main conductor. If there are multiple conductors that have not been set as the main conductor, the selection order is not limited.

[0042] A method for extracting the parasitic capacitance of an integrated circuit interconnect line in this embodiment is the first machine learning interconnect line parasitic capacitance solution scheme completely driven by physical principles rather than data-driven. It uses a neural network to directly solve the interconnect parasitic capacitance matrix of the interconnect conductor structure, similar to the basic idea of solving the interconnect line parasitic capacitance by the traditional boundary element method. Its solution principle has distinct physical significance and interpretability; this method uses the Green's function of the Poisson equation as the activation function of the hidden layer in the extreme learning machine, liberating the position of the equivalent point charge (Green's function excitation source) from the surface of the conductor to the inside of the conductor, and has higher computational flexibility compared with the traditional method.

[0043] The method for extracting the parasitic capacitance of interconnects provided in this embodiment obtains the model input by sampling on the surface of the interconnect conductor structure and obtains the excitation source (i.e., neurons) of the Green's function by sampling inside the conductor. Therefore, the calculation process of this method is not limited by the process deviation and random fluctuation of the interconnect conductor structure. For example, preferably, when there is a conductor with an irregular surface in an integrated circuit, each conductor with an irregular surface is regarded as a conductor with a regular surface (the irregular surface has protrusions or depressions, and the regular surface is flat. "Regarded as" means first treating the conductor with an irregular surface as a conductor with a flat surface), and the training described in S1 - S3 is performed; according to the actual surface of the conductor with an irregular surface, the training described in S1 - S3 is performed; among them, the number of surface sampling points and the number of internal sampling points obtained by the two samplings are the same, and the initial values of the weight coefficients of each neuron in the neural network during the second training are the weight coefficients of each neuron in the neural network obtained after the first training. That is, when dealing with an interconnect conductor structure with an irregular surface, first perform pre - training on it: train a neural network model for the interconnect conductor in an ideal state and make the distribution of its equivalent point charges geometrically similar, then change the position of the sampling points to map them to the actual surface of the conductor with process variations, keep its charge constant, and continue to make the distribution of the equivalent point charges and the sampling points geometrically approximate. Finally, use this as the initial state of the neural network for training to simulate the capacitance situation of the interconnect conductor with process deviation, and the parasitic capacitance matrix of the interconnect conductor with an irregular surface can be quickly solved with high precision.

[0044] In addition, the method for extracting the parasitic capacitance of interconnects provided in this embodiment is a machine - learning method for the parasitic capacitance of interconnect conductor structures completely driven by the physical bottom layer. Therefore, this method has high parallelization characteristics and software - hardware affinity, and will obtain faster calculation speed and higher calculation efficiency with the improvement of hardware performance such as GPUs and the improvement of machine - learning software frameworks.

[0045] As a preferred implementation manner, the construction method of the surface sampling point position coordinate set is as follows:

[0046] Read the binary file describing the physical layout of the integrated circuit and the file recording the information of each process layer in the integrated circuit, and establish a three - dimensional space model of each conductor in the integrated circuit;

[0047] According to the three - dimensional space model of each conductor, sample a preset number of sampling points on the surface of the conductor by means of uniform random sampling or uniform grid sampling to obtain the position coordinate set of the surface sampling points.

[0048] As a preferred implementation manner, the construction method of the internal sampling point position coordinate set is as follows:

[0049] Read a binary file describing the physical layout of an integrated circuit and a file recording the information of each process layer in the integrated circuit, and establish a three-dimensional space model for each conductor in the integrated circuit;

[0050] According to the three-dimensional space model of each conductor, set that all internal sampling points are distributed on the surface of the three-dimensional closed solid structure obtained by reducing the original side lengths of the conductor according to a preset sampling ratio parameter a After equal ratio reduction, sample the interior of the conductor to obtain a set of position coordinates of the internal sampling points.

[0051] The process layout file of the interconnect conductor includes a binary file describing the physical layout of the integrated circuit and a file recording the information of each process layer. Among them, the binary file describing the physical layout of the integrated circuit is the common GDSII file in the post-layout simulation process of the integrated circuit; for the content of the file about the information of each process layer, if it is a metal layer, the content includes the name, layer number, data type, height, and thickness of the metal layer. If it is a via layer, the content includes the name, layer number, data type, and the names of the upper and lower connected metal layers.

[0052] The GDSII stream format (GDSII) is a database file format that is used for data conversion of integrated circuit layouts and has become the de facto industry standard. GDSII is a binary file that contains planar geometric shapes, text or labels in the integrated circuit layout, and other relevant information and can be composed of a hierarchical structure. GDSII data can be used to reconstruct all or part of the layout information.

[0053] According to the process layout file of the interconnect conductor, obtain the coordinate sets of the sampling points on the three-dimensional space surface and inside the three-dimensional space of the conductor structure respectively. As an implementation example, the tool used to read the binary file describing the physical layout of the integrated circuit is the python package "python-gdsii". Among them, "python-gdsii" is a python library that can be used to read, create, modify, and save GDSII files. This software package also includes methods that can be used to convert binary GDS files to other simple text formats.

[0054] When sampling inside each interconnect conductor, first set the sampling rules and the density and distribution characteristics of the sampling points. The sampling rules can be set as random sampling with uniform distribution or grid sampling, etc. The position distribution of the sampling points is generally set on the surface of the three-dimensional closed solid structure obtained by reducing the original side lengths of the conductor according to the sampling ratio parameter a. For example, sample on the surface of the three-dimensional closed solid structure after reducing the conductor side length to 0.8 times and 0.9 times of the original length according to the set sampling rules and density.

[0055] The method for extracting the parasitic capacitance of the interconnecting wire provided by the method of this embodiment obtains the model input by sampling on the surface of the interconnecting conductor structure. Compared with the traditional finite element method, the dimension of the problem is reduced. When solving the three-dimensional interconnecting conductor structure, only sampling on the surface is required, and when solving the two-dimensional interconnecting conductor structure, only sampling on the boundary is required. At the same time, there is no need to perform mesh discretization processing on the interconnecting conductor structure. For example, when calculating the mutual capacitance of an isolated metal sphere, traditional boundary element algorithms, etc., need to perform complex mesh discretization on the spherical surface, while placing the equivalent point charge represented by the Green's function excitation source of the Poisson equation at the center of the sphere, only by solving this unknown variable can the electric field distribution in the external space of the conductor under the given voltage condition be determined. Therefore, this method has higher computational efficiency.

[0056] As a preferred implementation manner, in S3, the weight coefficients of each neuron in the single hidden layer of the neural network are trained by using the gradient descent method or the least squares method. In this implementation manner, the neural network can be trained by using the training method of the physics-informed neural network, that is, using the gradient descent method for backpropagation to train the network, or can be trained by the least squares method. At this time, this embodiment refers to the neural network as a physics-informed extreme learning machine, as Figure 2 shown. When using the gradient descent method, the mean square error function of the output value of the model and the above-mentioned ideal surface potential value of the conductor is used as the loss function in the backpropagation process. The optimizer that can be used can be Adam, AdamW, LBFGS, etc., without limitation. The software framework used to build and train this neural network can be Pytorch, Tensorflow, Jax, etc., without limitation. When using the training method of the physics-informed neural network, that is, the gradient descent method for backpropagation to train the network, the position coordinate information of the neurons can be selected whether to be called the training parameters. If it is selected as the training parameter, relatively more training time is required, which will make the accuracy of the solution result higher. In addition, when using the gradient descent method for training, the method of batch training can also be used. The specific operation is to train multiple different physics-informed extreme learning machine models in sequence, where the subsequent models are used to fit the residuals of the previous model training.

[0057] The physics-informed extreme learning machine of the neural network model constructed according to the set of position coordinates of the equivalent point charges integrates the physics-informed neural network and the extreme learning machine and has only one hidden layer. This model can be optimized by two training methods, the least squares method and the gradient descent method, corresponding to the training methods of the extreme learning machine and the physics-informed neural network respectively.

[0058] If the training method of the extreme learning machine is adopted, that is, the weight coefficients are solved directly by an analytical method (i.e., the least squares method), since there is a certain optimization space for the fitting residuals of the weight coefficients obtained by this training method, the fitting residuals of this training method can be reduced through further training. That is, as a preferred implementation, when training the weight coefficients of each neuron in the single hidden layer of the neural network by the least squares method, after the least squares method training is completed, another set of internal sampling point position coordinates is constructed for each conductor. According to the equivalent charge values of all equivalent point charges corresponding to each conductor obtained by the current training, the electrostatic potential jointly excited by all equivalent point charges on this conductor at the positions of each surface sampling point is calculated, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of this conductor is determined. The mean square error between the difference corresponding to each surface sampling point one by one and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge values of all equivalent point charges determined by two sets of internal sampling point position coordinates for each conductor.

[0059] If the gradient descent method is adopted, when the iteration reaches the termination condition, determine the equivalent charge values of all equivalent point charges in each conductor corresponding to the set of neuron weight coefficients with the best prediction performance, and jump to step S4; if the least squares method is adopted, after S3 is completed, determine the equivalent charge values of all equivalent point charges in each conductor, and jump to step S4.

[0060] The method for extracting the parasitic capacitance of the interconnecting line provided in this embodiment can flexibly configure the training method of the neural network according to different actual situations. For example, no matter which training method is used, a multi-stage training strategy can be adopted, and multiple different neural networks can be trained in sequence, where the subsequent model is used to fit the residuals of the previously trained model, so it has high accuracy.

[0061] It should be noted that if the least squares method is used for training, preferably two sets of internal sampling point position coordinates can be constructed, and the neural network is constructed and trained twice to improve the accuracy. Among them, the construction methods of these two sets of internal sampling point position coordinates can be the same. For example, as described above, according to the three-dimensional space model of each conductor, it is set that all internal sampling points are distributed on the surface of the three-dimensional closed solid structure obtained by equally scaling down each original side length of this conductor according to a preset sampling ratio parameter a to sample the interior of this conductor and obtain the set of internal sampling point position coordinates. The value of the sampling ratio parameter a can be adjusted according to actual needs. As an example, the corresponding to the first set of internal sampling point position coordinates, and the corresponding to the second set of internal sampling point position coordinates, that is, appropriately increase the sampling ratio parametera Obtaining internal points closer to the surface can accelerate the reduction rate of the loss function and residuals during subsequent training fitting processes, and has practical application value. The positions of the equivalent point charges in the second sampling do not coincide with the positions in the position coordinate set of the equivalent point charges in the first sampling.

[0062] An optional implementation. Please refer to Figure 3 , which is a framework process for the whole. Please refer to Figure 4 , which is a working process for the whole. Through the above steps, the accurate calculation of the interconnect parasitic capacitance parameter matrix of the interconnect conductor structure can be achieved.

[0063] Such as Figure 5 An interconnect conductor structure shown. By using this method to solve this structure, its corresponding interconnect capacitance matrix is obtained as follows:

[0064]

[0065] The unit of each value is . It can be seen from this matrix that the symmetry of this matrix is very high, indicating that the variance of this algorithm is small.

[0066] The calculation results of the self - capacitances of the conductors of the Figure 5 example conductor structure obtained by the method of this embodiment ( ) are compared with the calculation results of other methods. The results are shown in Table 1 below. It can be seen that the results of this method are extremely close to the calculation results of the random - walk method with the highest accuracy ( ), the average relative error is less than one percent, and the accuracy is higher than the calculation results of the Comsol software using the finite - element method ( ).

[0067]

[0068] Generally speaking, the method of this embodiment eliminates the computational cost brought by discrete grid division, ensures that the calculation results can achieve high accuracy while having low variance, and is easily applicable to interconnect conductor structures with non - Manhattan conductors. At the same time, it organically combines the artificial neural network with the physical problem of parasitic capacitance solving, can give full play to the flexible and efficient characteristics of the neural network, and brings new ideas for numerically solving the physical problem of parasitic capacitance.

[0069] Embodiment Two

[0070] This application also relates to an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above - mentioned method are implemented.

[0071] The electronic device can be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The so-called processor can be a Central Processing Unit (CPU), or can also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory can be used to store computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory.

[0072] The related technical solutions are the same as above and will not be elaborated here.

[0073] Embodiment 3

[0074] This application also relates to a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are realized.

[0075] Specifically, the memory can include high-speed random access memory, and can also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0076] The related technical solutions are the same as above and will not be elaborated here.

[0077] Embodiment 4

[0078] This application embodiment provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps of the method of the above embodiments of this application.

[0079] The related technical solutions are the same as above and will not be elaborated here.

[0080] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for extracting parasitic capacitance of an integrated circuit interconnect, characterized in that: include: S1, constructing a surface sampling point position coordinate set and an internal sampling point position coordinate set for each conductor in the integrated circuit, wherein each internal sampling point is regarded as the position of an equivalent point charge; constructing a parasitic capacitance matrix composed of interconnected capacitances between all conductors, with initial values ​​all being zero; S2. Select one conductor from all conductors as the main conductor, set its ideal surface potential value to 1, and the rest as slave conductors, set their ideal surface potential values ​​to 0; according to the ideal surface potential value of each conductor, generate a set of ideal surface potential values ​​corresponding to the surface sampling points of the conductor one by one; S3. Construct a neural network structure consisting of an input layer, a single hidden layer and an output layer, wherein the position coordinates of the surface sampling points are used as the input of the neural network, the mean square error between the ideal surface potential values ​​corresponding to the surface sampling points and the output of the neural network is used as the loss function, the number of neurons is the same as the number of all equivalent point charges corresponding to all conductors, the Green's function of the Poisson equation in three-dimensional space is used as the activation function of the single hidden layer, and the position coordinates of all equivalent point charges are used as the central coordinates of the hidden layer activation function; based on the set of surface sampling point position coordinates of all conductors and the set of one-to-one corresponding ideal surface potential values, the weight coefficients of each neuron in the single hidden layer of the neural network are trained, corresponding to the equivalent charge values ​​of each equivalent point charge, and the equivalent charge values ​​of all equivalent point charges in each conductor are obtained; S4. Calculate the charge of each conductor using the equivalent charge values ​​of all equivalent point charges in the conductor to calculate the interconnection capacitance between the two conductors, update the parasitic capacitance matrix, and repeat S2 until each conductor acts as a primary conductor.

2. The extraction method according to claim 1, characterized in that The surface sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional space model of each conductor, a preset number of sampling points are sampled on the surface of the conductor by uniform random sampling or uniform grid sampling to obtain a position coordinate set of the surface sampling points.

3. The extraction method according to claim 1, characterized in that The internal sampling point position coordinate set is constructed as follows: Reading a binary file describing the physical layout of the integrated circuit and a file recording information of each process layer in the integrated circuit, and establishing a three-dimensional spatial model of each conductor in the integrated circuit; According to the three-dimensional spatial model of each conductor, all internal sampling points are set to be distributed on the surface of the three-dimensional closed structure obtained by proportionally reducing the original side lengths of the conductor according to a preset sampling ratio parameter a, and the interior of the conductor is sampled to obtain a set of internal sampling point position coordinates.

4. The extraction method according to claim 1, characterized in that When there are conductors with irregular surfaces in the integrated circuit, each conductor with an irregular surface is treated as a conductor with a regular surface, and the training described in S1-S3 is performed; the training described in S1-S3 is performed according to the actual surface of the conductor with an irregular surface, wherein the number of surface sampling points and the number of internal sampling points obtained by executing S1 twice are the same, and the initial value of the weight coefficient of each neuron in the neural network during the second training is the weight coefficient of each neuron in the neural network obtained after the first training; and S4 is performed using the equivalent charge value of all equivalent point charges in each conductor finally obtained.

5. The extraction method according to any one of claims 1 to 4, characterized in that In S3, the gradient descent method or the least square method is used to train the weight coefficients of each neuron in a single hidden layer of the neural network.

6. The extraction method according to claim 5, characterized in that When the least square method is used to train the weight coefficients of each neuron in a single hidden layer of a neural network, after the least square method training is completed, another internal sampling point position coordinate set is constructed for each conductor, and the equivalent charge values ​​of all equivalent point charges corresponding to each conductor obtained by the current training are used to calculate the electrostatic potential jointly excited by all equivalent point charges on the conductor at the position of each surface sampling point, and the difference between the electrostatic potential corresponding to each surface sampling point and the ideal surface potential value of the conductor is determined. The mean square error between the difference corresponding to the surface sampling points one by one and the output of the neural network is used as the loss function, and the neural network structure is reconstructed and trained to obtain the equivalent charge values ​​of all equivalent point charges determined by the two internal sampling point position coordinate sets for each conductor.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed by a processor, the device where the storage medium is located is controlled to execute the steps of the method according to any one of claims 1 to 6.

9. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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