Power management circuit and display device

Abstract

The invention relates to a display device and a power management circuit. The display device includes a display panel that displays an image, a data driver that supplies a data voltage to the display panel, and a power management circuit that supplies the analog power supply voltage to the data driver through an output terminal. The power management circuit measures a load current output through the output terminal, and increases a voltage level of the analog power supply voltage based on the load current at a first increase time within a blanking period.

Description

Technical Field

[0001] One or more embodiments described herein relate to a power management circuit and a display device including the power management circuit. Background Art

[0002] The display device may include a display panel that displays an image, a data driver that provides a data voltage to the display panel, and a power management circuit that provides an analog power supply voltage to the data driver. The data driver may include a plurality of buffers (or amplifiers) that output the data voltage, and the buffer may output the data voltage using the analog power supply voltage as an operating voltage (or driving voltage). The power management circuit may output the analog power supply voltage to the data driver through an output terminal.

[0003] The analog power supply voltage supplied to the data driver may have ripples depending on the load of the output terminal outputting the analog power supply voltage. When the analog power supply voltage has ripples, the display quality of the display device may be degraded. Summary of the invention

[0004] One or more embodiments described herein provide a power management circuit that can provide an analog supply voltage with reduced ripple.

[0005] These and / or other embodiments provide a display device with improved display quality and reduced power consumption.

[0006] The display device according to the embodiment may include a display panel displaying an image, a data driver providing a data voltage to the display panel, and a power management circuit providing an analog power supply voltage to the data driver through an output terminal. The power management circuit may measure a load current output through the output terminal, and the power management circuit increases a voltage level of the analog power supply voltage based on the load current at a first increase time point within a blanking period.

[0007] In an embodiment, the power management circuit may calculate a target voltage level based on the magnitude of the load current, and increase the voltage level of the analog power supply voltage to the target voltage level at the first increase time point.

[0008] In an embodiment, the target voltage level may increase as the magnitude of the load current increases.

[0009] In an embodiment, the power management circuit can calculate a target voltage level based on the magnitude of the load current, increase the voltage level of the analog power supply voltage to an intermediate voltage level lower than the target voltage level at a first increase time point, and increase the voltage level of the analog power supply voltage to the target voltage level at a second increase time point within a blanking period after the first increase time point.

[0010] In an embodiment, the first increase time point may be after a predetermined delay time from a start time point of the blanking period.

[0011] In an embodiment, the power management circuit may measure the load current in an active period prior to the blanking period.

[0012] In an embodiment, the power management circuit includes: a voltage converter that converts an input voltage received through an input terminal into the analog power supply voltage; and a load sensor that measures the load current.

[0013] In an embodiment, the voltage converter may include: an inductor connected between the input terminal and a node, a first transistor connected between the node and ground and turned on in response to a first control signal, a second transistor connected between the node and the output terminal and turned on in response to a second control signal, and a gate driver that generates the first control signal and the second control signal.

[0014] In an embodiment, the load sensor may include: a half-duty cycle generation circuit that generates a second voltage based on a first voltage corresponding to the current flowing through the inductor; a sampling and holding circuit that generates a third voltage by sampling a voltage level of the second voltage at a reference time point within a conduction period of the second transistor; and a multiplier that generates a fourth voltage corresponding to the load current by multiplying the conduction period of the first transistor by the third voltage.

[0015] In an embodiment, the power management circuit may further include: a counter, the counter determining the first increase time point by counting a clock signal from a start time point of the blanking period.

[0016] The power management circuit according to the embodiment may include: a voltage converter that converts an input voltage received through an input terminal into an analog power supply voltage and provides the analog power supply voltage through an output terminal; and a load sensor that measures a load current output through the output terminal. The voltage converter may increase a voltage level of the analog power supply voltage based on the load current at a first increase time point within a blanking period.

[0017] In an embodiment, the voltage converter may calculate a target voltage level based on the magnitude of the load current, and increase the voltage level of the analog power supply voltage to the target voltage level at the first increase time point.

[0018] In an embodiment, the target voltage level may increase as the magnitude of the load current increases.

[0019] In an embodiment, the voltage converter can calculate a target voltage level based on the magnitude of the load current, increase the voltage level of the analog power supply voltage to an intermediate voltage level lower than the target voltage level at a first increase time point, and increase the voltage level of the analog power supply voltage to the target voltage level at a second increase time point within a blanking period after the first increase time point.

[0020] In an embodiment, the first increase time point may be after a predetermined delay time from a start time point of the blanking period.

[0021] In an embodiment, the load sensor may measure the load current in an active period before the blanking period.

[0022] In an embodiment, the voltage converter may include an inductor connected between the input terminal and a node, a first transistor connected between the node and ground and turned on in response to a first control signal, a second transistor connected between the node and the output terminal and turned on in response to a second control signal, and a gate driver that generates the first control signal and the second control signal.

[0023] In an embodiment, the load sensor may include: a half-duty cycle generation circuit, which generates a second voltage based on a first voltage corresponding to the current flowing through the inductor; a sampling and holding circuit, which generates a third voltage by sampling a voltage level of the second voltage at a reference time point within a conduction period of the second transistor; and a multiplier, which generates a fourth voltage corresponding to the load current by multiplying the conduction period of the first transistor by the third voltage.

[0024] In an embodiment, the power management circuit may further include: a counter, the counter determining the first increase time point by counting a clock signal from a start time point of the blanking period.

[0025] In an embodiment, the voltage converter may be a boost converter.

[0026] In the power management circuit according to the embodiment, the voltage level of the analog power supply voltage can be increased based on the load current at the first increase time point within the blanking period, so that undershoot of the analog power supply voltage can be prevented from occurring in the active period after the blanking period. Therefore, the ripple of the analog power supply voltage can be reduced.

[0027] In the display device according to the embodiment, undershoot of the analog power supply voltage may not occur, so that the power consumption of the display device can be reduced. In addition, ripple of the analog power supply voltage can be reduced, so that the display quality of the display device can be improved.

[0028] According to one or more embodiments, a power management circuit for a display device includes: an input terminal configured to receive a signal from a load sensor; and a voltage converter configured to adjust an analog power signal output through an output terminal coupled to a data driver, wherein the voltage converter is configured to adjust the analog power signal based on the signal from the load sensor, and the analog power signal is adjusted by the voltage converter in a blanking period of a frame to offset the change of the analog signal during an effective period of the frame. The voltage converter can be configured to increase the analog power supply voltage in the blanking period to offset the decrease of the analog power supply voltage in the effective period. When the load of the display device is at a first level in the blanking period, the voltage converter can be configured to increase the analog power supply voltage, and wherein the load of the display device is at a second level in the effective period, wherein the first level is less than the second level. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a block diagram showing a display device according to an embodiment.

[0031] Figure 2 is a block diagram illustrating a power management circuit according to an embodiment.

[0032] Figure 3 is a timing diagram showing analog power supply voltage according to an embodiment.

[0033] Figure 4 is a timing chart showing an analog power supply voltage according to a comparative example.

[0034] Figure 5 is a timing diagram showing analog power supply voltage according to an embodiment.

[0035] Figure 6is a diagram showing the embodiment including Figure 2 00140] Figure 2 is a diagram of an example of a voltage converter in a power management circuit.

[0036] Figure 7 is a diagram showing a flow path according to an embodiment of the present invention. Figure 6 Timing diagram of the current in the inductor of the voltage converter.

[0037] Figure 8 It is shown that the Figure 2 00147] Figure 2 is a diagram of an example of a load sensor in a power management circuit.

[0038] Fig. 9 is a diagram showing the embodiment including Figure 8 A circuit diagram of an example of a half-duty cycle generating circuit in a load sensor.

[0039] Fig.10 is a diagram showing the provision of Fig. 9 FIG. 1 is a timing diagram of an example of a first voltage generating circuit of a half duty cycle.

[0040] Fig.11 is a diagram showing a method for providing a Figure 8 FIG. 1 is a timing diagram of an example of a second voltage of a sample and hold circuit in a load sensor.

[0041] Fig.12 is a diagram showing the embodiment including Figure 8 A circuit diagram of an example of a load multiplier in a load sensor.

[0042] Fig.13 is a block diagram illustrating an electronic device according to an embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, a display device and a power management circuit according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0044] Figure 1 is a block diagram showing a display device 100 according to an embodiment.

[0045] Reference Figure 1 , the display device 100 may include a display panel 110 , a scan driver 120 , a data driver 130 , a power management circuit 140 , and a controller 150 .

[0046] The display panel 110 displays an image based on light output from a plurality of pixels PX. The pixels PX may receive a scan signal SS and a data voltage VDAT. Each of the pixels PX may emit or output light based on the scan signal SS and the data voltage VDAT.

[0047] The scan driver 120 may provide a scan signal SS to the display panel 110. The scan driver 120 may sequentially generate the scan signal SS based on the scan control signal CNT1 and sequentially provide the scan signal SS to the pixel rows. The scan control signal CNT1 may include, for example, a scan start signal, a scan clock signal, and the like.

[0048] The data driver 130 may provide a data voltage VDAT to the display panel 110. The data driver 130 may generate the data voltage VDAT based on the second image data IMD2 and the data control signal CNT2 provided from the controller 150 and the analog power supply voltage AVDD provided from the power management circuit 140. The data voltage VDAT is provided to the pixel PX of the display panel 110. The second image data IMD2 may include a grayscale value corresponding to light to be output from the pixel PX. The data control signal CNT2 may include, for example, an output data enable signal, a horizontal start signal, a load signal, etc. In an embodiment, the data driver 130 may include a plurality of buffers (or amplifiers) that output the data voltage VDAT.

[0049] The power management circuit 140 may provide the analog power supply voltage AVDD to the data driver 130 through an output terminal. The power management circuit 140 may generate the analog power supply voltage AVDD based on the input voltage VBAT and the power control signal CNT3. The analog power supply voltage AVDD may be provided to a buffer of the data driver 130. The buffer may output the data voltage VDAT using the analog power supply voltage AVDD as an operating voltage (or driving voltage). The input voltage VBAT may be a voltage provided by an external power source (e.g., a battery). The power control signal CNT3 may include an analog power supply voltage control signal ( Figure 2 The analog supply voltage control signal AVDD_CS in the circuit.

[0050] The controller 150 may control the operation (or driving) of the scan driver 120, the operation (or driving) of the data driver 130, and the operation (or driving) of the power management circuit 140. The controller 150 may generate a scan control signal CNT1, a second image data IMD2, a data control signal CNT2, and a power control signal CNT3 based on the first image data IMD1 and the controller control signal CONT. The controller 150 may provide the scan control signal CNT1 to the scan driver 120, the second image data IMD2 and the data control signal CNT2 to the data driver 130, and the power control signal CNT3 to the power management circuit 140. The first image data IMD1 may include a grayscale value corresponding to light to be output from the pixel PX. The controller control signal CONT may include, for example, a vertical synchronization signal, a horizontal synchronization signal, a tearing effect signal, a global clock signal, etc.

[0051] Figure 2 is a block diagram showing a power management circuit 200 according to an embodiment. Figure 2 The power management circuit 200 may correspond to Figure 1 The power management circuit 140 included in the display device 100. Figure 3 is a timing diagram showing an analog power supply voltage AVDD according to an embodiment.

[0052] Reference Figure 2 and Figure 3 , the power management circuit 200 may include a voltage converter 210 and a load sensor 220. In an embodiment, the power management circuit 200 may further include a counter 230.

[0053] The voltage converter 210 can receive an input voltage VBAT through an input terminal TIN and receive a voltage from a controller (eg, Figure 1 The controller 150 in the embodiment receives the analog power supply voltage control signal AVDD_CS. The analog power supply voltage control signal AVDD_CS may correspond to, for example, Figure 1 The power control signal CNT3 shown in FIG. 1 is a power control signal CNT3. The voltage converter 210 can convert the input voltage VBAT into an analog power voltage AVDD based on the analog power voltage control signal AVDD_CS. The voltage converter 210 can provide the analog power voltage AVDD through the output terminal TOUT. In an embodiment, the voltage converter 210 can provide the analog power voltage AVDD to the data driver (e.g., Figure 1 The data driver 130 in the embodiment provides an analog power supply voltage AVDD.

[0054] In an embodiment, the voltage converter 210 can adjust the voltage level of the input voltage VBAT. In an embodiment, the voltage converter 210 is a boost converter. In this case, the voltage converter 210 can increase the voltage level of the input voltage VBAT and generate an analog power supply voltage AVDD having a voltage level higher than the voltage level of the input voltage VBAT.

[0055] The voltage converter 210 may receive a fourth voltage VOUT corresponding to the load current ILD from the load sensor 220, and receive a control signal CS from the counter 230. The voltage converter 210 may control a voltage level of the analog power supply voltage AVDD based on the fourth voltage VOUT, and control an adjustment (e.g., increase) time point of the voltage level of the analog power supply voltage AVDD based on the control signal CS.

[0056] The load sensor 220 can measure the load current ILD outputted through the output terminal TOUT. The load sensor 220 can generate a fourth voltage VOUT corresponding to the load current ILD based on the first voltage DIN corresponding to the current flowing through the inductor included in the voltage converter 210, and provide the fourth voltage VOUT to the voltage converter 210. The size of the load current ILD can vary according to the size of the load connected to the output terminal TOUT. When the size of the load decreases, the size of the load current ILD can decrease, and when the size of the load increases, the size of the load current ILD can increase. In addition, the voltage level of the analog power supply voltage AVDD can vary according to the size of the load connected to the output terminal TOUT. In operation, when the size of the load decreases, the voltage level of the analog power supply voltage AVDD can increase, and when the size of the load increases, the voltage level of the analog power supply voltage AVDD can decrease.

[0057] In an embodiment, the voltage converter 210 may increase the voltage level of the analog power supply voltage AVDD based on the size of the load current ILD at the first increase time point TI1 within the blanking period BLK. One frame period may include a blanking period BLK and an active period ACT. The data driver 130 may not output the data voltage VDAT in the blanking period BLK, and output the data voltage VDAT in the active period ACT. Therefore, the size of the load connected to the output terminal TOUT in the blanking period BLK may be reduced, and the size of the load connected to the output terminal TOUT in the active period ACT may be increased. The blanking period BLK may be determined by the tearing effect signal TE. The tearing effect signal TE may have a high voltage level in the blanking period BLK, and a low voltage level in the active period ACT.

[0058] In an embodiment, the voltage converter 210 may calculate the target voltage level TVL based on the magnitude of the load current ILD, and increase the voltage level of the analog power supply voltage AVDD to the target voltage level TVL at the first increase time point TI1. Therefore, the voltage level of the analog power supply voltage AVDD may be increased to the target voltage level TVL once at the first increase time point TI1. The target voltage level TVL may increase as the magnitude of the load current ILD increases, and the target voltage level TVL may decrease as the magnitude of the load current ILD decreases.

[0059] The first increase time point TI1 may occur after a predetermined delay time T_DEL from the start time point TS of the blank period BLK. Figure 3As shown in , the delay time T_DEL may be less than the interval of the blanking period BLK. In an embodiment, the counter 230 may determine the first increase time point TI1 by counting the clock signal CLK from the start time point TS of the blanking period BLK. For example, the counter 230 may determine the first increase time point TI1 by counting the clock signal CLK from the time point at which the rising edge of the tearing effect signal TE occurs. The clock signal CLK may be, for example, an internal clock signal of the power management circuit 200. The counter 230 may generate a control signal CS for determining the first increase time point TI1 by counting the clock signal CLK, and provide the control signal CS to the voltage converter 210.

[0060] In an embodiment, the load sensor 220 may measure the load current ILD in the active period ACT before the blanking period BLK. Figure 3 As shown in , when the blanking period BLK is included in the nth frame period FRM[n] (n is a natural number greater than or equal to 2), the load sensor 220 can measure the load current ILD in the active period ACT of the n-1th frame period FRM[n-1]. Therefore, the voltage converter 210 can increase the voltage level of the analog power supply voltage AVDD at the first increase time point TI1 within the blanking period BLK based on the load current ILD measured in the active period ACT before the blanking period BLK.

[0061] Figure 4 is a timing chart showing an analog power supply voltage AVDD according to a comparative example.

[0062] Reference Figure 4 , also refer to Figure 2 and Figure 3, when the power management circuit 200 does not increase the voltage level of the analog power supply voltage AVDD within the blanking period BLK, the voltage level of the analog power supply voltage AVDD may be reduced at the end time point Te of the blanking period BLK. The voltage level of the analog power supply voltage AVDD may vary according to the size of the load connected to the output terminal that outputs the analog power supply voltage AVDD. When the size of the load decreases, the voltage level of the analog power supply voltage AVDD may increase, and when the size of the load increases, the voltage level of the analog power supply voltage AVDD may decrease. Therefore, the voltage level of the analog power supply voltage AVDD and the size of the load may be inversely proportional. Since the size of the load decreases as the data voltage is not output in the blanking period BLK, an overshoot OS of the analog power supply voltage AVDD (wherein the voltage level of the analog power supply voltage AVDD increases) may occur at the start time point TS of the blanking period BLK. In addition, since the size of the load increases as the data voltage is output in the active period ACT, an undershoot US of the analog power supply voltage AVDD (wherein the voltage level of the analog power supply voltage AVDD decreases) may occur at the end time point Te of the blanking period BLK. When the overall voltage level of the analog power supply voltage AVDD increases in an attempt to compensate for the decrease in the voltage level of the analog power supply voltage AVDD in the initial portion of the active period ACT, the power consumption of the power management circuit 200 may increase. In addition, when the undershoot US of the analog power supply voltage AVDD occurs in the active period ACT of the output data voltage, flickering of an image due to the undershoot US of the analog power supply voltage AVDD may occur, which may cause a decrease in the display quality of the corresponding image.

[0063] like Figure 3 As shown in, according to one or more embodiments, the voltage level of the analog power supply voltage AVDD may increase in the blanking period BLK, for example, at the first increase time point TI1 within the blanking period BLK. Therefore, the voltage level of the analog power supply voltage AVDD at the end time point Te of the blanking period BLK may be higher than the voltage level of the analog power supply voltage AVDD at the start time point TS of the blanking period BLK. Therefore, in the effective period ACT of the output data voltage, the undershoot US of the analog power supply voltage AVDD may be offset or may not occur at all.

[0064] In addition, since the increased voltage level of the analog power supply voltage AVDD at the first increase time point TI1 is determined based on the size of the load current, the voltage level of the analog power supply voltage AVDD can be controlled based on the size of the load connected to the output terminal that outputs the analog power supply voltage AVDD. Therefore, when the size of the load is large, the voltage level of the analog power supply voltage AVDD may be greatly increased to prevent the undershoot US of the analog power supply voltage AVDD from occurring in the active period ACT. In addition, when the magnitude of the load is small, the voltage level of the analog power supply voltage AVDD may be slightly increased to reduce the power consumption of the power management circuit 200.

[0065] Figure 5 1 is a timing diagram showing the analog power supply voltage AVDD according to an embodiment. Figure 2 and Figure 5 Description of the components and operation of the power management circuit 200, which are described with reference to Figure 2 and Figure 3 The description of the components and operation of the power management circuit 200 is substantially the same or similar.

[0066] Reference Figure 2 and Figure 5 In an embodiment, the voltage converter 210 may calculate the target voltage level TVL based on the magnitude of the load current ILD, increase the voltage level of the analog power supply voltage AVDD to an intermediate voltage level MVL lower than the target voltage level TVL at a first increase time point TI1, and increase the voltage level of the analog power supply voltage AVDD to the target voltage level TVL at a subsequent second increase time point TI2 within a blanking period BLK. Therefore, the voltage level of the analog power supply voltage AVDD may be gradually increased (for example, in this case, increased twice) to the target voltage level TVL at the first increase time point TI1 and the second increase time point TI2. Therefore, the voltage level of the analog power supply voltage AVDD may be increased smoothly, and the voltage level of the analog power supply voltage AVDD may not be suddenly increased within the blanking period BLK. Although Figure 5 Only two steps are shown, but in other embodiments the analog supply voltage may be increased by more than two steps within the blanking period BLK (eg using multiple intermediate voltage levels).

[0067] In an embodiment, the second increase time point TI2 may occur after a predetermined step time T_ST starting from the first increase time point TI1. The step time T_ST may be less than the interval between the first increase time point TI1 and the end time point Te of the blanking period BLK. In an embodiment, the counter 230 may determine the first increase time point TI1 and the second increase time point TI2 by counting the clock signal CLK starting from the start time point TS of the blanking period BLK. For example, the counter 230 may determine the first increase time point TI1 and the second increase time point TI2 by counting the clock signal CLK starting from the time point when the rising edge of the tearing effect signal TE occurs. The counter 230 may generate a control signal CS for determining the first increase time point TI1 and the second increase time point TI2 by counting the clock signal CLK, and provide the control signal CS to the voltage converter 210.

[0068] Figure 6 It is shown that the Figure 2 FIG. 2 is a diagram of an example of a voltage converter 210 in a power management circuit 200 . Figure 7 is shown to flow through the Figure 6 FIG. 2 is a timing diagram of the current IL1 of the inductor L1 in the voltage converter 210 .

[0069] Reference Figure 6 and Figure 7 , the voltage converter 210 may include an inductor L1, a first transistor M1, a second transistor M2, and a gate driver 211. However, in other embodiments, the voltage converter 210 may have a different configuration.

[0070] The inductor L1 may be connected between the input terminal TIN and the node ND. An inductor current IL1 may flow through the inductor L1. A voltage level of the analog power supply voltage AVDD may be controlled based on the inductor current IL1.

[0071] The first transistor M1 may be connected between the node ND and the ground GND and turned on in response to the first control signal CS1. The first transistor M1 may include a gate electrode receiving the first control signal CS1, a first electrode connected to the node ND, and a second electrode connected to the ground GND. The first transistor M1 may control the inductor current IL1 to flow through the inductor L1.

[0072] The second transistor M2 may be connected between the node ND and the output terminal TOUT and turned on in response to the second control signal CS2. The second transistor M2 may include a gate electrode receiving the second control signal CS2, a first electrode connected to the node ND, and a second electrode connected to the output terminal TOUT. The second transistor M2 may control the inductor current IL1 to flow through the inductor L1. The second transistor M2 may be turned on alternately with the first transistor M1, for example, because the first transistor M1 and the second transistor M2 have different conductivity. For example, the second transistor M2 may be turned on after the first transistor M1 is turned on and an electromotive force is generated in the inductor L1, so that the voltage at the node ND can be converted into the analog power supply voltage AVDD.

[0073] In an embodiment, as described above, the first transistor M1 and the second transistor M2 may be transistors of different types. For example, the first transistor M1 may be an N-type transistor (e.g., an NMOS transistor), and the second transistor M2 may be a P-type transistor (e.g., a PMOS transistor). In another embodiment, the first transistor M1 and the second transistor M2 may be transistors of the same type.

[0074] The gate driver 211 may generate a first control signal CS1 and a second control signal CS2 based on the analog power supply voltage control signal AVDD_CS, the fourth voltage VOUT and the control signal CS. The first control signal CS1 may be in the first period D (eg, see Figure 7 ), and has a turn-on voltage level in a second period 1-D between the second time point TP2 and the third time point TP3. As the first transistor M1 is turned on in the first period D and the second transistor M2 is turned off in the first period D, the magnitude of the inductor current IL1 may increase in the first period D. The second control signal CS2 may have a turn-off voltage level in the first period D and have a turn-on voltage level in the second period 1-D. As the first transistor M1 is turned off in the second period 1-D and the second transistor M2 is turned on in the second period 1-D, the magnitude of the inductor current IL1 may decrease in the second period 1-D. As the magnitude of the inductor current IL1 repeatedly increases and decreases according to the duty ratio of the first period D and the second period 1-D, the voltage level of the analog power supply voltage AVDD may repeatedly increase and decrease in a corresponding manner.

[0075] The average magnitude ILA of the inductor current IL1 may be substantially equal to the magnitude of the inductor current IL1 at a reference time point TPR at which ½ of the second period 1-D has passed.

[0076] Figure 8 It is shown that the Figure 22 is a diagram of an example of a load sensor 220 in a power management circuit 200. Fig. 9 It is shown that the Figure 8 2 is a circuit diagram of an example of a half duty generating circuit 221 in a load sensor 220. Fig.10 is a diagram showing the provision of Fig. 9 FIG. 2 is a timing diagram of an example of the first voltage DIN of the half duty cycle generating circuit 221. FIG. Fig.11 is a diagram showing a method for providing a Figure 8 FIG. 1 is a timing diagram of an example of a second voltage D OUT of the sample and hold circuit 222 in the load sensor 220 . Fig.12 is a diagram showing the embodiment including Figure 8 2 is a circuit diagram of an example of a multiplier 223 in a load sensor 220.

[0077] Reference Figures 6 to 12 , the load sensor 220 may include a half duty cycle generating circuit 221, a sample and hold circuit 222, and a multiplier 223. In another embodiment, the load sensor 220 may have a different configuration.

[0078] The half duty cycle generation circuit 221 may generate a second voltage DOUT based on a first voltage DIN corresponding to the current IL1 flowing through the inductor L1. In an embodiment, the first voltage DIN may be a voltage between opposite terminals of the second transistor M2 (e.g., a voltage between the node ND and the output terminal TOUT). Therefore, the first voltage DIN may have a voltage level of 0 in the first period D, and have a voltage level corresponding to the inductor current IL1 in the second period 1-D.

[0079] like Fig. 9 As shown in , the half duty cycle generation circuit 221 may include a first inverter INV1, a second inverter INV2, a first resistor R1, a first capacitor C1, a third resistor R3, a third inverter INV3, a fourth inverter INV4, a second resistor R2, a second capacitor C2, a differential amplifier DA, a third capacitor C3 and a first amplifier AMP1. In another embodiment, the half duty cycle generation circuit 221 may have a different configuration.

[0080] The first inverter INV1 and the second inverter INV2 can use the input voltage VBAT as an operating voltage (or driving voltage) to transmit the first voltage DIN. The first resistor R1 can be connected between the output terminal of the second inverter INV2 and the first node N1. The first capacitor C1 can be connected between the first node N1 and a reference potential (e.g., ground). The third resistor R3 can be connected between the first node N1 and ground. The voltage of the first node N1 can correspond to the value obtained by multiplying the input voltage VBAT, the first voltage DIN and a predetermined value (e.g., a value of 0.5).

[0081] The third inverter INV3 and the fourth inverter INV4 can use the input voltage VBAT as an operating voltage (or a driving voltage) to transmit the second voltage DOUT (as a feedback voltage). The second resistor R2 can be connected between the output terminal of the fourth inverter INV4 and the second node N2. The second capacitor C2 can be connected between the second node N2 and a reference potential (e.g., ground). The voltage of the second node N2 can correspond to the value obtained by multiplying the input voltage VBAT and the second voltage DOUT.

[0082] The differential amplifier DA may output a voltage difference between a voltage of the first node N1 and a voltage of the second node N2 to a third node N3. The third capacitor C3 may be connected between the third node N3 and ground. The first amplifier AMP1 may output a second voltage DOUT corresponding to a difference between a voltage of the third node N3 applied to a non-inverting terminal and a reference voltage VM applied to an inverting terminal.

[0083] The sampling and holding circuit 222 can generate the third voltage VIN by sampling the voltage level of the second voltage DOUT at the reference time point TPR within the conduction period of the second transistor M2. The conduction period of the second transistor M2 may be, for example, the second period 1-D. Since the magnitude of the inductor current IL1 at the reference time point TPR corresponds to the average magnitude ILA of the inductor current IL1, the voltage level of the third voltage VIN may be the average voltage level of the first voltage DIN within the second period 1-D. Therefore, the voltage level of the third voltage VIN may correspond to the average magnitude ILA of the inductor current IL1.

[0084] The multiplier 223 may generate a fourth voltage VOUT corresponding to the load current ILD by multiplying the third voltage VIN by the on-period of the first transistor M1. The on-period of the first transistor M1 may be a first period D.

[0085] like Fig.12As shown in , the multiplier 223 may include a second amplifier AMP2, a switch SW, a fifth inverter INV5, a third transistor M3, a fourth resistor R4, and a fourth capacitor C4. In another embodiment, the multiplier 223 may have a different configuration.

[0086] The non-inverting terminal of the second amplifier AMP2 can receive the third voltage VIN, the output terminal of the second amplifier AMP2 can be connected to the fourth node N4, and the inverting terminal of the second amplifier AMP2 can be connected to the output terminal of the second amplifier AMP2. The switch SW can be connected between the fourth node N4 and the fifth node N5. The switch SW can be turned on in response to the second control signal CS2. The fifth inverter INV5 can invert the second control signal CS2. The third transistor M3 can be connected between the fifth node N5 and the ground GND, and is turned on in response to the inverted second control signal CS2. The fourth resistor R4 can be connected between the fifth node N5 and the sixth node N6. The fourth capacitor C4 can be connected between the sixth node N6 and the ground GND. The voltage of the sixth node N6 can correspond to the fourth voltage VOUT, and the fourth voltage VOUT can correspond to the value obtained by multiplying the third voltage VIN and the first period D.

[0087] Fig.13 is a block diagram showing an electronic device 1100 according to an embodiment.

[0088] Reference Fig.13 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems.

[0089] The processor 1110 may perform a specific calculation or task. In an embodiment, the processor 1110 may be a microprocessor or a central processing unit (CPU), etc. The processor 1110 may be connected to other components via an address bus, a control bus, and a data bus, etc. In an embodiment, the processor 1110 may also be connected to an expansion bus (such as a peripheral component interconnect (PCI) bus). In an embodiment, the processor 1110 may provide the first image data ( Figure 1 The first image data IMD1 in the image and the controller control signal ( Figure 1 The controller control signal CONT in the controller).

[0090] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include: a nonvolatile memory device (such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM)) and / or a volatile memory device (such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.)

[0091] The storage device 1130 may include a solid state drive (SSD), a hard disk drive (HDD), and a compact disk read-only memory (CD-ROM). The I / O device 1140 may include an input device (such as a keyboard, a keyboard, a touch pad, a touch screen, or a mouse) and an output device (such as a speaker or a printer). The power supply 1150 may provide the power required for the electronic device 1100 to operate. In an embodiment, the power supply 1150 may provide an input voltage ( Figure 1 The display device 1160 may be connected to other components via a bus or other communication link. The display device 1160 may correspond to Figure 1 The display device 100.

[0092] In the power management circuit included in the display device 1160, the voltage level of the analog power supply voltage may be increased based on the load current at the first increase time point within the blanking period. Therefore, the undershoot of the analog power supply voltage may be partially offset or completely prevented from occurring in the effective period after the blanking period. Therefore, the formation of the analog power supply voltage ripple may be reduced or prevented. In addition, in the display device 1160, the undershoot of the analog power supply voltage may not occur, so that the power consumption of the display device 1160 may be reduced. In addition, the ripple of the analog power supply voltage may be reduced or prevented, so that the display quality of the display device may be improved.

[0093] The display device according to the embodiment can be applied to display devices included in computers, notebook computers, mobile phones, smart phones, smart tablets, smart watches, portable media players (PMPs), personal digital assistants (PDAs), or moving picture expert group standard audio layer 3 (MP3) players, etc.

[0094] The methods, processes and / or operations described herein can be performed by codes or instructions executed by computers, processors, controllers or other signal processing devices. Computers, processors, controllers or other signal processing devices can be those described herein, or can be one outside the elements described herein. Due to the detailed description of the algorithm constituting the basis of the method (or the operation of a computer, processor, controller or other signal processing device), the code or instructions for implementing the operation of the method embodiment can convert a computer, processor, controller or other signal processing device into a special processor for performing the method herein.

[0095] In addition, another embodiment may include a computer-readable medium (e.g., a non-transitory computer-readable medium) for storing the code or instructions. The computer-readable medium may be such a volatile or non-volatile memory or other storage device, which may be detachably or fixedly coupled to a computer, processor, controller or other signal processing device, which executes the code or instructions for performing the operations of the method embodiments or apparatus embodiments herein.

[0096] The controllers, processors, devices, multiplexers, amplifiers, circuits, drivers, counters, converters, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented, for example, in non-transient logic, which may include hardware, software, or both hardware and software. When implemented at least in part in hardware, the controllers, processors, devices, multiplexers, amplifiers, circuits, drivers, counters, converters, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to application specific integrated circuits, field programmable gate arrays, logic gate combinations, systems on chip, microprocessors, or other types of processing or control circuits. In some embodiments, these functions may be implemented by neural networks, machine learning logic, or other forms of artificial intelligence.

[0097] When implemented at least in part in software form, controllers, processors, devices, multiplexers, amplifiers, circuits, drivers, counters, converters, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing codes or instructions executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein, or may be one other than the elements described herein. Since the algorithms underlying the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiment may transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0098] Although the display device and the power management circuit according to the embodiments of the present invention have been described with reference to the accompanying drawings, the described embodiments are exemplary and can be modified and changed by a person having ordinary knowledge in the relevant technical field without departing from the technical spirit described in the appended claims. The embodiments can be combined to form additional embodiments.

Claims

1. A display device, wherein: The display device comprises: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel; and A power management circuit is configured to generate an analog power supply voltage and provide the analog power supply voltage to the data driver through an output terminal, wherein the power management circuit is configured to measure a load current output through the output terminal, and the power management circuit increases the voltage level of the analog power supply voltage based on the load current at a first increase time point within a blanking period.

2. The display device according to claim 1, wherein: The power management circuit is configured to: calculating a target voltage level based on the magnitude of the load current, and The voltage level of the analog power supply voltage is increased to the target voltage level at the first increase time point.

3. The display device according to claim 2, wherein: The target voltage level increases as the magnitude of the load current increases.

4. The display device according to claim 1, wherein: The power management circuit is configured to: Calculating a target voltage level based on the magnitude of the load current, increasing the voltage level of the analog power supply voltage to an intermediate voltage level lower than the target voltage level at the first increase time point, and The voltage level of the analog power supply voltage is increased to the target voltage level at a second increasing time point within a blanking period after the first increasing time point.

5. The display device according to claim 1, wherein: The power management circuit is configured to measure the load current in an active period preceding the blanking period.

6. The display device according to claim 1, wherein: The power management circuit comprises: a voltage converter configured to convert an input voltage received through an input terminal into the analog power supply voltage; and The load sensor is configured to measure the load current.

7. A power management circuit, wherein: The power management circuit comprises: a voltage converter configured to convert an input voltage received through the input terminal into an analog power supply voltage and provide the analog power supply voltage through the output terminal; and A load sensor is configured to measure a load current output through the output terminal, wherein the voltage converter is configured to increase a voltage level of the analog power supply voltage based on the load current at a first increase time point within a blanking period.

8. The power management circuit according to claim 7, wherein: The voltage converter is configured as: calculating a target voltage level based on the magnitude of the load current, and The voltage level of the analog power supply voltage is increased to the target voltage level at the first increase time point.

9. The power management circuit according to claim 8, wherein: The target voltage level increases as the magnitude of the load current increases.

10. The power management circuit according to claim 7, wherein: The voltage converter is configured as: Calculating a target voltage level based on the magnitude of the load current, increasing the voltage level of the analog power supply voltage to an intermediate voltage level lower than the target voltage level at the first increase time point, and The voltage level of the analog power supply voltage is increased to the target voltage level at a second increasing time point within a blanking period after the first increasing time point.

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