Shift register, driving circuit, display device and driving method

Abstract

The invention provides a shift register, a driving circuit, a display device and a driving method, and relates to the technical field of display. The shift register comprises a shift circuit configured to shift a first clock signal from a first clock end, a second clock signal from a second clock end, a first power supply voltage of a first power supply, a second power supply voltage of a second power supply and a first input signal from a first input end under the control of the first clock signal from the first clock end, the second clock signal from the second clock end, the first power supply voltage and the second power supply voltage; controlling the potentials of the first node and the second node; the gating circuit is configured to provide a first gating signal from a first gating end to a third node under the control of a gating input signal from a gating input end; the control circuit is configured to provide the potential of the first node to a fourth node under the control of the potential of the third node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to the first output end as a first output signal under the control of the potential of the fourth node and the potential of the second node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a display device and a driving method. Background Art

[0002] In order to achieve good compatibility between power consumption and high refresh rate, display products usually adopt regional refresh technology. By controlling the output of driving signals within a frame, it is possible to update only the data signals of some rows in the display product.

[0003] Display products usually use TFT (Thin Film Transistor) as a switch tube or driver tube. Due to the leakage of TFT, when using regional refresh technology, problems such as flickering bright and dark lines are prone to occur at the critical position of the refresh frequency switching. Summary of the invention

[0004] To at least partially solve the above problems, the present disclosure provides a shift register, a driving circuit, a display device and a driving method.

[0005] One aspect of the present disclosure provides a shift register, comprising: a shift circuit, configured to control the potentials of a first node and a second node under the control of a first clock signal from a first clock terminal, a second clock signal from a second clock terminal, a first power supply voltage of a first power supply, a second power supply voltage of a second power supply and a first input signal from a first input terminal; a gating circuit, configured to provide a first gating signal from a first gating terminal to a third node under the control of a gating input signal from a gating input terminal; a control circuit, configured to provide the potential of the first node to a fourth node under the control of the potential of the third node; and an output circuit, configured to provide the first power supply voltage or the second power supply voltage to a first output terminal as a first output signal under the control of the potential of the fourth node and the potential of the second node.

[0006] Another aspect of the present disclosure provides a driving circuit, comprising M cascaded shift registers as described above, where M is an integer greater than 1.

[0007] Another aspect of the present disclosure provides a display device including the driving circuit as described above.

[0008] Another aspect of the present disclosure provides a driving method, which is applied to the shift register as described above, and the method includes: in a gating phase, controlling the first gating signal to be a first level; and in a non-gating phase, controlling the first gating signal to be a second level. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic structural diagram of an exemplary pixel circuit is shown.

[0010] Figure 2A A schematic structural diagram of an exemplary shift register is shown.

[0011] Figure 2B A signal timing diagram of an exemplary shift register is shown.

[0012] Figure 2C A signal waveform diagram of an exemplary shift register is shown.

[0013] Figure 3 The block diagram of the shift register according to the embodiment of the present disclosure is schematically shown.

[0014] Figure 4 A block diagram of a shift register according to another embodiment of the present disclosure is schematically shown.

[0015] Figure 5A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0016] Figure 5B The waveform diagram of the output signal of the shift register in the high refresh frequency region according to the embodiment of the present disclosure is shown.

[0017] Figure 5C The waveform diagram of the output signal of the shift register in the low frequency region according to the embodiment of the present disclosure is shown.

[0018] Figure 5D A signal timing diagram of a shift register according to an embodiment of the present disclosure is shown.

[0019] Fig. 6A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0020] Figure 6B A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0021] Fig. 7A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0022] Figure 7B A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0023] Figure 8 A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0024] Fig. 9A block diagram of a shift register according to another embodiment of the present disclosure is schematically shown.

[0025] Fig.10 A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0026] Fig.11 The schematic diagram shows the structure of a driving circuit according to an embodiment of the present disclosure.

[0027] Fig. 12A The schematic diagram shows a structure of a driving circuit according to another embodiment of the present disclosure.

[0028] Fig. 12B The schematic diagram shows a structure of a driving circuit according to another embodiment of the present disclosure.

[0029] Fig.13 The structural diagram of a display device according to an embodiment of the present disclosure is schematically shown.

[0030] Fig.14 The flowchart of the driving method according to the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0033] In addition, in the description of the embodiments of the present disclosure, the term "electrically connected" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0034] The source and drain of the switch transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiment of the present disclosure, according to its function, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0035] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish that the amplitudes of the two power supply voltages are different. For example, the following description is made by taking the "first power supply voltage" as a relatively low voltage and the "second power supply voltage" as a relatively high voltage as an example. Those skilled in the art will understand that the present disclosure is not limited to this.

[0036] It should be noted that in the description of the embodiments of the present disclosure, INPUT1 can represent both the first input signal terminal and the first input signal provided by the first input terminal. Similarly, the symbol CK can represent both the first clock terminal and the first clock signal provided by the first clock terminal; the symbol CB can represent both the second clock terminal and the second clock signal provided by the second clock terminal; OUT1 can represent both the first output terminal and the first output signal output by the first output terminal; VGL can represent both the first power supply and the first power supply voltage; VGH can represent both the second power supply and the second power supply voltage; MS1 can represent both the first selection terminal and the first selection signal, and so on. The following embodiments are the same and will not be repeated.

[0037] Figure 1 A schematic structural diagram of an exemplary pixel circuit is shown.

[0038] like Figure 1 As shown, the pixel circuit 100 may be a 7T1C pixel circuit. In the pixel circuit 100, transistors M1 to M2 and transistors M4 to M7 may be switch transistors, transistor M3 is a driving transistor, transistors M3 to M7 are P-type transistors, and transistors M1 and M2 are N-type transistors.

[0039] In the T1 phase of the pixel circuit 100, the enable signal EM is at a high level and controls the transistors M5 and M6 to be turned off; the reset signal RST1 is at a high level and controls the transistor M1 to be turned on, so as to pull the potential of the node Q1 down to the initialization signal Vinit1, so that the capacitor Cst can be reset by the initialization signal Vinit.

[0040] In the T2 phase of the pixel circuit 100, the reset signal RST1 is at a low level and the control transistor M1 is turned off; the drive signal NGate is at a high level and the control transistor M2 is turned on, the drive signal PGate is at a low level and the control transistor M4 is turned on, and the data signal Vdata is charged to the capacitor Cst through the transistor M4, the drive transistor M3 and the transistor M2. When Vgs of the drive transistor M3 = V(Q1)-V(Q2) = V(Q1)-Vdata = Vth, the drive transistor M3 is turned off, and the voltage maintained by the capacitor Cst is V(Q1) = Vdata + Vth. At the same time, the drive signal PGate is at a low level and the control transistor M7 is turned on, so as to use the initialization signal Vinit to reset the anode of the light emitting element EL.

[0041] In the T3 stage of the operation of the pixel circuit 100, the driving signal NGate is at a low level and controls the transistor M2 to be turned off, the driving signal PGate is at a high level and controls the transistors M4 and M7 to be turned off, the enable signal EM is at a low level and controls the transistors M5 and M6 to be turned on, and the Vgs of the driving transistor M3 is V(Q1)-V(Q2)=Vdata+Vth-ELVDD, so that the light-emitting element EL can emit light according to the potential of the data signal Vdata.

[0042] In the pixel circuit of this example, if the driving signal NGate is at a high level, the transistor M2 is turned on, and the data signal Vdata can be written into the pixel circuit 100, thereby updating the brightness of the light-emitting element EL of the pixel circuit 100. Accordingly, the pixel row where the pixel circuit 100 is located is refreshed in the current frame. If the driving signal NGate is low, the transistor M2 is always turned off, the data signal Vdata will not be written into the pixel circuit 100, the brightness of the light-emitting element EL will not change, and the brightness of the pixel row where the pixel circuit 100 is located in the current frame remains unchanged.

[0043] Therefore, by controlling the potential of the driving signal NGate, it is possible to determine whether the pixel brightness is refreshed, thereby achieving partial refresh of the display screen. In display products, a shift register can usually be used to enable the driving signal NGate.

[0044] Figure 2A A schematic structural diagram of an exemplary shift register is shown.

[0045] like Figure 2A As shown, an exemplary shift register 200 may be a 16T3C+10T4C circuit.

[0046] In the high frequency region, the selection signal MS is at a low level. When the input signal Scan(n-1) and the input signal Q9(n-2) are both at a low level, the transistors M8 and M9 are turned on, the selection signal MS applies a low level to the node Q3, the transistor M10 is turned on, and the potential of the node Q4 is equal to the potential of the node Q5. When the input signal Scan(n-1) is at a high level, the potentials of the nodes Q5 and Q4 are both low, the transistor M11 is turned on, and the drive signal NGate outputted from the output end is VGH. When the input signal Scan(n-1) is at a low level, the potentials of the nodes Q5 and Q4 are both high, the transistor M11 is turned off, and the transistor M12 is turned on. In addition, when the clock signal CB is low, the potential of the node Q6 is further pulled down, and the potential of the node Q7 is also a potential lower than VGL, so the transistor M13 is turned on, and the drive signal NGate outputted from the output end is VGL.

[0047] In the low frequency region, the selection signal MS is at a high level. When the input signal Scan(n-1) and the input signal Q9(n-2) are both at a low level, the transistors M8 and M9 are turned on, the selection signal MS is applied at a high level to the node Q3, and the transistor M10 is turned off. When the input signal Scan(n-1) is at a low level, the potential of the node Q5 is high, the potential of the node Q8 is low, and the output end outputs a step-shaped signal; when the clock signal CB changes from a high level to a low level, the potentials of the nodes Q6 and Q7 are further pulled down due to the bootstrap effect of the capacitor, and the drive signal NGate outputted from the output end is VGL. When the input signal Scan(n-1) is at a high level, the low potential of the node Q5 cannot be applied to the node Q4 due to the cut-off of the transistor M10, therefore, the node Q4 remains at a high level, the transistor M11 remains cut-off, and at the same time, the node Q7 remains at a low level, the transistor M13 remains turned on, and the drive signal NGate outputted from the output end is VGL.

[0048] Therefore, in the high-frequency region, the level of the driving signal NGate outputted from the output end can change with the change of the input signal Scan(n-1), while in the low-frequency region, no matter whether the input signal Scan(n-1) is at a high level or a low level, the driving signal NGate outputted from the output end is always VGL, thereby realizing the selection of the driving signal NGate.

[0049] However, due to the precision of components and process factors, the shift register cannot work in an ideal state, resulting in a high incidence of bright band problems at the critical position of the refresh frequency switching. When the selection signal MS switches from high frequency to low frequency, the signal timing diagram and signal waveform diagram of the shift register 200 can be respectively as shown in FIG. Figure 2B and Figure 2C shown.

[0050] Figure 2Bshows a signal timing diagram of an example shift register, Figure 2C FIG. 1 shows a signal waveform diagram of an exemplary shift register. Figure 2C In FIG. 1 , the solid line may represent the signal waveform of the last row of the high frequency, and the dotted line may represent the signal waveform of the normal row of the high frequency.

[0051] like Figure 2B and Figure 2C As shown, in this example, when the selection signal MS is switched from high frequency to low frequency, it is necessary to experience the process of switching the selection signal MS from low level to high level. At this time, the gate voltages of transistors M8 and M9 will be different from those of the last row in the high frequency area relative to the normal row in the high frequency area, so that the cut-off degree of transistors M8 and M9 is not sufficient, resulting in the high level of the selection signal MS being applied to node Q3 through leakage, thereby affecting the potential of node Q3. The potential of node Q3 will slowly increase, so that the conduction degree of transistors M10 and M12 is not sufficient, so that the potential of node Q7 is not low enough, and thus the conduction degree of transistor M13 is not as sufficient as that of the normal row in the high frequency area, resulting in the drive signal NGate outputted by the last row in the high frequency area not being low enough, and the output drive signal NGate has a higher step. Therefore, the pixel current outputted by the last row in the high frequency area is different from the pixel current outputted by the normal row in the high frequency area, and the last row in the high frequency area will have problems such as flickering bright and dark lines.

[0052] For example, a plurality of shift registers 200 connected in cascade can drive a plurality of pixel rows in a pixel array. For example, the low levels of the plurality of drive signals NGate output by the plurality of shift registers 200 connected in cascade are shifted and output in sequence. For example, when the drive signal NGate is at a high level, the pixel circuit can be refreshed by the data signal, and at this time, the effective level of the drive signal NGate is at a high level. When the effective level of the drive signal NGate output by the shift register lasts for a long time, there is a period in which the drive signals NGate output by the two adjacent shift registers are at a high level at the same time. For example, a multi-stage shift register shifts and outputs a drive signal NGate having a high level, and before the drive signal NGate output by the m-th shift register jumps from a high level to a low level, the drive signal NGate output by the m+1-th shift register jumps from a low level to a high level.

[0053] When the cascaded multiple shift registers 200 scan multiple pixel rows row by row, the level of the selection signal MS may jump. For example, the cascaded multiple shift registers 100 may include 1000-level shift registers. When the first 500-level shift registers sequentially output the drive signal NGate, the selection signal MS is at a low level. At this time, the first 500-level shift registers sequentially output the drive signal NGate to refresh the first 500 pixel rows in the pixel circuit. When the last 500-level shift registers sequentially output the drive signal NGate, the selection signal MS jumps from a low level to a high level. At this time, the level of the drive signal NGate sequentially output by the last 500-level shift registers is always at a high level, and the last 500 pixel rows in the pixel circuit are not refreshed.

[0054] After the driving signal NGate outputted by the 500th level jumps from a high level to a low level, the selection signal MS may jump from a low level to a high level. At this time, the moment of the level jump of the selection signal MS may occur after the driving signal NGate outputted by the 501st level shift register jumps from a low level to a high level and before the high level jumps to a low level. At this time, the driving signal NGate outputted by the 501st level shift register appears at a high level. In this case, as described above, the transistor M2 in the pixel circuit 100 is briefly turned on, causing the data signal to be partially written, so that the 501st pixel row will have a display abnormality problem.

[0055] In view of this, the present disclosure provides a shift register to at least partially solve the problem of flickering bright and dark lines at the high-frequency switching low-frequency position.

[0056] Figure 3 The block diagram of the shift register according to the embodiment of the present disclosure is schematically shown.

[0057] like Figure 3 As shown, the shift register 300 may include a shift circuit 310 , a gating circuit 320 , a control circuit 330 , and an output circuit 340 .

[0058] The shift circuit 310 may be electrically connected to the first input terminal INPUT1, the first clock terminal CK, the second clock terminal CB, the first power supply VGL, and the second power supply VGH. Under the control of the first clock signal CK from the first clock terminal CK, the second clock signal CB from the second clock terminal CB, the first power supply voltage VGL of the first power supply VGL, the second power supply voltage VGH of the second power supply VGH, and the first input signal INPUT1 from the first input terminal INPUT1, the shift circuit 310 may control the potentials of the first node N1 and the second node N2.

[0059] The gate circuit 320 may be electrically connected to the gate input terminal MSINPUT and the first gate terminal MS1. Under the control of the gate input signal MSINPUT from the gate input terminal MSINPUT, the gate circuit 320 may provide the first gate signal MS1 from the first gate terminal MS1 to the third node N3.

[0060] For example, the selection input signal MSINPUT can control the selection circuit 320 to switch between the on and off states. When the selection input signal MSINPUT controls the selection circuit 320 to be in the on state, the first selection signal MS1 is written into the third node N3. When the selection input signal MSINPUT controls the selection circuit 320 to be in the off state, the potential of the third node N3 can maintain the state of the previous stage.

[0061] Under the control of the potential of the third node N3 , the control circuit 330 may provide the potential of the first node N1 to the fourth node N4 .

[0062] For example, the potential of the third node N3 can control the control circuit 330 to switch between the on and off states. When the potential of the third node N3 controls the control circuit 330 to be in the on state, the potential of the first node N1 is written into the fourth node N4. When the potential of the third node N3 controls the control circuit 330 to be in the off state, the potential of the fourth node N4 can maintain the state of the previous stage.

[0063] The output circuit 340 may be electrically connected to the first power supply VGL, the second power supply VGH and the first output terminal OUT1. Under the control of the potential of the fourth node N4 and the potential of the second node N2, the output circuit 340 may provide the first power supply voltage VGL or the second power supply voltage VGH to the first output terminal OUT as the first output signal OUT1.

[0064] For example, the potential of the second node N2 can control the first power supply VGL and the first output terminal OUT1 to be in a connected state or a cut-off state. When the first power supply VGL and the first output terminal OUT1 are in a connected state, the output circuit 340 provides the first power supply voltage VGL to the first output terminal OUT1, and the first output terminal OUT1 outputs a low level signal.

[0065] For example, the potential of the fourth node N2 can control the second power supply VGH and the first output terminal OUT1 to be in a connected state or a cut-off state. When the second power supply VGH and the first output terminal OUT1 are in a connected state, the output circuit 340 provides the second power supply voltage VGH to the first output terminal OUT1, and the first output terminal OUT1 outputs a high level signal.

[0066] In the embodiment of the present disclosure, the first input signal OUT1 may be a scanning signal for driving the transistor M2 in the pixel circuit 100 described above. For example, when the level of the first input signal OUT is high, the transistor M2 is turned on, and the data signal can be written, thereby achieving screen refresh. When the level of the first input signal OUT is low, the transistor M2 is turned off, and the data signal cannot be written, thereby achieving the screen not being refreshed and remaining unchanged.

[0067] According to an embodiment of the present disclosure, by directly providing the potential of the second node N2 in the shift circuit 310 to the output circuit 340, when the first selection signal MS1 is switched between high and low levels, the fluctuation of the potential of the third node N3 will not affect the potential of the second node N2, thereby improving the bright band problem at the critical position of the refresh frequency switching and effectively improving the display performance.

[0068] Optionally, under the control of the first clock signal CK, the first power supply voltage VGL, and the first input signal INPUT1 , the shift circuit 310 may provide at least one of the second power supply voltage VGH and the second clock signal CB to the first node N1 .

[0069] For example, based on the first clock signal CK and the first power supply voltage VGL, the shift circuit 310 can control the second clock terminal CB and the first node N1 to be in a connected state or a cut-off state. Based on the first clock signal CK and the first input signal INPUT1, the shift circuit 310 can control the second power supply VGH and the first node N1 to be in a connected state or a cut-off state.

[0070] When the second clock terminal CB is connected to the first node N1, the shift circuit 310 provides the second clock signal CB to the first node N1. Or when the second power supply VGH is connected to the first node N1, the shift circuit 310 provides the second power supply voltage VGH to the first node N1. Or when the second clock terminal CB is connected to the first node N1 and the second power supply VGH is connected to the first node N1, the shift circuit 310 provides the second clock signal CB and the second power supply voltage VGH to the first node N1.

[0071] Optionally, under the control of the potential of the first clock signal CK1 , the shift circuit 310 may provide the first input signal INPUT1 to the second node N2 .

[0072] For example, based on the first clock signal CK1, the shift circuit 310 can control the first input terminal INPUT1 to be in a connected state or a cutoff state with the second node N2. When the first input terminal INPUT1 is in a connected state with the second node N2, the shift circuit 310 provides the first input signal INPUT1 to the second node N2.

[0073] Optionally, the gate circuit 320 may also be electrically connected to the first power supply VGL and the fourth input terminal. Under the control of the fourth input signal from the fourth input terminal, the gate circuit 320 may control the potential of the third node N3 using the first power supply voltage VGL.

[0074] In the embodiment of the present disclosure, the gating circuit 320 is electrically connected to the fourth input terminal, the third node N3 and the first power supply VGL. Under the control of the fourth input signal, the gating circuit 320 can reset the third node N3 using the first power supply voltage VGL and pull down the potential of the third node N3.

[0075] For example, based on the fourth input signal, the gate circuit 320 can control the first power supply VGL and the third node N3 to be in a connected state or a cut-off state. When the first power supply VGL and the third node N3 are in a connected state, the gate circuit 320 provides the first power supply voltage VGL to the third node N3.

[0076] For example, when the potential of the third node N3 is at a high level, the first output signal OUT1 output by the output circuit 340 does not refresh the corresponding pixel row. After the display screen refreshes a frame, the gating circuit 320 pulls the potential of the third node N3 down again, so that in the refresh process of the next frame, the gating signal MS controls the potential of the third node N3 again. After the display screen refreshes a frame, when the potential of the third node N3 is at a low level, the gating circuit 320 also writes the first power supply voltage VGL into the third node N3 to ensure that the potential of the third node N3 is stably maintained at a low potential. Resetting the potential of the third node N3 based on the gating circuit 320 can improve the working stability of the circuit.

[0077] Optionally, under the control of the potential of the third node N3, the control circuit 330 may also control the potential of the fourth node N4.

[0078] For example, under the control of the potential of the fourth node N4, the control circuit 330 may store the level of the first selection signal MS1 to stabilize the potential of the third node N3.

[0079] Optionally, the control circuit 330 may also be electrically connected to the first power supply VGL. Under the control of the first power supply voltage VGL, the control circuit 330 may control the potential of the third node N3.

[0080] For example, under the control of the first power source VGL, the control circuit 330 may store the level of the first selection signal MS1 to stabilize the potential of the third node N3.

[0081] Optionally, the control circuit 330 may also be electrically connected to the second power supply VGH and the second node N2. Under the control of the potential of the second node N2, the control circuit 330 may control the potential of the fourth node N4 using the second power supply voltage VGH.

[0082] For example, based on the potential of the second node N2, the control circuit 330 can control the second power supply VGH and the fourth node N4 to be in a connected state or a cut-off state. When the second power supply VGH and the fourth node N4 are in a connected state, the control circuit 330 can provide the second power supply voltage VGH to the fourth node N4, and the voltage of the fourth node N4 is at a high level. Under the control of the high level, the first input terminal OUT1 and the second power supply VGH are in a cut-off state, so that the second power supply voltage VGH can be prevented from affecting the first output terminal OUT1 to output a low-level signal.

[0083] Optionally, the control circuit 330 may also be electrically connected to the second strobe terminal and the second power supply VGH. Under the control of the second strobe signal from the second strobe terminal, the control circuit 330 may control the potential of the fourth node N4 using the second power supply voltage VGH.

[0084] For example, based on the potential of the second selection signal, the control circuit 330 can control the second power supply VGH and the fourth node N4 to be in a connected state or a cut-off state. When the second power supply VGH and the fourth node N4 are in a connected state, the control circuit 330 can provide the second power supply voltage VGH to the fourth node N4, and the voltage of the fourth node N4 is at a high level. Under the control of the high level, the first input terminal OUT1 and the second power supply VGH are in a cut-off state, so that the second power supply voltage VGH can be prevented from affecting the first output terminal OUT1 to output a low-level signal.

[0085] In an embodiment of the present disclosure, the second selection signal may be an inverted signal of the first selection signal MS1 .

[0086] Optionally, the selection input signal MSINPUT may come from another shift register cascaded with the shift register 300. The selection input signal MSINPUT provided by the other shift register may be used to select the first output signal OUT1 output by the shift register 300.

[0087] For example, the shift register 300 may be an m-th stage shift register, and the selection input terminal MSINPUT may be electrically connected to the second output terminal of the m-1-th stage shift register and the m-2-th stage shift register, respectively.

[0088] Figure 4 A block diagram of a shift register according to another embodiment of the present disclosure is schematically shown.

[0089] like Figure 4 As shown, the shift register 400 may include a shift circuit 410, a gating circuit 420, a control circuit 430, and an output circuit 440. In the embodiment of the present disclosure, the shift circuit 410, the control circuit 430, and the output circuit 440 are similar to the shift circuit 310, the control circuit 330, and the output circuit 340 described above, respectively, and are not described again for simplicity.

[0090] The gating input terminal MSINPUT connected to the gating circuit 420 may include a first input terminal INPUT1 and a second input terminal INPUT2, and accordingly, the gating input signal MSINPUT may include a first input signal INPUT2 from the first input terminal INPUT1 and a second input signal INPUT2 from the second input terminal INPUT2. Under the control of the first input signal INPUT2 from the first input terminal INPUT1 and the second input signal INPUT2 from the second input terminal INPUT2, the gating circuit 420 may provide the first gating signal MS1 from the first gating terminal MS1 to the third node N3.

[0091] For example, the first input signal INPUT2 and the second input signal INPUT2 can control the gating circuit 420 to switch between the on and off states. When the first input signal INPUT2 and the second input signal INPUT2 control the gating circuit 420 to be in the on state, the first gating signal MS1 is written into the third node N3. When the first input signal INPUT2 and the second input signal INPUT2 control the gating circuit 420 to be in the off state, the potential of the third node N3 can maintain the state of the previous stage.

[0092] Optionally, under the control of the potential of the first node N1, the potential of the second node N2 and the first power voltage VGL, the shift circuit 410 provides the second power voltage VGH or the first power voltage VGL to the second output terminal OUT2 as the second output signal OUT2.

[0093] For example, based on the potential of the second node N2 and the first power supply voltage VGL, the shift circuit 410 can control the first power supply VGL and the second input terminal OUT2 to be in a connected state or a cut-off state.

[0094] In the embodiment of the present disclosure, the second output signal OUT2 outputted from the second input terminal OUT2 is provided to other shift registers cascaded with the shift register 400 to implement shift driving of the cascaded multiple shift registers.

[0095] For example, the shift register 400 may be an m-th shift register, the second output signal OUT2 may be provided to the first input terminal of the m+1-th shift register, or the second output signal OUT2 may be provided to the first input terminal of the m+2-th shift register.

[0096] Optionally, the control circuit 430 may also be electrically connected to the second output terminal OUT2 and the second power supply VGH. Under the control of the second output signal OUT2, the control circuit 430 may control the potential of the fourth node N4 using the second power supply voltage VGH.

[0097] For example, based on the potential of the second output signal OUT2, the control circuit 330 can control the second power supply VGH and the fourth node N4 to be in a connected state or a cut-off state. When the second power supply VGH and the fourth node N4 are in a connected state, the control circuit 330 can provide the second power supply voltage VGH to the fourth node N4, and the voltage of the fourth node N4 is at a high level. Under the control of the high level, the first input terminal OUT1 and the second power supply VGH are in a cut-off state, so that the second power supply voltage VGH can be prevented from affecting the first output terminal OUT1 to output a low-level signal.

[0098] Figure 5A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0099] like Figure 5A As shown, the shift register 500 may include a shift circuit 510 , a gating circuit 520 , a control circuit 530 , and an output circuit 540 .

[0100] The output circuit 540 may include a first transistor T1 , a second transistor T2 , and a first capacitor C1 .

[0101] A gate of the first transistor T1 is electrically connected to the fourth node N4 , a first electrode of the first transistor T1 is electrically connected to the second power supply VGH, and a second electrode of the first transistor T1 is electrically connected to the first output terminal OUT1 .

[0102] A gate of the second transistor T2 is electrically connected to the second node N2 , a first electrode of the second transistor T2 is electrically connected to the first output terminal OUT1 , and a second electrode of the second transistor T2 is electrically connected to the first power supply VGL.

[0103] A first end of the first capacitor C1 is electrically connected to the second power source VGH, and a second end of the first capacitor C1 is electrically connected to the fourth node N4.

[0104] The gating circuit 520 may include a third transistor T3 , a fourth transistor T4 , and a fifth transistor T5 .

[0105] A gate of the third transistor T3 is electrically connected to the first input terminal INPUT1 , a first electrode of the third transistor T3 is electrically connected to the third node N3 , and a second electrode of the third transistor T3 is electrically connected to the fifth node N5 .

[0106] A gate of the fourth transistor T4 is electrically connected to the second input terminal INPUT2 , a first electrode of the fourth transistor T4 is electrically connected to the fifth node N5 , and a second electrode of the fourth transistor T4 is electrically connected to the first selection terminal MS1 .

[0107] A gate of the fifth transistor T5 is electrically connected to the fourth input terminal INPUT4 , a first electrode of the fifth transistor T5 is electrically connected to the third node N3 , and a second electrode of the fifth transistor T5 is electrically connected to the first power source VGL.

[0108] The control circuit 530 may include a sixth transistor T6, a seventh transistor T7, and a second capacitor C2.

[0109] A gate of the sixth transistor T6 is electrically connected to the third node N3 , a first electrode of the sixth transistor T6 is electrically connected to the first node N1 , and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4 .

[0110] A gate of the seventh transistor T7 is electrically connected to the second node N2 , a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4 , and a second electrode of the seventh transistor T7 is electrically connected to the second power supply VGH.

[0111] A first end of the second capacitor C2 is electrically connected to the fourth node N4 , and a second end of the second capacitor C2 is electrically connected to the third node N3 .

[0112] The shift circuit 510 may include eighth to twenty-third transistors T8 to T23 and third to sixth capacitors C3 to C6 .

[0113] A gate of the eighth transistor T8 is electrically connected to the first clock terminal CK, a first electrode of the eighth transistor T8 is electrically connected to the first power source VGL, and a second electrode of the eighth transistor T8 is electrically connected to the sixth node N6.

[0114] A gate of the ninth transistor T9 is electrically connected to the first power source VGL, a first electrode of the ninth transistor T9 is electrically connected to the sixth node N6, and a second electrode of the ninth transistor T9 is electrically connected to the eleventh node N11.

[0115] A gate of the tenth transistor T10 is electrically connected to the second clock terminal CB, a first electrode of the tenth transistor T10 is electrically connected to the eighth node N8, and a second electrode of the tenth transistor T10 is electrically connected to the first node N1.

[0116] A gate of the eleventh transistor T11 is electrically connected to the first node N1 , a first electrode of the eleventh transistor T11 is electrically connected to the second power supply VGH, and a second electrode of the eleventh transistor T11 is electrically connected to the second output terminal OUT2 .

[0117] A gate of the twelfth transistor T12 is electrically connected to the sixth node N6 , a first electrode of the twelfth transistor T12 is electrically connected to the second power supply VGH, and a second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7 .

[0118] A gate of the thirteenth transistor T13 is electrically connected to the tenth node N10 , a first electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6 , and a second electrode of the thirteenth transistor T13 is electrically connected to the first clock terminal CK.

[0119] A gate of the fourteenth transistor T14 is electrically connected to the tenth node N10 , a first electrode of the fourteenth transistor T14 is electrically connected to the first node N1 , and a second electrode of the fourteenth transistor T14 is electrically connected to the second power supply VGH.

[0120] A gate of the fifteenth transistor T15 is electrically connected to the ninth node N9, a first electrode of the fifteenth transistor T15 is electrically connected to the seventh node N7, and a second electrode of the fifteenth transistor T15 is electrically connected to the second clock terminal CB.

[0121] A gate of the sixteenth transistor T16 is electrically connected to the control terminal CX, a first electrode of the sixteenth transistor T16 is electrically connected to the second power supply VGH, and a second electrode of the sixteenth transistor T16 is electrically connected to the tenth node N10.

[0122] A gate of the seventeenth transistor T17 is electrically connected to the first clock terminal CK, a first electrode of the seventeenth transistor T17 is electrically connected to the first input terminal INPUT1, and a second electrode of the seventeenth transistor T17 is electrically connected to the tenth node N10.

[0123] A gate of the eighteenth transistor T18 is electrically connected to the first clock terminal CK, a first electrode of the eighteenth transistor T18 is electrically connected to the first input terminal INPUT1, and a second electrode of the eighteenth transistor T18 is electrically connected to the twelfth node N12.

[0124] A gate of the nineteenth transistor T19 is electrically connected to the first power source VGL, a first electrode of the nineteenth transistor T19 is electrically connected to the tenth node N10, and a second electrode of the nineteenth transistor T19 is electrically connected to the second node N2.

[0125] A gate of the twentieth transistor T20 is electrically connected to the first power source VGL, a first electrode of the twentieth transistor T20 is electrically connected to the twelfth node N12, and a second electrode of the twentieth transistor T20 is electrically connected to the ninth node N9.

[0126] A gate of the twenty-first transistor T21 is electrically connected to the ninth node N9 , a first electrode of the twenty-first transistor T21 is electrically connected to the second node N2 , and a second electrode of the twenty-first transistor T21 is electrically connected to the ninth node N9 .

[0127] A gate of the twenty-second transistor T22 is electrically connected to the second node N2 , a first electrode of the twenty-second transistor T22 is electrically connected to the second output terminal OUT2 , and a second electrode of the twenty-second transistor T22 is electrically connected to the first power source VGL.

[0128] A gate of the twenty-third transistor T23 is electrically connected to the eleventh node N11 , a first electrode of the twenty-third transistor T23 is electrically connected to the second clock terminal CB, and a second electrode of the twenty-third transistor T23 is electrically connected to the eighth node N8 .

[0129] A first end of the third capacitor C3 is electrically connected to the first node N1 , and a second end of the third capacitor C3 is electrically connected to the second power source VGH.

[0130] A first end of the fourth capacitor C4 is electrically connected to the eleventh node N11 , and a second end of the fourth capacitor C4 is electrically connected to the eighth node N8 .

[0131] A first end of the fifth capacitor C5 is electrically connected to the seventh node N7, and a second end of the fifth capacitor C5 is electrically connected to the ninth node N9.

[0132] A first end of the sixth capacitor C6 is electrically connected to the second output end OUT2 , and a second end of the sixth capacitor C6 is electrically connected to the first power source VGL.

[0133] In the embodiment of the present disclosure, the first transistor T1 to the twenty-third transistor T23 are P-type TFT transistors. For example, a thin film transistor whose active layer is low temperature doped polysilicon (LTPS). Those skilled in the art can understand that the first transistor T1 to the twenty-third transistor T23 in the present disclosure can also be an N-type TFT transistor, for example, a thin film transistor whose active layer is indium gallium zinc oxide (IGZO), and the level of the gate turn-on signal of each transistor can be changed accordingly.

[0134] In addition, those skilled in the art will appreciate that the capacitor may be implemented as a single capacitor or a plurality of capacitor units connected in parallel or in series, as long as the corresponding functions can be achieved.

[0135] In the description of the embodiments of the present disclosure, the first node N1 to the twelfth node N12 do not represent actually existing components, but represent junction points of related circuit connections in a circuit diagram.

[0136] Optionally, for multiple cascaded shift drivers, the shift register 500 can be the m-th level shift driver, the first input terminal INPUT1 can be connected to the second output terminal of the m-1-th level shift driver, the second input terminal INPUT2 can be connected to the eighth node N8 of the m-2-th level shift driver, and the fourth input terminal INPUT4 can be connected to the seventh node N7 of the m-1-th level shift driver.

[0137] Figure 5B shows a waveform diagram of an output signal of a shift register in a high refresh frequency region according to an embodiment of the present disclosure, Figure 5C shows a waveform diagram of an output signal of a shift register in a low frequency region according to an embodiment of the present disclosure, Figure 5D FIG. 1 shows a signal timing diagram of a shift register according to an embodiment of the present disclosure. Figure 5D In FIG. 1 , the solid line may represent the signal waveform of the last row of the high frequency, and the dotted line may represent the signal waveform of the normal row of the high frequency.

[0138] Below Figure 5A The structure of the shift register 500 shown in FIG. Figure 5B to Figure 5D The working process of the shift register provided by the embodiment of the present disclosure is described.

[0139] In the high refresh frequency region, the first selection signal MS1 is at a low level.

[0140] At time t1 , the first input signal INPUT1 is at a low level, the first clock signal CK is at a high level, the second clock signal CB is at a low level, the second input signal INPUT2 is at a low level, and the fourth input signal INPUT4 is at a high level.

[0141] The third transistor T3 and the fourth transistor T5 are turned on, and the first selection signal MS1 is written into the third node N3. The potential of the fourth node N4 is consistent with the potential of the first node N1, so the output of the first output terminal OUT1 is consistent with the output of the second output terminal OUT2.

[0142] At time t2 , the first input signal INPUT1 is at a high level, the first clock signal CK is at a low level, the second clock signal CB is at a high level, the second input signal INPUT2 is at a high level, and the fourth input signal INPUT4 is at a high level.

[0143] The seventeenth transistor T17, the eighth transistor T8 and the eighteenth transistor T18 are turned on. The first power supply voltage VGL is written into the sixth node N6 through the eighth transistor T8, and then written into the eleventh node N11 through the ninth transistor T9, and the potentials of the sixth node N6 and the eleventh node N11 are pulled down, and at this time the twelfth transistor T12 and the twenty-third transistor T23 are turned on. The second clock signal CB is written into the eighth node N8, and the potential of the eighth node N8 is pulled up. At this time, the tenth transistor T10 is turned off by the second clock signal CB. The second power supply voltage VGH is written into the seventh node N7 through the twelfth transistor T12, and the potential of the seventh node N7 is high.

[0144] The first input signal INPUT1 is written into the tenth node N10 through the seventeenth transistor T17, and is written into the twelfth node N12 through the eighteenth transistor T18, and the potentials of the tenth node N10 and the twelfth node N12 are pulled up, and the fourteenth transistor T14 is turned off. The potential of the tenth node N10 is written into the second node N2, and the potential of the twelfth node N12 is written into the ninth node N9. The twenty-first transistor T21 and the twenty-second transistor T22 are turned off. At this time, the potential of the first node N1 remains at the low potential of the previous period, and the second output terminal OUT2 keeps outputting the low level signal of the previous period.

[0145] The third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off, the potential of the third node N3 remains at the low level of the previous period, the sixth transistor T6 is turned on, and the second capacitor C2 stores a low level. The potential of the first node N1 is written to the fourth node N4, the potential of the tenth node N10 is written to the second node N2, and the first transistor T1 and the second transistor T2 are turned off. At this time, the first output terminal OUT1 keeps outputting the low level signal of the previous period.

[0146] At time t3 , the first input signal INPUT1 is at a high level, the first clock signal CK is at a high level, the second clock signal CB is at a low level, the second input signal INPUT2 is at a low level, and the fourth input signal INPUT4 is at a high level.

[0147] The seventeenth transistor T17, the eighth transistor T8 and the eighteenth transistor T18 are turned off. Under the action of the fourth capacitor C4, the potential of the eleventh node N11 is kept at a low level, and the twenty-third transistor T23 is turned on. The second clock signal CB is written into the eighth node N8 through the twenty-third transistor T23, and the potential of the eighth node N8 is pulled down. The tenth transistor T10 is turned on, the potential of the eighth node N8 is written into the first node N1, the potential of the first node N1 is pulled down, and the eleventh transistor T11 is turned on.

[0148] Under the action of the fifth capacitor C5, the potential of the ninth node N9 is kept at a high level, and the twenty-first transistor T21 is turned off. The potentials of the tenth node N10 and the second node N2 are kept at a high level in the previous period, and the twenty-second transistor T22 is turned off.

[0149] At this time, the second power supply voltage VGH is written into the second output terminal OUT2 through the eleventh transistor T11, and the second output terminal OUT2 outputs a high level signal.

[0150] The third transistor T3 and the fifth transistor T5 are turned off. Under the action of the second capacitor C2, the potential of the third node N3 remains at the low level of the previous period, and the sixth transistor T6 is turned on. The potential of the first node N1 is written to the fourth node N4, the potential of the tenth node N10 is written to the second node N2, the first transistor T1 is turned on, and the second transistor T2 is turned off. At this time, the first output terminal OUT1 outputs a high level signal.

[0151] In the low refresh frequency region, the first selection signal MS1 is at a high level.

[0152] In the low refresh frequency area, the potential changes of the first node N1, the tenth node N10, and the second node N2 to the eighth node N8 can refer to the potential changes of the first node N1, the tenth node N10, the second node N2 to the eighth node N8 in the high refresh frequency area, and will not be repeated for the sake of simplicity.

[0153] The high level of the first selection signal MS1 is written into the third node N3, so that the potential of the third node N3 is pulled high. Under the control of the high level of the third node N3, the sixth transistor T6 is always kept in the cut-off state, the potential of the fourth node N4 is always kept at the high level of the previous period, and the potential of the second node N2 is always kept at the low level of the previous period. Therefore, the second transistor T2 is turned on, and the first output terminal OUT1 keeps outputting a low level signal. At this time, the pixel row electrically connected to the first output terminal OUT1 is not refreshed.

[0154] When the second node N2 is at a low level, the second transistor T2 is turned on, the first output terminal OUT1 outputs a low level, and the seventh transistor T7 is turned on. The second power supply voltage VGH is written to the fourth node N4 through the seventh transistor T7, the potential of the fourth node N4 is pulled up, and the first transistor T1 is turned off. At this time, the first input terminal OUT1 can stably output a low level signal, thereby ensuring that the pixel row electrically connected to the first output terminal OUT1 is not refreshed.

[0155] Fig. 6A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0156] like Fig. 6AAs shown, the shift register 600A may include first to fourth transistors T1 to T4, sixth to twenty-third transistors T6 to T23, and first to sixth capacitors C1 to C6.

[0157] The first to fourth transistors T1 to T4 , the sixth to twenty-third transistors T6 to T23 , and the first to sixth capacitors C1 to C6 included in the shift register 600A can refer to the shift register 500 described above, and will not be described again for simplicity.

[0158] In an embodiment of the present disclosure, the first capacitor C1 and the second capacitor C2 can be large enough so that in a low refresh frequency region, such as in a 1 Hz refresh frequency region, the first capacitor C1 and the second capacitor C2 can maintain a high level within a frame time. Compared with the shift register 500, the transistor T5 is removed from the shift register 600A, so that the transistor T5 no longer periodically charges and discharges the second capacitor C2, thereby reducing the power consumption of the shift register. At the same time, the potential of the third node N3 will not fluctuate periodically due to the periodic charging and discharging of the second capacitor C2, thereby improving the stability of the potential of the first node N1, making the on or off state of the first transistor T1 more stable.

[0159] Figure 6B A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0160] like Figure 6B As shown, the shift register 600A may include first to fourth transistors T1 to T4, sixth to twenty-third transistors T6 to T23, and first to sixth capacitors C1 to C6.

[0161] The first to fourth transistors T1 to T4 , the sixth to twenty-third transistors T6 to T23 , the first capacitor C1 , and the third to sixth capacitors C3 to C6 included in the shift register 600B can refer to the shift register 500 described above, and will not be described again for simplicity.

[0162] In the embodiment of the present disclosure, a first end of the second capacitor C2 is electrically connected to the first power source VGL, and a second end of the second capacitor C2 is connected to the third node N3.

[0163] In an embodiment of the present disclosure, the first capacitor C1 and the second capacitor C2 can be large enough so that in a low refresh frequency region, such as in a 1 Hz refresh frequency region, the first capacitor C1 and the second capacitor C2 can maintain a high level within a frame time. Compared with the shift register 500, the transistor T5 is removed from the shift register 600B, so that the transistor T5 no longer periodically charges and discharges the second capacitor C2, thereby reducing the power consumption of the shift register. At the same time, the potential of the third node N3 will not fluctuate periodically due to the periodic charging and discharging of the second capacitor C2, thereby improving the stability of the potential of the first node N1, making the on or off state of the first transistor T1 more stable.

[0164] Fig. 7A A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0165] like Fig. 7A As shown, the shift register 700A may include first to twenty-third transistors T1 to T23 and first to sixth capacitors C1 to C6.

[0166] The first to sixth transistors T1 to T6 , the eighth to twenty-third transistors T8 to T23 , and the first to sixth capacitors C1 to C6 included in the shift register 700A can refer to the shift register 500 described above, and will not be described again for simplicity.

[0167] In the embodiment of the present disclosure, a gate of the seventh transistor T7 is electrically connected to the second output terminal OUT2, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the second power supply VGH.

[0168] In the embodiment of the present disclosure, by connecting the first input signal INPUT1 to the gate of the third transistor T3, connecting the second input signal INPUT2 to the gate of the fourth transistor T4, and connecting the second output signal OUT2 to the gate of the seventh transistor T7, the gate of the third transistor T3 and the gate of the fourth transistor T4 can be written with signals only before the second output signal OUT2 is at a high level, thereby ensuring that the writing of the first selection signal MS1 only affects the output of the first output signal OUT1 of this row, thereby improving the stability of the first output signal OUT1.

[0169] In some embodiments, the access positions of the first input signal INPUT1 and the second input signal INPUT2 can be swapped.

[0170] Figure 7B A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0171] like Figure 7B As shown, the shift register 700B may include first to twenty-third transistors T1 to T23 and first to sixth capacitors C1 to C6.

[0172] The first transistor T1 to the second transistor T4 , the fifth transistor T5 to the sixth transistor T6 , the eighth transistor T8 to the twenty-third transistor T23 , and the first capacitor C1 to the sixth capacitor C6 included in the shift register 700B can refer to the shift register 500 described above, and will not be repeated here for the sake of simplicity.

[0173] In the embodiment of the present disclosure, a gate of the third transistor T3 is electrically connected to the second input terminal INPUT2, a first electrode of the third transistor T3 is electrically connected to the third node N3, and a second electrode of the third transistor T3 is electrically connected to the fifth node N5.

[0174] In the embodiment of the present disclosure, a gate of the fourth transistor T4 is electrically connected to the first input terminal INPUT1, a first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and a second electrode of the fourth transistor T4 is electrically connected to the first selection terminal MS1.

[0175] In the embodiment of the present disclosure, a gate of the seventh transistor T7 is electrically connected to the second output terminal OUT2, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the second power supply VGH.

[0176] In the embodiment of the present disclosure, by connecting the second input signal INPUT2 to the gate of the third transistor T3, connecting the first input signal INPUT1 to the gate of the fourth transistor T4, and connecting the second output signal OUT2 to the gate of the seventh transistor T7, the gate of the third transistor T3 and the gate of the fourth transistor T4 can be written with signals only before the second output signal OUT2 is at a high level, thereby ensuring that the writing of the first selection signal MS1 only affects the output of the first output signal OUT1 of this row, thereby improving the stability of the first output signal OUT1.

[0177] In the embodiment of the present disclosure, since the level at the eighth node N8 is usually higher than the level of the second output signal OUT2, the level of the second input signal INPUT2 is usually higher than the level of the first input signal INPUT1, that is, the transistor connected to the first input signal INPUT1 can be turned on more fully. By using the first input signal INPUT1 to control the fourth transistor T4, the fourth transistor T4 can be turned on more fully, so that the first selection signal MS1 can be written to the third node N3 more fully, and the stability of the potential of the third node N3 can be improved.

[0178] Optionally, for shift register 700A and shift register 700B, the fifth transistor T5 can be removed as shown in shift register 600A; or, as shown in shift register 600B, while removing the fifth transistor T5, the access method of the second capacitor C2 can be changed to one end of the second capacitor C2 connected to the first power supply VGL and the other end connected to the third node N3, which will not be described here for the sake of simplicity.

[0179] In some embodiments, such as in shift register 500, shift register 600A, shift register 600B, etc., based on similar reasons, the access positions of the first input signal INPUT1 and the second input signal INPUT2 can also be exchanged, that is, the first input signal INPUT1 is connected to the gate of the fourth transistor T4, and the second input signal INPUT2 is connected to the gate of the third transistor T3. For the sake of simplicity, it will not be repeated here.

[0180] Figure 8 A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0181] like Figure 8 As shown, the shift register 800 may include first to twenty-third transistors T1 to T23 and first to sixth capacitors C1 to C6.

[0182] The first to sixth transistors T1 to T6 , the eighth to twenty-third transistors T8 to T23 , and the first to sixth capacitors C1 to C6 included in the shift register 800 may refer to the shift register 500 described above, and will not be described again for simplicity.

[0183] In the embodiment of the present disclosure, the gate of the seventh transistor T7 is electrically connected to the second selection terminal MS2, the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and the second electrode of the seventh transistor T7 is electrically connected to the second power supply VGH.

[0184] In the embodiment of the present disclosure, the second selection signal MS2 from the second selection terminal MS2 can be an inverse signal of the first selection signal MS1. By counting the second selection signal MS2 at the gate of the seventh transistor T7, in the low refresh frequency region, the first selection signal MS1 is at a high level, and the second selection signal MS2 is at a low level. The second selection signal MS2 can control the seventh transistor T7 to turn on, and the second power supply voltage VGH is written to the fourth node N4, so that the potential of the fourth node N4 is high, and the potential of the fourth node N4 can control the first transistor T1 to be cut off, thereby ensuring that the first output terminal OUT1 outputs a low level. At the same time, the fourth node N4 no longer needs to rely on the first capacitor C1 and the second capacitor C2 to maintain a high potential, which can improve the stability of the potential of the fourth node N4.

[0185] Optionally, for the shift register 800, the fifth transistor T5 can be removed as shown in the shift register 600A; or, as shown in the shift register 600B, while removing the fifth transistor T5, the access method of the second capacitor C2 can be changed to one end of the second capacitor C2 connected to the first power supply VGL and the other end connected to the third node N3; or, as shown in the shift register 700B, the access positions of the first input signal INPUT1 and the second input signal INPUT2 can be swapped, that is, the first input signal INPUT1 is connected to the gate of the fourth transistor T4, and the second input signal INPUT2 is connected to the gate of the third transistor T3. For the sake of simplicity, it will not be repeated here.

[0186] Optionally, the selection input signal MSINPUT may come from the shift register itself, and other shift registers cascaded with the shift register. The selection input signal MSINPUT provided by the other shift registers may be used to select the first output signal OUT1 output by the shift register.

[0187] For example, the shift register may be an m-th stage shift register, and the selection input terminal MSINPUT may be electrically connected to the second output terminal of the m-th stage shift register and the (m-1)-th stage shift register, respectively.

[0188] Fig. 9 A block diagram of a shift register according to another embodiment of the present disclosure is schematically shown.

[0189] like Fig. 9 As shown, the shift register 900 may include a shift circuit 910, a gating circuit 920, a control circuit 930, and an output circuit 940. In the embodiment of the present disclosure, the shift circuit 910, the control circuit 930, and the output circuit 940 are respectively similar to the shift circuit 310, the control circuit 330, and the output circuit 340 described above, and are not described again for simplicity.

[0190] The gating input terminal MSINPUT connected to the gating circuit 920 may include a second output terminal OUT2 and a third input terminal INPUT3, and accordingly, the gating input signal MSINPUT may include a second output signal OUT2 from the second output terminal OUT2 and a third input signal INPUT3 from the third input terminal INPUT3. Under the control of the second output signal OUT2 and the third input signal INPUT3, the gating circuit 920 may provide the first gating signal MS1 from the first gating terminal MS1 to the third node N3.

[0191] For example, the second output signal OUT2 and the third input signal INPUT3 can control the gating circuit 920 to switch between the on and off states. When the second output signal OUT2 and the third input signal INPUT3 control the gating circuit 920 to be in the on state, the first gating signal MS1 is written into the third node N3. When the second output signal OUT2 and the third input signal INPUT3 control the gating circuit 920 to be in the off state, the potential of the third node N3 can maintain the state of the previous stage.

[0192] Fig.10 A schematic structural diagram of a shift register according to another embodiment of the present disclosure is shown schematically.

[0193] like Fig.10 As shown, the shift register 1000 may include first to twenty-third transistors T1 to T23 and first to sixth capacitors C1 to C6.

[0194] The first transistor T1 to the second transistor T4 , the fifth transistor T5 to the twenty-third transistor T23 , and the first capacitor C1 to the sixth capacitor C6 included in the shift register 1000 can refer to the shift register 500 described above, and will not be described again for the sake of simplicity.

[0195] In the embodiment of the present disclosure, a gate of the third transistor T3 is electrically connected to the second output terminal OUT2, a first electrode of the third transistor T3 is electrically connected to the third node N3, and a second electrode of the third transistor T3 is electrically connected to the fifth node N5.

[0196] In the embodiment of the present disclosure, a gate of the fourth transistor T4 is electrically connected to the third input terminal INPUT3, a first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and a second electrode of the fourth transistor T4 is electrically connected to the first selection terminal MS1.

[0197] Optionally, for multiple cascaded shift drivers, the shift register 900 may be an m-th shift driver, the third input terminal INPUT3 may be connected to the eighth node N8 of the m-1-th shift driver, and the fourth input terminal INPUT4 may be connected to the seventh node N7 of the m-1-th shift driver.

[0198] In an embodiment of the present disclosure, by respectively connecting the second output signal OUT2 and the third input signal INPUT3 to the third transistor T3 and the fourth transistor T4, the third transistor T3 and the fourth transistor T4 can be turned on one clock signal cycle later, that is, the time that the first capacitor C1 and the second capacitor C2 need to maintain the voltage can be shorter, thereby effectively improving the stability of the potential of the fourth node N4.

[0199] Optionally, for the shift register 1000, the fifth transistor T5 can be removed as shown in the shift register 600A; or, as shown in the shift register 600B, while removing the fifth transistor T5, the access mode of the second capacitor C2 can be changed to one end of the second capacitor C2 connected to the first power supply VGL and the other end connected to the third node N3; or, as shown in the shift register 700B, the signals connected to the gate of the third transistor T3 and the gate of the fourth transistor T4 can be exchanged, such as connecting the third input signal INPUT3 to the gate of the third transistor T3 and connecting the second output signal OUT2 to the gate of the fourth transistor T4; or, as shown in the shift register 800, the gate of the seventh transistor can be changed to connect to the second selection signal MS2, etc. For the sake of simplicity, it will not be repeated here.

[0200] Fig.11 The schematic diagram shows the structure of a driving circuit according to an embodiment of the present disclosure.

[0201] like Fig.11 As shown, the driving circuit 1100 may include M cascaded shift registers, where M is an integer greater than 1. The M shift registers include a first-stage shift register ST1, ..., an m-th-stage shift register STm, ..., and an M-th-stage shift register STM.

[0202] In the embodiments of the present disclosure, the shift register may be any one of the shift register 300, the shift register 400, the shift register 500, the shift register 600A, the shift register 600B, the shift register 700A, the shift register 700B, the shift register 800, the shift register 900, and the shift register 1000 described above. For example, the M shift registers may all be the shift register 300. For another example, the M shift registers may all be the shift register 900. No further description is given here.

[0203] In an embodiment of the present disclosure, the input signal of the first input terminal INPUT1 of the first stage shift register ST1 may be the start signal GSTV. The input signal of the first input terminal INPUT1 of the mth stage shift register STm may be the first output signal OUT1(m-1) of the first output terminal OUT1 of the m-1th stage shift register STm-1.

[0204] Fig. 12A The schematic diagram shows a structure of a driving circuit according to another embodiment of the present disclosure.

[0205] like Fig. 12A As shown, the driving circuit includes M shift registers connected in cascade.

[0206] In an embodiment of the present disclosure, the strobe input terminal MSINPUT of the shift register 1200A may include a first input terminal INPUT1 and a second input terminal INPUT2.

[0207] In the embodiment of the present disclosure, the first input terminal INPUT1 of the m-th shift register is electrically connected to the second output terminal OUT2 of the m-1-th shift register, the second input terminal INPUT2 of the m-th shift register is electrically connected to the eighth node N8 of the m-2-th shift register, and the fourth input terminal INPUT4 of the m-th shift register is connected to the seventh node N7 of the m-1-th shift register. 2<m≤M, m is an integer, and M is an integer greater than 2.

[0208] In the disclosed embodiment, the first clock terminal CK of the m-th shift register is electrically connected to the clock signal line ck, and the second clock terminal CB of the m-th shift register is electrically connected to the clock signal line cb. The first clock terminal CK of the m+1-th shift register is electrically connected to the clock signal line cb, and the second clock terminal CB of the m+1-th shift register is electrically connected to the clock signal line ck.

[0209] In the embodiment of the present disclosure, the first selection terminal MS1 of each of the M shift registers is electrically connected to the selection signal line ms. The M shift registers are electrically connected to the first power supply VGL through the first power supply line vgl. The M shift registers are electrically connected to the second power supply VGH through the second power supply line vgh.

[0210] Fig. 12B The schematic diagram shows a structure of a driving circuit according to another embodiment of the present disclosure.

[0211] like Fig. 12B As shown, the driving circuit 1200B includes M cascaded shift registers.

[0212] In the embodiment of the present disclosure, the selection input terminal MSINPUT of the shift register may include a second output terminal OUT2 and a third input terminal INPUT3, that is, the second output signal OUT2 output by the shift register may be used as an input signal of the shift register.

[0213] In the embodiment of the present disclosure, the first input terminal INPUT1 of the m-th shift register is electrically connected to the second output terminal OUT2 of the m-1-th shift register, the third input terminal INPUT3 of the m-th shift register is electrically connected to the eighth node N8 of the m-1-th shift register, and the fourth input terminal INPUT4 of the m-th shift register is connected to the seventh node N7 of the m-1-th shift register. 2<m≤M, m is an integer, and M is an integer greater than 2.

[0214] In the disclosed embodiment, the first clock terminal CK of the m-th shift register is electrically connected to the clock signal line ck, and the second clock terminal CB of the m-th shift register is electrically connected to the clock signal line cb. The first clock terminal CK of the m+1-th shift register is electrically connected to the clock signal line cb, and the second clock terminal CB of the m+1-th shift register is electrically connected to the clock signal line ck.

[0215] In the embodiment of the present disclosure, the first selection terminal MS1 of each of the M shift registers is electrically connected to the selection signal line ms. The M shift registers are electrically connected to the first power supply VGL through the first power supply line vgl. The M shift registers are electrically connected to the second power supply VGH through the second power supply line vgh.

[0216] Fig.13 The structural diagram of a display device according to an embodiment of the present disclosure is schematically shown.

[0217] like Fig.13 As shown, the display device 1300 may include a driving circuit 1310 .

[0218] In the embodiment of the present disclosure, the driving circuit 1310 may be any one of the driving circuit 1100 , the driving circuit 1200A and the driving circuit 1200B described above, which will not be described in detail here.

[0219] Fig.14 The flowchart of the driving method according to the embodiment of the present disclosure is schematically shown.

[0220] like Fig.14 As shown, the driving method may include operations S1410 to S1420.

[0221] In operation S1410, in a gating stage, a gating signal is controlled to be a first level.

[0222] In operation S1420, in a non-selection stage, the selection signal is controlled to be a second level.

[0223] In the embodiment of the present disclosure, operations S1410 to S1420 are similar to the operations performed by the shift register 500 described above, and are not described in detail herein.

[0224] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0225] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0226] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: a shift circuit configured to control the potentials of the first node and the second node under the control of a first clock signal from the first clock terminal, a second clock signal from the second clock terminal, a first power supply voltage of the first power supply, a second power supply voltage of the second power supply, and a first input signal from the first input terminal; a gating circuit configured to provide a first gating signal from the first gating terminal to the third node under the control of a gating input signal from the gating input terminal; a control circuit configured to provide the potential of the first node to a fourth node under the control of the potential of the third node; as well as The output circuit is configured to provide the first power supply voltage or the second power supply voltage to a first output terminal as a first output signal under the control of the potential of the fourth node and the potential of the second node.

2. The shift register according to claim 1, wherein: The output circuit includes a first transistor, a second transistor and a first capacitor; The gate of the first transistor is electrically connected to the fourth node, the first electrode of the first transistor is electrically connected to the second power supply, and the second electrode of the first transistor is electrically connected to the first output terminal; The gate of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the first output terminal, and the second electrode of the second transistor is electrically connected to the first power supply; A first end of the first capacitor is electrically connected to the second power source, and a second end of the first capacitor is electrically connected to the fourth node.

3. The shift register according to claim 1, wherein: The gating circuit includes a third transistor and a fourth transistor, the gating input terminal includes the first input terminal and the second input terminal, and the gating input signal includes the first input signal and a second input signal from the second input terminal; The gate of the third transistor is electrically connected to the first input terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fifth node; The gate of the fourth transistor is electrically connected to the second input terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the first selection terminal; The gating circuit is configured to provide a first gating signal from a first gating terminal to a third node under the control of the first input signal and the second input signal.

4. The shift register according to claim 1, wherein: The shift circuit is configured as: Under the control of the first clock signal, the first power supply voltage and the first input signal, providing at least one of the second clock signal and the second power supply voltage to the first node; Under the control of the first clock signal, providing the first input signal to the second node; as well as Under the control of the potential of the first node, the potential of the second node, and the first power supply voltage, the first power supply voltage or the second power supply voltage is provided to the second output terminal as a second output signal.

5. The shift register according to claim 4, wherein: The gating circuit includes a third transistor and a fourth transistor, the gating input terminal includes the second output terminal and a third input terminal, and the input signal includes the second output signal and a third input signal from the third input terminal; wherein the gate of the third transistor is electrically connected to the second output terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the fifth node; The gate of the fourth transistor is electrically connected to the third input terminal, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the first selection terminal; The gating circuit is configured to provide a first gating signal from a first gating terminal to a third node under the control of the second output signal and the third input signal.

6. The shift register according to claim 3 or 5, wherein: The gating circuit is also electrically connected to the first power supply and the fourth input terminal, and the gating circuit further includes a fifth transistor; wherein the gate of the fifth transistor is electrically connected to the fourth input terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first power supply; The gating circuit is further configured to control the potential of the third node using the first power supply voltage under the control of a fourth input signal from the fourth input terminal.

7. The shift register according to claim 1, wherein: The control circuit includes a sixth transistor and a second capacitor; wherein the gate of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the third node; The control circuit is further configured to control the potential of the third node under the control of the potential of the fourth node.

8. The shift register according to claim 1, wherein: The control circuit is also electrically connected to the first power supply, and the control circuit includes a sixth transistor and a second capacitor; wherein the gate of the sixth transistor is electrically connected to the third node, the first electrode of the sixth transistor is electrically connected to the first node, and the second electrode of the sixth transistor is electrically connected to the fourth node; A first end of the second capacitor is electrically connected to the first power supply, and a second end of the second capacitor is electrically connected to the third node; Wherein, the control circuit is further configured to control the potential of the third node under the control of the first power supply voltage.

9. The shift register according to claim 7 or 8, wherein: The control circuit is also electrically connected to the second node and the second power supply, and the control circuit further includes a seventh transistor; The gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second power supply; The control circuit is further configured to control the potential of the fourth node using the second power supply voltage under the control of the potential of the second node.

10. The shift register according to claim 7 or 8, wherein: The control circuit is also electrically connected to the second output terminal and the second power supply, and the control circuit further includes a seventh transistor; The gate of the seventh transistor is electrically connected to the second output terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second power supply; The control circuit is further configured to control the potential of the fourth node using the second power supply voltage under the control of the second output signal.

11. The shift register according to claim 7 or 8, wherein: The control circuit is also electrically connected to the second selection terminal and the second power supply, and the control circuit also includes a seventh transistor; The gate of the seventh transistor is electrically connected to the second selection terminal, the first electrode of the seventh transistor is electrically connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the second power supply; The control circuit is further configured to control the potential of the fourth node using the second power supply voltage under the control of the second selection signal from the second selection terminal.

12. A driving circuit, comprising M cascaded shift registers according to any one of claims 1 to 11, wherein M is an integer greater than 1.

13. The driving circuit according to claim 12, wherein: The first input terminal of the m-th shift register is electrically connected to the second output terminal of the m-1-th shift register, the selection input terminal of the m-th shift register is electrically connected to the first output terminal of the m-1-th shift register and the m-2-th shift register respectively, and the fourth input terminal of the m-th shift register is electrically connected to the m-1-th shift register, 2<m≤M, m is an integer, and M is an integer greater than 2.

14. The driving circuit according to claim 12, wherein: The first input terminal of the m-th shift register is electrically connected to the second output terminal of the m-1-th shift register, the selection input terminal of the m-th shift register is electrically connected to the second output terminal of the m-th shift register and the m-1-th shift register respectively, and the fourth input terminal of the m-th shift register is electrically connected to the m-1-th shift register, 1<m≤M, m is an integer.

15. A display device, comprising: A drive circuit as claimed in any one of claims 12 to 14.

16. A driving method, applied to the shift register according to any one of claims 1 to 11, the method comprising: In the gating stage, controlling the first gating signal to be at a first level; as well as In the non-selection stage, the first selection signal is controlled to be at a second level.

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