Compensation circuit and memory

Abstract

The invention relates to the technical field of semiconductors, in particular to a compensation circuit and a memory, the compensation circuit is applied to a memory cell, the compensation circuit is connected with a bit line connected with the memory cell, and the compensation circuit is configured as follows: when the bit line is driven, a first compensation current is provided for the bit line; the compensation circuit is further configured to provide a second compensation current to the bit line when the word line connected with the storage unit is driven, and the current value of the second compensation current is smaller than that of the first compensation current. The segmented compensation current is used for compensation during word line driving and compensation during bit line driving, so that the influence of inrush current on the memory unit when the memory unit is opened is reduced, the power consumption of the memory is reduced, and the stability of the memory is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a compensation circuit and a memory. Background Art

[0002] Phase Change Memory (PCM) is the most powerful competitor for the new generation of non-volatile memory devices. The storage unit (cell) in the PCM is mainly realized by phase change materials, and the information of the storage unit is read, written and erased through the reversible change of the phase change material between the crystalline state and the amorphous state. The PCM has the characteristics of high integration density, low power consumption, high read and write times and strong anti-interference.

[0003] Applying different pulse voltages to the memory cells in the phase change memory can realize the writing and erasing of the memory cell data. Using strong short pulses to raise the material temperature to above the melting temperature, and then quickly cooling the material to achieve the material transformation from polycrystalline to amorphous state, that is, the erasing process (reset, the state of the memory cell changes from 1 to 0); using medium-strong long pulses to raise the material temperature to above the crystallization temperature and below the melting temperature, and keep it for a period of time, to achieve the material transformation from amorphous to crystalline state, that is, the writing process (set, the state of the memory cell changes from 0 to 1).

[0004] In the integrated test of phase change memory, based on the specific unit reading method in the integrated device, we often select the intermediate state between the set state and the reset state voltage as the read voltage. This makes the impact of read crosstalk mainly concentrated on the set state of the device. During repeated reading, due to the continuous action of the current flowing through, the storage cell is gradually "written" from the set state to the reset state, resulting in read interference of the device. Summary of the invention

[0005] The main purpose of the present application is to provide a compensation circuit and a memory, which are at least used to improve the accuracy of memory data reading.

[0006] To achieve the above-mentioned purpose, the first aspect of the present application proposes a compensation circuit, which is applied to a memory cell, and the compensation circuit is connected to a bit line connected to the memory cell, and is configured to: provide a first compensation current to the bit line when the bit line is driven; the compensation circuit is also configured to: provide a second compensation current to the bit line when a word line connected to the memory cell is driven, and the current value of the second compensation current is less than the current value of the first compensation current.

[0007] In some embodiments, the storage unit is a phase change storage unit, and the phase change storage unit has a critical current value at which the bidirectional threshold switch is in an on state; the current value of the first compensation current is greater than the critical current value, and the current value of the second compensation current is less than the critical current value.

[0008] In some embodiments, a current value of the first compensation current is the same as a current value when the bit line is driven.

[0009] In some embodiments, a current value of the second compensation current is the same as a current value when the word line is driven.

[0010] In some embodiments, the compensation circuit also includes: a voltage providing unit, connecting the word line and the bit line, configured to: provide a first driving voltage to the word line, and provide a second driving voltage to the bit line, wherein the voltage value of the second driving voltage is less than the voltage value of the first driving voltage.

[0011] In some embodiments, the compensation circuit current is disposed in a bit line driver, and the bit line driver is connected to the bit line.

[0012] In some embodiments, the compensation circuit includes: a control unit, configured to provide a first control signal when the bit line is driven, and to provide a second control signal when the word line is driven; a compensation unit, connecting the control unit and the bit line, configured to provide the first compensation current to the bit line according to the first control signal, or to provide the second compensation current to the bit line according to the second control signal.

[0013] In some embodiments, the compensation unit includes: a current mirror, an output end of the current mirror is connected to the bit line, and a control end of the current mirror is connected to the control unit.

[0014] In a second aspect, the present application further proposes a memory, comprising: a memory array, the memory array comprising: a plurality of memory cells arranged in an array, a plurality of word lines and a plurality of bit lines, each of the word lines connecting a plurality of the memory cells arranged in the same row, and each of the bit lines being used to connect a plurality of the memory cells arranged in the same column; a compensation circuit as mentioned in the first aspect above, connected to the bit line, configured to: provide a first compensation current to the bit line when the bit line is driven, and provide a second compensation current to the bit line when the word line is driven.

[0015] In some embodiments, the memory further includes: a selection drive module, connecting the multiple word lines and the multiple bit lines, and configured to: select a target word line among the multiple word lines, and select a target bit line among the multiple bit lines, so as to select a target memory cell based on the target word line and the target bit line; the compensation circuit is configured to compensate the target memory cell.

[0016] The compensation circuit provided in the present application uses segmented compensation currents to compensate for word line driving and bit line driving, respectively, thereby reducing the impact of inrush current on the memory cell when the memory cell is turned on, which not only reduces the power consumption of the memory but also improves the stability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of a compensation circuit provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of a voltage waveform when a storage unit is read according to an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a current waveform of a compensation current provided by a compensation circuit provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of a specific structure of a compensation circuit provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0024] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] Applying different pulse voltages to the memory cells in the phase change memory can realize writing and erasing of the memory cell data.

[0026] A strong short pulse is used to raise the material temperature to above the melting temperature, and then the material is quickly cooled to realize the transformation of the material from polycrystalline to amorphous state, which is the erasing process (reset, the state of the storage unit changes from 1 to 0); a medium-strong long pulse is used to raise the material temperature to above the crystallization temperature and below the melting temperature, and maintain it for a period of time to realize the transformation of the material from amorphous state to crystalline state, which is the writing process (set, the state of the storage unit changes from 0 to 1).

[0027] In the reading process of phase change memory, a pulse signal that does not change the state of the material is often applied, and the state of the storage unit is recognized by judging the resistance value.

[0028] refer to Figure 1 , Figure 1 The schematic diagram of the structure of the phase change memory provided in the present embodiment, in some embodiments, the phase change memory 100 includes a word line (Word Line, WL) 101, a bit line (Bit Line, BL) 102, an ovonic threshold switch (Ovonic Threshold Switch, OTS) 110 and a phase change memory unit (Phase Change Memory, PCM) 120. Among them, one end of the phase change memory unit 120 is connected to the word line 101 through the bidirectional threshold switch 110, and the other end of the phase change memory unit 120 is connected to the bit line 102.

[0029] The current flowing through the device is the most important factor affecting the read interference of the device. All factors including voltage and temperature can be converted into the influence of current. Phase change memory 100 will inevitably bring interference during data reading. The source of this interference is mainly due to the inrush current (inrush current) when the phase change memory unit 120 is opened due to the external voltage of the three-dimensional memory device. A high current will flow into the phase change memory unit 120 at the moment it is opened, and then the current tends to be stable. When reading data at high speed, this effect will accumulate heat as the number of reads increases, and then cause amorphous areas in the material, gradually "writing" the memory unit from the set state to the reset state, causing the memory to misread data.

[0030] An embodiment of the present application provides a compensation circuit, which is applied to a memory cell, wherein the compensation circuit is connected to a bit line connected to the memory cell, and is configured to: provide a first compensation current to the bit line when the bit line is driven; the compensation circuit is also configured to: provide a second compensation current to the bit line when a word line connected to the memory cell is driven, wherein the current value of the second compensation current is less than the current value of the first compensation current. The compensation circuit provided in this embodiment is at least used to improve the accuracy of memory data reading.

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0033] refer to Figure 2 , Figure 2 The compensation circuit 200 provided in this embodiment is applied to a storage unit 210; it should be noted that the storage unit 210 provided in this embodiment can be a storage unit in a phase change access memory, or a storage unit in other memories; for example, a static random access memory, a dynamic random access memory, a ferroelectric random access memory, or a phase change random access memory.

[0034] The compensation circuit 200 is connected to the bit line 230 to which the memory cell 210 is connected, and the compensation circuit 200 is configured to provide a first compensation current to the bit line 230 when the bit line 230 is driven.

[0035] The compensation circuit 200 is further configured to provide a second compensation current to the bit line 230 when the word line 220 connected to the memory cell 210 is driven, wherein a current value of the second compensation current is smaller than a current value of the first compensation current.

[0036] It should be noted that the memory includes multiple memory cells, and the memory selects the target memory cell through the corresponding word line and the corresponding bit line. The process of selecting the corresponding word line and the corresponding bit line is "when word line 220 is driven, or bit line 230 is driven" in the above description.

[0037] In some embodiments, a voltage supply unit is also included, which connects the word line 220 and the bit line 230. The voltage supply unit is configured to: provide a first driving voltage V1 to the word line 220, and provide a second driving voltage V2 to the bit line 230, wherein the voltage value of the second driving voltage V2 is less than the voltage value of the first driving voltage V1.

[0038] For reading data from a memory cell, refer to Figure 2 and Figure 3 , Figure 3 A schematic diagram of a voltage waveform when reading a storage unit provided in this embodiment. The data reading of the storage unit starts at time A, the data reading is completed at time D, and the data reading of the storage unit is terminated at time F.

[0039] Specifically, driving voltages are applied to the word line 220 and the bit line 230, respectively. For the word line 220, referring to curve 11, at time B, a first driving voltage V1 is applied to both ends of the word line 220, the voltage of the word line 220 slowly rises to the first driving voltage V1 and remains unchanged, at time E, the driving voltage to the word line 220 is stopped, and the voltage of the word line 220 slowly drops to 0. For the bit line 230, referring to curve 13, at time A, a second driving voltage V2 is applied to both ends of the bit line 230, the voltage of the bit line 230 slowly drops to the second driving voltage V2 and remains unchanged, at time C, the memory cell is turned on based on the first driving voltage V1 of the word line 220 at this time, and the voltage stored in the memory cell interacts with the voltage of the bit line 230, that is, the data stored in the memory cell interacts with the bit line 230.

[0040] The data of the storage cell is read out by comparing the voltage of the bit line 230 with the voltage of the data line. Referring to curve 12, for the data line, a constant capacitance is given on the data line as the voltage threshold for reading; when the voltage of the bit line 230 is greater than the voltage threshold, the data stored in the output storage cell is "1"; when the voltage of the bit line 230 is less than the voltage threshold, the data stored in the output storage cell is "0". When reading data in this way, the bit line 230 also needs to be connected to the compensation circuit 200, which is used to maintain the bidirectional threshold switch corresponding to the storage cell in the on state when the storage cell is turned on.

[0041] Specifically, at time A, the data line is connected to a constant capacitor, causing the voltage of the data line to begin to drop, and the voltage of the bit line 230 begins to drop based on the provision of the second driving voltage V2. At times A to C, the voltage of the data line drops to the same voltage as the voltage provided by the constant capacitor and remains unchanged, and the voltage of the bit line 230 drops to the second driving voltage V2 and remains unchanged. At time C, the memory cell is turned on based on the voltage of the word line 220 at this moment, and the arc of the memory cell interacts with the charge of the bit line 230 at this moment; when the data stored in the memory cell is "1", the memory cell pulls up the voltage of the bit line 230 to be greater than the voltage of the data line, and the data stored in the memory cell read through the bit line 230 and the data line is "1"; when the data stored in the memory cell is "0", the memory cell pulls down the voltage of the bit line 230, and since the voltage of the bit line 230 is the lowest voltage, it remains unchanged and is less than the voltage of the data line, and the data stored in the memory cell read through the bit line 230 and the data line is "0". The data is read out at time D to ensure that the bit line 230 and the memory cell are fully connected. The first driving voltage V1 is turned off at time E, and the second driving voltage V2 is turned off between time E and time F. At time F, the voltages of the word line 220 and the bit line 230 are both 0, completing a data readout phase.

[0042] Based on the above, it can be known that the time A to time B is the voltage change stage of the bit line 230, and the time B to time F is the word line driving time. Figure 2 and Figure 4 , Figure 4 A schematic diagram of a current waveform of a compensation current provided by the compensation circuit provided in this embodiment. It should be noted that: Figure 4 The middle curve 21 represents the magnitude of the first compensation current I1, the curve 22 represents the magnitude of the second compensation current I2, and the curve 23 is a combination of the magnitudes of the first compensation current I1 and the second compensation current I2, and corresponds to Figure 3 Illustration of the size of the compensation current provided by the compensation circuit in each stage.

[0043] When the bit line 230 is driven (i.e., moment A to moment B), the compensation circuit 200 provides a first compensation current I1 to the bit line 230; when the word line 220 is driven (i.e., moment B to moment F), the compensation circuit 200 provides a second compensation current I2 to the bit line 230, wherein the current value of the first compensation current I1 is greater than the current value of the second compensation current I2.

[0044] Among them, in the driving stage of the bit line 230, the larger compensation current (first compensation current I1) makes the voltage of the bit line 230 more stable when pulling down the voltage of the bit line 230, and at this time the memory cell 210 is not turned on, and the larger current does not cause the inrush current to the memory cell 210, and the larger compensation current can avoid the leakage problem of the bit line 230. In the driving stage of the word line 220, a smaller compensation current (second compensation current I2) is used during the climbing process of the word line 220. Since the memory cell 210 will be turned on in this process, the smaller compensation current reduces the impact of the inrush current on the memory cell 210 at the moment the memory cell 210 is turned on, and the smaller compensation current can also reduce the power consumption of the device.

[0045] In addition, during the word line 220 driving phase, providing a smaller compensation current can effectively avoid the resonance problem, thereby preventing the memory cell 210 from being opened again during the data reading process. The smaller compensation current reduces the voltage drop on the word line 220, increases the data read window margin, and is beneficial to the operation of the memory.

[0046] In summary, for the compensation circuit provided in this embodiment, the compensation current is set in segments and used for compensation during word line driving and compensation during bit line driving respectively, thereby reducing the impact of the inrush current on the memory cell when the memory cell is turned on, which not only reduces the power consumption of the memory, but also improves the stability of the memory.

[0047] In some embodiments, the memory cell 210 is a phase change memory cell, which is formed based on a chalcogenide compound, including at least one of a compound of arsenic (As), selenium (Se) and germanium (Ge), a compound of AsSeGe and silicon (Si), a compound of AsSeGeSi and indium (In), and a compound of AsSeGe and indium (In).

[0048] In some embodiments, the phase-change memory cell has a critical current value at which the bidirectional threshold switch is in an on state, and the current value of the first compensation current I1 is greater than the critical current value. By setting the current value of the first compensation current I1 to be greater than the critical current value, the memory cell 210 is ensured to be in an off state, thereby avoiding the memory cell 210 from being turned on during the bit line 230 driving process, thereby preventing a large inrush current from being caused.

[0049] In some embodiments, the current value of the first compensation current I1 is the same as the current value when the bit line 230 is driven.

[0050] In some embodiments, the current value of the first compensation current I1 ranges from 15uA to 40uA, for example, 20uA, 25uA, 30uA, and 35uA.

[0051] In some embodiments, the current value of the first compensation current I1 is 120% to 150% of the critical current value, that is, assuming that the critical current value is X, the current value of the first compensation current I1 is in the range of 1.2X to 1.5X.

[0052] In some embodiments, the current value of the second compensation current I2 is less than the critical current value. By setting the current value of the second compensation current I2 less than the critical current value, the memory cell 210 is ensured to remain in an open state, thereby avoiding the memory cell 210 from being opened twice during the word line 220 driving process.

[0053] In some embodiments, the current value of the second compensation current I2 is the same as the current value when the word line 220 is driven.

[0054] In some embodiments, the current value of the second compensation current I2 ranges from 1uA to 10uA, for example, 3uA, 5uA, 7uA, and 9uA.

[0055] In some embodiments, the current value of the second compensation current I2 is 20% to 80% of the critical current value, that is, assuming that the critical current value is X, the current value of the second compensation current I2 is in the range of 0.2X to 0.8X.

[0056] In some embodiments, the compensation circuit 200 is disposed in a bit line driver connected to the bit lines.

[0057] refer to Figure 5 , Figure 5 A schematic diagram of a specific structure of the compensation circuit provided in this embodiment. In some embodiments, the compensation circuit 200 includes a control unit 202 and a compensation unit 203. The control unit 202 is configured to provide a first control signal when the bit line 230 is driven, and to provide a second control signal when the word line 220 is driven. The compensation unit 203 connects the control unit 202 and the bit line 230, and the compensation unit 203 is configured to provide a first compensation current I1 to the bit line according to the first control signal, or to provide a second compensation current I2 to the bit line according to the second control signal.

[0058] In some embodiments, the compensation unit 203 includes a current mirror, an output terminal of the current mirror is connected to the bit line 230 , and a control terminal of the current mirror is connected to the control unit 202 .

[0059] In one example, the first control signal and the second control signal change the output current of the current mirror by changing the connected resistor or the connected power supply of the bias circuit in the current mirror, so that the compensation unit 203 provides the first compensation current I1 or the second compensation current I2.

[0060] In one example, the current mirror is divided into a first current mirror and a second current mirror, wherein the first current mirror is used to provide a first compensation current I1, and the second current mirror is used to provide a second compensation current I2; the first current mirror and the second current mirror are connected to a control unit 202, and the control unit 202 controls the first current mirror to connect to a bit line 230 based on a first control signal to provide the first compensation current I1 to the bit line 230; or, the control unit 202 controls the second current mirror to connect to the bit line 230 based on a second control signal to provide the second compensation current I2 to the bit line 230.

[0061] Continue to refer Figure 5 In some embodiments, a word line switch tube 221 is provided on the word line 220, and a bit line switch tube 231 is provided on the bit line 230. The word line switch tube 221 and the bit line switch tube 231 are used to select the storage cell 210 based on the word line 220 and the bit line 230, thereby realizing data reading of the storage cell 210.

[0062] For the compensation circuit provided in this embodiment, the compensation current is set in segments and is used for compensation during word line driving and compensation during bit line driving respectively, thereby reducing the impact of the inrush current on the memory cell when the memory cell is turned on, which not only reduces the power consumption of the memory but also improves the stability of the memory.

[0063] It should be noted that, in the absence of conflict, the features disclosed in the compensation circuits provided in the above embodiments may be randomly combined to obtain new compensation circuit embodiments.

[0064] This embodiment also provides a memory, which is at least used to improve the accuracy of reading data from the memory.

[0065] The memory includes: a memory array, the memory array includes: a plurality of memory cells arranged in an array, a plurality of word lines and a plurality of bit lines, each of the word lines is connected to a plurality of the memory cells arranged in the same row, and each of the bit lines is used to connect a plurality of the memory cells arranged in the same column; a compensation circuit as provided in the above embodiment is connected to the bit line, and the compensation circuit is configured to provide a first compensation current to the bit line when the bit line is driven, and to provide a second compensation current to the bit line when the word line is driven.

[0066] In some embodiments, the memory also includes: a selection drive module, connecting the multiple word lines and the multiple bit lines, configured to: select a target word line among the multiple word lines, and select a target bit line among the multiple bit lines, so as to select a target memory cell based on the target word line and the target bit line; the compensation circuit is configured to compensate the target memory cell.

[0067] The memory provided in this embodiment is described in detail below with reference to the accompanying drawings. Figure 6 , Figure 6 A schematic diagram of the structure of the memory provided in this embodiment.

[0068] refer to Figure 6 , the memory 400 includes a storage array 402, a selection driving module 401 and a compensation circuit.

[0069] The memory array 402 includes a plurality of memory cells 210 arranged in an array, a plurality of word lines 220, and a plurality of bit lines 230. Each word line 220 connects a plurality of memory cells 210 arranged in a row, and each bit line 230 is used to connect a plurality of memory cells 210 arranged in a column.

[0070] The selection driving module 401 is connected to the multiple word lines 220 and the multiple bit lines 230. The selection driving module is configured to select a target word line from the multiple word lines and select a target bit line from the multiple bit lines to select a target memory cell based on the target word line and the target bit line.

[0071] The compensation circuit, such as the compensation circuit described in the above embodiment, is connected to the bit line connected to the target memory cell.

[0072] The storage unit 210 marked by the dotted box 403 is used as the target storage unit. Figure 2 The compensation circuit is connected to the bit line 230 connected to the memory cell 210, and the compensation circuit 200 is configured to provide a first compensation current to the bit line 230 when the bit line 230 is driven. The compensation circuit 200 is also configured to provide a second compensation current to the bit line 230 when the word line 220 connected to the memory cell 210 is driven, wherein the current value of the second compensation current is less than the current value of the first compensation current.

[0073] In some embodiments, the selection driving module 401 includes a word line driver and a bit line driver, wherein the word line driver is used to connect multiple word lines 220, and the word line driver is used to select a target word line from the multiple word lines 220; the bit line driver is used to connect multiple bit lines 230, and the bit line driver is used to select a target bit line from the multiple bit lines 230.

[0074] refer to Figure 5 In some embodiments, a word line switch tube 221 is provided on each word line 220 of the multiple word lines 220, and the selection driving module 401 selects the target word line based on the word line switch tube 221; a bit line switch tube 231 is provided on each bit line 230 of the multiple bit lines 230, and the selection driving module 401 selects the target bit line based on the bit line switch tube 231.

[0075] In some embodiments, the word line driver is connected to the word line switch tube 221 on each word line 220 of the plurality of word lines 220 , and the word line driver selects the target word line by turning on the corresponding word line switch tube 221 .

[0076] In some embodiments, the bit line driver is connected to a bit line switch tube 231 on each bit line 230 among the plurality of bit lines 230 , and the bit line driver selects a target bit line by turning on a corresponding bit line switch tube 231 .

[0077] In some embodiments, the memory provided in this embodiment is applied to a storage system, and the storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0078] For the memory provided in this embodiment, the compensation current is set in segments and is used for compensation during word line driving and bit line driving respectively, thereby reducing the impact of the inrush current on the memory cell when the memory cell is turned on, which not only reduces the power consumption of the memory, but also improves the stability of the memory.

[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0080] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0081] The above is a detailed introduction to a compensation circuit and a memory provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A compensation circuit, applied to a storage unit, characterized in that: The compensation circuit is connected to the bit line connected to the memory cell, and is configured to provide a first compensation current to the bit line when the bit line is driven; the compensation circuit is also configured to provide a second compensation current to the bit line when the word line connected to the memory cell is driven, and the current value of the second compensation current is smaller than the current value of the first compensation current.

2. The compensation circuit according to claim 1, characterized in that: The storage unit is a phase change storage unit having a critical current value at which a bidirectional threshold switch is in an on state; the current value of the first compensation current is greater than the critical current value, and the current value of the second compensation current is less than the critical current value.

3. The compensation circuit according to claim 2, characterized in that: A current value of the first compensation current is the same as a current value when the bit line is driven.

4. The compensation circuit according to claim 2, characterized in that: A current value of the second compensation current is the same as a current value when the word line is driven.

5. The compensation circuit according to claim 1, characterized in that: Also includes: The voltage supply unit is connected to the word line and the bit line, and is configured to: supply a first driving voltage to the word line and supply a second driving voltage to the bit line, wherein the voltage value of the second driving voltage is smaller than the voltage value of the first driving voltage.

6. The compensation circuit according to claim 1, characterized in that: The compensation circuit current is arranged in a bit line driver, and the bit line driver is connected to the bit line.

7. The compensation circuit according to any one of claims 1 to 6, characterized in that: The compensation circuit comprises: A control unit configured to: provide a first control signal when the bit line is driven, and provide a second control signal when the word line is driven; The compensation unit is connected to the control unit and the bit line, and is configured to provide the first compensation current to the bit line according to the first control signal, or provide the second compensation current to the bit line according to the second control signal.

8. The compensation circuit according to claim 7, characterized in that: The compensation unit comprises: a current mirror, an output end of the current mirror is connected to the bit line, and a control end of the current mirror is connected to the control unit.

9. A memory, characterized in that: include: A memory array, the memory array comprising: a plurality of memory cells arranged in an array, a plurality of word lines and a plurality of bit lines, each of the word lines connecting a plurality of the memory cells arranged in the same row, and each of the bit lines connecting a plurality of the memory cells arranged in the same column; The compensation circuit according to any one of claims 1 to 8, connected to the bit line, and configured to: provide a first compensation current to the bit line when the bit line is driven, and provide a second compensation current to the bit line when the word line is driven.

10. The memory according to claim 9, characterized in that: Also includes: A selection driving module is connected to the plurality of word lines and the plurality of bit lines, and is configured to: select a target word line from the plurality of word lines, and select a target bit line from the plurality of bit lines, so as to select a target memory cell based on the target word line and the target bit line; The compensation circuit is configured to compensate a target memory cell.

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