Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises an input sub-circuit which is configured to control the potentials of a first node and a second node in response to a first clock signal provided by a first clock signal line and a second clock signal provided by a second clock signal line; the first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and a third clock signal provided by a third clock signal line; a second control sub-circuit configured to control the potential of a third node in response to the signal of the first node, the signal of the second node and a fourth clock signal provided by a fourth clock signal line; the output sub-circuit is configured to output a first output signal in response to a signal of the first node, or to output a second output signal in response to a signal of the third node.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and in particular relates to a shift register, a gate driving circuit and a display device. Background Art

[0002] In the field of display technology, for example, a pixel array of a liquid crystal display panel or an organic light emitting diode (OLED) display panel generally includes multiple rows of gate lines and multiple columns of data lines interlaced with the gate lines. The gate lines can be driven by a bound integrated drive circuit.

[0003] The gate drive on array (GOA) technology is a technology commonly used in display panels at present, which is to manufacture the row scanning drive signal circuit on the array substrate to realize the driving mode of scanning the gate row by row. At present, with the continuous improvement of the resolution requirements of existing display products, the display products with higher resolution have more stages of shift registers in the internal integrated gate drive circuit, thereby increasing the capacitance and resistance load of the clock signal line and the power signal line, and further affecting the display picture. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a gate driving circuit and a display device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a shift register, comprising a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input subcircuit, a first control subcircuit, a second control subcircuit and an output subcircuit;

[0006] The input subcircuit is configured to control the potentials of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line;

[0007] The first control subcircuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line;

[0008] The second control subcircuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node and the fourth clock signal provided by the fourth clock signal line;

[0009] The output sub-circuit is configured to output a first output signal in response to a signal at the first node, or to output a second output signal in response to a signal at the third node.

[0010] In some embodiments, within a clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the third clock signal, and a pulse of the third clock signal precedes a pulse of the fourth clock signal.

[0011] In some embodiments, within a clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the fourth clock signal, and a pulse of the fourth clock signal precedes a pulse of the third clock signal.

[0012] In some embodiments, the first clock signal and the second clock signal have the same timing; the third clock signal has an opposite timing to the first clock signal; and the fourth clock signal and the third clock signal have the same timing.

[0013] In some embodiments, the first clock signal and the second clock signal include a first level; the potential of the first level of the first clock signal is different from the potential of the first level of the second clock signal; and / or,

[0014] The third clock signal and the fourth clock signal include a third level; a potential of the third level of the third clock signal is different from a potential of the third level of the fourth clock signal.

[0015] In some embodiments, the potential of the first level of the first clock signal is less than the potential of the first level of the second clock signal; and / or,

[0016] The potential of the third level of the third clock signal is lower than the potential of the third level of the fourth clock signal.

[0017] In some embodiments, the first clock signal and the second clock signal further include a second level, the second level being different from the first level; the potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; and / or,

[0018] The third clock signal and the fourth clock signal further include a fourth level, and the fourth level is different from the third level; and a potential of the fourth level of the third clock signal is different from a potential of the fourth level of the fourth clock signal.

[0019] In some embodiments, the potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or,

[0020] The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

[0021] In some embodiments, the shift register further includes a first power signal line, a second power signal line, a third power signal line and a fourth power signal line;

[0022] The input subcircuit is electrically connected to the first power signal line, the first control subcircuit is electrically connected to the third power signal line, the second control subcircuit is electrically connected to the fourth power signal line, and the output subcircuit is electrically connected to the second power signal line and the third power signal line.

[0023] In some embodiments, the potential of the first power signal transmitted by the first power signal line is less than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is less than the potential of the fourth power signal transmitted by the fourth power signal line; and the potential of the second power signal is less than the potential of the third power signal.

[0024] In some embodiments, the potential of the first level of the first clock signal is equal to the potential of the first power signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power signal;

[0025] The potential of the first level of the second clock signal is equal to the potential of the second power signal, and the potential of the second level of the second clock signal is equal to the potential of the third power signal;

[0026] The potential of the third level of the third clock signal is equal to the potential of the first power signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power signal;

[0027] The potential of the third level of the fourth clock signal is equal to the potential of the second power signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power signal.

[0028] In some embodiments, a pulse width of a first level of the first clock signal is smaller than a pulse width of a second level; and / or a pulse width of a third level of the third clock signal is smaller than a pulse width of a fourth level.

[0029] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0030] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0031] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0032] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0033] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0034] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0035] A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0036] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

[0037] In some embodiments, the input subcircuit includes a first transistor, a second transistor, and a third transistor;

[0038] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0039] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0040] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

[0041] In some embodiments, the shift register further comprises an isolation subcircuit;

[0042] The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolate the first node from the output subcircuit electrically connected to the first node; and isolate the second node from the second control subcircuit electrically connected to the second node;

[0043] The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; and the second control subcircuit is electrically connected to the fourth node.

[0044] In some embodiments, the isolation subcircuit includes an eleventh transistor and a twelfth transistor;

[0045] The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line;

[0046] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

[0047] In some embodiments, the isolation subcircuit includes an eleventh transistor and a twelfth transistor;

[0048] The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line;

[0049] The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

[0050] In some embodiments, the first control subcircuit includes a fourth transistor, a fifth transistor and a third capacitor;

[0051] The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the fifth node;

[0052] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node;

[0053] The second plate of the third capacitor is electrically connected to the fifth node.

[0054] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor;

[0055] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor;

[0056] The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line;

[0057] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

[0058] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor;

[0059] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the capacitor;

[0060] The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line;

[0061] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node;

[0062] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a preset control terminal.

[0063] In some embodiments, the input subcircuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0064] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0065] A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0066] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line;

[0067] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

[0068] In some embodiments, the shift register further comprises an isolation subcircuit;

[0069] The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolate the first node from the output subcircuit electrically connected to the first node; isolate the first node from the second control subcircuit electrically connected to the first node; and isolate the second node from the second control subcircuit electrically connected to the second node;

[0070] The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; and the second control subcircuit is electrically connected to the fourth node and the fifth node.

[0071] In some embodiments, the input subcircuit includes a first transistor, a second transistor, a third transistor, and a fourteenth transistor;

[0072] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line;

[0073] A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node;

[0074] The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line;

[0075] The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

[0076] In some embodiments, the first control subcircuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor and a third capacitor;

[0077] The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the second electrode plate of the third capacitor;

[0078] The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node;

[0079] The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line;

[0080] The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

[0081] In some embodiments, the second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor;

[0082] The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor;

[0083] The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line;

[0084] The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node;

[0085] The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to a preset control terminal.

[0086] In some embodiments, the output subcircuit includes a ninth transistor, a tenth transistor, and a second capacitor;

[0087] The first electrode of the ninth transistor is electrically connected to the third power signal line and the first electrode plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node;

[0088] The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node;

[0089] The second plate of the second capacitor is electrically connected to the third node.

[0090] In the second aspect, the embodiment of the present disclosure also provides a gate drive circuit, comprising N cascaded shift registers; except for the first-stage shift register, the signal input terminal of the i+1-th stage shift register is electrically connected to the signal output terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0091] In some embodiments, the first clock signal line in the i-th level shift register is multiplexed as the fourth clock signal line in the i+1-th level shift register, the second clock signal line in the i-th level shift register is multiplexed as the first clock signal line in the i+1-th level shift register, the third clock signal line in the i-th level shift register is multiplexed as the second clock signal line in the i+1-th level shift register, and the fourth clock signal line in the i-th level shift register is multiplexed as the third clock signal line in the i+1-th level shift register.

[0092] In some embodiments, the first clock signal line in the i-th level shift register is multiplexed as the third clock signal line in the i+1-th level shift register, the second clock signal line in the i-th level shift register is multiplexed as the fourth clock signal line in the i+1-th level shift register, the third clock signal line in the i-th level shift register is multiplexed as the first clock signal line in the i+1-th level shift register, and the fourth clock signal line in the i-th level shift register is multiplexed as the second clock signal line in the i+1-th level shift register.

[0093] In a third aspect, an embodiment of the present disclosure further provides a display device, comprising a pixel driving circuit and a gate driving circuit as described in any one of the second aspects, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] Figure 1 A schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure;

[0095] Figure 2 Example 1 provided for the embodiment of the present disclosure, a timing diagram of each clock signal line within a clock cycle;

[0096] Figure 3 Example 2 provided for an embodiment of the present disclosure, a timing diagram of each clock signal line within a clock cycle;

[0097] Figure 4 Example 3 provided for the embodiment of the present disclosure, a timing diagram of each clock signal line within a clock cycle;

[0098] Figure 5a A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure;

[0099] Figure 5b A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure;

[0100] Figure 6 A circuit diagram of a 12T3C circuit structure provided in an embodiment of the present disclosure;

[0101] Figure 7 A circuit diagram of another 12T3C circuit structure provided in an embodiment of the present disclosure;

[0102] Figure 8 A circuit diagram of a 13T3C circuit structure provided in an embodiment of the present disclosure;

[0103] Fig. 9 A circuit diagram of another 13T3C circuit structure provided in an embodiment of the present disclosure;

[0104] Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure;

[0105] Fig.11 A circuit diagram of a 16T3C circuit structure provided in an embodiment of the present disclosure;

[0106] Fig.12 A circuit diagram of another 16T3C circuit structure provided in an embodiment of the present disclosure;

[0107] Fig.13 A timing diagram of an exemplary shift register provided in an embodiment of the present disclosure;

[0108] Fig.14 A timing diagram of another exemplary shift register provided for an embodiment of the present disclosure;

[0109] Fig.15 A timing diagram of another exemplary shift register provided for an embodiment of the present disclosure;

[0110] Fig.16 A schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure;

[0111] Fig.17 A schematic diagram of another gate driving circuit provided by an embodiment of the present disclosure;

[0112] Fig.18 The embodiments of the present disclosure provide Figure 6 The circuit diagram of the shift register cascade of the 12T3C circuit structure shown;

[0113] Fig.19 The embodiments of the present disclosure provide Figure 8 The circuit diagram of the shift register cascade of the 13T3C circuit structure shown;

[0114] Fig. 20 The embodiments of the present disclosure provide Fig.11 The circuit diagram of the shift register cascade of the 16T3C circuit structure shown;

[0115] Fig.21 The embodiments of the present disclosure provide Figure 7 The circuit diagram of the shift register cascade of the 12T3C circuit structure shown;

[0116] Fig. 22 The embodiments of the present disclosure provide Fig. 9 The circuit diagram of the shift register cascade of the 13T3C circuit structure shown;

[0117] Fig.23 The embodiments of the present disclosure provide Fig.12The circuit diagram of the shift register cascade of the 16T3C circuit structure is shown. DETAILED DESCRIPTION

[0118] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0119] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantitative restrictions, but indicate that there is at least one. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0120] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0121] In the related art, the shift register will access a group of clock signals with opposite timings, and for clock signals with the same timing, the same clock signal line will be used for transmission. For display products with higher resolution, the more the level of the shift register in the internally integrated gate drive circuit is, the more the capacitance and resistance load of the same clock signal line will be. The increase in load will extend the time for the shift register to output the signal, thereby affecting the effective working time of the pixel, and then affecting the display screen. At the same time, the more the level of the shift register in the gate drive circuit is, the more transistors are connected to the same clock signal line, and the greater the parasitic capacitance generated, which further affects the display screen. In addition, the more the level of the shift register in the gate drive circuit is, the more transistors are connected to the same power signal line, and the load increases, which easily causes the power signal transmitted by the power signal line to fluctuate, and ultimately causes fine horizontal stripes and other defects on the display screen, affecting the display effect.

[0122] In view of this, an embodiment of the present disclosure provides a shift register, which includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit; the input sub-circuit is configured to control the potential of the first node and the second node in response to the first clock signal provided by the first clock signal line and the second clock signal provided by the second clock signal line; the first control sub-circuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line; the second control sub-circuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node and the fourth clock signal provided by the fourth clock signal line; the output sub-circuit is configured to output a first output signal in response to the potential of the first node, or to output a second output signal in response to the potential of the third node.

[0123] The shift register provided in the embodiment of the present disclosure includes multiple clock signal lines, namely a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The multiple clock signal lines are used to provide clock signals, thereby dispersing the load on a single clock signal line in the above-mentioned related technology, thereby reducing product power consumption and improving display effects.

[0124] The specific circuit structure of the shift register provided by the embodiment of the present disclosure is described in detail below.

[0125] Figure 1 A schematic diagram of a shift register structure provided by an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the shift register includes a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, a fourth clock signal line CKL4, an input sub-circuit 1, a first control sub-circuit 2, a second control sub-circuit 3 and an output sub-circuit 4.

[0126] Among them, the input sub-circuit 1 is electrically connected to the first clock signal line CKL1, the second clock signal line CKL2, the first node N1 and the second node N2; on this basis, the input sub-circuit 1 is configured to control the potential of the first node N1 and the second node N2 in response to the first clock signal CK1 provided by the first clock signal line CKL1 and the second clock signal CK2 provided by the second clock signal line CKL2.

[0127] For example, Figure 1 As shown, the shift register further includes a signal input terminal Input and a signal output terminal OUT, which are electrically connected to the signal input line and the pixel driving circuit respectively. The signal input line is used to provide an input signal. The shift register is configured to provide a gate row scanning signal to the pixel driving circuit.

[0128] For example, Figure 1 As shown, the shift register further includes a first power signal line VGL1, which is used to provide a first power signal. An input subcircuit 1 in the shift register is electrically connected to a signal input terminal Input and the first power signal line VGL1. The input subcircuit 1 is configured to respond to a first clock signal CK1, a second clock signal CK2, and control the potential of the first node N1 and the second node N2 based on the input signal and the first power signal.

[0129] Continue as Figure 1 As shown, the first control subcircuit 2 is electrically connected to the third clock signal line CKL3, the first node N1 and the second node N2; on this basis, the first control subcircuit 2 is configured to control the potential of the first node N1 in response to the signal of the second node N2 and the third clock signal CK3 provided by the third clock signal line CKL3.

[0130] For example, Figure 1 As shown, the shift register further includes a third power signal line VGH1, and the third power signal line VGH1 is used to provide a third power signal. The first control subcircuit 2 in the shift register is electrically connected to the third power signal line VGH1. The first control subcircuit 2 is configured to respond to the signal of the second node N2, and control the potential of the first node N1 according to the third clock signal CK3 and the third power signal.

[0131] Continue as Figure 1As shown, the second control subcircuit 3 is electrically connected to the first node N1, the second node N2, the third node N3 and the fourth clock signal line CKL4. On this basis, the second control subcircuit 3 is configured to control the potential of the third node N3 in response to the signal of the first node N1, the signal of the second node N2 and the fourth clock signal CK4 provided by the fourth clock signal line CKL4.

[0132] For example, Figure 1 As shown, the shift register further includes a fourth power signal line VGH2, and the fourth power signal line VGH2 is used to provide a fourth power signal. The second control subcircuit 3 in the shift register is electrically connected to the fourth power signal line VGH2. The second control subcircuit 3 is configured to respond to the signal of the first node N1, the signal of the second node N2 and the fourth clock signal CK4, and control the potential of the third node N3 according to the fourth clock signal CK4 and the fourth power signal.

[0133] Continue as Figure 1 As shown, the output subcircuit 4 is electrically connected to the first node N1 and the third node N3. On this basis, the output subcircuit 4 is configured to output a first output signal in response to a signal at the first node N1, or to output a second output signal in response to a signal at the third node N3.

[0134] For example, Figure 1 As shown, the shift register further includes a second power signal line VGL2, wherein the second power signal line VGL2 is used to provide a second power signal. The output subcircuit 4 in the shift register is electrically connected to the second power signal line VGL2 and the third power signal line VGH1. The output subcircuit 4 is configured to respond to the signal of the first node N1 and output the first output signal according to the second power signal. Alternatively, the output subcircuit 4 is configured to respond to the signal of the third node N3 and output the second output signal according to the third power signal.

[0135] The first output signal and the second output signal can both be used as gate row scanning signals of the pixel driving circuit, and can also be used as input signals of the next stage shift register cascaded to the current stage shift register.

[0136] Exemplarily, the input signal is a pulse signal; the first output signal is a low level signal, and the second output signal is a high level signal.

[0137] Exemplarily, the first power signal line VGL1 and the second power signal line VGL2 are the same, and are different from the third power signal line VGH1 and the fourth power signal line VGH2. That is, the first power signal and the second power signal are the same and can be transmitted using the same power signal line.

[0138] Exemplarily, the third power signal line VGH1 is the same as the fourth power signal line VGH2 and is different from the first power signal line VGL1 and the second power signal line VGL2. That is, the third power signal is the same as the fourth power signal and can be transmitted using the same power signal line.

[0139] Exemplarily, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different. In this case, the first power signal and the second power signal can be the same, and the third power signal and the fourth power signal can be the same, but they are transmitted using different power signal lines.

[0140] Exemplarily, when the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different, the first power signal and the second power signal may be the same or different. The third power signal and the fourth power signal may be the same or different. However, the potential of the first power signal and the potential of the second power signal are both smaller than the potential of the third power signal and the potential of the fourth power signal.

[0141] The shift register provided by the embodiment of the present disclosure includes multiple clock signal lines, namely, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. Multiple clock signal lines are used to provide clock signals to disperse the load on a single clock signal line in the above-mentioned related technology, so that the number of transistors connected to a single clock signal line can be reduced, so as to shorten the signal output time, reduce the power consumption of the product, and improve the uniformity of the large-screen display quality. In addition, for the same power supply signal, such as the first power supply signal and the second power supply signal, the same power supply signal line (that is, the first power supply signal line VGL1 and the second power supply signal line VGL2 are the same) can be used for transmission; for example, the third power supply signal and the fourth power supply signal can both be used for transmission using the same power supply signal line (the third power supply signal line VGH1 and the fourth power supply signal line VGH2 are the same). In this way, the signal line layout space can be reduced, which is conducive to achieving a narrow frame. Alternatively, for the same power supply signal, different power supply signal lines are used for transmission. For example, the first power signal and the second power signal can be transmitted using different first power signal lines VGL1 and second power signal lines VGL2; the third power signal and the fourth power signal can be transmitted using different third power signal lines VGH1 and fourth power signal lines VGH2. This can avoid signal fluctuations caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output.

[0142] In some embodiments, Figure 2Example 1 provided in the embodiment of the present disclosure is a timing diagram of each clock signal line within a clock cycle, such as Figure 2 As shown, within a clock cycle T, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the third clock signal, and the pulse of the third clock signal precedes the pulse of the fourth clock signal.

[0143] It should be noted that the "pulse" of the clock signal here refers to the trigger period of the effective level of a clock signal. The present disclosure takes the effective level as a low level as an example. A low-level signal corresponding to a rising edge turning into a falling edge is recorded as a pulse of the clock signal.

[0144] Exemplarily, the pulse width of the effective level of the first clock signal, the pulse width of the effective level of the second clock signal, the pulse width of the effective level of the third clock signal, and the pulse width of the effective level of the fourth clock signal are consistent.

[0145] For example, within a clock cycle T, the effective level cut-off time of the first clock signal can be used as the triggering time of the effective level of the second clock signal; the effective level cut-off time of the second clock signal can be used as the triggering time of the effective level of the third clock signal; the effective level cut-off time of the third clock signal can be used as the triggering time of the effective level of the fourth clock signal.

[0146] Exemplarily, within a clock cycle T, there is a preset time interval between the cut-off moment of the effective level of the first clock signal and the triggering moment of the effective level of the second clock signal; there is a preset time interval between the cut-off moment of the effective level of the second clock signal and the triggering moment of the effective level of the third clock signal; there is a preset time interval between the cut-off moment of the effective level of the third clock signal and the triggering moment of the effective level of the fourth clock signal; wherein the preset time interval is less than the time interval of the effective level.

[0147] This embodiment uses clock signals with different timings. The timings of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are changed in sequence. Compared with the situation where the timings are the same, it is possible to avoid signal mutations caused by changing the timings at the same time, which would affect the display effect.

[0148] In some embodiments, Figure 3 Example 2 provided in the embodiment of the present disclosure is a timing diagram of each clock signal line within a clock cycle, such as Figure 3 As shown, within a clock cycle T, the pulse of the first clock signal precedes the pulse of the second clock signal, the pulse of the second clock signal precedes the pulse of the fourth clock signal, and the pulse of the fourth clock signal precedes the pulse of the third clock signal.

[0149] For example, within a clock cycle T, the effective level cut-off time of the first clock signal can be used as the triggering time of the effective level of the second clock signal; the effective level cut-off time of the second clock signal can be used as the triggering time of the effective level of the fourth clock signal; the effective level cut-off time of the fourth clock signal can be used as the triggering time of the effective level of the third clock signal.

[0150] Exemplarily, within a clock cycle T, there is a preset time interval between the cut-off moment of the effective level of the first clock signal and the triggering moment of the effective level of the second clock signal; there is a preset time interval between the cut-off moment of the effective level of the second clock signal and the triggering moment of the effective level of the fourth clock signal; there is a preset time interval between the cut-off moment of the effective level of the fourth clock signal and the triggering moment of the effective level of the third clock signal; wherein the preset time interval is less than the time interval of the effective level.

[0151] This embodiment uses clock signals with different timings. The timings of the first clock signal, the second clock signal, the fourth clock signal and the third clock signal are changed in sequence. Compared with the situation where the timings are the same, it is possible to avoid signal mutations caused by changing the timings at the same time, which would affect the display effect.

[0152] In some embodiments, Figure 2 or Figure 3 As shown, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have the same potential at valid levels and the same potential at invalid levels.

[0153] In some embodiments, Figure 4 Example 3 provided in the embodiment of the present disclosure is a timing diagram of each clock signal line within a clock cycle, such as Figure 4 As shown, the first clock signal CK1 and the second clock signal CK2 have the same timing. The fourth clock signal CK4 and the third clock signal CK3 have the same timing.

[0154] It should be noted that the timing in the circuit refers to the switching of the signal between high and low potentials in the order of time. The same timing means that the potential jump time nodes of the compared signals are consistent, but it does not mean that the potentials of the two are the same at the same time node.

[0155] like Figure 4 As shown, the timing of the third clock signal CK3 is opposite to that of the first clock signal CK1. The opposite timing means that the potential transition time nodes of the compared signals are inconsistent within the same clock cycle T. Alternatively, it can be understood that the signal waveforms of the first clock signal CK1 and the third clock signal CK3 are the same in the entire working scanning phase, but the transition time node of the effective level of the third clock signal CK3 is later than the preset duration t' of the transition time node of the effective level of the first clock signal CK1.

[0156] Here, the first clock signal line CKL1 , the second clock signal line CKL2 , the third clock signal line CKL3 , and the fourth clock signal line CKL4 are all different.

[0157] In the shift register provided in this embodiment, different clock signal lines, namely, the first clock signal line CKL1 and the second clock signal line CKL2, are used for transmission of the first clock signal CK1 and the second clock signal CK2 with the same timing; the third clock signal CK3 and the fourth clock signal CK4 with the same timing are transmitted using the third clock signal line CKL3 and the fourth clock signal line CKL4. In this way, the number of transistors connected to a single clock signal line can be reduced, thereby reducing the load on each clock signal line, shortening the signal output time, and improving the uniformity of image quality of large-screen displays.

[0158] In some embodiments, Figure 4 As shown, the first clock signal CK1 and the second clock signal CK2 include a first level; the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2.

[0159] Exemplarily, the clock cycles T of the first clock signal CK1 and the second clock signal CK2 are of the same length.

[0160] Exemplarily, the first level is a low level (i.e., a valid level) in the clock cycle T, and the potential of the low level of the first clock signal CK1 is different from the potential of the low level of the second clock signal CK2. For example, the potential of the low level of the first clock signal CK1 may be greater than the potential of the low level of the second clock signal CK2, or may be less than the potential of the low level of the second clock signal CK2.

[0161] Exemplarily, the absolute value of the amplitude of the first clock signal CK1 is greater than the absolute value of the amplitude of the second clock signal CK2.

[0162] Continue as Figure 4 As shown, the third clock signal CK3 and the fourth clock signal CK4 include a third level; the potential of the third level of the third clock signal CK3 is different from the potential of the third level of the fourth clock signal CK4.

[0163] Exemplarily, the clock cycles T of the third clock signal CK3 and the fourth clock signal CK4 are of the same length.

[0164] For example, Figure 4 As shown, the clock cycles T of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 are all the same in length.

[0165] Exemplarily, the third level is a low level (i.e., a valid level) in the clock cycle T, and the potential of the low level of the third clock signal CK3 is different from the potential of the low level of the fourth clock signal CK4. For example, the potential of the low level of the third clock signal CK3 may be greater than the potential of the low level of the fourth clock signal CK4, or may be less than the potential of the low level of the fourth clock signal CK4.

[0166] Exemplarily, the absolute value of the amplitude of the third clock signal CK3 is greater than the absolute value of the amplitude of the fourth clock signal CK4.

[0167] In some embodiments, Figure 4 As shown, the first level of the first clock signal CK1 is lower than the first level of the second clock signal CK2, so as to avoid hysteresis problems in at least some transistors in the input sub-circuit 1 and affect transistor characteristics.

[0168] Continue as Figure 4 As shown, the potential of the third level of the third clock signal CK3 is lower than the potential of the third level of the fourth clock signal CK4, thereby reducing the impact of threshold loss of at least some transistors in the first control subcircuit 2 and the second control subcircuit 3.

[0169] In some embodiments, Figure 4 As shown, the first clock signal CK1 and the second clock signal CK2 further include a second level, which is different from the first level; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0170] Exemplarily, the second level is a high level (i.e., an invalid level) in the clock cycle T, and the potential of the high level of the first clock signal CK1 is different from the potential of the high level of the second clock signal CK2. For example, the potential of the high level of the first clock signal CK1 may be greater than the potential of the high level of the second clock signal CK2, or may be less than the potential of the high level of the second clock signal CK2.

[0171] Continue as Figure 4 As shown, the third clock signal CK3 and the fourth clock signal CK4 further include a fourth level, which is different from the third level; the potential of the fourth level of the third clock signal CK3 is different from the potential of the fourth level of the fourth clock signal CK4.

[0172] Exemplarily, the fourth level is a high level (i.e., an invalid level) in the clock cycle T, and the potential of the high level of the third clock signal CK3 is different from the potential of the high level of the fourth clock signal CK4. For example, the potential of the high level of the third clock signal CK3 may be greater than the potential of the high level of the fourth clock signal CK4, or may be less than the potential of the high level of the fourth clock signal CK4.

[0173] In some embodiments, Figure 4 As shown, the potential of the second level of the first clock signal CK1 is greater than the potential of the second level of the second clock signal CK2; and / or, the potential of the fourth level of the third clock signal CK3 is greater than the potential of the fourth level of the fourth clock signal CK4, thereby reducing the impact of threshold loss of some transistors in the shift register.

[0174] In some embodiments, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different. The first power signal and the second power signal are both low-level signals, but the potential of the first power signal is different from the potential of the second power signal. The third power signal and the fourth power signal are both high-level signals, but the potential of the third power signal is different from the potential of the fourth power signal. The potential of the low-level signal is less than the potential of the high-level signal.

[0175] Exemplarily, considering the influence of threshold loss of some transistors in the shift register, the potential of the first power signal is set to be smaller than the potential of the second power signal.

[0176] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, thereby improving the turn-off characteristics of at least some transistors in the output sub-circuit 4 .

[0177] In some embodiments, Figure 4 As shown, the potential of the first level of the first clock signal CK1 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the second level of the first clock signal CK1 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the first level of the second clock signal CK2 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the second level of the second clock signal CK2 is equal to the potential of the third power signal transmitted by the third power signal line VGH1; the potential of the third level of the third clock signal CK3 is equal to the potential of the first power signal transmitted by the first power signal line VGL1, and the potential of the fourth level of the third clock signal CK3 is equal to the potential of the fourth power signal transmitted by the fourth power signal line VGH2; the potential of the third level of the fourth clock signal CK4 is equal to the potential of the second power signal transmitted by the second power signal line VGL2, and the potential of the fourth level of the fourth clock signal CK4 is equal to the potential of the third power signal transmitted by the third power signal line VGH1.

[0178] In some embodiments, Figure 4 As shown, the pulse width of the first level of the first clock signal CK1 is smaller than the pulse width of the second level; and / or the pulse width of the third level of the third clock signal CK3 is smaller than the pulse width of the fourth level.

[0179] Exemplarily, the first level is a low level in a clock cycle T, and the second level is a high level in a clock cycle T; the pulse width of the low level of the first clock signal CK1 is smaller than the pulse width of the high level. The clock cycle T of the first clock signal CK1 and the second clock signal CK2 are the same in duration. Therefore, the pulse width of the low level of the second clock signal CK2 is smaller than the pulse width of the high level.

[0180] Exemplarily, the third level is a low level in the clock cycle T, and the fourth level is a high level in the clock cycle T; the pulse width of the low level of the third clock signal CK3 is smaller than the pulse width of the high level. The clock cycle T of the third clock signal CK3 and the fourth clock signal CK4 are the same in duration. Therefore, the pulse width of the low level of the fourth clock signal CK4 is smaller than the pulse width of the high level.

[0181] In this embodiment, after the pulse width is widened, the first node N1 (or the fifth node N5) can be quickly pulled down, thereby ensuring that the output signal is output quickly to ensure the display quality.

[0182] Figure 5a A schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure; Figure 5b A schematic diagram of another structure of a shift register provided in an embodiment of the present disclosure. In some embodiments, Figure 5a As shown, the shift register also includes an isolation sub-circuit 5; the isolation sub-circuit 5 is configured to isolate the first node N1 and the first control sub-circuit 2 electrically connected to the first node N1; isolate the first node N1 and the output sub-circuit 4 electrically connected to the first node N1; and isolate the second node N2 and the second control sub-circuit 3 electrically connected to the second node N2.

[0183] like Figure 5a As shown, the first control subcircuit 2 is electrically connected to the fifth node N5; the output subcircuit 4 is electrically connected to the fifth node N5; and the second control subcircuit 3 is electrically connected to the fourth node N4 and the first node N1.

[0184] like Figure 5a As shown, the isolation subcircuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1 and the second power signal line VGL2. The isolation subcircuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal; at the same time, connect the second node N2 and the fourth node N4 in response to the first power signal.

[0185] Or, if Figure 5bAs shown, the isolation subcircuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5 and the first power signal line VGL1. The isolation subcircuit 5 is configured to connect the first node N1 and the fifth node N5, and the second node N2 and the fourth node N4 in response to the first power signal.

[0186] In this embodiment, an isolation sub-circuit 5 is added to improve the stability of the output signal.

[0187] The above-mentioned shift register can adopt a circuit structure of 12T3C (i.e., 12 transistors and 3 capacitors); or, the shift register can also adopt a circuit structure of 13T3C (i.e., 13 transistors and 3 capacitors); or, the shift register can also adopt a circuit structure of 16T3C (i.e., 16 transistors and 3 capacitors).

[0188] It should be noted that the transistors in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0189] It should be noted that the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor; wherein, the N-type thin film transistor refers to a thin film transistor in which an N-type ion is doped in an active layer; the P-type thin film transistor refers to a thin film transistor in which a P-type ion is doped in an active layer. The working level signal of the N-type thin film transistor is a high level signal; the working level signal of the P-type thin film transistor is a low level signal.

[0190] For ease of understanding, the present disclosure is described in the following embodiments by taking a P-type thin film transistor as an example, but the present disclosure is not limited to a P-type thin film transistor.

[0191] It should be noted that in the embodiment of the present disclosure, the circuit structure inside the shift register may be a structure with other numbers of transistors in addition to the 12T3C, 13T3C and 16T3C listed above, and the embodiment of the present disclosure is not limited to this.

[0192] The shift registers of the circuit structures of 12T3C, 13T3C and 16T3C are described in detail below using different embodiments.

[0193] In some embodiments, a 12T3C circuit structure is used as an example for description. Figure 2 or Figure 3 Timing control of the clock signal lines shown. Figure 6 A circuit diagram of a 12T3C circuit structure provided in an embodiment of the present disclosure, such as Figure 6 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0194] Continue as Figure 6 As shown, for the input subcircuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2. Specifically, the first clock signal CK1 can control the on-off of the first transistor T1, and when the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on-off of the second transistor T2, and when the second transistor T2 responds to the signal of the first node N1 and turns on, the second clock signal CK2 can be transmitted to the second node N2. The second clock signal CK2 controls the on-off of the third transistor T3, and when the third transistor T3 responds to the second clock signal CK2 and turns on, the first power signal can be transmitted to the second node N2.

[0195] Optionally, for the input sub-circuit 1 , the first electrode of the second transistor T2 may be electrically connected to the first clock signal line CKL1 .

[0196] Continue as Figure 6As shown, for the first control subcircuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5. Specifically, the signal of the fifth node N5 can control the on-off of the fourth transistor T4, and when the fourth transistor T4 responds to the signal of the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on-off of the fifth transistor T5, and when the fifth transistor T5 responds to the signal of the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6.

[0197] The second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the first electrode plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0198] Continue as Figure 6 As shown, for the second control subcircuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first electrode plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second electrode plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1. Specifically, the signal of the fourth node N4 can control the on-off of the sixth transistor T6. When the sixth transistor T6 responds to the signal of the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on-off of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal of the seventh node N7 can be transmitted to the third node N3. The signal of the first node N1 may control the eighth transistor T8 to be turned on. When the eighth transistor T8 responds to the signal of the first node N1 and is turned on, the fourth power signal may be transmitted to the third node N3.

[0199] The second electrode of the sixth transistor T6 , the first electrode of the seventh transistor T7 , and the second electrode plate of the first capacitor C1 are all electrically connected to the seventh node N7 .

[0200] Continue as Figure 6As shown, for the output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first electrode plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second electrode plate of the second capacitor C2 is electrically connected to the third node N3. Specifically, the signal of the third node N3 controls the on-off of the ninth transistor T9. When the ninth transistor T9 responds to the signal of the third node N3 and turns on, the third power signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal of the fifth node N5 controls the on-off of the tenth transistor T10. When the tenth transistor T10 responds to the signal of the fifth node N5 and turns on, the second power signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0201] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9. For example, the potential of the third power signal is 7.5V, and the potential of the fourth power signal is 8V.

[0202] Exemplarily, the potential of the first power signal is less than that of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output. For example, the potential of the first power signal is -8V, and the potential of the fourth power signal is -7.5V.

[0203] Continue as Figure 6 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the first power signal line VGL1 (or the second power signal line VGL2). Specifically, the first power signal controls the on and off of the eleventh transistor T11 and the twelfth transistor T12. When the eleventh transistor T11 responds to the first power signal and turns on, the signal of the second node N2 can be transmitted to the fourth node N4. When the twelfth transistor T12 responds to the first power signal and turns on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0204] In this embodiment, four clock signal lines with different timings and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, so as to shorten the signal output time and improve the uniformity of the large-screen display quality. At the same time, the timing of each clock signal line is different, avoiding the impact of changing the timing on the display effect. In addition, the use of different power signal lines can avoid signal fluctuations caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output.

[0205] In some embodiments, another 12T3C circuit structure is used as an example for description. Figure 4 Timing control of the clock signal lines shown. Figure 7 A circuit diagram of another 12T3C circuit structure provided in an embodiment of the present disclosure, such as Figure 7 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0206] Continue as Figure 7 As shown, for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0207] For the input subcircuit 1, specifically, the first clock signal CK1 can control the on-off of the first transistor T1, and when the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on-off of the second transistor T2, and when the second transistor T2 responds to the signal of the first node N1 and turns on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on-off of the third transistor T3, and when the third transistor T3 responds to the second clock signal CK2 and turns on, the first power signal can be transmitted to the second node N2.

[0208] For example, Figure 4 As shown, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2.

[0209] Continue as Figure 7 As shown, for the first control subcircuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0210] For the first control subcircuit 2, specifically, the signal of the fifth node N5 can control the on-off of the fourth transistor T4, and when the fourth transistor T4 responds to the signal of the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on-off of the fifth transistor T5, and when the fifth transistor T5 responds to the signal of the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6.

[0211] The second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the first electrode plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0212] Continue as Figure 7 As shown, for the second control subcircuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power supply signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1.

[0213] For the second control subcircuit 3, specifically, the signal of the fourth node N4 can control the on-off of the sixth transistor T6, and when the sixth transistor T6 responds to the signal of the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on-off of the seventh transistor T7, and when the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal of the seventh node N7 can be transmitted to the third node N3. The signal of the first node N1 can control the turn-on of the eighth transistor T8, and when the eighth transistor T8 responds to the signal of the first node N1 and turns on, the fourth power signal can be transmitted to the third node N3.

[0214] The second electrode of the sixth transistor T6 , the first electrode of the seventh transistor T7 , and the second electrode plate of the first capacitor C1 are all electrically connected to the seventh node N7 .

[0215] Continue as Figure 7 As shown, for the output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0216] For the output sub-circuit 4, the signal of the third node N3 controls the on-off of the ninth transistor T9. When the ninth transistor T9 responds to the signal of the third node N3 and turns on, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal of the fifth node N5 controls the on-off of the tenth transistor T10. When the tenth transistor T10 responds to the signal of the fifth node N5 and turns on, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0217] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0218] Exemplarily, the potential of the first power signal is smaller than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0219] Continue as Figure 7 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0220] Exemplarily, for the isolation sub-circuit 5, the first power signal controls the on-off of the eleventh transistor T11, and when the eleventh transistor T11 responds to the first power signal and turns on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on-off of the twelfth transistor T12, and when the twelfth transistor T12 responds to the second power signal and turns on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0221] In this embodiment, four clock signal lines with different potentials and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, so as to shorten the signal output time and improve the uniformity of the large-screen display quality. At the same time, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different, which can avoid signal fluctuations caused by excessive load on a single power signal line, and is conducive to improving the stability of signal output.

[0222] In some embodiments, a 13T3C circuit structure is used as an example for description. The 13T3C circuit structure adopts Figure 2 or Figure 3 Timing control of the clock signal lines shown. Figure 8 A circuit diagram of a 13T3C circuit structure provided in an embodiment of the present disclosure, such as Figure 8 As shown, Figure 6 Compared with the 12T3C circuit shown in the figure, the present embodiment adds a thirteenth transistor T13 in the second control sub-circuit 3 to improve the stability of the output signal and prevent the display effect from flickering.

[0223] like Figure 8 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0224] Among them, the circuit structure, connection relationship and working principle of the input subcircuit 1, the first control subcircuit 2, the output subcircuit 4 and the isolation subcircuit 5 are similar to those mentioned above. Figure 6The circuit structures, connection relationships and working principles of the input subcircuit 1, the first control subcircuit 2, the output subcircuit 4 and the isolation subcircuit 5 in the 12T3C circuit shown are the same, and the details can be found in the above description, which will not be repeated here.

[0225] Continue as Figure 8 As shown, for the second control subcircuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first electrode plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second electrode plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the preset control terminal VEL. Specifically, the signal of the fourth node N4 can control the on and off of the sixth transistor T6, and when the sixth transistor T6 responds to the signal of the fourth node N4 and is turned on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on-off of the seventh transistor T7. When the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal of the seventh node N7 can be transmitted to the third node N3. The signal of the first node N1 can control the conduction of the eighth transistor T8. When the eighth transistor T8 responds to the signal of the first node N1 and turns on, the fourth power signal can be transmitted to the third node N3. The preset control terminal VEL is connected to the preset control signal, and the preset control signal controls the on-off of the thirteenth transistor T13. When the thirteenth transistor T13 responds to the preset control signal and turns on, the fourth power signal can be transmitted to the first node N1.

[0226] It should be noted that, in the initialization phase before the shift register working phase, the preset control signal is a low level signal, and the thirteenth transistor T13 is turned on; in the formal working phase, the preset control signal is always a high level signal, and the thirteenth transistor T13 is turned off.

[0227] In some embodiments, another 13T3C circuit structure is used as an example for description. Figure 4 Timing control of the clock signal lines shown. Fig. 9 A circuit diagram of another 13T3C circuit structure provided in an embodiment of the present disclosure, such as Fig. 9 As shown, Figure 7Compared with the 12T3C circuit shown in the figure, the present embodiment adds a thirteenth transistor T13 in the second control sub-circuit 3 to improve the stability of the output signal and prevent the display effect from flickering.

[0228] like Fig. 9 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. The second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1. The output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2. The isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0229] Continue as Fig. 9 As shown, for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2.

[0230] For the input subcircuit 1, specifically, the first clock signal CK1 can control the on-off of the first transistor T1, and when the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on-off of the second transistor T2, and when the second transistor T2 responds to the signal of the first node N1 and turns on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on-off of the third transistor T3, and when the third transistor T3 responds to the second clock signal CK2 and turns on, the first power signal can be transmitted to the second node N2.

[0231] Exemplarily, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2 ; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2 .

[0232] Continue as Fig. 9As shown, for the first control subcircuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the fifth node N5; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the second plate of the third capacitor C3 is electrically connected to the fifth node N5.

[0233] For the first control subcircuit 2, specifically, the signal of the fifth node N5 can control the on-off of the fourth transistor T4, and when the fourth transistor T4 responds to the signal of the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on-off of the fifth transistor T5, and when the fifth transistor T5 responds to the signal of the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6.

[0234] The second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the first electrode plate of the third capacitor C3 are all electrically connected to the sixth node N6.

[0235] Continue as Fig. 9 As shown, for the second control subcircuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first electrode plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second electrode plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the first node N1; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the preset control terminal VEL.

[0236] For the second control subcircuit 3, specifically, the signal of the fourth node N4 can control the on-off of the sixth transistor T6, and when the sixth transistor T6 responds to the signal of the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on-off of the seventh transistor T7, and when the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal of the seventh node N7 can be transmitted to the third node N3. The signal of the first node N1 can control the turn-on of the eighth transistor T8, and when the eighth transistor T8 responds to the signal of the first node N1 and turns on, the fourth power signal can be transmitted to the third node N3.

[0237] The preset control signal is connected to control the on-off of the thirteenth transistor T13 . When the thirteenth transistor T13 responds to the preset control signal and is turned on, the fourth power signal can be transmitted to the first node N1 .

[0238] It should be noted that, in the initialization phase before the shift register working phase, the preset control signal is a low level signal, and the thirteenth transistor T13 is turned on; in the formal working phase, the preset control signal is always a high level signal, and the thirteenth transistor T13 is turned off.

[0239] Continue as Fig. 9 As shown, for the output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0240] For the output sub-circuit 4, the signal of the third node N3 controls the on-off of the ninth transistor T9. When the ninth transistor T9 responds to the signal of the third node N3 and turns on, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal of the fifth node N5 controls the on-off of the tenth transistor T10. When the tenth transistor T10 responds to the signal of the fifth node N5 and turns on, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0241] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0242] Exemplarily, the potential of the first power signal is smaller than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0243] Continue as Fig. 9 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0244] Exemplarily, for the isolation sub-circuit 5, the first power signal controls the on-off of the eleventh transistor T11, and when the eleventh transistor T11 responds to the first power signal and turns on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on-off of the twelfth transistor T12, and when the twelfth transistor T12 responds to the second power signal and turns on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0245] In this embodiment, four clock signal lines with different potentials and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, so as to shorten the signal output time and improve the uniformity of the large-screen display quality. At the same time, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different, which can avoid the signal fluctuation caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output. In addition, the load on each power signal line is balanced, for example, the first power signal line VGL1 is connected to the third transistor T3 and the eleventh transistor T11, the second power signal line VGL2 is connected to the tenth transistor T10 and the twelfth transistor T12; the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0246] In some embodiments, Fig.10 A structural diagram of another shift register provided in an embodiment of the present disclosure is shown in FIG. Fig.10 As shown, the shift register also includes an isolation sub-circuit 5; the isolation sub-circuit 5 is configured to isolate the first node N1 and the first control sub-circuit 2 electrically connected to the first node N1; isolate the first node N1 and the output sub-circuit 4 electrically connected to the first node N1; isolate the first node N1 and the second control sub-circuit 3 electrically connected to the first node N1; and isolate the second node N2 and the second control sub-circuit 3 electrically connected to the second node N2.

[0247] like Fig.10 As shown, the first control subcircuit 2 is electrically connected to the fifth node N5; the output subcircuit 4 is electrically connected to the fifth node N5; and the second control subcircuit 3 is electrically connected to the fourth node N4 and the fifth node N5.

[0248] like Fig.10As shown, the isolation subcircuit 5 is electrically connected to the first node N1, the second node N2, the fourth node N4, the fifth node N5, the first power signal line VGL1 and the second power signal line VGL2. The isolation subcircuit 5 is configured to connect the first node N1 and the fifth node N5 in response to the second power signal; at the same time, connect the second node N2 and the fourth node N4 in response to the first power signal.

[0249] Alternatively, the isolation subcircuit 5 electrically connects the first node N1, the second node N2, the fourth node N4, the fifth node N5 and the first power signal line VGL1. The isolation subcircuit 5 is configured to connect the first node N1 and the fifth node N5, and the second node N2 and the fourth node N4 in response to the first power signal.

[0250] In this embodiment, an isolation sub-circuit 5 is added to improve the stability of the output signal.

[0251] Take a 16T3C circuit structure as an example to illustrate. The 16T3C circuit structure adopts Figure 2 or Figure 3 Timing control of the clock signal lines shown. Fig.11 A circuit diagram of a 16T3C circuit structure provided in an embodiment of the present disclosure, such as Fig.11 As shown, Figure 8 Compared with the 13T3C circuit shown in FIG. 1 , the present embodiment adds a fourteenth transistor T14 in the input sub-circuit 1 , and adds a fifteenth transistor T15 and a sixteenth transistor T16 in the first control sub-circuit 2 .

[0252] like Fig.11 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourteenth transistor T14; the first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3; the second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1; the output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2; the isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0253] Among them, the circuit structure, connection relationship and working principle of the second control subcircuit 3, the output subcircuit 4 and the isolation subcircuit 5 are similar to those mentioned above. Figure 8 The circuit structures, connection relationships and working principles of the second control subcircuit 3, the output subcircuit 4 and the isolation subcircuit 5 in the 13T3C circuit shown are the same, and the details can be found in the above description, which will not be repeated here.

[0254] Continue as Fig.11 As shown, for the input subcircuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the eighth node N8, and the control electrode is electrically connected to the first clock signal line CKL1. Specifically, the first clock signal CK1 can control the on-off of the first transistor T1, and when the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on-off of the second transistor T2, and when the second transistor T2 responds to the signal of the first node N1 and turns on, the second clock signal CK2 can be transmitted to the second node N2. The second clock signal CK2 controls the on-off of the third transistor T3. When the third transistor T3 responds to the second clock signal CK2 and turns on, the first power signal can be transmitted to the second node N2. The first clock signal CK1 can also control the on-off of the fourteenth transistor T14. When the fourteenth transistor T14 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the eighth node N8.

[0255] Continue as Fig.11As shown, for the first control subcircuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the second electrode plate of the third capacitor C3; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first electrode plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, the second electrode is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power signal line VGL1; the second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and the control electrode is electrically connected to the control electrode of the fourth transistor T4. Specifically, the signal of the fifth node N5 can control the on and off of the fourth transistor T4, and when the fourth transistor T4 responds to the signal of the fifth node N5 and is turned on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on-off of the fifth transistor T5, and when the fifth transistor T5 responds to the signal of the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6. The first power signal can control the on-off of the fifteenth transistor T15, and when the fifteenth transistor T15 responds to the first power signal and turns on, the signal of the eighth node N8 can be transmitted to the ninth node N9; the signal of the ninth node N9 can control the on-off of the sixteenth transistor T16, and when the sixteenth transistor T16 responds to the signal of the ninth node N9 and turns on, the signal of the ninth node N9 can be transmitted to the fifth node N5.

[0256] In this embodiment, four clock signal lines with different timings and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, so as to shorten the signal output time and improve the uniformity of the large-screen display quality. At the same time, the timing of each clock signal line is different, so as to avoid the influence of changing the timing at the same time on the display effect. In addition, the use of different power signal lines can avoid the signal fluctuation caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output. In addition, the load on each power signal line is balanced, for example, the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0257] Optionally, for the first control sub-circuit 2 , the first electrode of the fifth transistor T5 may be electrically connected to the fourth power signal line VGH2 .

[0258] In some embodiments, another 16T3C circuit structure is used as an example for description. Figure 4Timing control of the clock signal lines shown. Fig.12 A circuit diagram of another 16T3C circuit structure provided in an embodiment of the present disclosure, such as Fig.12 As shown, Fig. 9 Compared with the 13T3C circuit shown in FIG. 1 , the present embodiment adds a fourteenth transistor T14 in the input sub-circuit 1 , and adds a fifteenth transistor T15 and a sixteenth transistor T16 in the first control sub-circuit 2 .

[0259] like Fig.12 As shown, the input subcircuit 1 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourteenth transistor T14; the first control subcircuit 2 includes a fourth transistor T4, a fifth transistor T5, a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3; the second control subcircuit 3 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a thirteenth transistor T13 and a first capacitor C1; the output subcircuit 4 includes a ninth transistor T9, a tenth transistor T10 and a second capacitor C2; the isolation subcircuit 5 includes an eleventh transistor T11 and a twelfth transistor T12.

[0260] Continue as Fig.12 As shown, for the input sub-circuit 1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the second clock signal line CKL2; the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the eighth node N8, and the control electrode is electrically connected to the second clock signal line CKL2.

[0261] For the input subcircuit 1, specifically, the first clock signal CK1 can control the on-off of the first transistor T1, and when the first transistor T1 responds to the first clock signal CK1 and turns on, the input signal can be transmitted to the first node N1. The signal of the first node N1 can control the on-off of the second transistor T2, and when the second transistor T2 responds to the signal of the first node N1 and turns on, the first clock signal CK1 can be transmitted to the second node N2. The second clock signal CK2 controls the on-off of the third transistor T3, and when the third transistor T3 responds to the second clock signal CK2 and turns on, the first power supply signal can be transmitted to the second node N2. The second clock signal CK2 can also control the on-off of the fourteenth transistor T14, and when the fourteenth transistor T14 responds to the second clock signal CK2 and turns on, the input signal can be transmitted to the eighth node N8.

[0262] For example, Figure 4 As shown, the potential of the first level of the first clock signal CK1 is different from the potential of the first level of the second clock signal CK2; the potential of the second level of the first clock signal CK1 is different from the potential of the second level of the second clock signal CK2, which can avoid the problem of transistor hysteresis caused by the gate-source of the third transistor T3 and the first transistor T1 being at the same voltage difference for a long time, and the gate-source of the fourteenth transistor T14 and the first transistor T1 being at the same voltage difference for a long time, affecting the transistor characteristics.

[0263] Continue as Fig.12 As shown, for the first control subcircuit 2, the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3, the second electrode is electrically connected to the second electrode of the fifth transistor T5, and the control electrode is electrically connected to the second plate of the third capacitor C3; the first electrode of the fifth transistor T5 is electrically connected to the third power signal line VGH1, the second electrode is electrically connected to the first plate of the third capacitor C3, and the control electrode is electrically connected to the second node N2; the first electrode of the fifteenth transistor T15 is electrically connected to the eighth node N8, the second electrode is electrically connected to the first electrode of the sixteenth transistor T16 and the control electrode of the sixteenth transistor T16, and the control electrode is electrically connected to the first power signal line VGL1; the second electrode of the sixteenth transistor T16 is electrically connected to the fifth node N5, and the control electrode is electrically connected to the control electrode of the fourth transistor T4.

[0264] For the first control subcircuit 2, specifically, the signal of the fifth node N5 can control the on-off of the fourth transistor T4, and when the fourth transistor T4 responds to the signal of the fifth node N5 and turns on, the third clock signal CK3 can be transmitted to the sixth node N6. The signal of the second node N2 can control the on-off of the fifth transistor T5, and when the fifth transistor T5 responds to the signal of the second node N2 and turns on, the third power signal can be transmitted to the sixth node N6. The first power signal can control the on-off of the fifteenth transistor T15, and when the fifteenth transistor T15 responds to the first power signal and turns on, the signal of the eighth node N8 can be transmitted to the ninth node N9; the signal of the ninth node N9 can control the on-off of the sixteenth transistor T16, and when the sixteenth transistor T16 responds to the signal of the ninth node N9 and turns on, the signal of the ninth node N9 can be transmitted to the fifth node N5.

[0265] The control electrode of the fourth transistor T4, the second plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, the second electrode of the sixteenth transistor T16, and the control electrode of the sixteenth transistor T16 are all electrically connected to the ninth node N9.

[0266] Continue as Fig.12As shown, for the second control subcircuit 3, the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4, the second electrode is electrically connected to the first electrode of the seventh transistor T7, and the control electrode is electrically connected to the fourth node N4 and the first electrode plate of the first capacitor C1; the first electrode of the seventh transistor T7 is electrically connected to the second electrode plate of the first capacitor C1, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fourth clock signal line CKL4; the first electrode of the eighth transistor T8 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the fifth node N5; the first electrode of the thirteenth transistor T13 is electrically connected to the fourth power signal line VGH2, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the preset control terminal VEL.

[0267] For the second control subcircuit 3, specifically, the signal of the fourth node N4 can control the on-off of the sixth transistor T6, and when the sixth transistor T6 responds to the signal of the fourth node N4 and turns on, the fourth clock signal CK4 can be transmitted to the seventh node N7. The fourth clock signal CK4 can control the on-off of the seventh transistor T7, and when the seventh transistor T7 responds to the fourth clock signal CK4 and turns on, the signal of the seventh node N7 can be transmitted to the third node N3. The signal of the fifth node N5 can control the turn-on of the eighth transistor T8, and when the eighth transistor T8 responds to the signal of the fifth node N5 and turns on, the fourth power signal can be transmitted to the third node N3.

[0268] The preset control signal is connected to control the on-off of the thirteenth transistor T13 . When the thirteenth transistor T13 responds to the preset control signal and is turned on, the fourth power signal can be transmitted to the fifth node N5 .

[0269] Continue as Fig.12 As shown, for the output sub-circuit 4, the first electrode of the ninth transistor T9 is electrically connected to the third power signal line VGH1 and the first plate of the second capacitor C2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the third node N3; the first electrode of the tenth transistor T10 is electrically connected to the second power signal line VGL2, the second electrode is electrically connected to the signal output terminal OUT, and the control electrode is electrically connected to the fifth node N5; the second plate of the second capacitor C2 is electrically connected to the third node N3.

[0270] For the output sub-circuit 4, the signal of the third node N3 controls the on-off of the ninth transistor T9. When the ninth transistor T9 responds to the signal of the third node N3 and turns on, the third power supply signal is transmitted to the signal output terminal OUT, thereby outputting the second output signal. The signal of the fifth node N5 controls the on-off of the tenth transistor T10. When the tenth transistor T10 responds to the signal of the fifth node N5 and turns on, the second power supply signal is output to the signal output terminal OUT, thereby outputting the first output signal.

[0271] Exemplarily, the potential of the third power signal is lower than the potential of the fourth power signal, which can improve the turn-off characteristic of the ninth transistor T9.

[0272] Exemplarily, the potential of the first power signal is smaller than the potential of the second power signal, which can reduce the threshold loss of the tenth transistor T10 and ensure output.

[0273] Continue as Fig.12 As shown, for the isolation sub-circuit 5, the first electrode of the eleventh transistor T11 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first power signal line VGL1; the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second power signal line VGL2.

[0274] Exemplarily, for the isolation sub-circuit 5, the first power signal controls the on-off of the eleventh transistor T11, and when the eleventh transistor T11 responds to the first power signal and turns on, the signal of the second node N2 can be transmitted to the fourth node N4. The second power signal controls the on-off of the twelfth transistor T12, and when the twelfth transistor T12 responds to the second power signal and turns on, the signal of the first node N1 can be transmitted to the fifth node N5.

[0275] In this embodiment, four clock signal lines with different potentials and four power signal lines with different potentials are used to reduce the number of transistors connected to a single clock signal line and a single power signal line, thereby reducing the load on each clock signal line and each power signal line, so as to shorten the signal output time and improve the uniformity of the large-screen display quality. At the same time, the first power signal line VGL1, the second power signal line VGL2, the third power signal line VGH1 and the fourth power signal line VGH2 are all different, which can avoid the signal fluctuation caused by excessive load on a single power signal line, which is conducive to improving the stability of signal output. In addition, the load on each power signal line is balanced, for example, the third power signal line VGH1 is connected to the ninth transistor T9 and the fifth transistor T5, and the fourth power signal line VGH2 is connected to the eighth transistor T8 and the thirteenth transistor T13, which can further improve the display effect.

[0276] In some embodiments, the above Figure 7 12T3C shown, such as Fig. 9 13T3C shown and Fig.12 In the circuit structure of 16T3C shown, the first transistor T1 and the third transistor T3 in the input sub-circuit 1 can be connected to the same first clock signal line CKL1, and the second transistor T2 is connected to the second clock signal line CKL2.

[0277] Exemplarily, the input subcircuit 1 includes a first transistor T1, a second transistor T2 and a third transistor T3; the first electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1; the first electrode of the third transistor T3 is electrically connected to the first power signal line VGL1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first clock signal line CKL1.

[0278] In some embodiments, the above Figure 7 12T3C shown, such as Fig. 9 13T3C shown and Fig.12 In the circuit structure of 16T3C shown, the eleventh transistor T11 and the twelfth transistor T12 in the isolation sub-circuit 5 can also be connected to the same first power signal line VGL1 to ensure the stability of the output signal during the isolation process.

[0279] The working principle of the shift register provided by the embodiment of the present disclosure is further described in detail below.

[0280] In some embodiments, Fig.13 An exemplary timing diagram of a shift register provided in an embodiment of the present disclosure is shown in FIG. Fig.13 As shown, using Figure 2 The 12T3C circuit structure of the timing control of the clock signal line shown in FIG. Figure 6 The 12T3C circuit structure shown in FIG. 1 is used as an example to illustrate that the working stages specifically include the first stage t1, the second stage t2, the third stage t3, the fourth stage t4, the fifth stage t5, the sixth stage t6, the seventh stage t7, the eighth stage t8, the ninth stage t9, the tenth stage t10, the eleventh stage t11, and the twelfth stage t12, wherein:

[0281] In the first stage t1, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is a valid level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, the first node N1 and the fifth node N5 are written with a high-level signal, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, the third node N3 maintains the high potential of the previous stage unchanged, and the ninth transistor T9 is turned off. At this time, the output signal remains the same as the previous stage, and the signal output terminal OUT outputs the first output signal of the low potential.

[0282] In the second stage t2, the input signal transmitted by the signal input terminal Input is a high-level signal, the second clock signal CK2 is a valid level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the third transistor T3 is turned on, the second node N2 is written with a low-level signal, the fifth transistor T5 is turned on, the sixth node N6 is written with a high-level signal, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. The first node N1 and the fifth node N5 maintain the high potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also in the off state, the third node N3 maintains the high potential of the previous stage unchanged, and the ninth transistor T9 is turned off. The output signal at this time maintains the previous stage, and the signal output terminal OUT outputs the first output signal of the low potential.

[0283] In the third stage t3, the input signal transmitted by the signal input terminal Input is a high-level signal, the third clock signal CK3 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off. The second node N2 and the fourth node N4 maintain the low potential of the previous stage, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. However, the seventh transistor T7 remains in the off state, so the third node N3 maintains the high potential of the previous stage unchanged, and the ninth transistor T9 is turned off. The output signal at this time maintains the previous stage, and the signal output terminal OUT outputs the first output signal of the low potential.

[0284] In the fourth stage t4, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the eighth transistor T8 and the tenth transistor T10 are all turned off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and the sixth node N6 is written with a high-level signal. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, the seventh node N7 is written with a low-level signal, and the seventh transistor T7 is turned on, the third node N3 is written with a low-level signal, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-potential second output signal.

[0285] In the fifth stage t5, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is a valid level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, the first node N1 and the fifth node N5 are written with a high-level signal, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, the third node N3 maintains the low potential of the previous stage unchanged, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-potential second output signal.

[0286] In the sixth stage t6, the input signal transmitted by the signal input terminal Input is a high-level signal, the second clock signal CK2 is a valid level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the third transistor T3 is turned on, the second node N2 is written with a low-level signal, the fifth transistor T5 is turned on, the sixth node N6 is written with a high-level signal, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. The first node N1 and the fifth node N5 maintain the high potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, and the seventh transistor T7 is also in the off state, the third node N3 maintains the low potential of the previous stage unchanged, the ninth transistor T9 is turned on, and the signal output terminal OUT outputs a high-potential second output signal.

[0287] In the seventh stage t7, the input signal transmitted by the signal input terminal Input is a high-level signal, the third clock signal CK3 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off. The second node N2 and the fourth node N4 maintain the low potential of the previous stage, the sixth transistor T6 is turned on, and the seventh node N7 is written with a high-level signal. However, the seventh transistor T7 remains in the off state, so the third node N3 maintains the high potential of the previous stage unchanged, the third node N3 maintains the low potential of the previous stage unchanged, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-potential second output signal.

[0288] The working state of the eighth stage t8 is the same as the working state of the fourth stage t4. Specifically, in the eighth stage t8, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 both maintain the high potential of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off. The second node N2 maintains the low potential of the previous stage, the fifth transistor T5 is turned on, and the sixth node N6 is written with a high-level signal. The fourth node N4 maintains the low potential of the previous stage, the sixth transistor T6 is turned on, the seventh node N7 is written with a low-level signal, and the seventh transistor T7 is turned on, the third node N3 is written with a low-level signal, and the ninth transistor T9 is turned on. At this time, the signal output terminal OUT outputs a high-potential second output signal.

[0289] In the ninth stage t9, the input signal transmitted by the signal input terminal Input is a low-level signal, the first clock signal CK1 is a valid level, which can be understood as a low level, and the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first transistor T1 is turned on, the first node N1 is written with a low-level signal, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, the fourth transistor T4 is turned on, and the sixth node N6 is written with a high-level signal. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, which is a low potential V1 at this time, the tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-level first output signal.

[0290] In the tenth stage t10, the input signal transmitted by the signal input terminal Input is a low-level signal, the second clock signal CK2 is a valid level, which can be understood as a low level, and the first clock signal CK1, the third clock signal CK3 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 and the fifth node N5 maintain the low potential V1 of the previous stage, the eighth transistor T8 remains turned on, the third node N3 continues to be written with a high-level signal, the ninth transistor T9 remains turned off, the tenth transistor T10 remains turned on, and the signal output terminal OUT continues to output the first output signal of the low potential.

[0291] In the eleventh stage t11, the input signal transmitted by the signal input terminal Input is a low-level signal, the third clock signal CK3 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. At the same time, the fourth transistor T4 is turned on, the sixth node N6 is written with a low-level signal, and the low potential V1 of the fifth node N5 is further pulled down to the low potential V2 by the action of the third capacitor C3, the tenth transistor T10 is continuously turned on, and the signal output terminal OUT outputs the first output signal of the low potential.

[0292] In the twelfth stage t12, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are cut off. At the same time, the fourth transistor T4 is turned on, and the sixth node N6 is written with a high-level signal. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, which is a low potential V1 at this time, the tenth transistor T10 is turned on, and the signal output terminal OUT outputs the first output signal of a low potential (that is, Fig.13 OUT1 in the output. Fig.13 OUT2 in the figure represents the signal outputted from the signal output terminal OUT of the next cascaded shift register.

[0293] In some embodiments, Fig.14 Another exemplary timing diagram of a shift register provided in the embodiment of the present disclosure is as follows: Fig.14 As shown, using Figure 3 The 12T3C circuit structure of the timing control of the clock signal line shown in FIG. Figure 6 The 12T3C circuit structure shown in the figure is used as an example for explanation, and its working stages specifically include the first stage t_1, the second stage t_2, the third stage t_3, the fourth stage t_4, the fifth stage t_5, the sixth stage t_6, the seventh stage t_7, the eighth stage t_8, the ninth stage t_9, the tenth stage t_10, the eleventh stage t_11, and the twelfth stage t_12.

[0294] Here and above Fig.13 The difference between the timings shown is that the fourth clock signal CK4 of the third stage t_3, the seventh stage t_7 and the eleventh stage t_11 is at a valid level, and the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are at an invalid level; the third clock signal CK3 of the fourth stage t_4, the eighth stage t_8 and the twelfth stage t_12 is at a valid level, and the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 are at an invalid level.

[0295] The working principles of the first stage t_1 and the first stage t1, the second stage t_2 and the second stage t2, the fifth stage t_5 and the fifth stage t5, the sixth stage t_6 and the sixth stage t6, the ninth stage t_9 and the ninth stage t9, and the tenth stage t_10 and the tenth stage t10 are the same, and the repeated parts are not repeated here.

[0296] like Fig.14 As shown, in the eleventh stage t11, the input signal transmitted by the signal input terminal Input is a high-level signal, the fourth clock signal CK4 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, the fourth transistor T4 is turned on, and the sixth node N6 is written with a high-level signal. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. The fifth node N5 is connected to the first node N1, which is a low potential V1 at this time, the tenth transistor T10 is turned on, and the signal output terminal OUT outputs a low-potential first output signal.

[0297] like Fig.14 As shown, in the twelfth stage t_12, the input signal transmitted by the signal input terminal Input is a low-level signal, the third clock signal CK3 is a valid level, which can be understood as a low level, and the first clock signal CK1, the second clock signal CK2 and the fourth clock signal CK4 are invalid levels, which can be understood as a high level. The eleventh transistor T11 and the twelfth transistor T12 are normally open. At this time, the first node N1 maintains the low potential V1 of the previous stage, the second transistor T2 is turned on, the second node N2 is written with a high-level signal, and the fifth transistor T5 and the sixth transistor T6 are turned off. At the same time, the eighth transistor T8 is turned on, the third node N3 is written with a high-level signal, and the ninth transistor T9 is turned off. At the same time, the fourth transistor T4 is turned on, the sixth node N6 is written with a low-level signal, and the low potential V1 of the fifth node N5 is further pulled down to the low potential V2 by the action of the third capacitor C3, the tenth transistor T10 is continuously turned on, and the signal output terminal OUT outputs the first output signal of the low potential.

[0298] In some embodiments, Fig.15 Another exemplary timing diagram of a shift register provided in the embodiment of the present disclosure is as follows: Fig.15 As shown, using Figure 4 The 12T3C circuit structure of the timing control of the clock signal line shown in FIG. Figure 7 The 12T3C circuit structure shown in FIG. 1 is used as an example to illustrate that the working stages specifically include the first stage t_21, the second stage t_22, the third stage t_23, the fourth stage t_24, the fifth stage t_25 and the sixth stage t_26, wherein:

[0299] In the first stage t_21, the input signal transmitted by the signal input terminal Input is a high-level signal, the first clock signal CK1 is the first level, and the second clock signal CK2 is the first level, which can be understood as a low level; the third clock signal CK3 is the fourth level, and the fourth clock signal CK4 is the fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, and the first transistor T1 and the third transistor T3 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally open twelfth transistor T12, thereby controlling the potential of the first node N1 and the fifth node N5 to be a high potential. At the same time, the first power supply signal is a low-level signal, and the first power supply signal is transmitted to the fourth node N4 through the third transistor T3 and the normally open eleventh transistor T11, thereby controlling the potential of the second node N2 and the fourth node N4 to be a low potential. Correspondingly, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all turned off, and the output signal at this time remains the same as the previous stage, such as Figure 8 As shown, the low potential output of the previous stage is maintained.

[0300] In the second stage t_22, the first clock signal CK1 is at the second level, the second clock signal CK2 is at the second level, which can be understood as a high level; the third clock signal CK3 is at the third level, and the fourth clock signal CK4 is at the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, and the fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is low at this time, and the ninth transistor T9 is turned on, thereby outputting the second output signal, that is, the third power supply signal of high potential.

[0301] In the third stage t_23, the input signal is a high-level signal, the first clock signal CK1 is the first level, the second clock signal CK2 is the first level, which can be understood as a low level; the third clock signal CK3 is the fourth level, and the fourth clock signal CK4 is the fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, and the potential of the third node N3 is stably maintained at the low potential of the previous stage. At this time, the ninth transistor T9 can remain turned on, thereby outputting the second output signal, that is, the third power supply signal of the high potential.

[0302] In the fourth stage t_24, the input signal is a low-level signal, the first clock signal CK1 is the second level, the second clock signal CK2 is the second level, which can be understood as a high level; the third clock signal CK3 is the third level, and the fourth clock signal CK4 is the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the high potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are all turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, and the fourth clock signal CK4 is transmitted to the third node N3 through the turned-on sixth transistor T6 and the turned-on seventh transistor T7. The potential of the third node N3 is low at this time, and the ninth transistor T9 is turned on, thereby outputting the second output signal, that is, the third power supply signal of high potential.

[0303] In the fifth stage t_25, the input signal is a low-level signal, the first clock signal CK1 is a first level, and the second clock signal CK2 is a first level, which can be understood as a low level; the third clock signal CK3 is a fourth level, and the fourth clock signal CK4 is a fourth level, which can be understood as a high level. At this time, the seventh transistor T7 is turned off, the first transistor T1 and the second transistor T2 are turned on, so that the input signal is transmitted to the fifth node N5 through the first transistor T1 and the normally open twelfth transistor T12, thereby controlling the potential of the first node N1 and the fifth node N5 to be a low potential. At the same time, the first power supply signal is a low-level signal, and the first power supply signal is transmitted to the fourth node N4 through the third transistor T3 and the normally open eleventh transistor T11, thereby controlling the potential of the second node N2 and the fourth node N4 to be a low potential. Correspondingly, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 are turned on, and because the eighth transistor T8 is turned on, the third node N3 is a high level, so the ninth transistor T9 is turned off. At the same time, affected by threshold loss, the potential of the fifth node N5 is slightly higher than the potential of the second power signal. At this time, the tenth transistor T10 is not fully turned on, so the potential of the first output signal will be slightly higher than the potential of the second power signal.

[0304] In the sixth stage t_26, the input signal is a low-level signal, the first clock signal CK1 is the second level, the second clock signal CK2 is the second level, which can be understood as a high level; the third clock signal CK3 is the third level, and the fourth clock signal CK4 is the third level, which can be understood as a low level. At this time, the first transistor T1 and the third transistor T3 are turned off, the seventh transistor T7 is turned on, and under the storage effect of the second capacitor C2, the first node N1 and the fifth node N5 maintain the low potential of the previous stage, and the second node N2 and the fourth node N4 maintain the low potential of the previous stage. Correspondingly, the eighth transistor T8 and the tenth transistor T10 are turned on, and the fourth power supply signal is transmitted to the third node N3 through the turned-on eighth transistor T8, and the potential of the third node N3 is pulled up to a high potential. At this time, the ninth transistor T9 is turned off. At the same time, the potential of the fifth node N5 can be reduced to a lower potential than the second power supply signal through the coupling of the second capacitor C2. At this time, the tenth transistor T10 is fully turned on, and the potential of the signal output terminal OUT is reduced to the potential of the second power supply signal, that is, the first output signal.

[0305] The above is a complete introduction to the shift register provided in the embodiment of the present disclosure.

[0306] In addition, an embodiment of the present disclosure also provides a gate drive circuit, comprising N cascaded shift registers; except for the first-stage shift register, the signal input terminal Input of the i+1-stage shift register is electrically connected to the signal output terminal OUT of the i-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0307] In some embodiments, Fig.16 A schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure is shown in FIG. Fig.16 As shown, the first clock signal line CKL1 in the i-th level shift register is multiplexed as the fourth clock signal line CKL4 in the i+1-th level shift register, the second clock signal line CKL2 in the i-th level shift register is multiplexed as the first clock signal line CKL1 in the i+1-th level shift register, the third clock signal line CKL3 in the i-th level shift register is multiplexed as the second clock signal line CKL2 in the i+1-th level shift register, and the fourth clock signal line CKL4 in the i-th level shift register is multiplexed as the third clock signal line CKL3 in the i+1-th level shift register.

[0308] like Fig.16 The gate drive circuit shown is suitable for Figure 2 or Figure 3 The driving timing is shown.

[0309] In some embodiments, Fig.17 A schematic diagram of another gate drive circuit provided by an embodiment of the present disclosure is shown in FIG. Fig.17 As shown, the first clock signal line CKL1 in the i-th level shift register is multiplexed as the third clock signal line CKL3 in the i+1-th level shift register, the second clock signal line CKL2 in the i-th level shift register is multiplexed as the fourth clock signal line CKL4 in the i+1-th level shift register, the third clock signal line CKL3 in the i-th level shift register is multiplexed as the first clock signal line CKL1 in the i+1-th level shift register, and the fourth clock signal line CKL4 in the i-th level shift register is multiplexed as the second clock signal line CKL2 in the i+1-th level shift register.

[0310] like Fig.17 The gate drive circuit shown is suitable for Figure 4 The driving timing is shown.

[0311] Fig.18 The embodiments of the present disclosure provide Figure 6 The circuit diagram of the shift register cascade of the 12T3C circuit structure is shown. Fig.19 The embodiments of the present disclosure provide Figure 8 The circuit diagram of the shift register cascade of the 13T3C circuit structure is shown in FIG. Fig. 20 The embodiments of the present disclosure provide Fig.11 The circuit diagram of the shift register cascade of the 16T3C circuit structure is shown.

[0312] In some embodiments, Fig.18 or Fig.19 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1-th stage shift register cascaded with the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0313] The timing of the output signal terminal OUT of the i-th stage shift register is as follows: Fig.13 The OUT signal shown in FIG. 1 and the timing of the output signal terminal OUT2 of the i+1-th stage shift register are shown in FIG. Fig.13 Alternatively, the timing of the output signal terminal OUT of the i-th stage shift register is as shown in FIG. Fig.14 The OUT signal shown in FIG. 1 and the timing of the output signal terminal OUT2 of the i+1-th stage shift register are shown in FIG. Fig.14 OUT2 signal shown.

[0314] In some embodiments, Fig. 20 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the second clock signal line CKL2; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal line CKL1; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1th shift register cascaded with the i-th shift register, the control electrode of the first transistor T1 is electrically connected to the fourth clock signal line CKL4; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the first clock signal line CKL1; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the second clock signal line CKL2; the first electrode of the sixth transistor T6 is electrically connected to the third clock signal line CKL3; and the control electrode of the seventh transistor T7 is electrically connected to the third clock signal line CKL3.

[0315] Fig.21 The embodiments of the present disclosure provide Figure 7 The circuit diagram of the shift register cascade of the 12T3C circuit structure is shown. Fig. 22 The embodiments of the present disclosure provide Fig. 9 The circuit diagram of the shift register cascade of the 13T3C circuit structure is shown in FIG. Fig.23 The embodiments of the present disclosure provide Fig.12 The circuit diagram of the shift register cascade of the 16T3C circuit structure is shown.

[0316] In some embodiments, Fig.21 or Fig. 22As shown, for the i-th shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1-th shift register cascaded with the i-th shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0317] In some embodiments, Fig.23 As shown, for the i-th stage shift register, the control electrode of the first transistor T1 is electrically connected to the first clock signal line CKL1; the first electrode of the second transistor T2 is electrically connected to the first clock signal line CKL1; the control electrode of the third transistor T3 is electrically connected to the second clock signal line CKL2; the control electrode of the fourteenth transistor T14 is electrically connected to the second clock signal line CKL2; the first electrode of the fourth transistor T4 is electrically connected to the third clock signal line CKL3; the first electrode of the sixth transistor T6 is electrically connected to the fourth clock signal line CKL4; and the control electrode of the seventh transistor T7 is electrically connected to the fourth clock signal line CKL4. For the i+1th shift register cascaded with the i-th shift register, the control electrode of the first transistor T1 is electrically connected to the third clock signal line CKL3; the first electrode of the second transistor T2 is electrically connected to the third clock signal line CKL3; the control electrode of the third transistor T3 is electrically connected to the fourth clock signal line CKL4; the control electrode of the fourteenth transistor T14 is electrically connected to the fourth clock signal line CKL4; the first electrode of the fourth transistor T4 is electrically connected to the first clock signal line CKL1; the first electrode of the sixth transistor T6 is electrically connected to the second clock signal line CKL2; and the control electrode of the seventh transistor T7 is electrically connected to the second clock signal line CKL2.

[0318] Since the i-th shift register and the i+1-th shift register cascaded with each other in the gate drive circuit are respectively electrically connected to a set of clock signals with different timings, that is, the first clock signal CK1 and the second clock signal CK2, which are different in timing from the third clock signal CK3 and the fourth clock signal CK4, the timings of the two are not affected.

[0319] In addition, an embodiment of the present disclosure further provides a display device, which includes a pixel driving circuit and a gate driving circuit as described above, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

[0320] For example, the display device can be any product with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations on the present disclosure.

[0321] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, characterized in that: comprising a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, an input subcircuit, a first control subcircuit, a second control subcircuit and an output subcircuit; The input subcircuit is configured to control the potentials of the first node and the second node in response to a first clock signal provided by the first clock signal line and a second clock signal provided by the second clock signal line; The first control subcircuit is configured to control the potential of the first node in response to the signal of the second node and the third clock signal provided by the third clock signal line; The second control subcircuit is configured to control the potential of the third node in response to the signal of the first node, the signal of the second node and the fourth clock signal provided by the fourth clock signal line; The output sub-circuit is configured to output a first output signal in response to a signal at the first node, or to output a second output signal in response to a signal at the third node.

2. The shift register according to claim 1, characterized in that: In one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the third clock signal, and a pulse of the third clock signal precedes a pulse of the fourth clock signal.

3. The shift register according to claim 1, characterized in that: In one clock cycle, a pulse of the first clock signal precedes a pulse of the second clock signal, a pulse of the second clock signal precedes a pulse of the fourth clock signal, and a pulse of the fourth clock signal precedes a pulse of the third clock signal.

4. The shift register according to claim 1, wherein: The first clock signal and the second clock signal have the same timing; the third clock signal and the first clock signal have opposite timing; the fourth clock signal and the third clock signal have the same timing.

5. The shift register according to claim 4, characterized in that: The first clock signal and the second clock signal include a first level; a potential of the first level of the first clock signal is different from a potential of the first level of the second clock signal; and / or, The third clock signal and the fourth clock signal include a third level; a potential of the third level of the third clock signal is different from a potential of the third level of the fourth clock signal.

6. The shift register according to claim 5, characterized in that: The potential of the first level of the first clock signal is lower than the potential of the first level of the second clock signal; and / or, The potential of the third level of the third clock signal is lower than the potential of the third level of the fourth clock signal.

7. The shift register according to claim 5, characterized in that: The first clock signal and the second clock signal further include a second level, the second level being different from the first level; The potential of the second level of the first clock signal is different from the potential of the second level of the second clock signal; and / or, The third clock signal and the fourth clock signal further include a fourth level, and the fourth level is different from the third level; A potential of a fourth level of the third clock signal is different from a potential of a fourth level of the fourth clock signal.

8. The shift register according to claim 7, characterized in that: The potential of the second level of the first clock signal is greater than the potential of the second level of the second clock signal; and / or, The potential of the fourth level of the third clock signal is greater than the potential of the fourth level of the fourth clock signal.

9. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes a first power signal line, a second power signal line, a third power signal line and a fourth power signal line; The input subcircuit is electrically connected to the first power signal line, the first control subcircuit is electrically connected to the third power signal line, the second control subcircuit is electrically connected to the fourth power signal line, and the output subcircuit is electrically connected to the second power signal line and the third power signal line.

10. The shift register according to claim 9, characterized in that: The potential of the first power signal transmitted by the first power signal line is lower than the potential of the second power signal transmitted by the second power signal line; the potential of the third power signal transmitted by the third power signal line is lower than the potential of the fourth power signal transmitted by the fourth power signal line; The potential of the second power signal is lower than the potential of the third power signal.

11. The shift register according to claim 10, characterized in that: The potential of the first level of the first clock signal is equal to the potential of the first power signal, and the potential of the second level of the first clock signal is equal to the potential of the fourth power signal; The potential of the first level of the second clock signal is equal to the potential of the second power signal, and the potential of the second level of the second clock signal is equal to the potential of the third power signal; The potential of the third level of the third clock signal is equal to the potential of the first power signal, and the potential of the fourth level of the third clock signal is equal to the potential of the fourth power signal; The potential of the third level of the fourth clock signal is equal to the potential of the second power signal, and the potential of the third level of the fourth clock signal is equal to the potential of the third power signal.

12. The shift register according to any one of claims 4 to 8, characterized in that: The pulse width of the first level of the first clock signal is smaller than the pulse width of the second level; and / or the pulse width of the third level of the third clock signal is smaller than the pulse width of the fourth level.

13. The shift register according to any one of claims 1 to 3, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

14. The shift register according to any one of claims 1 to 8, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line.

15. The shift register according to any one of claims 1 to 8, characterized in that: The input subcircuit includes a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the first clock signal line.

16. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes an isolation subcircuit; The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolating the first node and the output subcircuit electrically connected to the first node; and, isolating the second node from the second control subcircuit electrically connected to the second node; The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; The second control subcircuit is electrically connected to a fourth node.

17. The shift register according to claim 16, characterized in that: The isolation subcircuit includes an eleventh transistor and a twelfth transistor; The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line; The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second power signal line.

18. The shift register according to claim 16, characterized in that: The isolation subcircuit includes an eleventh transistor and a twelfth transistor; The eleventh transistor has a first electrode electrically connected to the second node, a second electrode electrically connected to the fourth node, and a control electrode electrically connected to the first power signal line; The first electrode of the twelfth transistor is electrically connected to the first node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the first power signal line.

19. The shift register according to claim 16, characterized in that: The first control subcircuit includes a fourth transistor, a fifth transistor and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the fifth node; The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node; The second plate of the third capacitor is electrically connected to the fifth node.

20. The shift register according to claim 16, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

21. The shift register according to claim 16, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node; The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a preset control terminal.

22. The shift register according to claim 16, characterized in that: The input subcircuit includes a first transistor, a second transistor, a third transistor and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the second clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line; The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the first clock signal line.

23. The shift register according to any one of claims 1 to 8, characterized in that: The shift register further includes an isolation subcircuit; The isolation subcircuit is configured to isolate the first node from the first control subcircuit electrically connected to the first node; isolating the first node and the output subcircuit electrically connected to the first node; isolating the first node from the second control subcircuit electrically connected to the first node; and isolating the second node from the second control subcircuit electrically connected to the second node; The first control subcircuit is electrically connected to the fifth node; the output subcircuit is electrically connected to the fifth node; The second control subcircuit is electrically connected to the fourth node and the fifth node.

24. The shift register according to claim 23, characterized in that: The input subcircuit includes a first transistor, a second transistor, a third transistor and a fourteenth transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal line; A first electrode of the second transistor is electrically connected to the first clock signal line, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first node; The first electrode of the third transistor is electrically connected to the first power signal line, the second electrode is electrically connected to the second node, and the control electrode is electrically connected to the second clock signal line; The first electrode of the fourteenth transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the eighth node, and the control electrode is electrically connected to the second clock signal line.

25. The shift register according to claim 24, characterized in that: The first control subcircuit includes a fourth transistor, a fifth transistor, a fifteenth transistor, a sixteenth transistor and a third capacitor; The first electrode of the fourth transistor is electrically connected to the third clock signal line, the second electrode is electrically connected to the second electrode of the fifth transistor, and the control electrode is electrically connected to the second electrode plate of the third capacitor; The first electrode of the fifth transistor is electrically connected to the third power signal line, the second electrode is electrically connected to the first electrode plate of the third capacitor, and the control electrode is electrically connected to the second node; The first electrode of the fifteenth transistor is electrically connected to the eighth node, the second electrode is electrically connected to the first electrode of the sixteenth transistor and the control electrode of the sixteenth transistor, and the control electrode is electrically connected to the first power signal line; The second electrode of the sixteenth transistor is electrically connected to the fifth node, and the control electrode is electrically connected to the control electrode of the fourth transistor.

26. The shift register according to claim 25, characterized in that: The second control subcircuit includes a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a first capacitor; The first electrode of the sixth transistor is electrically connected to the fourth clock signal line, the second electrode is electrically connected to the first electrode of the seventh transistor, and the control electrode is electrically connected to the fourth node and the first electrode plate of the first capacitor; The first electrode of the seventh transistor is electrically connected to the second electrode plate of the first capacitor, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fourth clock signal line; The first electrode of the eighth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the fifth node; The first electrode of the thirteenth transistor is electrically connected to the fourth power signal line, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to a preset control terminal.

27. The shift register according to claim 23, characterized in that: The output subcircuit includes a ninth transistor, a tenth transistor and a second capacitor; The first electrode of the ninth transistor is electrically connected to the third power signal line and the first electrode plate of the second capacitor, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node; The first electrode of the tenth transistor is electrically connected to the second power signal line, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the fifth node; The second plate of the second capacitor is electrically connected to the third node.

28. A gate drive circuit, characterized in that: It comprises N cascaded shift registers; except for the first stage shift register, the signal input end of the i+1th stage shift register is electrically connected to the signal output end of the ith stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

29. The gate driving circuit according to claim 28, characterized in that: The first clock signal line in the shift register of the i-th level is multiplexed as the fourth clock signal line in the shift register of the i+1-th level, the second clock signal line in the shift register of the i-th level is multiplexed as the first clock signal line in the shift register of the i+1-th level, the third clock signal line in the shift register of the i-th level is multiplexed as the second clock signal line in the shift register of the i+1-th level, and the fourth clock signal line in the shift register of the i-th level is multiplexed as the third clock signal line in the shift register of the i+1-th level.

30. The gate driving circuit according to claim 28, characterized in that: The first clock signal line in the shift register at the i-th level is multiplexed as the third clock signal line in the shift register at the i+1-th level, the second clock signal line in the shift register at the i-th level is multiplexed as the fourth clock signal line in the shift register at the i+1-th level, the third clock signal line in the shift register at the i-th level is multiplexed as the first clock signal line in the shift register at the i+1-th level, and the fourth clock signal line in the shift register at the i-th level is multiplexed as the second clock signal line in the shift register at the i+1-th level.

31. A display device, characterized in that: It comprises a pixel driving circuit and a gate driving circuit as claimed in any one of claims 28 to 30, wherein the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate control signal to the pixel driving circuit.

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