Semiconductor Processing Quality Automated Online Inspection System and Method

Abstract

This invention discloses a visual automatic online inspection system and method for semiconductor processing quality, relating to the field of semiconductor processing technology. The invention includes: for a series of feature point combinations with different quantities, using the local image of each feature point within the combination as the input layer and the corresponding electrical detection result as the output layer, training the detection model until convergence to obtain the detection model; selecting feature point combinations for different quantities based on the probability distribution of the input local images of each feature point within the series of feature point combinations with different quantities into the output layer of the corresponding detection model; and extracting the local images of specific feature point combinations for each chip etched area within the wafer to be inspected according to the feature point combinations with different quantities, inputting them into the corresponding detection model to obtain the electrical prediction result for each chip etched area within the wafer to be inspected. This invention improves the speed of semiconductor visual inspection.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor processing technology, and in particular relates to a visual automatic online inspection system and method for semiconductor processing quality. Background Technology

[0002] With the rapid development of semiconductor technology, the requirements for the processing quality of semiconductor products are also increasing. Traditional semiconductor processing quality inspection relies heavily on manual visual inspection and simple mechanical inspection equipment, which is not only inefficient but also has limited inspection accuracy, making it difficult to meet the high standards required by the modern semiconductor industry. Summary of the Invention

[0003] The purpose of this invention is to provide a visual automatic online inspection system and method for semiconductor processing quality, which improves the speed of semiconductor visual inspection by selectively selecting feature points.

[0004] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution:

[0005] This invention provides a method for automatic online visual inspection of semiconductor processing quality, comprising:

[0006] Obtain the chip etching area within the wafer;

[0007] Acquire sample images and electrical test results of the chip etched area within the sample wafer;

[0008] For each chip etched area

[0009] Multiple feature points are obtained by analyzing the image features of each sample image.

[0010] By combining feature points of different quantities, a series of feature point combinations under different quantities are obtained.

[0011] For a series of feature point combinations with different quantities, the local image of each feature point within the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model.

[0012] Based on the probability distribution of the output layer of the detection model corresponding to the local image input of each feature point in a series of feature point combinations under different quantity states, feature point combinations under different quantity states are selected.

[0013] Acquire wafer images of the chip etching area within the wafer to be inspected;

[0014] The local image of the specific feature point combination of each chip etched region in the wafer to be tested is extracted according to the feature point combination under different quantity states. The local image is then input into the corresponding detection model to obtain the electrical prediction result of each chip etched region in the wafer to be tested.

[0015] This invention also discloses a method for automatic online visual inspection of semiconductor processing quality, comprising,

[0016] Obtain the electrical prediction results of each chip etched area within the wafer to be inspected;

[0017] Mark the etched areas of the chip where the electrical prediction results are poor.

[0018] This invention also discloses a method for automatic online visual inspection of semiconductor processing quality, comprising,

[0019] Obtain the electrical prediction results of each chip etched area within the wafer to be inspected;

[0020] Chip etching areas with poor electrical performance prediction results are discarded.

[0021] This invention also discloses a visual automatic online inspection system for semiconductor processing quality.

[0022] An online inspection unit is used to acquire the chip etching area within the wafer;

[0023] Acquire sample images and electrical test results of the chip etched area within the sample wafer;

[0024] For each chip etched area

[0025] Multiple feature points are obtained by analyzing the image features of each sample image.

[0026] By combining feature points of different quantities, a series of feature point combinations under different quantities are obtained.

[0027] For a series of feature point combinations with different quantities, the local image of each feature point within the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model.

[0028] Based on the probability distribution of the output layer of the detection model corresponding to the local image input of each feature point in a series of feature point combinations under different quantity states, feature point combinations under different quantity states are selected.

[0029] Acquire wafer images of the chip etching area within the wafer to be inspected;

[0030] The local image of the specific feature point combination of each chip etched region in the wafer to be tested is extracted according to the feature point combination under different quantity states and input into the corresponding detection model to obtain the electrical prediction result of each chip etched region in the wafer to be tested.

[0031] The defect marking unit is used to obtain the electrical prediction results of each chip etched area in the wafer to be inspected;

[0032] Mark the etched areas of the chip with poor electrical performance prediction results;

[0033] The defective product rejection unit is used to obtain the electrical prediction results of each chip etched area in the wafer to be inspected;

[0034] Chip etching areas with poor electrical performance prediction results are discarded.

[0035] This invention analyzes and filters feature point combinations of different quantities for each chip etching region using an online detection unit to examine sample images and electrical test results of the chip etching region within a sample wafer. During the identification of the wafer image of the chip etching region within the wafer to be detected, local images of specific feature point combinations for each chip etching region within the wafer to be detected are extracted according to different quantities of feature point combinations and input into the corresponding detection model. In this process, because fewer feature point combinations are prioritized for detection and identification, the online identification speed is improved while maintaining accuracy.

[0036] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the functional units and information flow of an embodiment of the semiconductor processing quality visual automatic online inspection system described in this invention;

[0039] Figure 2 This is a schematic diagram of the steps of an embodiment of the online detection unit described in this invention;

[0040] Figure 3 This is a schematic diagram of the steps of a defective product marking unit according to an embodiment of the present invention;

[0041] Figure 4This is a schematic flowchart of the defective product rejection unit according to an embodiment of the present invention;

[0042] Figure 5 This is a flowchart illustrating step S6 of the present invention in one embodiment;

[0043] Figure 6 This is a flowchart illustrating step S65 of the present invention in one embodiment.

[0044] Figure 7 This is a flowchart illustrating step S652 of the present invention in one embodiment;

[0045] Figure 8 This is a flowchart illustrating step S8 of the present invention in one embodiment;

[0046] Figure 9 This is a flowchart illustrating step S83 of the present invention in one embodiment.

[0047] The attached diagram lists the components represented by each number as follows:

[0048] 1-Online detection unit, 2-Defective product marking unit, 3-Defective product rejection unit. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0051] Please see Figures 1 to 4As shown, this invention provides a semiconductor processing quality visual automatic online inspection system, functionally divided into an online inspection unit 1, a defective product marking unit 2, and a defective product rejection unit 3. Since wafer fabs use an assembly line method for wafer etching, the inspection process needs to maintain both speed and accuracy. In this solution, the online inspection unit 1 is responsible for quickly and accurately detecting the chip etching areas within the wafer, specifically the electrical prediction results of each chip etching area within the wafer to be inspected. Then, the defective product marking unit 2 marks the defective chip etching areas within the wafer, and the defective product rejection unit 3 can reject the defective chip etching areas within the wafer, specifically by scrapping the positive wafer or by shielding it.

[0052] During operation, the system first executes step S1, where the online detection unit 1 acquires the etched chip area within the wafer. This is because multiple chips are typically etched within a single wafer, each corresponding to a specific etched area. Next, step S2 acquires sample images and electrical test results of the etched chip area within the sample wafer. The electrical test results typically include DC testing, AC testing, power consumption testing, parameter testing, functional testing, noise testing, and failure analysis. DC testing includes testing the chip's input / output voltage, current, and leakage current, among other static parameters. AC testing measures the chip's response to high-frequency signals, such as propagation delay, rise time, and fall time, reflecting dynamic performance. Power consumption testing measures the chip's power consumption in different operating modes, including static and dynamic power consumption. Parameter testing includes testing key circuit parameters such as amplifier gain, bias voltage, and input / output impedance. Functional testing verifies the chip's functionality in actual operation, such as verifying the logic function of logic circuits and memory read / write functions. Noise testing measures the chip's noise floor and signal-to-noise ratio to determine its signal integrity. Failure analysis involves in-depth analysis of anomalies discovered during electrical testing to determine the cause of chip failure, such as short circuits or open circuits.

[0053] In subsequent work, the online detection unit 1 first executes step S3 for each chip etched area to obtain multiple feature points based on the image features of each sample image. These feature points, in image processing, are used to describe special, easily identifiable points in an image. They are typically located in prominent, unchanging positions within the image, helping to establish correspondences between different images. Feature point detection and matching are fundamental to many computer vision tasks, such as image stitching, object recognition, and stereo matching. In this scheme, feature points can be corner points, edge feature points, blob features, scale-invariant feature points, region-based feature points, and angle and direction information.

[0054] Next, online detection unit 1 can execute step S4 to combine feature points of different quantities to obtain a series of feature point combinations under different quantities. Then, step S5 can be executed to train the detection model until convergence, using the local image of each feature point in the series of feature point combinations under different quantities as the input layer and the corresponding electrical detection result as the output layer. Next, step S6 can be executed to filter feature point combinations under different quantities based on the probability distribution of the input local image of each feature point in the series of feature point combinations under different quantities to the output layer of the corresponding detection model. Feature point combinations with a larger number of feature points are processed faster, but may have lower detection accuracy. Therefore, this scheme prepares feature point combinations under different quantities of feature points.

[0055] During online inspection of the wafer to be inspected, step S7 is first executed to acquire a wafer image of the chip etching area within the wafer. Then, step S8 is executed to extract local images of specific feature point combinations for each chip etching area within the wafer according to different numbers of feature point combinations. These images are then input into the corresponding detection model to obtain the electrical prediction results for each chip etching area within the wafer. During online inspection, feature point combinations with fewer feature points can be detected first. If the detection accuracy is insufficient, then feature point combinations with more feature points will be detected. This approach balances detection speed and accuracy.

[0056] In this system, the defective marking unit 2 can first execute step S021 to obtain the electrical prediction result of each chip etched area in the wafer to be inspected, and then execute step S022 to mark the chip etched area with poor electrical prediction result, thereby realizing the marking of defective chips.

[0057] In this system, the defective chip rejection unit 3 can first execute step S031 to obtain the electrical prediction results of each chip etched area in the wafer to be inspected, and then execute step S032 to reject the chip etched areas with poor electrical prediction results, thereby achieving the rejection of defective chips.

[0058] Please see Figure 5As shown, each chip etched area of ​​the wafer contains a large number of feature points, but not every feature point is relevant to quality detection, and the correlation varies. Generally, the more feature points there are, the higher the accuracy of wafer quality detection. To filter out valuable feature point combinations of different quantity states, the online detection unit 1 can first execute step S61 to obtain the total number of feature points. Next, it can execute step S62 to perform gradient partitioning from the total number of all feature points in descending order to obtain multiple quantity states. Next, it can execute step S63 to extract feature points of the corresponding quantity state from all feature points under each quantity state constraint and combine them to obtain feature point combinations of different quantity states.

[0059] To verify the detection accuracy of different feature point combinations, step S64 can be performed. For each quantity state, the local image of each feature point within each feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model for each feature point combination in each quantity state. Next, step S65 can be performed. Sample images of the chip etching area within the wafer and the electrical detection results are used as test data to test the detection model and obtain the estimated recognition accuracy of the detection model for each feature point combination in each quantity state. Next, step S66 can be performed to obtain the target recognition accuracy, which can be set by the operator. Finally, step S67 can be performed to remove the feature point combinations corresponding to the detection models in different quantity states whose estimated recognition accuracy is lower than the target recognition accuracy, thus filtering out the feature point combinations in different quantity states. The number of the filtered feature point combinations varies, but all are relevant to wafer quality inspection.

[0060] Please see Figure 6 As shown, since the wafer detection accuracy of detection models with different feature point combinations varies, to quantify this, for each feature point combination under each quantity state, the online detection unit 1 first executes step S651 to input the local images of different sample graphics under the feature point combination into the input layer of the corresponding detection model, and obtains the recognition accuracy of the detection model for different sample graphics based on the probability of each output item in the output layer of the detection model. Next, step S652 can be executed to obtain the estimated recognition accuracy of the detection model corresponding to the feature point combination under that quantity state based on the numerical characteristics of the recognition accuracy of the detection model for different sample graphics. Finally, step S653 can be executed to summarize and obtain the estimated recognition accuracy of the detection model for each feature point combination under each quantity state.

[0061] Please see Figure 7As shown, since each chip etched area corresponds to multiple sample images, the recognition accuracy of the detection model for different sample images varies. Simply taking the average of the recognition results cannot fully represent the recognition accuracy of the detection model. Similarly, simply taking the minimum value is not sufficiently representative. Therefore, in this solution, step S6521 is executed to arrange the recognition accuracy of the detection model for different sample images in numerical order to obtain a recognition accuracy series. Next, step S6522 is executed to calculate the average difference between each value in the recognition accuracy series and its adjacent values ​​as the filtering step size. Next, step S6523 is executed to select the minimum value in the recognition accuracy series as the estimation reference value. Next, step S6524 is executed, starting from the estimated reference value, calculating the difference with adjacent values ​​sequentially from smallest to largest along the recognition accuracy series. Next, step S6525 is executed to determine whether the difference is less than the filtering step size. If so, step S6526 is executed to change the adjacent values ​​of the estimated reference value to the estimated reference value, and step S6524 is executed to continue calculating the difference. Otherwise, step S6527 can be executed to stop, and the average of all estimated participating values ​​can be used as the estimated recognition accuracy of the detection model corresponding to the feature point combination under this quantity state.

[0062] In short, this approach selects several low-value recognition accuracy rates and uses them to calculate the estimated recognition accuracy of the detection model.

[0063] To supplement the explanation of the implementation process of steps S6521 to S6527 above, source code for some functional modules is provided, with comparative explanations in the comments. To avoid data leakage involving trade secrets, data that does not affect the implementation of the solution has been anonymized, and the same applies below.

[0064] #include <iostream>

[0065] #include <vector>

[0066] #include <algorithm>

[0067] #include <numeric>

[0068] / / Example of the following namespaces

[0069] using namespace std;

[0070] / / Calculate the average of the differences between each value in the recognition accuracy series and its adjacent values ​​as the filtering step size.

[0071] double calculateStepSize(const vector <double>& accuracies) {

[0072] vector <double>differences

[0073] for (size_t i = 1; i < accuracies.size(); ++i) {

[0074] differences.push_back(accuracies[i] - accuracies[i - 1]);

[0075] }

[0076] / / Calculate the mean of the differences

[0077] double stepSize = accumulate(differences.begin(), differences.end(), 0.0) / differences.size();

[0078] return stepSize;

[0079] }

[0080] / / Calculate and estimate recognition accuracy

[0081] double estimateAccuracy(const vector <double>& accuracies) {

[0082] / / Sort the recognition accuracy by numerical value

[0083] vector <double>sortedAccuracies = accuracies;

[0084] sort(sortedAccuracies.begin(), sortedAccuracies.end());

[0085] / / Calculate the filtering step size

[0086] double stepSize = calculateStepSize(sortedAccuracies);

[0087] / / The initial estimated value is the minimum value of the sequence.

[0088] double estimateValue = sortedAccuracies.front();

[0089] / / Calculate the difference along the recognition accuracy sequence starting from the minimum value.

[0090] for (size_t i = 1; i < sortedAccuracies.size(); ++i) {

[0091] double difference = sortedAccuracies[i] - estimateValue;

[0092] if (difference < stepSize) {

[0093] / / If the difference is less than the filtering step size, update the estimated participation value.

[0094] estimateValue = sortedAccuracies[i];

[0095] } else {

[0096] / / Stop calculation if the difference is greater than or equal to the filtering step size.

[0097] break

[0098] }

[0099] }

[0100] / / Return the mean of the estimated participating values ​​as the estimated recognition accuracy.

[0101] double estimatedAccuracy = estimateValue;

[0102] return estimatedAccuracy.

[0103] }

[0104] int main() {

[0105] / / Example of recognition accuracy for different sample images

[0106] vector <double>accuracies = {0.82, 0.85, 0.83, 0.88, 0.87, 0.90};

[0107] / / Calculate the estimated recognition accuracy of the detection model corresponding to the feature point combination under this quantity state.

[0108] double estimatedAccuracy = estimateAccuracy(accuracies);

[0109] / / Output estimated recognition accuracy

[0110] cout << "Estimated recognition accuracy: " << estimatedAccuracy < <endl;

[0111] return 0;

[0112] }

[0113] This code implements an algorithm to calculate the estimated recognition accuracy of a combination of feature points under a specific number of conditions by detecting the recognition accuracy sequence of the detection model. First, the recognition accuracy sequence is arranged in ascending order. Then, the average difference between adjacent values ​​in the sequence is calculated as the filtering step size. Next, starting from the minimum value in the sequence, the difference between adjacent values ​​is calculated step by step, and it is determined whether it is less than the filtering step size. Finally, the average of the values ​​that meet the condition is taken as the estimated recognition accuracy of that feature point combination. This process helps to extract representative accuracies for model evaluation and optimization.

[0114] Please see Figure 8 As shown, during the quality inspection of the wafer to be inspected, the online inspection unit 1 can first execute step S81 to obtain each feature point combination in each quantity state for each chip etching area in the wafer to be inspected.

[0115] For each chip etched area within the wafer to be inspected, step S82 can be executed first, selecting each quantity state sequentially in ascending order of the numerical value of the number of feature points. Next, step S83 can be executed to verify whether the combination of multiple feature points within each quantity state can yield an electrical prediction result that achieves the target recognition accuracy. If so, step S84 can be executed to obtain the electrical prediction result for that chip etched area within the wafer to be inspected.

[0116] If not, it indicates that the number of selected feature points is insufficient for accurate wafer quality assessment. Therefore, step S85 can be executed to stop the current selection of feature point states, select a larger number of feature point states, and iteratively test the combinations of multiple feature points included. Next, step S82 can be executed to determine if an electrical prediction result that achieves the target recognition accuracy can be obtained, until an electrical prediction result that achieves the target recognition accuracy is obtained, or until all feature point states are exhausted. Finally, step S86 can be executed to summarize the electrical prediction results for each etched area of ​​a chip within the wafer to be inspected.

[0117] Please see Figure 9 As shown, during the verification of multiple feature point combinations within each quantity state, it is necessary to continuously determine whether an electrical prediction result that achieves the target recognition accuracy can be obtained. However, if all feature point combinations in the low quantity state are tested first, and then all feature point combinations in the high quantity state are tested, it will also affect the speed of wafer online quality inspection. Therefore, step S831 can be executed first, selecting feature point combinations as specific feature point combinations in descending order of the estimated recognition accuracy value corresponding to each feature point combination. Next, step S832 can be executed, inputting the local image of the specific feature points into the corresponding detection model to obtain the probability of each output item in the output layer, and calculating the recognition accuracy. Next, step S833 can be executed to determine whether the target recognition accuracy has been achieved. If so, step S834 can be executed, inputting the local image of the specific feature points into the corresponding detection model to obtain the output result as the electrical prediction result.

[0118] As mentioned above, it's not feasible to test all feature point combinations under low-quantity conditions before testing all feature point combinations under high-quantity conditions. Therefore, step S835 can be executed first to select the feature point combination with the smaller estimated recognition accuracy as the updated specific feature point combination. Next, step S836 can be executed to input the local image of the updated specific feature points into the corresponding detection model to obtain the probability of each output item in the output layer, and calculate the updated recognition accuracy. Next, step S837 can be executed to continuously obtain the updated recognition accuracy and determine if the value continues to decrease. If not, it indicates that there is still a need to continue testing the detection model under this quantity condition, so step S833 can be executed to continuously obtain the updated recognition accuracy. If yes, it indicates that there is no need to continue testing the detection model under this quantity condition, so step S838 can be executed to stop the current selection of feature point quantity conditions.

[0119] To provide supplementary explanation of the implementation process of steps S831 to S838 above, source code of some functional modules is provided, with comparative explanations in the comments.

[0120] #include <iostream>

[0121] #include <vector>

[0122] #include <algorithm>

[0123] #include<opencv2 / opencv.hpp>

[0124] / / Example of the following namespaces

[0125] using namespace std;

[0126] using namespace cv;

[0127] / / Define the data structure for the electrical prediction results

[0128] struct ElectricalEstimationResult {

[0129] double estimated resistance;

[0130] double estimated capacity;

[0131] / / Other electrical parameters

[0132] };

[0133] / / Define the data structure for feature points

[0134] struct FeaturePoint {

[0135] Point2f location;

[0136] Mat localImage;

[0137] };

[0138] / / Define the data structure for feature point combinations

[0139] struct FeaturePointCombination {

[0140] vector <featurepoint>points;

[0141] double estimatedAccuracy; / / Estimated recognition accuracy of the detection model

[0142] };

[0143] / / Example detection model function, returning the probability of each output item.

[0144] double applyModelForProbability(const vector <featurepoint>&featurePoints) {

[0145] / / Example model application

[0146] return 0.7 + (rand() % 30) / 100.0; / / Returns the recognition accuracy of the example, a random value between 0.7 and 1.0.

[0147] }

[0148] / / Verify and return the electrical prediction results

[0149] ElectricalEstimationResult validateAndEstimate(const vector <featurepoint>& featurePoints, double targetAccuracy) {

[0150] double recognitionAccuracy = applyModelForProbability(featurePoints);

[0151] ElectricalEstimationResult result = {0.0, 0.0};

[0152] if (recognitionAccuracy >= targetAccuracy) {

[0153] / / Example electrical prediction results

[0154] result.estimatedResistance = 1.0 + rand() % 10 / 10.0;

[0155] result.estimatedCapacitance = 0.5 + rand() % 5 / 10.0;

[0156] }

[0157] return result;

[0158] }

[0159] / / Validate multiple feature point combinations within each quantity state and update the specific feature point combinations.

[0160] ElectricalEstimationResult evaluateAndUpdateCombinations(vector <featurepointcombination>& combinations, double targetAccuracy) {

[0161] / / Sort by estimated recognition accuracy from highest to lowest

[0162] sort(combinations.begin(), combinations.end(), [](constFeaturePointCombination& a, const FeaturePointCombination& b) {

[0163] return a.estimatedAccuracy > b.estimatedAccuracy;

[0164] });

[0165] double previousAccuracy = -1.0; / / Used to record the accuracy of the previous recognition.

[0166] ElectricalEstimationResult finalResult = {0.0, 0.0};

[0167] for (size_t i = 0; i < combinations.size(); ++i) {

[0168] auto& combination = combinations[i];

[0169] / / Use the current combination of feature points to perform electrical prediction

[0170] ElectricalEstimationResult result = validateAndEstimate(combination.points, targetAccuracy);

[0171] double currentAccuracy = applyModelForProbability(combination.points);

[0172] / / Determine if the target recognition accuracy has been achieved

[0173] if (result.estimatedResistance != 0.0 ||result.estimatedCapacitance != 0.0) {

[0174] return result; / / If the target recognition accuracy is achieved, return the electrical prediction result.

[0175] } else {

[0176] / / If the target recognition accuracy is not achieved, update to the next feature point combination.

[0177] if (previousAccuracy != -1.0 && currentAccuracy <previousAccuracy) {

[0178] / / If the recognition accuracy starts to decrease, stop selecting the current quantity state.

[0179] break

[0180] }

[0181] }

[0182] / / Record the current recognition accuracy

[0183] previousAccuracy = currentAccuracy;

[0184] }

[0185] / / If the goal is not achieved, return the default result.

[0186] return finalResult;

[0187] }

[0188] int main() {

[0189] / / Example feature points and estimated recognition accuracy

[0190] vector <featurepoint>featurePoints;

[0191] for (int i = 0; i < 10; ++i) {

[0192] FeaturePoint point;

[0193] point.location = Point2f(i * 10, i * 10);

[0194] point.localImage = Mat::zeros(10, 10, CV_8UC1);

[0195] featurePoints.push_back(point);

[0196] }

[0197] / / Example feature point combinations and their estimated recognition accuracy

[0198] vector <featurepointcombination>combinations = {

[0199] {featurePoints, 0.9},

[0200] {featurePoints, 0.85},

[0201] {featurePoints, 0.8}

[0202] };

[0203] / / Set target recognition accuracy

[0204] double targetAccuracy = 0.87;

[0205] / / Evaluate the combination and obtain electrical prediction results

[0206] ElectricalEstimationResult finalEstimation =evaluateAndUpdateCombinations(combinations, targetAccuracy);

[0207] / / Output results

[0208] cout << "Electrical prediction result - Resistance: " << finalEstimation.estimatedResistance

[0209] << ", Capacitance: " << finalEstimation.estimatedCapacitance << endl;

[0210] return 0;

[0211] }

[0212] This code implements a process of detailed verification and iterative updates for multiple feature point combinations within each quantity state. First, the code sorts the feature point combinations according to their estimated recognition accuracy. Then, it inputs these combinations one by one into the detection model for recognition. If the current combination cannot achieve the target recognition accuracy, the code selects the next combination with a lower accuracy and continues iterative updates until the recognition accuracy no longer decreases or reaches the target accuracy. Finally, the code returns the corresponding electrical property prediction result or a default result. This process ensures that the optimal combination is selected among the feature point combinations, thus providing accurate electrical property predictions.

[0213] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved.

[0214] It should also be noted that each block in the block diagram and / or flowchart, as well as combinations of blocks in the block diagram and / or flowchart, can be implemented using hardware that performs the corresponding function or action, such as circuits or ASICs (Application Specific Integrated Circuits), or using a combination of hardware and software, such as firmware.

[0215] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0216] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.< / featurepointcombination> < / featurepoint> < / featurepointcombination> < / featurepoint> < / featurepoint> < / featurepoint> < / algorithm> < / vector> < / iostream> < / double> < / double> < / double> < / double> < / double> < / numeric> < / algorithm> < / vector> < / iostream>

Claims

1. A method for automatic online visual inspection of semiconductor processing quality, characterized in that, include, Obtain the chip etching area within the wafer; Acquire sample images and electrical test results of the chip etched area within the sample wafer; For each chip etched area Multiple feature points are obtained by analyzing the image features of each sample image. By combining feature points of different quantities, a series of feature point combinations under different quantities are obtained. For a series of feature point combinations with different quantities, the local image of each feature point within the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model. Based on the probability distribution of the output layer of the detection model corresponding to the local image input of each feature point in a series of feature point combinations under different quantity states, feature point combinations under different quantity states are selected. Acquire wafer images of the chip etching area within the wafer to be inspected; The local image of the specific feature point combination of each chip etched region in the wafer to be tested is extracted according to the feature point combination under different quantity states. The local image is then input into the corresponding detection model to obtain the electrical prediction result of each chip etched region in the wafer to be tested.

2. The method according to claim 1, characterized in that, The step of filtering feature point combinations under different quantity states based on the probability distribution of the output layer of the detection model corresponding to the local image input of each feature point in a series of feature point combinations under different quantity states. include, Obtain the total number of feature points; Starting from the total number of all feature points, a gradient partitioning is performed from largest to smallest to obtain multiple quantity states; Under each quantity state constraint, feature points corresponding to the quantity state are extracted from all feature points and combined to obtain feature point combinations under different quantity states. For each quantity state, the local image of each feature point in each feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model for each feature point combination in each quantity state. The detection model was tested using sample images of the chip etched area within the wafer and electrical test results as test data to obtain the estimated recognition accuracy of the detection model for each feature point combination under each quantity state. Obtain the target recognition accuracy; Feature point combinations under different number of states are filtered out by eliminating the detection model whose estimated recognition accuracy is less than the target recognition accuracy.

3. The method according to claim 2, characterized in that, The step of using sample images of the etched areas within the wafer and electrical test results as test data to test the detection model and obtain the estimated recognition accuracy of the detection model for each feature point combination under each quantity state includes: For each combination of feature points in each quantity state, perform the following steps respectively. The local images of different sample images under the feature point combination are input into the input layer of the corresponding detection model. The recognition accuracy of the detection model for different sample images is obtained based on the probability of each output item in the output layer of the detection model. Based on the numerical characteristics of the recognition accuracy of the detection model for different sample images, the estimated recognition accuracy of the detection model corresponding to the combination of feature points under this quantity state is obtained; The estimated recognition accuracy of the detection model for each feature point combination under each quantity state is obtained by summarizing.

4. The method according to claim 3, characterized in that, The step of obtaining the estimated recognition accuracy of the detection model corresponding to the combination of feature points under the given quantity state based on the numerical characteristics of the recognition accuracy of the detection model for different sample images. include, The recognition accuracy of the detection model for different sample images is arranged in numerical order to obtain a recognition accuracy series; The mean of the differences between each value and its adjacent values ​​in the recognition accuracy sequence is calculated and used as the filtering step size; The minimum value within the recognition accuracy series is selected as the estimated reference value; Starting from the estimated participation value, calculate the difference with the adjacent values ​​sequentially from smallest to largest along the recognition accuracy sequence; Determine whether the difference is less than the filtering step size; If so, then change the adjacent values ​​of the estimated participation value to the estimated participation value, and continue to calculate the difference; If not, then stop, and take the mean of all the estimated participating values ​​as the estimated recognition accuracy of the detection model corresponding to the feature point combination in that quantity state.

5. The method according to claim 1, characterized in that, The step of extracting specific feature point combinations for each chip etched region within the wafer to be inspected according to feature point combinations under different quantity states, inputting the local image of these combinations into the corresponding detection model, and obtaining the electrical prediction result for each chip etched region within the wafer to be inspected. include, For each chip etched area within the wafer to be inspected, obtain each combination of feature points for each quantity state; For each etched area of ​​a chip within the wafer to be inspected, perform the following steps separately. Each quantity state is selected sequentially in ascending order of its numerical value. Within each quantity state, the combination of multiple feature points is examined to determine whether an electrical prediction result that achieves the target recognition accuracy can be obtained. If so, the electrical properties of the etched area of ​​the chip within the wafer to be tested are estimated. If not, stop selecting the quantity state this time, select the quantity state with a larger value and iteratively check and judge the combination of multiple feature points contained therein to obtain the electrical prediction result that achieves the target recognition accuracy, until the electrical prediction result that achieves the target recognition accuracy is obtained, or exhaust all the quantity states of feature points. The electrical prediction results for each etched area of ​​the chip within the wafer to be tested are summarized.

6. The method according to claim 5, characterized in that, The step of verifying and judging whether the combination of multiple feature points in each quantity state can yield an electrical prediction result that achieves the target recognition accuracy includes: Feature point combinations are selected as specific feature point combinations in descending order of their estimated recognition accuracy. The probability of each output item in the output layer is obtained by inputting a local image of the specific feature points into the corresponding detection model, and the recognition accuracy is calculated. Determine whether the target recognition accuracy has been achieved. If so, the output of the corresponding detection model obtained by inputting the local image of the specific feature point is used as the electrical prediction result.

7. The method according to claim 6, characterized in that, The step of verifying and judging whether the combination of multiple feature points in each quantity state can yield an electrical prediction result that achieves the target recognition accuracy also includes, If not, the feature point combination with the smaller estimated recognition accuracy is selected as the updated specific feature point combination. The updated local image of the specific feature points is input into the corresponding detection model to obtain the probability of each output item of the output layer, and the updated recognition accuracy is calculated. The system continuously obtains updated recognition accuracy and determines whether the value continues to decrease. If not, the updated recognition accuracy will continue to be obtained; If so, then stop the current selection of feature points.

8. A method for automatic online visual inspection of semiconductor processing quality, characterized in that, include, Obtain the electrical prediction results of each chip etched area in the wafer to be inspected in the semiconductor processing quality automatic online visual inspection method according to any one of claims 1 to 7; Mark the etched areas of the chip where the electrical prediction results are poor.

9. A method for automatic online visual inspection of semiconductor processing quality, characterized in that, include, Obtain the electrical prediction results of each chip etched area in the wafer to be inspected in the semiconductor processing quality automatic online visual inspection method according to any one of claims 1 to 7; Chip etching areas with poor electrical performance prediction results are discarded.

10. A visual automatic online inspection system for semiconductor processing quality, characterized in that, An online inspection unit is used to acquire the chip etching area within the wafer; Acquire sample images and electrical test results of the chip etched area within the sample wafer; For each chip etched area Multiple feature points are obtained by analyzing the image features of each sample image. By combining feature points of different quantities, a series of feature point combinations under different quantities are obtained. For a series of feature point combinations with different quantities, the local image of each feature point within the feature point combination is used as the input layer, and the corresponding electrical detection result is used as the output layer. The detection model is trained until convergence to obtain the detection model. Based on the probability distribution of the output layer of the detection model corresponding to the local image input of each feature point in a series of feature point combinations under different quantity states, feature point combinations under different quantity states are selected. Acquire wafer images of the chip etching area within the wafer to be inspected; The local image of the specific feature point combination of each chip etched region in the wafer to be tested is extracted according to the feature point combination under different quantity states and input into the corresponding detection model to obtain the electrical prediction result of each chip etched region in the wafer to be tested. The defect marking unit is used to obtain the electrical prediction results of each chip etched area in the wafer to be inspected; Mark the etched areas of the chip with poor electrical performance prediction results; The defective product rejection unit is used to obtain the electrical prediction results of each chip etched area in the wafer to be inspected; Chip etching areas with poor electrical performance prediction results are discarded.

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