Protection circuit capable of reducing chip area

Abstract

The invention relates to the technical field of circuit protection, in particular to a protection circuit capable of reducing the area of a chip. The protection circuit comprises a soft start circuit, a cycle time generation circuit, a timing circuit and a protection signal generation circuit, the timing circuit comprises a plurality of D triggers connected in series, and a first end of the cycle time generation circuit is connected with a first end of the protection signal generation circuit and receives an external circuit abnormal signal. According to the protection circuit, the cycle time signal is generated by using the soft start circuit and the cycle time generation circuit, and the cycle time of the cycle time signal is far greater than the cycle time generated by an oscillator in the power supply chip, so that the number of D triggers is greatly reduced on the basis of additionally adding a small number of devices by the protection circuit; the chip area is reduced; meanwhile, the protection circuit in the invention realizes the function of soft start when the circuit works normally, and realizes the function of the protection circuit when the circuit is in an abnormal condition, so that the circuit realizes function multiplexing.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit protection, and in particular to a protection circuit capable of reducing chip area. Background Art

[0002] The protection circuit is an indispensable component of the internal circuit of the power chip. When receiving an abnormal signal from the external circuit of the power chip, the protection circuit usually outputs a high-level signal (the protection circuit outputs a low-level signal when the circuit is working normally) for a period of time T0, and then switches to output a low-level signal, so that the external circuit of the power chip is shut down for a period of time T0 and then starts working again. If the external circuit of the power chip still has an abnormal condition, the protection circuit continues to shut down the external circuit of the power chip for a period of time T0 and then starts working again until the external circuit of the power chip returns to normal.

[0003] The protection circuit in the prior art usually uses the oscillator and D flip-flop inside the power chip in combination to achieve the function of outputting a high-level signal for a period of time T0 and then switching to output a low-level signal. However, since the output of the oscillator inside the power chip is a high-frequency signal, many D flip-flops are required to obtain the time T0, thereby increasing the chip area. Summary of the invention

[0004] In view of this, the present invention provides a protection circuit with reduced chip area to solve the technical problem that more D flip-flops are required to be provided in the protection circuit of the prior art, thereby increasing the chip area.

[0005] The technical solution provided by the present invention is as follows: In a first aspect, the present invention provides a protection circuit for reducing chip area, comprising: a soft start circuit, a cycle time generation circuit, a timing circuit, and a protection signal generation circuit, wherein a first end of the cycle time generation circuit is connected to a first end of the protection signal generation circuit and receives an external circuit abnormality signal; When the external circuit abnormality signal is a low-level signal, the cycle time generating circuit generates a low-level signal and makes the soft start circuit in a working state, the timing circuit is in a non-working state according to the low-level signal, and the protection signal generating circuit outputs a low-level protection signal according to the low-level signal and the timing circuit; When the external circuit abnormal signal is a high-level signal, the working states of the cycle time generating circuit and the soft start circuit influence each other so that the cycle time generating circuit outputs a cycle time signal, the timing circuit outputs a periodic signal according to the cycle time signal and the reset signal, the protection signal generating circuit outputs a reset signal according to the periodic signal, and the protection signal generating circuit also outputs a protection signal according to the external circuit abnormal signal and the reset signal.

[0006] In an optional embodiment, the soft start circuit, whose first end, second end and third end are respectively connected to the second end, third end and fourth end of the cycle time generating circuit, whose first end is also connected to the external power supply, and whose second end is grounded; the cycle time generating circuit, whose fifth end is connected to the first end of the timing circuit; the timing circuit, whose second end, third end and fourth end are respectively connected to the second end, third end and fourth end of the protection signal generating circuit; the protection signal generating circuit, whose fifth end outputs the protection signal.

[0007] In an optional embodiment, the soft start circuit includes a first current source and a first capacitor, one end of the first current source is connected to an external power supply and a second end of a cycle time generating circuit, the other end of the first current source is connected to one end of the first capacitor and a fourth end of the cycle time generating circuit, and the other end of the first capacitor is connected to a third end of the cycle time generating circuit and is grounded.

[0008] In an optional embodiment, the cycle time generating circuit includes a first switch tube, a second switch tube, a comparator, a first inverter, a first AND gate, a second current source and a second capacitor; the first input end of the first AND gate receives an external circuit abnormality signal, the second input end of the first AND gate is connected to the output end of the comparator, the output end of the first AND gate is connected to the first end of the second switch tube, the second end of the second switch tube is connected to one end of the second capacitor, the first end of the first switch tube and grounded, the third end of the second switch tube is connected to the other end of the second capacitor, the input end of the first inverter and one end of the second current source, the other end of the second current source is connected to an external power supply, the output end of the first inverter is connected to the second end of the first switch tube and the first end of the timing circuit, the third end of the first switch tube is connected to the third end of the soft start circuit and the positive input end of the comparator, and the negative input end of the comparator receives a first voltage.

[0009] In an optional implementation, the output terminal of the first inverter outputs a periodic time signal.

[0010] In an optional embodiment, the timing circuit includes a plurality of D flip-flops connected in series, among which the clock input terminal of the first D flip-flop is connected to the fifth terminal of the cycle time generating circuit, and the reset terminal of the first D flip-flop is grounded, and starting from the second D flip-flop, the clock input terminal of each D flip-flop is connected to the inverting output terminal and the signal input terminal of the previous D flip-flop, and the reset terminal of each D flip-flop is connected to the second terminal of the protection signal generating circuit.

[0011] In an optional embodiment, the protection signal generating circuit includes a second AND gate, an RS trigger and a second inverter, the first input end of the second AND gate is connected to the cycle time generating circuit and receives an external circuit abnormality signal, the second input end of the second AND gate receives a reset signal output by the RS trigger, the second AND gate outputs a protection signal, the reset end of the RS trigger is connected to the inverting output end of the last D trigger among multiple D triggers, the set end of the RS trigger is connected to the inverting output end of the first D trigger among multiple D triggers, the output end of the RS trigger is connected to the input end of the second inverter, and the output end of the second inverter serves as the second end of the protection signal generating circuit.

[0012] In an optional embodiment, the protection signal generating circuit includes a second AND gate, an RS trigger, a second inverter and a third inverter. The first input end of the second AND gate is connected to the cycle time generating circuit and receives an external circuit abnormality signal. The second input end of the second AND gate receives a reset signal output by the RS trigger. The second AND gate outputs a protection signal. The input end of the third inverter is connected to the output end of the last D trigger among multiple D triggers. The output end of the third inverter is connected to the reset end of the RS trigger. The set end of the RS trigger is connected to the inverting output end of the first D trigger among multiple D triggers. The output end of the RS trigger is connected to the input end of the second inverter. The output end of the second inverter serves as the second end of the protection signal generating circuit.

[0013] In an optional implementation, the number of D flip-flops is determined according to the period of the periodic time signal and a preset off time when an external circuit is abnormal.

[0014] In an optional implementation, the timing circuit includes at least two D flip-flops.

[0015] In a second aspect, the present invention provides an analog integrated circuit control chip, comprising the first aspect of the present invention and the protection circuit for reducing chip area of ​​any one of the first aspects.

[0016] In a third aspect, the present invention provides a power supply circuit, comprising the analog integrated circuit control chip of the second aspect of the present invention.

[0017] The technical solution of the present invention has the following advantages: The protection circuit for reducing chip area provided by the present invention utilizes a soft start circuit and a cycle time generation circuit to generate a cycle time signal. Since the cycle time of the cycle time signal is much greater than the cycle time generated by an oscillator inside a power chip, the protection circuit greatly reduces the number of D flip-flops on the basis of adding a small number of additional devices, thereby reducing the chip area. At the same time, the protection circuit in the present invention realizes the function of soft start when the circuit works normally, and realizes the function of the protection circuit when an abnormal condition occurs in the circuit, so that the circuit realizes functional multiplexing.

[0018] The analog integrated circuit control chip provided by the present invention has the protection circuit for reducing the chip area, thereby reducing the volume of the analog integrated circuit control chip.

[0019] The power supply circuit provided by the present invention further reduces the volume of the power supply circuit when an analog integrated circuit control chip is arranged in the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A structural block diagram of a protection circuit for reducing chip area in an embodiment of the present invention; Figure 2 It is a schematic diagram of the structure of a protection circuit for reducing chip area in an embodiment of the present invention; Figure 3 is a waveform diagram of each signal in the protection circuit when the external circuit is in normal operation in an embodiment of the present invention; Figure 4 A first waveform diagram of each signal in the protection circuit when the external circuit is in abnormal operation in an embodiment of the present invention; Figure 5 A second waveform diagram of each signal in the protection circuit when the external circuit is in abnormal operation in an embodiment of the present invention; Figure 6 FIG. 4 is a schematic diagram of the structure of another protection circuit for reducing chip area in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] The embodiment of the present invention provides a protection circuit for reducing chip area, such as Figure 1 As shown, the protection circuit includes: a soft start circuit 10, a cycle time generating circuit 20, a timing circuit 30 and a protection signal generating circuit 40, the timing circuit 30 includes a plurality of D flip-flops connected in series, a first end of the cycle time generating circuit 20 is connected to a first end of the protection signal generating circuit 40 and receives an external circuit abnormality signal, i.e., a first signal S1; When the external circuit abnormality signal is a low-level signal, the cycle time generating circuit 20 generates a low-level signal and makes the soft start circuit 10 in a working state, the timing circuit 30 is in a non-working state according to the low-level signal, and the protection signal generating circuit 40 outputs a low-level protection signal according to the low-level signal and the timing circuit 30 in a non-working state; When the external circuit abnormality signal is a high-level signal, the working states of the cycle time generating circuit 20 and the soft start circuit 10 affect each other, causing the working state of the cycle time generating circuit 20 to change periodically. The cycle time generating circuit 20 outputs a cycle time signal, and the timing circuit 30 outputs multiple periodic signals according to the cycle time signal and the reset signal input by the protection signal generating circuit 40. The protection signal generating circuit 40 outputs a protection signal that periodically changes between high and low levels according to the external circuit abnormality signal and the reset signal. The reset signal is generated by the protection signal generating circuit 40 through logical processing based on the multiple periodic signals output by the timing circuit 30.

[0027] The soft start circuit 10, whose first end, second end and third end are respectively connected to the second end, third end and fourth end of the cycle time generating circuit 20, whose first end is also connected to the external power supply, and whose second end is grounded; the cycle time generating circuit 20, whose fifth end is connected to the first end of the timing circuit 30; the timing circuit 30, whose second end, third end and fourth end are respectively connected to the second end, third end and fourth end of the protection signal generating circuit 40; the protection signal generating circuit 40, whose fifth end outputs the protection signal, i.e., the tenth signal S10.

[0028] Specifically, the protection circuit is a protection circuit inside the power chip, and the external circuit abnormal signal can be a signal generated when a fault occurs in the external circuit (such as a short circuit, etc.). When the external circuit works normally, the external circuit abnormal signal is a low-level signal. When an abnormality occurs in the external circuit, the external circuit abnormal signal is a high-level signal.

[0029] Among them, when the external circuit abnormal signal is a low-level signal, the first end of the cycle time generating circuit is at a low level. Based on the low-level signal, the fifth end of the cycle time generating circuit is also at a low level, that is, no high-level signal is input to the timing circuit, and the timing circuit does not work (is in a non-working state), and the first end of the protection signal generating circuit receives the external circuit abnormal signal, and its first end is also at a low level; at the same time, since the timing circuit is in a non-working state, the second end, the third end and the fourth end connected to the protection signal generating circuit and the timing circuit also have no level signal input, therefore, the protection signal generating circuit is also in a non-working state, and the protection signal output from its fifth end is also a low-level signal. In addition, when a low level is input to the first end of the cycle time generating circuit, the soft start circuit will be in a normal working state.

[0030] When the external circuit abnormal signal is a high-level signal, the first end of the cycle time generation circuit is at a high level, and the high-level signal is input into the cycle time generation circuit to change its working state, further changing the working state of the soft start circuit connected thereto, and the change in the working state of the soft start circuit will affect the cycle time generation circuit, causing the working state of the cycle time generation circuit to change again. Therefore, based on the mutual influence of the working states of the cycle time generation circuit and the soft start circuit, the fifth end of the cycle time generation circuit outputs a cycle time signal, which is a signal that periodically changes between high and low levels.

[0031] Based on the periodic time signal, the timing circuit enters the working state. At the same time, based on the connection between the timing circuit and the protection signal generating circuit, the protection signal generating circuit receives the signal output by the timing circuit, performs logic processing, and then inputs it to the reset end of the timing circuit to reset the D flip-flop. As a result, the timing circuit outputs multiple periodically changing signals under the action of the periodic time signal and the reset signal input by the protection signal generating circuit. Based on the structural design of the protection signal generating circuit, the waveforms of the protection signal and the reset signal output by it are the same, and the reset signal is determined according to the multiple periodically changing signals output by the timing circuit. As a result, the protection signal is also a periodically changing signal.

[0032] Among them, the protection signal output by the protection signal generating circuit first outputs a high-level signal and then outputs a low-level signal, that is, the external circuit is first shut down for a period of time (high-level signal duration) and then restarts to work; if the external circuit is still in an abnormal state after re-working, that is, the external circuit abnormal signal is still a high-level signal, the protection circuit continues to output a high-level signal, thus, if the external circuit abnormal signal is always a high-level signal, the protection signal output by the protection circuit is a signal with periodic changes in high and low levels. In addition, the requirements for the shutdown time are different in different application scenarios, and the shutdown time can be changed by changing the number of D flip-flops. At the same time, the operation of the timing circuit is also affected by the periodic time signal. Therefore, the number of D flip-flops is determined according to the period of the periodic time signal and the preset shutdown time when the external circuit is abnormal.

[0033] In the present invention, a soft start circuit and a cycle time generating circuit are used to generate a cycle time signal. Since the cycle time of the cycle time signal is much larger than the cycle time generated by the oscillator inside the power chip, the protection circuit can significantly reduce the number of D flip-flops on the basis of adding a small number of additional devices, thereby reducing the chip area. At the same time, the protection circuit in the present invention realizes the soft start function when the circuit is working normally, and realizes the function of the protection circuit when an abnormal condition occurs in the circuit, so that the circuit can realize functional multiplexing.

[0034] In an optional embodiment, if Figure 2 As shown, the soft start circuit includes a first current source I1 and a first capacitor C1, one end of the first current source I1 is connected to an external power supply and a second end of the cycle time generating circuit, the other end of the first current source I1 is connected to one end of the first capacitor C1 and a fourth end of the cycle time generating circuit, and the other end of the first capacitor C1 is connected to a third end of the cycle time generating circuit and is grounded.

[0035] The cycle time generating circuit includes a first switch tube M1, a second switch tube M2, a comparator A1, a first inverter NOT1, a first AND gate AND1, a second current source I2 and a second capacitor C2; a first input end of the first AND gate AND1 is connected to a first end of the protection signal generating circuit and receives an external circuit abnormality signal, a second input end of the first AND gate AND1 is connected to an output end of the comparator A1, an output end of the first AND gate AND1 is connected to a first end of the second switch tube M2, a second end of the second switch tube M2 is connected to one end of the second capacitor C2 and a first end of the first switch tube M1 and is grounded, a third end of the second switch tube M2 is connected to the other end of the second capacitor C2, an input end of the first inverter NOT1 and one end of the second current source I2, the other end of the second current source I2 is connected to an external power supply, an output end of the first inverter NOT1 is connected to a second end of the first switch tube M1 and a first end of the timing circuit, a third end of the first switch tube M1 is connected to a third end of the soft start circuit and a positive input end of the comparator A1, and a negative input end of the comparator A1 receives a first voltage.

[0036] In a plurality of D flip-flops connected in series, the clock input terminal of the first D flip-flop is connected to the fifth terminal of the cycle time generating circuit, the reset terminal of the first D flip-flop is grounded, and starting from the second D flip-flop, the clock input terminal of each D flip-flop is connected to the inverting output terminal and the signal input terminal of the previous D flip-flop, and the reset terminal of each D flip-flop is connected to the second terminal of the protection signal generating circuit. In addition, the number of D flip-flops in the timing circuit can be at least two. Compared with the protection circuit using an oscillator and a D flip-flop, the number of D flip-flops used is greatly reduced.

[0037] The protection signal generating circuit includes a second AND gate AND2, an RS trigger A2 and a second inverter NOT2. The first input end of the second AND gate AND2 is connected to the cycle time generating circuit and receives an external circuit abnormality signal. The second input end of the second AND gate AND2 receives a reset signal output by the RS trigger A2. The second AND gate AND2 outputs a protection signal. The reset end of the RS trigger A2 (the third end of the protection signal generating circuit) is connected to the inverting output end of the last D trigger among multiple D triggers (the third end of the timing circuit). The set end of the RS trigger A2 (the fourth end of the protection signal generating circuit) is connected to the inverting output end of the first D trigger among multiple D triggers (the fourth end of the timing circuit). The output end of the RS trigger A2 is connected to the input end of the second inverter NOT2. The output end of the second inverter NOT2 serves as the second end of the protection signal generating circuit.

[0038] Specifically, when the external circuit is in a normal working state, that is, when the external circuit abnormal signal is a low-level signal, the first signal S1 is a low-level signal. Therefore, at this time, the tenth signal S10 output by the second AND gate AND2 and the signal output by the first AND gate AND1 are also low-level. Since the first AND gate AND1 outputs a low-level signal, the second switch tube M2 is turned off, the second current source I2 continues to charge the second capacitor C2, the first inverter NOT1 inputs a high level, the fourth signal S4 output by the first inverter NOT1 is a low level, the first switch tube M1 is turned off, the first current source I1 continues to charge the first capacitor C1, and the voltage of the third signal S3 continues to increase. When the voltage of the third signal S3 increases to be greater than the first voltage V1, the second signal S2 output by the comparator A1 switches from a low level to a high level and always maintains a high level state. After that, the voltage of the third signal S3 continues to increase until the first capacitor C1 is fully charged. In addition, since the fourth signal S4 is always a low level, after the low-level fourth signal S4 is input into the timing circuit, the timing circuit is always in a non-working state. From the above analysis, when the external circuit is in normal working state, only the soft start circuit in the protection circuit is in normal working state, and the protection circuit is only used as a soft start circuit; Figure 3 The waveform diagram of each signal in the protection circuit when the external circuit is in normal working state is shown. Figure 3 It can be seen that when the external circuit is in a normal working state, the third signal S3 (ie, the soft start signal) gradually increases, and when the third signal S3 increases to a maximum value, the circuit completes the startup process.

[0039] When the external circuit is in an abnormal working state, that is, the external circuit abnormal signal is a high level signal, the first signal S1 switches to a high level, and Figure 3It can be seen that when the external circuit is in a normal working state, the second signal S2 is in a high level state, so at this time, the output of the first AND gate AND1 is switched from a low level to a high level, the second switch tube M2 is turned on, the input end of the first inverter NOT1 is pulled low, the fourth signal S4 is switched to a high level, the first switch tube M1 is turned on, and the third signal S3 is switched to a low level. At this time, the second signal S2 output by the comparator A1 is also switched to a low level. After that, the output of the first AND gate AND1 is switched from a high level to a low level, the second switch tube M2 is turned off, and the second current source I2 charges the second capacitor C2. When the terminal voltage of the second capacitor C2 is greater than the first When the flip threshold voltage of the first inverter NOT1 is reached, the fourth signal S4 is switched from a high level to a low level, the first switch tube M1 is turned off, the first current source I1 starts to charge the first capacitor C1, and the voltage of the third signal S3 starts to increase gradually. When the voltage of the third signal S3 increases to be greater than the first voltage V1, the second signal S2 output by the comparator A1 is switched from a low level to a high level. At this time, the output of the first AND gate AND1 is switched from a low level to a high level, the second switch tube M2 is turned on again, the input end of the first inverter NOT1 is pulled low, the fourth signal S4 is switched to a high level, and the circuit enters the next cycle. At this time, it can be obtained as follows Figure 4 As shown in the first waveform diagram when the external circuit is in an abnormal working state, the fourth signal S4 can also be called a periodic time signal.

[0040] Depend on Figure 4 It can be seen from the waveform that when the circuit is in an abnormal working state, after the first signal S1 switches to a high level for a short time, the second signal S2 switches from a high level state to a low level state. This short time is the feedback adjustment time of the circuit. In each subsequent cycle, the second signal S2 switches from a high level state to a low level state after this short time; the time for the fourth signal S4 to maintain a high level = the time for the third signal S3 to maintain a low level ≈ the time for the second capacitor C2 to be charged to a terminal voltage greater than the flip threshold voltage of the first inverter NOT1.

[0041] At the same time, by Figure 2 It can be seen that the first signal S1 and the ninth signal S9 output the tenth signal S10 after passing through the second AND gate AND2, and when the circuit is in an abnormal working state, the first signal S1 is always at a high level, so the waveform of the tenth signal S10 is the same as the waveform of the ninth signal S9. At this time, the number of D flip-flops in the timing circuit is first designed to be three, and then the waveform of the ninth signal S9 is analyzed: Since the fourth signal S4 is input to the clock input terminal of the first D flip-flop, the fifth signal S5 is input to the clock input terminal of the second D flip-flop, and the sixth signal S6 is input to the clock input terminal of the third D flip-flop, the waveforms of the fifth signal S5, the sixth signal S6 and the seventh signal S7 can be obtained according to the waveform of the fourth signal S4, as shown in FIG. Figure 5 shown.

[0042] like Figure 5 As shown, the initial signals of the fifth signal S5, the sixth signal S6 and the seventh signal S7 are all high-level signals. When the rising edge of the fourth signal S4 arrives, the fifth signal S5 is converted to a level and output. When the rising edge of the fifth signal S5 arrives, the sixth signal S6 is converted to a level and output. When the rising edge of the sixth signal S6 arrives, the seventh signal S7 is converted to a level and output. At this time, since the seventh signal S7 is input to the R terminal (reset terminal) of the RS trigger A2, the signal input to the R terminal of the RS trigger is in phase with the seventh signal S7, and the signal input to the S terminal (set terminal) of the RS trigger is the fifth signal S5. That is, at this time, according to the waveform of the fifth signal S5 and the waveform of the seventh signal S7, the waveform of the ninth signal S9 (also called the reset signal) at the output terminal of the RS trigger A2 can be obtained. In the first cycle of the fourth signal S4, the fifth signal S5 is a low level and the seventh signal S7 is a high level. Therefore, the ninth signal S9 is a high level. In the second cycle of the fourth signal S4, the fifth signal S5 is a high level and the seventh signal S7 is a high level. Therefore, the ninth signal S9 is a high level. The signal S9 remains at a high level. In the third cycle of the fourth signal S4, the fifth signal S5 is at a low level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 is at a high level. In the fourth cycle of the fourth signal S4, the fifth signal S5 is at a high level and the seventh signal S7 is at a low level. Therefore, the ninth signal S9 is at a low level. At this time, since the ninth signal S9 is input into the CL terminal (clear terminal) of the second D flip-flop and the third D flip-flop through the second inverter NOT2, and the D flip-flop CL terminal is reset when receiving a high level, therefore, when the ninth signal S9 is at a low level, the second D flip-flop and the third D flip-flop are immediately reset, and the seventh signal S7 and the sixth signal S6 are restored to the initial high level state. At this time, the fifth signal S5 is at a high level and the seventh signal S7 is at a high level. Therefore, the ninth signal S9 remains at a low level. Afterwards, in the fifth cycle of the fourth signal S4, the fifth signal S5 is at a low level and the seventh signal S7 is at a high level. The ninth signal S9 is switched to a high level again. Afterwards, the circuit works continuously in a cycle according to the above working process.

[0043] Therefore, when the tenth signal S10 (protection signal) output by the protection circuit is at a high level, the external circuit is controlled to enter a protection state; when the tenth signal S10 (protection signal) output by the protection circuit is at a low level, the external circuit is controlled to enter a normal working state; if the abnormal condition of the external circuit still exists, the circuit enters the protection state again.

[0044] In an optional embodiment, if Figure 6As shown, the protection signal generating circuit includes a second AND gate AND2, an RS trigger A2, a second inverter NOT2 and a third inverter NOT3, the first input end of the second AND gate AND2 is connected to the cycle time generating circuit and receives the external circuit abnormality signal, the second input end of the second AND gate AND2 receives the reset signal output by the RS trigger A2, the second AND gate AND2 outputs a protection signal, the input end of the third inverter NOT3 (the third end of the protection signal generating circuit) is connected to the output end of the last D trigger among multiple D triggers (the third end of the timing circuit), the output end of the third inverter NOT3 is connected to the reset end of the RS trigger A2, the set end of the RS trigger A2 (the fourth end of the protection signal generating circuit) is connected to the inverting output end of the first D trigger among multiple D triggers (the fourth end of the timing circuit), the output end of the RS trigger A2 is connected to the input end of the second inverter NOT2, and the output end of the second inverter NOT2 serves as the second end of the protection signal generating circuit.

[0045] Specifically, by setting a third inverter NOT3 in the protection signal generating circuit, the input end of the third inverter NOT3 is connected to the output end of the last D flip-flop, that is, the eighth signal S8 outputted from the output end of the last D flip-flop is inverted and then inputted into the RS flip-flop A2. The eighth signal S8 actually has the same waveform as the seventh signal S7 outputted from the inverting output end of the last D flip-flop. However, by further setting a third inverter NOT3 in the protection signal generating circuit, the current capability of the signal can be improved and the circuit response speed can be accelerated.

[0046] The present invention also provides an analog integrated circuit control chip, comprising the protection circuit for reducing chip area of ​​the above embodiment.

[0047] The present invention further provides a power supply circuit, comprising the analog integrated circuit control chip of the above embodiment.

[0048] Specifically, when an analog integrated circuit control chip is provided in the power supply circuit, the chip can control the power supply process of the power supply circuit, and in addition to the analog integrated circuit control chip, a power circuit and other structures can also be provided in the power supply circuit. Since the above-mentioned protection circuit for reducing the chip area is provided in the analog integrated circuit control chip, the volume of the analog integrated circuit control chip is reduced; and when the analog integrated circuit control chip is provided in the power supply circuit, the volume of the power supply circuit is further reduced.

[0049] Although the exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims, and such modifications and variations all fall within the scope defined by the appended claims. For other examples, those of ordinary skill in the art should readily understand that the order of the process steps may be changed while maintaining the scope of protection of the present invention.

[0050] In addition, the scope of application of the present invention is not limited to the processes, mechanisms, manufactures, material compositions, means, methods and steps of the specific embodiments described in the specification. From the disclosure of the present invention, it will be easily understood by those skilled in the art that the processes, mechanisms, manufactures, material compositions, means, methods or steps that currently exist or will be developed in the future, which perform substantially the same functions as the corresponding embodiments described in the present invention or obtain substantially the same results, can be applied according to the present invention. Therefore, the claims attached to the present invention are intended to include these processes, mechanisms, manufactures, material compositions, means, methods or steps within their scope of protection.

Claims

1. A protection circuit for reducing chip area, characterized in that: include: A soft start circuit, a cycle time generating circuit, a timing circuit and a protection signal generating circuit, wherein a first end of the cycle time generating circuit is connected to a first end of the protection signal generating circuit and receives an external circuit abnormality signal; When the external circuit abnormality signal is a low-level signal, the cycle time generating circuit generates a low-level signal and makes the soft start circuit in a working state, the timing circuit is in a non-working state according to the low-level signal, and the protection signal generating circuit outputs a low-level protection signal according to the low-level signal and the timing circuit; When the external circuit abnormal signal is a high-level signal, the working states of the cycle time generating circuit and the soft start circuit influence each other so that the cycle time generating circuit outputs a cycle time signal, the timing circuit outputs a periodic signal according to the cycle time signal and the reset signal, the protection signal generating circuit outputs a reset signal according to the periodic signal, and the protection signal generating circuit also outputs a protection signal according to the external circuit abnormal signal and the reset signal.

2. The chip area reducing protection circuit according to claim 1, characterized in that: A soft start circuit, wherein the first end, the second end and the third end are respectively connected to the second end, the third end and the fourth end of the cycle time generating circuit, the first end is also connected to an external power supply, and the second end is grounded; a cycle time generating circuit, a fifth terminal of which is connected to the first terminal of the timing circuit; a timing circuit, wherein the second end, the third end and the fourth end of the timing circuit are respectively connected to the second end, the third end and the fourth end of the protection signal generating circuit; The protection signal generating circuit has a fifth terminal which outputs a protection signal.

3. The chip area reducing protection circuit according to claim 2, characterized in that: The soft start circuit includes a first current source and a first capacitor, one end of the first current source is connected to an external power supply and a second end of a cycle time generating circuit, the other end of the first current source is connected to one end of the first capacitor and a fourth end of the cycle time generating circuit, and the other end of the first capacitor is connected to a third end of the cycle time generating circuit and is grounded.

4. The chip area reducing protection circuit according to claim 2, characterized in that: The cycle time generating circuit includes a first switch tube, a second switch tube, a comparator, a first inverter, a first AND gate, a second current source and a second capacitor; The first input end of the first AND gate receives an external circuit abnormality signal, the second input end of the first AND gate is connected to the output end of the comparator, the output end of the first AND gate is connected to the first end of the second switch tube, the second end of the second switch tube is connected to one end of the second capacitor, the first end of the first switch tube and grounded, the third end of the second switch tube is connected to the other end of the second capacitor, the input end of the first inverter and one end of the second current source, the other end of the second current source is connected to an external power supply, the output end of the first inverter is connected to the second end of the first switch tube and the first end of the timing circuit, the third end of the first switch tube is connected to the third end of the soft start circuit and the positive input end of the comparator, and the negative input end of the comparator receives the first voltage.

5. The chip area reducing protection circuit according to claim 4, characterized in that: The output terminal of the first inverter outputs a periodic time signal.

6. The chip area reducing protection circuit according to claim 2, characterized in that: The timing circuit includes a plurality of D flip-flops connected in series. Among the plurality of D flip-flops connected in series, a clock input terminal of the first D flip-flop is connected to the fifth terminal of the cycle time generating circuit, and a reset terminal of the first D flip-flop is grounded. Starting from the second D flip-flop, a clock input terminal of each D flip-flop is connected to the inverting output terminal and the signal input terminal of the previous D flip-flop, and a reset terminal of each D flip-flop is connected to the second terminal of the protection signal generating circuit.

7. The chip area reducing protection circuit according to claim 6, characterized in that: The protection signal generating circuit includes a second AND gate, an RS trigger and a second inverter; The first input end of the second AND gate is connected to the cycle time generating circuit and receives the external circuit abnormality signal, the second input end of the second AND gate receives the reset signal output by the RS trigger, the second AND gate outputs a protection signal, the reset end of the RS trigger is connected to the inverting output end of the last D trigger among the multiple D triggers, the set end of the RS trigger is connected to the inverting output end of the first D trigger among the multiple D triggers, the output end of the RS trigger is connected to the input end of the second inverter, and the output end of the second inverter serves as the second end of the protection signal generating circuit.

8. The chip area reducing protection circuit according to claim 6, characterized in that: The protection signal generating circuit includes a second AND gate, an RS trigger, a second inverter and a third inverter; The first input end of the second AND gate is connected to the cycle time generating circuit and receives the external circuit abnormality signal, the second input end of the second AND gate receives the reset signal output by the RS trigger, the second AND gate outputs a protection signal, the input end of the third inverter is connected to the output end of the last D trigger among the multiple D triggers, the output end of the third inverter is connected to the reset end of the RS trigger, the set end of the RS trigger is connected to the inverting output end of the first D trigger among the multiple D triggers, the output end of the RS trigger is connected to the input end of the second inverter, and the output end of the second inverter serves as the second end of the protection signal generating circuit.

9. The chip area reducing protection circuit according to claim 6, characterized in that: The number of D flip-flops is determined according to the period of the periodic time signal and the preset off time when the external circuit is abnormal.

10. The chip area reducing protection circuit according to claim 6, characterized in that: The timing circuit includes at least two D flip-flops.

11. An analog integrated circuit control chip, characterized in that: A chip area reducing protection circuit comprising the chip area reducing protection circuit as described in any one of claims 1 to 10.

12. A power supply circuit, characterized in that: Includes the analog integrated circuit control chip as described in claim 11.

Images