High-bit-width Ethernet gfp scrambling method and system

Abstract

The invention discloses a high-bit-width Ethernet gfp scrambling method and system, and relates to the technical field of optical communication, and the high-bit-width Ethernet gfp scrambling method comprises the following steps: moving data needing to be scrambled in a beat to a high bit, replacing all invalid data which moves to a low bit and does not need to be scrambled with 0, and recording the moving byte quantity; converting single-bit adding and winding into parallel adding and winding of the current bit width, and performing exclusive-or operation on the shifted data and a parallel polynomial to obtain scrambled data and new scrambling state data; based on the byte number of the invalid data, the scrambling state shift condition number is subjected to remainder operation, a shift compensation value is determined, reverse shift is carried out on the new scrambling state data, and compensated scrambling state data is obtained; and performing reverse shift on the scrambled data based on the recorded moved byte amount so as to perform shift recovery. According to the application, the high-bit-width gfp scrambling can be feasible on the implementation of the asic circuit, the resources can be saved, and the time sequence can be improved.

Description

Technical Field

[0001] The present application relates to the field of optical communication technology, and in particular to a high-bitwidth Ethernet GFP scrambling method and system. Background Art

[0002] With the continuous development of science and technology, the demand for data bandwidth is getting higher and higher. Against this background, 5G came into being. In order to meet the transmission characteristics of high capacity and low latency of 5G signals, the network also tends to be integrated and interconnected.

[0003] The integration of PTN (Packet Transport Network) and OTN (Optical Transport Network) equipment is an inevitable trend. In high-speed POTN (Packet over Optical Network) chips, Ethernet services are mapped to the OTN frame structure through GFP (Generic Framing Procedure).

[0004] As the capacity increases, in order to reduce the system clock of the chip and increase the data processing bit width. As the system requirements continue to increase, from the initial 1G, 10G, 100G, 400G to the current 1.6T transmission bandwidth requirements. The data processing bit width is also from 8b, 64b, 512b to 2024b. In the GFP processing process, scrambling is a key core technology. At present, there are many parallel multi-bit processing methods, but because Eth (Ethernet) data is bubbled, the mapping of Eth to GFP has different rates on both sides, so the rate adjustment is required. IPG (Inter-Packet Gap) is inserted between Eth packets to adjust the rate. The size of the inserted IPG (i.e. bubble) is variable; and the frame length is variable, ranging from 64 to 9600B. Therefore, the number of valid bytes in a beat is not fixed, and the position is also not fixed. Therefore, the amount of data scrambled in one beat is different. Scrambling different amounts of data requires parallel scrambling polynomials of different bit widths. When the data bit width is low, different amounts of data can be scrambled by a selected method. When the bit width is wide, this method will cause disadvantages such as consuming logic resources and timing differences. Summary of the invention

[0005] The present application provides a high-bit-width Ethernet GFP scrambling method and system, which can make high-bit-width GFP scrambling feasible in ASIC circuit implementation and can also save resources and timing.

[0006] In a first aspect, an embodiment of the present application provides a high-bitwidth Ethernet GFP scrambling method, the high-bitwidth Ethernet GFP scrambling method comprising:

[0007] Move the data that needs to be scrambled within a beat to the high bit, replace all the invalid data that does not need to be scrambled and is moved to the low bit with 0, and record the amount of bytes moved;

[0008] Convert the single-bit convolution into parallel convolution of the current bit width, and perform XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

[0009] Taking the modulus of the number of scrambling state shift situations based on the number of bytes of invalid data, determining a shift compensation value, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data;

[0010] The scrambled data is reverse shifted based on the recorded shifted byte amount to perform shift recovery.

[0011] In combination with the first aspect, in one implementation, invalid data that does not require scrambling is determined based on sop and eop identifiers of the data packet.

[0012] In combination with the first aspect, in one implementation, the invalid data that does not require scrambling includes bubble data and a core header of a gfp frame.

[0013] In combination with the first aspect, in one implementation, when there are multiple gfp frames in one shot, the bubble data at a low position is moved first, and then the bubble data at a high position is moved.

[0014] In combination with the first aspect, in one implementation, performing an XOR operation on the shifted data and the parallel polynomial to obtain scrambled data includes:

[0015] The shifted data is XORed in two stages to obtain the first data;

[0016] The first data is XORed with a first scrambling coefficient of a parallel polynomial based on bit width cyclic extension to obtain scrambled data.

[0017] In combination with the first aspect, in one implementation, the parallel polynomial is Y=X 43 +1.

[0018] In combination with the first aspect, in one implementation, the shift compensation value cm is calculated according to the formula: cm=(wd / 8-sz)%43, where wd is the data bit width and sz is the number of bytes that need to be scrambled in one beat.

[0019] In a second aspect, an embodiment of the present application provides a high-bitwidth Ethernet GFP scrambling system, the high-bitwidth Ethernet GFP scrambling system comprising:

[0020] A shift unit, which is used to move the data that needs to be scrambled within a beat to a high position, replace all invalid data that does not need to be scrambled and is moved to a low position with 0, and record the amount of bytes moved;

[0021] A scrambling unit, which is used to convert the single-bit scrambling into a parallel scrambling of the current bit width, and perform an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

[0022] a compensation unit, which modulo the number of scrambling state shift situations based on the number of bytes of invalid data to determine a shift compensation value, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data;

[0023] A shift recovery unit reversely shifts the scrambled data based on the recorded shifted byte amount to perform shift recovery.

[0024] In combination with the second aspect, in one implementation, the shift unit determines invalid data that does not need to be scrambled based on sop and eop identifiers of the data packet.

[0025] In combination with the second aspect, in one implementation, the invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame;

[0026] When there are multiple gfp frames in one shot, the shift unit first shifts the bubble data at a low position, and then shifts the bubble data at a high position.

[0027] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0028] The high-bit-width Ethernet GFP scrambling method of the present application moves data that need to be scrambled within one beat to a high position, replaces all invalid data that does not need to be scrambled and is moved to a low position with 0, and records the amount of bytes moved; converts the single-bit convolution into a parallel convolution of the current bit width, and performs an XOR operation on the shifted data and a parallel polynomial to obtain scrambled data and new scrambled state data; modulo the number of scrambled state shift situations based on the number of bytes of invalid data, determines a shift compensation value, and reversely shifts the new scrambled state data to obtain compensated scrambled state data; reversely shifts the scrambled data based on the recorded amount of moved bytes to perform shift recovery.

[0029] That is, the present application shifts the data to be scrambled, uses a common bit-width parallel algorithm to scramble, and then compensates according to the number of invalid bytes. By optimizing the compensation value, the compensation can be completed within one beat, reducing the constraints on the upstream module, providing timing, and making high-bit-width GFP scrambling feasible in ASIC circuit implementation. And it saves resources and timing. And the method has universality, making it more widely applicable to the scenario of scrambling and descrambling data with bubbles. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A serial scrambler for implementing the method of the present application;

[0031] Figure 2 This is a flow chart of an embodiment of a high-bitwidth Ethernet GFP scrambling method of the present application;

[0032] Figure 3 It is the scrambled front shift scene graph in this application;

[0033] Figure 4 It is the scrambled front shift scene graph in this application;

[0034] Figure 5 This is a parallel scrambling flow chart in this application;

[0035] Figure 6 A schematic diagram of the data portion of the scrambling coefficient of the 512-bit parallel scrambler in this application;

[0036] Figure 7 It is a schematic diagram of the 43-bit state portion of the scrambling coefficient of the 512-bit parallel scrambler in this application;

[0037] Figure 8 This is a structural block diagram of an embodiment of a high-bit-width Ethernet GFP scrambling system of the present application. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In order to solve the problems in the prior art, the present application provides a compensation-based universal GFP scrambler parallel scrambling for data with bubbles, thereby reducing the consumption of logic resources, reducing chip power consumption, reducing chip costs and chip investment risks, and enhancing the competitiveness of system equipment.

[0040] First of all, it should be noted that the derivation process of the compensated universal GFP scrambler is as follows:

[0041] like Figure 1 As shown, according to the G.7041 protocol, the scrambling process of gfp is Y=X 43 +1 self-synchronous scrambling, where X is the input value or current state and Y is the output value or next state. GFP's serial scrambler:

[0042] Y(t)=X(t)^Y(t-43);

[0043] Scrambler status update:

[0044] {Y(t-43),Y(t-42),Y(t-41),...,Y(t-2),Y(t-1)}={Y(t-42),Y(t-41),...,Y(t-1),Y(t)};

[0045] When X(t) is 0:

[0046] Y(t)=X(t)^Y(t-43)=Y(t-43);

[0047] Scrambler status update:

[0048] {Y(t-43),Y(t-42),Y(t-41),...,Y(t-2),Y(t-1)}={Y(t-42),Y(t-41),...,Y(t-1),Y(t-43)};

[0049] This is equivalent to the scrambler state being cyclically shifted left by one position. If the scrambler state is cyclically shifted right by one position, it is equivalent to not scrambling 0.

[0050] If N consecutive 0s are scrambled, it is equivalent to the scrambler state being cyclically shifted left by N bits. If the scrambler state is cyclically shifted right by N bits, it is also restored to the original state.

[0051] If the bus width is wdbit, and there are sz bytes in one beat of data that need to be scrambled, in order to use the same scrambler, the data that does not need to be scrambled in the current beat can be replaced with 0, and the sz bytes of valid data can be moved to the top of the whole beat, with the tail being 0. Scramble the whole beat of wdbit data, and the first sz bytes after scrambling are the valid data after scrambling. Then cyclically right-shift the scrambler by (wd / 8-sz)%43 bits to get the state after only sz bytes are scrambled. Then use the same method to scramble the next beat of data.

[0052] Compensation optimization method:

[0053] When N is large, more cyclic shifts are needed, which is difficult to implement in a one-shot circuit. The usual method is to implement it by using a multi-stage pipeline, and no subsequent data can be involved in the scrambler during the multi-stage processing. This introduces two problems:

[0054] 1. Reduced bandwidth utilization;

[0055] 2. If it is serial channel processing, then the upstream module is restricted and the same channel cannot be shot continuously;

[0056] Based on the above, when the input x(t) is 0, the value of the scrambler's stat43bit will not change, but will slide: stat[42:0]<={stat[41:0],stat

[42] }. Then, if all the data that needs to be scrambled in one beat is moved to the top, and then the invalid data is replaced with all 0s, all the data of the whole beat is scrambled, and then the invalid 0s are compensated, the scrambling polynomial is unified and can be realized.

[0057] Moreover, there are only 43 cases of scrambling states {Y(t-43), Y(t-42), Y(t-41), ..., Y(t-2), Y(t-1)} during the shifting process, so the amount of data that needs to be compensated can be converted to 43 through (wd / 8-sz)%43. In this way, only 43 cases need to be processed in one beat, so the requirement can be met in one beat in terms of timing.

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0059] In a first aspect, an embodiment of the present application provides a high-bitwidth Ethernet GFP scrambling method.

[0060] In one embodiment, referring to Figure 2 As shown, Figure 2 This is a flow chart of an embodiment of a high-bitwidth Ethernet GFP scrambling method of the present application. Figure 2 As shown, the high-bitwidth Ethernet GFP scrambling method includes:

[0061] S1. Move the data that needs to be scrambled in one beat to the high bit, replace all the invalid data that does not need to be scrambled and is moved to the low bit with 0, and record the amount of bytes moved;

[0062] It is worth noting that see Figure 3 As shown in the figure, the left side of the picture is the MAC frame, and the right side is the GFP frame; the GFP protocol maps the MAC message to the GFP frame;

[0063] For gfp frames:

[0064] PLI+cHEC is the core header

[0065] Type+tHEC is the type header

[0066] Gfp externsion header is an extension header and is generally not used;

[0067] Gfp payload: It is the payload field, which contains the mac message;

[0068] In the entire gfp frame, only the core header is not scrambled, and the rest are scrambled.

[0069] When the data bit width reaches 512b, 2028b, etc., there may be multiple GFP frames in one beat of the Ethernet bus structure, and the number of valid bytes that need to be scrambled in one beat will increase. Therefore, the traditional traversal method cannot meet the requirements of circuit design.

[0070] Taking 512b as an example, it may appear Figure 4 For the three scenarios, scenarios 1 to 3 need to be shifted, the data to be scrambled is moved to the high bit, and the invalid data in the low bit is replaced with 0.

[0071] See also Figure 4 As shown, this embodiment mainly determines invalid data that does not need to be scrambled according to the sop and eop identifiers of the data packet, and the invalid data that does not need to be scrambled includes bubble data and the core header of the gfp frame.

[0072] The following describes how to handle scenarios 1 to 3:

[0073] Scenario 1: The eop of the previous frame (such as eop_a) and the sop of the next frame (such as sop_a) are in the same beat. The invalid data between the eop of the previous frame and the sop of the next frame needs to be moved to the end of the data, and the invalid data at the end is replaced with 0.

[0074] Since the position of each sop and eop is known during the shift, if the invalid bytes between eop_a and sop_a are moved first, the positions of eop_b and sop_b will change, and the marks eop_b and sop_b will also change accordingly, increasing the design complexity; if the invalid bytes between eop_b and sop_b are moved first, the positions of eop_a and sop_a will not change, so there is no need to recalculate the position information. Therefore, in this embodiment, the invalid bytes between eop_b and sop_b are moved first, and then the invalid bytes between eop_a and sop_a are moved, and the amount of bytes moved is recorded at the same time;

[0075] Scenario 2: If only sop exists in a beat, the data before sop is invalid. Move the invalid bytes before sop to the end of the data, replace the invalid data at the end with 0, and record the amount of bytes moved.

[0076] Scenario 3: There is only eop in a beat, and there are related bytes of the core header before eop. The core header usually has 4 bytes. It is necessary to determine the number of bytes occupied by the core header in the current beat in combination with the situation of the previous beat. In this embodiment, the core header is data that does not need to be scrambled, and it will also be treated as invalid data and moved to the end of the data. The invalid data at the end is replaced with 0, and the amount of bytes moved is recorded at the same time.

[0077] In specific implementation, three different circuits can be designed for three scenarios, each circuit is used to identify and process its corresponding scenario, so that the relevant scenarios can be shifted through the cooperation of these three circuits to move invalid data to a low position. It is understandable that if there are other scenarios that require shifting, the above method can also be used, and this embodiment will not be repeated here.

[0078] S2, converting the single-bit wrapping into a parallel wrapping of the current bit width, and performing an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

[0079] like Figure 5 As shown, taking 512 bits as an example, the entire calculation process first converts the single-bit convolution into 512-bit parallel convolution through an algorithm. The shifted data is XORed with the parallel polynomial to obtain the scrambled data and the scrambled state data. A multi-stage pipeline design is adopted; data scrambling: the data part is first divided into two pipelines (d2_r and d2_l) and XORed to obtain the first data d3_reg, and then XORed with the first scrambling coefficient d_s3 based on the bit width cyclic extension to obtain the scrambled data. Get new_st43: Similarly, the data part is divided into two stages of pipelines (stat2_r and stat2_l) and XORed to obtain the second data stat3_reg, and then XORed with the second scrambling coefficient stat_s3 to obtain the new scrambled state data new_st43.

[0080] It is worth mentioning that when the processing logic of one beat is large, the logic needs to be separated and developed for multi-beat processing, which is called pipeline design.

[0081] like Figure 1The structure of the scrambler shown in the figure, the input data and the scrambling coefficient are XORed to obtain the scrambled data and the new scrambling coefficient, which is a single bit; if multiple bits are processed and scrambled at the same time, such as 512 bits per shot, the serial scrambler must be designed into a parallel scrambler through an algorithm;

[0082] Specifically, st_43 is processed by the algorithm to obtain d_s3. For example, d_s3 is 512 bits, and is XORed with the 512 bits of data bit by bit. For details, see Figure 6 , Figure 6 The last column is d_s3.

[0083] Figure 6 It is the data part of the scrambling coefficient of the 512-bit parallel scrambler, where s42~s0 represent the scrambling state coefficient of the scrambler 43 bits; d511~d0 represent the 512 data to be scrambled, with high bits first; data

[511] ~data[0] represent the scrambled data.

[0084] The process of deriving the parallel scrambling coefficient: According to the principle of the serial scrambler, Y(t) = X(t)^Y(t-43),

[0085] The first data scramble:

[0086] data

[511] =d511+s42;

[0087] New Y(t-43)=s41,...,Y(t)=d511+s42;

[0088] The second data scrambling:

[0089] data

[510] =d510+s41,

[0090] New Y(t-43)=s40,...,Y(t)=d510+s41

[0091] And so on, the 43rd data is scrambled:

[0092] data

[469] =d469+s0;

[0093] New Y(t-43)=d511+s42,...,Y(t)=d469+s0

[0094] The 44th data is scrambled:

[0095] data

[468] =d468+d511+s42;

[0096] The new Y(t-43)=d510+s41,,...,Y(t)=d468+d511+s42.

[0097] The scrambling of the remaining data is also processed in the above manner, which will not be described in detail in this embodiment.

[0098] After st_43 is processed by the algorithm, stat_s3 is obtained. Stat_s3 is still 43 bits. It is XORed with stat to obtain a new scrambling coefficient. For details, please refer to Figure 7 , Figure 7 The last column is stat_s3.

[0099] Figure 7 It is the 43-bit state part of the scrambling coefficient of the 512-bit parallel scrambler. According to the rules of the scrambling serial scrambler, s

[42] ~s[0] should be the last 43 data after this scrambling, that is, the scrambled data data

[42] ~data[0].

[0100] S3, taking the modulus of the number of scrambling state shift situations based on the number of bytes of invalid data, determining a shift compensation value, and performing a reverse shift on the new scrambling state data to obtain compensated scrambling state data;

[0101] It is worth noting that the movement to the high position in step S1 refers to the leftward shift ( Figure 3 The reverse shift in step S3 is a rightward shift.

[0102] It can be understood that after the above steps, the number of invalid bytes M (i.e. wd / 8-sz) is already known, and then the optimized compensation value is obtained through cm=(wd / 8-sz)%43, and then the new_st43 is circularly shifted right by the optimized compensation value to obtain the compensated new_st43, and then new_st43 is stored by channel to achieve serialization.

[0103] S4. Reverse shift the scrambled data based on the recorded shifted byte amount to perform shift recovery.

[0104] Taking the above scenario as an example, the recovery process after winding is exactly the opposite of the data shift before winding. The processing order is scenario 3, scenario 2, and scenario 1:

[0105] Scenario 3: According to the number of bytes marked for left shift at that time, directly shift the data right by the same number of bytes;

[0106] Scenario 2: According to the number of bytes marked as left shifted at that time, the data is shifted right by the same number of bytes;

[0107] Scenario 1: First move and restore the invalid bytes between eop_a and sop_a, and then move the invalid bytes between eop_b and sop_b.

[0108] At this point, high-bitwidth Ethernet GFP scrambling has been achieved.

[0109] In summary, the high-bit-width Ethernet GFP scrambling method in the present application moves the data that needs to be scrambled within one beat to a high position, replaces all invalid data that does not need to be scrambled and is moved to a low position with 0, and records the amount of bytes moved; converts the single-bit convolution into a parallel convolution of the current bit width, and performs an XOR operation on the shifted data and a parallel polynomial to obtain the scrambled data and new scrambled state data; modulo the number of scrambled state shift situations based on the number of bytes of invalid data, determines a shift compensation value, and reversely shifts the new scrambled state data to obtain compensated scrambled state data; reversely shifts the scrambled data based on the recorded amount of moved bytes to perform shift recovery.

[0110] That is, the present application shifts the data to be scrambled, uses a common bit-width parallel algorithm to scramble, and then compensates according to the number of invalid bytes. By optimizing the compensation value, the compensation can be completed within one beat, reducing the constraints on the upstream module, providing timing, and making high-bit-width GFP scrambling feasible in ASIC circuit implementation. And it saves resources and timing. And the method has universality, making it more widely applicable to the scenario of scrambling and descrambling data with bubbles.

[0111] In a second aspect, an embodiment of the present application also provides a high-bitwidth Ethernet GFP scrambling system.

[0112] In one embodiment, referring to Figure 8 , Figure 8 This is a structural block diagram of an embodiment of the high-bitwidth Ethernet GFP scrambling system of the present application. Figure 8 As shown, the high-bitwidth Ethernet GFP scrambling system includes:

[0113] A shift unit, which is used to move the data that needs to be scrambled within a beat to a high position, replace all invalid data that does not need to be scrambled and is moved to a low position with 0, and record the amount of bytes moved;

[0114] A scrambling unit, which is used to convert the single-bit scrambling into a parallel scrambling of the current bit width, and perform an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data;

[0115] a compensation unit, which modulo the number of scrambling state shift situations based on the number of bytes of invalid data to determine a shift compensation value, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data;

[0116] A shift recovery unit reversely shifts the scrambled data based on the recorded shifted byte amount to perform shift recovery.

[0117] Furthermore, in one embodiment, the shift unit determines invalid data that does not need to be scrambled according to sop and eop identifiers of the data packet.

[0118] Further, in one embodiment, the invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame;

[0119] When there are multiple gfp frames in one shot, the shift unit first shifts the bubble data at a low position, and then shifts the bubble data at a high position.

[0120] Further, in one embodiment, performing an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data includes:

[0121] The shifted data is XORed in two stages to obtain the first data;

[0122] The first data is XORed with a first scrambling coefficient of a parallel polynomial based on bit width cyclic extension to obtain scrambled data.

[0123] Furthermore, in one embodiment, the parallel polynomial is Y=X 43 +1, the compensation unit calculates the shift compensation value cm according to the formula: cm=(wd / 8-sz)%43, where wd is the data bit width and sz is the number of bytes that need to be scrambled in one beat.

[0124] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0125] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0126] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0127] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0128] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0129] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A high bit width Ethernet GFP scrambling method, characterized in that: The high-bitwidth Ethernet GFP scrambling method comprises: Move the data that needs to be scrambled within a beat to the high bit, replace all the invalid data that does not need to be scrambled and is moved to the low bit with 0, and record the amount of bytes moved; Convert the single-bit convolution into parallel convolution of the current bit width, and perform XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data; Taking the modulus of the number of scrambling state shift situations based on the number of bytes of invalid data, determining a shift compensation value, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data; The scrambled data is reverse shifted based on the recorded shifted byte amount to perform shift recovery.

2. The high bit width Ethernet GFP scrambling method according to claim 1, characterized in that: Invalid data that does not need to be scrambled is determined based on the sop and eop identifiers of the data packet.

3. The high bit width Ethernet GFP scrambling method according to claim 1 or 2, characterized in that: The invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame.

4. The high bit width Ethernet GFP scrambling method as claimed in claim 3, characterized in that: When there are multiple gfp frames in one shot, the bubble data at the lower position is moved first, and then the bubble data at the higher position is moved.

5. The high bit width Ethernet GFP scrambling method according to claim 1, characterized in that: The step of performing an XOR operation on the shifted data and the parallel polynomial to obtain scrambled data includes: The shifted data is XORed in two stages to obtain the first data; The first data is XORed with a first scrambling coefficient of a parallel polynomial based on bit width cyclic extension to obtain scrambled data.

6. The high bit width Ethernet GFP scrambling method according to claim 1 or 5, characterized in that: The parallel polynomial is Y=X 43 +1.

7. The high bit width Ethernet GFP scrambling method according to claim 6, characterized in that: The shift compensation value cm is calculated according to the formula: cm=(wd / 8-sz)%43, where wd is the data bit width and sz is the number of bytes that need to be scrambled in one beat.

8. A high bit width Ethernet GFP scrambling system, characterized in that: The high-bitwidth Ethernet GFP scrambling system comprises: A shift unit, which is used to move the data that needs to be scrambled within a beat to a high position, replace all invalid data that does not need to be scrambled and is moved to a low position with 0, and record the amount of bytes moved; A scrambling unit, which is used to convert the single-bit scrambling into a parallel scrambling of the current bit width, and perform an XOR operation on the shifted data and the parallel polynomial to obtain the scrambled data and the new scrambled state data; a compensation unit, which modulo the number of scrambling state shift situations based on the number of bytes of invalid data to determine a shift compensation value, so as to reversely shift the new scrambling state data to obtain compensated scrambling state data; A shift recovery unit reversely shifts the scrambled data based on the recorded shifted byte amount to perform shift recovery.

9. The high bit width Ethernet GFP scrambling system as claimed in claim 8, characterized in that: The shift unit determines invalid data that does not need to be scrambled according to the sop and eop identifiers of the data packet.

10. The high bit width Ethernet GFP scrambling system according to claim 8, characterized in that: The invalid data that does not need to be scrambled includes bubble data and a core header of a gfp frame; When there are multiple gfp frames in one shot, the shift unit first shifts the bubble data at a low position, and then shifts the bubble data at a high position.

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