SerDes method and apparatus with protocol independent in-band management channel

Abstract

The invention relates to a SerDes method and device with a protocol independent in-band management channel. In-band communication methods and transceivers are provided to implement protocol-independent management channels. An illustrative in-band communication method includes buffering an outbound data stream from a host-side receiver with a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing an outbound data stream having additional words after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and free words, where adjacent message words are potentially separated by a predetermined number of free words.

Description

Technical Field

[0001] The present disclosure relates generally to serializer / deserializer transceivers and, more particularly, to transceivers that provide an in-band communication channel for exchanging management information. Background Art

[0002] The Institute of Electrical and Electronics Engineers (IEEE) Standards Association has published the IEEE standard for Ethernet, namely IEEE Standard 802.3-2015, which will be familiar to those of ordinary skill in the art to which this application belongs. The Ethernet standard provides a general media access control specification for local area network (LAN) operation at selected speeds from 1Mb / s to 100Gb / s through coaxial cables, twinaxial cables, twisted pair cables, fiber optic cables, and electrical backplanes, as well as various channel signal constellations. As the demand for higher and higher data rates continues, the standard is expanding. Even if the equalizer is forced to operate at a faster symbol rate, such extensions of the standard must account for increased channel attenuation and dispersion. With PAM4 or larger signal constellations over distances spanning more than a few meters, the proposed bit rate per channel rises to more than 50Gbps, and it becomes increasingly difficult to provide affordable mass-produced network hardware that ensures consistently robust performance.

[0003] For distance spans of no more than two meters, attenuation is reasonably limited, so that passive copper cables, also known as direct attach cables or "DACs", can generally be employed. Data centers with larger distance spans may need to rely on active optical cable (AOC) designs with data recovery and remodulation (DRR) chips in the cable connectors to convert electrical interface signals into optical signals for transmission over optical fibers, even though such cables typically have a higher cost. More sophisticated DRR chips also enable active Ethernet cable (AEC) designs to provide affordable, high-bandwidth data transmission over distance spans of up to at least seven meters using electrical conductors. The DRR devices in AOC and AEC designs typically exchange management information via a dedicated channel, such as a twisted pair between end connectors. (Examples of management information may include configuration information, status information, firmware updates, etc.) This dedicated channel may add undesirable material cost and volume to the active cable.

[0004] Like most integrated circuit devices, DRR chips have become so complex that it is impractical for electronic device designers to design integrated circuit devices from scratch. Instead, electronic device designers rely on predefined modular units of integrated circuit layout design, arranging and joining them as needed to achieve the various functions of the desired device. Each modular unit has a defined interface and behavior that has been verified by its creator. Although it may take a lot of time and investment to create each modular unit, the availability of modular unit reuse and further development greatly reduces product cycle time and achieves better products. Predefined units can be organized hierarchically, where a given unit contains one or more lower-level units and is in turn contained in a higher-level unit. Many organizations have such predefined modular unit libraries for sale or licensing, including, for example, embedded processors, memories, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, etc. Predefined modular units are also called cells, blocks, cores, and macros, which have different meanings and variations ("IP cores", "soft macros"), but are often used interchangeably.

[0005] Modular cells can be expressed in different ways, for example, in the form of a hardware description language (HDL) file, or as a fully routed design that can be printed directly onto a range of manufacturing process masks. Fully routed design files are typically process specific, which means that additional design work is often required to migrate modular cells to different processes or manufacturers. Modular cells in HDL form require subsequent synthesis, placement, and routing steps to implement, but they are process independent, which means that different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement the cells using a wide range of manufacturing processes. Due to their higher-level representation, HDL cells can be more amenable to modification and the use of variable design parameters, while fully routed cells can provide better predictability in terms of area requirements, reliability, and performance. Although there are no fixed rules, digital module designs are more commonly specified in HDL form, while analog and mixed-signal cells are more commonly specified as lower-level physical descriptions.

[0006] For device designs that employ modern data communications standards, which continue to evolve toward higher symbol rates and greater bit counts per channel symbol, a serializer-deserializer (SerDes) core is often required. At higher symbol rates, channel symbols become more attenuated and dispersed as they propagate, resulting in increasingly severe intersymbol interference (ISI) at the receiving end of the channel. When attempting to detect channel symbols, the receiver must cope with this ISI in addition to the channel noise that contaminates the received signal. There is at least one such SerDes core design that eliminates any need for dedicated conductors for management information. See, for example, U.S. Patent 10,212,260 "SerDes Architecture with Hidden Reverse Channel Protocol". However, it is protocol specific, limiting the versatility of the core. Summary of the invention

[0007] Therefore, an in-band communication method and transceiver implementing a protocol-independent management channel are disclosed herein. An illustrative in-band communication method includes: buffering an outbound data stream from a host-side receiver using a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream representing the outbound data stream having an additional word after every N words of the outbound data stream, the line-side data stream having a second bit rate derived from a fill level of the data stream buffer, the additional words including message words and idle words, wherein adjacent message words are separated by a predetermined number of idle words.

[0008] An illustrative in-band communication transceiver includes: a data stream buffer, insertion logic, and a line-side transmitter. The data stream buffer is configured to buffer an outbound data stream from a host-side receiver, the outbound data stream having a first bit rate. The insertion logic is configured to create a line-side data stream representing the outbound data stream by inserting an additional word after every N words of the outbound data stream, the additional words forming a sequence including message words and idle words, wherein adjacent message words are separated by a predetermined number of idle words, the predetermined number being greater than zero. The line-side transmitter is configured to transmit the line-side data stream at a second bit rate, the second bit rate being derived from a fill level of the data stream buffer.

[0009] The aforementioned method and transceiver may be embodied as a semiconductor IP core stored on a non-transitory information storage medium. When used by a properly configured computer, the semiconductor IP core provides a circuit and / or process mask design for manufacturing an integrated circuit device having the aforementioned transceiver component to implement the aforementioned communication method.

[0010] Each of the foregoing methods, transceivers, and core implementations may be embodied alone or in combination, and may be combined with any one or more of the following optional features: 1. A transmit buffer configured to store a group of message words, the group including a first message word. 2. A sequence of additional words including a message preamble separated from the first message word by a predetermined number of idle words. 3. The predetermined number of idle words is greater than one. 4. N is 10 4 or greater. 5. A line-side receiver configured to receive a line-side data stream representing an inbound data stream having additional words after every N words of the inbound data stream, the additional words comprising a receive message word and an idle word, wherein adjacent receive message words are separated by a predetermined number of idle words. 6. An extraction logic configured to store the receive message words in a receive buffer, and to store the inbound data stream in a data stream buffer. 7. A host-side transmitter, the host-side transmitter configured to transmit the inbound data stream without the additional words. 8. Each of the idle words in the line-side data stream representing the inbound data stream includes a status field indicating whether the remote transceiver is synchronized with the additional words. 9. Each of the idle words in the line-side data stream representing the outbound data stream includes a status field indicating whether the extraction logic is synchronized with the additional words. 10. The extraction logic configured to pause a write clock of the data stream buffer when storing the receive message words in the receive buffer. 11. The extraction logic configured to implement a finite state machine for implementing and maintaining synchronization with the additional words. 12. The insertion logic is configured to pause a read clock of the data stream buffer while inserting the additional words. 13. The insertion logic is configured to implement a finite state machine for transmitting packets of message words with a predetermined number of idle words between adjacent message words. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a perspective view of an illustrative active cable.

[0012] Figure 2 is a functional block diagram of an illustrative active cable.

[0013] Figure 3 is a functional block diagram of an illustrative communication channel.

[0014] Figure 4 is a flow chart of an illustrative finite state machine for message transmission.

[0015] Figure 5 is a flow chart of an illustrative finite state machine for receive lock detection.

[0016] Figure 6 is a flow chart of an illustrative finite state machine for message reception. DETAILED DESCRIPTION

[0017] Although specific embodiments are presented in the drawings and the following description, it should be kept in mind that they do not limit the present disclosure. Instead, they provide a basis for one of ordinary skill in the art to identify alternatives, equivalents, and modifications that are included within the scope of the appended claims.

[0018] Figure 1 It is a perspective view of an illustrative cable that can be used to provide a high-bandwidth communication link between devices in a routing network. The routing network can be, for example, the Internet, a wide area network, a storage area network, or a local area network or includes, for example, the Internet, a wide area network, a storage area network, or a local area network. The linked device can be a computer, a switch, a router, etc. The cable includes a first end connector 100 and a second end connector 101, which are electrically connected via an electrical conductor in a line 106 or optically coupled via an optical fiber in the line 106. The electrical conductor can be a conductive wire arranged in pairs, such as having a twinax conductor. The twinax conductor can be compared to a coaxial conductor, but has two inner conductors instead of one. The inner conductor can be driven using differential signals, and their shared shielding operation is used to reduce crosstalk with other twinax conductors in the cable. Depending on the performance criteria, it is also possible to adopt other paired or single-ended conductor implementations.

[0019] According to the Ethernet standard, each conductor pair can provide unidirectional transmission of differential signals. For optical cables, optical fibers can provide unidirectional transmission of optical signals. In order to achieve robust performance over more extended cable lengths, each end connector 100, 101 may include a powered transceiver that performs clock and data recovery (CDR) and remodulation of data streams, hereinafter referred to as data recovery and remodulation (DRR) devices. DRR devices process data streams traveling in each direction. Note that the transceiver not only performs CDR and remodulation of inbound data streams to the host interface when these inbound data streams leave the cable, but also performs CDR and remodulation of outbound data streams from the host interface when these outbound data streams enter the cable.

[0020] It is acknowledged that outbound data streams may be expected to comply with relevant standards (e.g., the 400 Gbps Ethernet standard) and may be expected to experience substantially no degradation as a result of their passage through the receptacle pins of the network interface port and the connector plug pins of the cable assembly. However, the modulation quality and equalization strategies employed by the electronics manufacturer of the transmitting network interface are generally unknown, and the minimum requirements of the standard may not be sufficient for transmission over extended cable lengths, particularly where the electronics manufacturer of the receiving network interface is different from the electronics manufacturer of the transmitting network interface. As with the transmitting network interface, the equalization and demodulation strategies employed by the electronics manufacturer of the receiving network interface are generally unknown and may not be able to cope with the attenuation and interference caused by signal transmission over extended cable lengths, particularly where the connectors are not fully seated or the contacts have lost their luster. By performing DRR on both inbound and outbound data streams, the illustrative cable ensures that the electrical signals carried by the cable conductors are able to withstand the attenuation and interference encountered between the end connectors of the cable, thereby ensuring consistently robust data transmission over extended cable lengths without regard to these factors.

[0021] Figure 2 yes Figure 1 Functional block diagram of an illustrative cable. End connector 100 includes a plug that is adapted to adapt to a standard-compliant Ethernet port in a first host device to receive an electrical input signal carrying an outbound data stream from the host device and provide an electrical output signal carrying an inbound data stream to the host device. Similarly, end connector 101 includes a plug that adapts to an Ethernet port of a second host device. End connector 100 includes a first DRR device 202 for performing CDR and remodulation on data streams entering and leaving the cable at end connector 100, and end connector 101 includes a second DRR device 204 for performing CDR and remodulation on data streams entering and leaving the cable at end connector 101. The DRR devices 202, 204 can each be an integrated circuit device mounted on a printed circuit board and connected to connector plug pins via circuit board traces.

[0022] In at least some contemplated embodiments, the printed circuit boards also each support a microcontroller unit (MCU) 206. Each DRR device 202, 204 is coupled to a corresponding MCU device 206 that configures the operation of the DRR device via a first two-wire bus. At power-on, the MCU device 206 loads equalization parameters from a flash memory 207 into a configuration register 208 of the DRR device. The host device can access the MCU device 206 via a second two-wire bus that operates according to the I2C bus protocol and / or the faster MDIO protocol. With this access to the MCU device 206, the host device can adjust the operating parameters of the cable and monitor the performance of the cable.

[0023] Each DRR device 202, 204 includes a set 220 of host-side transmitters and receivers ("transceivers") for communicating with a host device and a set 222 of line-side transmitters and receivers for transmitting and receiving via conductor pairs or optical fibers along the length of line 106. The DRR devices of the illustrated cable are each coupled to a set 226 of photoelectric emitters (PE) and photodetectors (PD) for converting between electrical signals of the DRR devices and optical signals transmitted through the optical fibers. For ease of illustration, only one communication channel is shown, but in practice, the cable may use multiple communication channels on corresponding differential conductor pairs or optical fibers, or multiple multiplexed channels on a single conductor pair or optical fiber to support higher communication bandwidths. The DRR device may include a memory 224 for providing a first-in, first-out (FIFO) buffer between the transceiver sets 220, 222. The embedded controller 228 coordinates the operation of the transmitter and receiver by, for example, setting initial equalization parameters and ensuring that a training phase is completed across all channels and links before enabling the transmitter and receiver to enter the data transmission phase. Embedded controller 228 employs set of registers 208 to receive commands and parameter values ​​and to provide responses that potentially include status information and performance data.

[0024] As previously mentioned, messages need to be exchanged between the two end connectors 100, 101. In-band messaging techniques provide a way to avoid the added bulk and cost that would be associated with a dedicated channel for management information. An in-band messaging technique that is independent of the data stream communication protocol is disclosed herein. In this technique, line-side signaling uses a slightly higher symbol rate than host-side signaling. As further described below, the increase in baud rate is not expected to exceed about 10 parts per million (ppm), which should be well within the channel tolerance.

[0025] Figure 3 An illustrative communication channel from a local transmitter 362 to a remote receiver 364 is shown to illustrate the in-band messaging technique. For ease of illustration, only one direction is shown. In practice, a second identical channel from a remote transmitter to a local receiver would be provided for communication in the opposite direction.

[0026] In the local transmitter, the host side receiver 302 (from Figure 2The transceiver set 220 of the receiver receives the outbound analog signal 300. Based on the analog signal 300 and / or the symbol decision margin of the receiver, the clock recovery module 304 derives a sampling clock signal for recovering the outbound data stream from the outbound analog signal 300. A first-in-first-out (FIFO) buffer 306 provides temporary storage of the outbound data stream until the recovered portion can be retransmitted by the line-side transmitter 312. The FIFO buffer 306 provides fill level information 308 to a timing regeneration filter (TRF) block 310, which derives a phase offset signal from the fill level information 308. The line-side transmitter 312 includes a clock generator that generates a transmit clock signal based on the phase offset signal. The frequency of the transmit clock signal is adaptively adjusted based on the phase offset signal from the TRF block 310 to maintain a relatively stable fill level of the FIFO buffer 306.

[0027] Modulo-M divider 314 converts the transmit clock signal to a word clock signal for insertion logic 315, where M is the number of channel symbols that can be retrieved in parallel from FIFO buffer 306. Note that channel symbols can be 1-bit symbols (e.g., bipolar modulation), 2-bit symbols (e.g., quadrature amplitude modulation), or higher. Typical values ​​of M include 32, 64, and 128. Divider 314 enables message insertion logic 315 to operate at a lower clock frequency.

[0028] The message insertion logic 315 includes a clock demultiplexer 316, an outbound message buffer 318, a modulo-N divider or counter 320, a data multiplexer 322, and an embedded controller 324. The clock demultiplexer 316 directs the word clock to the FIFO buffer 306 or (when enabled by the embedded controller 324) the message buffer 318 to read the data word or message word, respectively. In addition to the message word, or in the absence of a message, the insertion logic 315 can control the data multiplexer to periodically select an idle mode from the idle logic 319. The counter 320 asserts the message transceiver interval clock signal once for every N pulses of the word clock signal. Illustrative values ​​of N include 10 4 , 10 5 , 10 6 , 10 7 , 2 14 , 2 15 , 2 16 , 2 17 , 2 18 , 2 19 , 2 20Other values ​​will also be suitable. Lower values ​​will shorten the message interval, reducing latency, but will increase the message bandwidth and potentially increase the transmit clock frequency to the point where the performance of the communication channel begins to degrade. Higher values ​​will lengthen the message interval, increase latency, and reduce the message bandwidth, but will minimize any impact on performance. A net message rate of about 1 kilobaud is expected to be sufficient, allowing N to potentially be set as high as 10 in a four-lane 100Gbd cable. 5 Higher messaging rates are also contemplated, limited only by the ability of the TRF block 310 to limit the timing jitter potentially caused by the intermittent insertion of additional messages and idle words.

[0029] When the message interval clock is deasserted, the demultiplexer 316 directs the word clock signal as a read clock signal to the FIFO buffer 306, and the data multiplexer 322 forwards the word from the outbound data stream to the line side transmitter 312. When the message interval clock signal is asserted, the demultiplexer 316 directs the word clock signal as a read clock to the message buffer 318 (when the buffer 318 is enabled by the controller 324), and the data multiplexer 322 forwards the message word to the line side transmitter 312 as an additional word to be inserted into the retransmitted outbound data stream. As discussed further below, the controller 324 may alternatively use the multiplexer 322 to insert an idle pattern as an additional word to be inserted into the line side outbound data stream. The embedded controller 324 operates in response to the message interval clock to control the outbound message buffer content, monitor the local inbound message buffer content (described further below), and insert the idle pattern and preamble according to the messaging protocol.

[0030] The retransmitted outbound data stream is transmitted as analog signal 300 over the cable to the remote receiver 364. At the remote receiver 364, the line side receiver 332, with the help of clock recovery module 334, converts the analog signal into a digital sequence representing the outbound data stream, which includes the additional symbols provided by the insertion logic 315. (Hereinafter, the term "additional" symbols will be used with reference to the insertion logic, while these symbols will be referred to as "extra" symbols when referring to the extraction logic 353.) The clock recovery module 334 derives a sampling clock signal for the line side receiver 332 from the analog signal 330 and / or the symbol decision margin of the receiver. The modulo-M divider 336 converts the sampling clock signal into a word clock signal for the extraction logic 338.

[0031] The extraction logic 338 includes a clock demultiplexer 350, a receive message buffer 352, a scan logic 353, an interval counter 354, a data demultiplexer 356, and an embedded controller 358. The clock demultiplexer 350 directs the word clock signal to the FIFO buffer 340 or the receive message buffer 352, this time as a write clock signal. The interval counter 354 converts the word clock signal to a message transceiver interval clock signal for the clock demultiplexer 350, the data demultiplexer 356, and the controller 358. When the message transceiver interval clock signal is deasserted, the clock demultiplexer 350 and the data demultiplexer 356 direct the word clock signal and the word of the outbound data stream to the FIFO buffer 340, respectively. When the message transceiver interval clock signal is asserted, the clock demultiplexer 350 and the data demultiplexer 356 may direct the word clock signal and the current data word to the message buffer 352, respectively, thereby extracting the message word from the outbound data stream. When the additional words are expected to be an idle pattern or a preamble pattern, the controller 358 disables the receive message buffer and these additional words are not stored in the FIFO buffer or the receive message buffer. The scan logic 353 may be used to scan the periodic idle pattern initially to achieve synchronization, and thereafter may be used to maintain synchronization and monitor the synchronization ("lock") status of the transceiver at the other end of the cable. The controller 358 implements a finite state machine to control the scan logic 353, store the contents in the remote receive message buffer 352, and control the idle logic at the local end of the cable to provide idle patterns, synchronization status, and message preamble patterns according to the protocol outlined below.

[0032] The remote receiver 364 further includes a TRF block 344, which derives a phase offset signal for a clock generator of a host-side transmitter based on the fill level of the FIFO buffer 340. The host-side transmitter 346 generates a transmit clock with a frequency that is adaptively adjusted as needed to maintain a relatively stable fill level. The host-side transmitter 346 converts the outbound data stream into an analog signal 348, which transmits the outbound data stream to the host. The insertion logic 315 and the extraction logic 338 can be independent of any communication protocol being implemented by the host-side and line-side transmitters and receivers, so that the IP core of the logic can be easily adapted for use with different SerDes modules. With this design, the host side of the DRR device can continue to operate at a standard clock frequency to support error-free traffic at the established line rate, while the line side operates at a slightly higher clock frequency to enable message transceiving.

[0033] The embedded controller 324 for the local transmitter of the insertion logic 315 can also be used as the embedded controller for the extraction logic of the local receiver, using the idle logic 319 and the local scan logic to implement the messaging protocol described below. Similarly, the embedded controller 358 of the remote receiver can also be used as the embedded controller for the insertion logic of the remote transmitter, using the idle and scan logic at the remote end of the cable to implement the messaging protocol in cooperation with the local end of the cable. Each embedded controller can implement Figure 4 (Message transmission), Figure 5 (Receive Lock Detect) and Figure 6 (Message Received) finite state machine. Each of the transitions in the finite state machine is provided with a 3-digit label (e.g., 410), where the rightmost digit indicates the originating state, the middle digit indicates the destination state, and the leftmost digit indicates the figure number. Thus, Figure 4 The example 410 in FIG. 4 occurs between the initial zero state (INIT) and the first state (NO_LOCK). All state transitions except to and from the initial state occur in modulo-N counting (ie, according to the interval clock signal).

[0034] Figure 4 An illustrative finite state machine for message transmission is shown, which has six states: an initial (INIT) state, a "no lock" (NO_LOCK) state, a "local lock" (LLOCK) state, an idle (IDLE) state, a space (SPACE) state, and a message word (WORD) state. The initial state represents the situation where the insertion logic 315 is disabled, whether due to an error, a reset, or the de-assertion of the enable signal (i.e., when the in-band messaging channel is disabled). The no lock state represents the situation where the insertion logic 315 has been enabled but the local extraction logic has not yet been synchronized to the message transceiving interval clock of the remote end. The local lock state represents the situation where the local extraction logic has been synchronized to the interval clock of the remote end, but the remote extraction logic has not yet been synchronized to the message transceiving interval clock of the local insertion logic. The idle state represents the situation where interval clock synchronization has been achieved in both directions, but there are no pending messages in the local transmit message buffer. The space state represents the intra-packet interval between message words. The message word state represents the transmission of the next message word.

[0035] The initial state is a state that can be reached via transitions 400-405. Each of these transitions can be triggered when the finite state machine is in the associated origination state of the transition and the enable signal is deasserted and / or the reset signal is asserted. Transitions 404-405 can additionally be triggered if the controller asserts a transmit error signal when the finite state machine is in the space state or the message word state, the transmit error signal indicating that an error has been encountered before completing the transmission of the complete message.

[0036] The unlocked state can be reached via conversion 410-415. When the controller's firmware sets the assertion enable signal, conversion 410 occurs. While converting, the controller selects idle logic to pass the default "idle" mode with a status field, which indicates that the local extraction logic has not yet achieved locking, that is, it has not yet synchronized with the message transceiver interval clock of the far end. As long as the local extraction logic remains asynchronous with the remote interval clock, conversion 411 will be repeated after every N outbound data stream words, retaining the unlocked state and maintaining the inserted additional word in an idle mode with an "unlocked" status field. If the local extraction logic determines later that synchronization with the remote interval clock has been lost, conversions 412-413 are triggered, and the additional word is set to the default idle mode and status field as before. Conversions 414, 415 are similarly triggered, but in addition to setting the additional word to an idle mode with an "unlocked" state, the controller also sets the message sending state to false and sets the transmission error state to true.

[0037] The local locked state can be reached via transitions 421-425. Transition 421 occurs when the local extraction logic is synchronized with the remote interval clock ("local lock"), and the controller updates the status field accompanying the default idle mode to indicate that local lock has been achieved ("lock status field"). This setting of the additional word is also used for transitions 421-425. Transition 422 is repeated after every N data stream words until the local extraction logic determines that the status field from the remote transceiver indicates that it has synchronized with the local interval clock ("remote lock"). If the status field from the remote transceiver indicates that it has lost synchronization with the local interval clock, transitions 423-425 occur. For transitions 424, 425 (these transitions occur if remote lock is lost during message transmission), the controller sets the message send status to false and sets the transmission error status to true.

[0038] The idle state can be reached via transitions 432, 433, 435. Transition 432 occurs when the local extraction logic confirms that both local lock and remote lock have been achieved. The additional word is set to an idle mode with a lock status field. As long as the transmit message ready flag remains deasserted, the controller will remain in the idle state using transition 433. Transition 435 occurs after the previous message has been successfully transmitted, that is, when the controller determines that the message word counter matches the predetermined message length and selects the last content of the transmit message buffer as the additional word to be inserted. The controller sets the message send status to true and sets the transmit error status to false.

[0039] The space state can be reached via transitions 443-445. Transition 443 occurs when both the local locked and remote locked states are true while the transmit message ready flag is asserted. The controller sets the message send state to false, the error state to false, the idle counter to zero, the message counter to zero, and the message data to the message preamble mode. Assuming that the local locked and remote locked states remain true, the controller uses transition 444 to remain in the space state as long as the idle counter is less than the predetermined intra-message idle count. During each traversal of transition 444, the controller sets the additional word to idle mode with the lock state field and increments the idle counter. Transition 445 occurs when the controller selects the next unsent content of the transmit message buffer as the additional word and increments the message word counter.

[0040] The message word state can only be reached via transition 454, which occurs when the idle counter reaches a predetermined in-message idle count (assuming the local locked and remote locked states remain true). The controller selects the idle pattern with the locked state field as the additional word and resets the idle counter.

[0041] In summary, the controller uses a finite state machine to ensure that both local locking and remote locking are achieved before entering the idle state. Once entering the idle state, the controller waits for the message data to be transmitted, and then uses the preamble to start the transmission process. Between the preamble and the first message word and between each pair of message words, the controller provides one or more spaces filled with idle mode to facilitate maintaining locking during message transmission. The number of spaces can range from 1 to 3 or more. If both locks are maintained, the controller returns to the idle state after the last word of the message is transmitted, thereby setting the message transmission bit. If synchronization is lost, the controller switches to an unlocked or local locked state until synchronization is restored, thereby setting the transmission error bit. In at least some conceived embodiments, the message buffer saves 32 word packets. The message word may be shorter than the channel word, for example, the message word may be 32 bits, while the channel word is 128 bits. In this case, the idle mode and lock state fields can be used to fill the message word. Each message word packet can include a payload and a checksum, and a message preamble is added in front.

[0042] Figure 5An illustrative finite state machine for use by extraction logic to receive lock detection is shown, the machine having eight states: an initial lock (INIT_LK) state, a seek lock (SEEK) state, a tentative lock (TENT) state, a found lock (FOUND) state, a remote lock (REM_LK) state, an idle lock (IDLE_LK) state, a space lock (SP_LK) state, and a message lock (MSG_LK) state. All transitions except the transitions to INIT and SEEK are in modulo-N counting. The initial lock state represents a situation where the extraction logic is disabled due to a reset or due to the de-assertion of an enable signal. The seek lock state represents a situation where the firmware is set to enable the extraction logic by the assertion of the enable signal, but the controller has not yet found an instance of an idle pattern in the data stream. The tentative lock state represents a situation where the logic has found an instance of an idle pattern and is verifying whether the idle pattern repeats at an expected interval. The found lock state represents a situation where the logic has verified that a predetermined number of idle patterns repeat at an expected interval and is waiting for the remote transceiver to achieve lock. The Remote Locked state represents the condition where at least one remote lock indication has been received and the logic is verifying that the remote lock indication is maintained for a predetermined number of repetitions. The Idle Locked state represents the condition where the logic has verified the required number of local and remote lock indications and a new message preamble has not been detected. The Space Locked state represents the condition where spaces within a message are expected, whether due to detection of a new message preamble or a new message word. The Message Locked state represents the condition where a message word is expected.

[0043] The initial lock state can be reached via transitions 500-507, each of which occurs when the reset signal is asserted or the enable signal is deasserted. For each of these transitions, the logic sets the idle lock signal (used by the finite state machine for message reception) to false.

[0044] During SEEK, the locking logic scans the data stream for a match to the default idle pattern. As it scans, the logic keeps track of the position of the first bit in the sequence. If the idle pattern is not detected within a message interval, the logic adjusts the position of the first bit as it scans the next message interval for the default idle pattern. Once the default idle pattern is detected, the modulo-N counter is reset to mark the location of the extra word in the data stream and pauses the data stream buffer write clock or otherwise discards the extra word from the data stream.

[0045] The seek lock state may be reached via transitions 510-512. Transition 510 occurs when the enable signal is asserted. Transitions 511 and 521 occur when a word sample from the data stream fails to match the idle pattern, causing the logic to set the local idle lock and remote idle lock bits to zero.

[0046] The tentative lock state can be reached via conversion 521-526, each of which causes the logic to set the local idle lock and remote idle lock bits to zero. When a word sample from the data stream matches the idle pattern, conversion 521 occurs, and the logic sets the local lock counter to zero. When a subsequent word sample from the data stream that is in the expected interval matches the idle pattern but has not yet reached the minimum idle count, conversion 522 occurs, causing the logic to increment the local lock counter. When a subsequent word sample in the interval count unexpectedly fails to match the idle pattern, conversions 523 and 524 occur, and when this occurs, the logic resets the local lock counter. When the local lock history count falls below the threshold, conversions 525 and 526 occur, and if this occurs, the local lock counter is reset again.

[0047] Finding the locked state can be achieved via transitions 532-534. In each case, the logic sets the local idle locked signal to true and the remote idle locked signal to false. When an expected idle pattern is detected, transition 532 occurs so that the local lock counter reaches the predetermined target, but the status field accompanying the idle pattern does not indicate that a remote lock is achieved. The logic sets the local lock history count to one. When an expected idle pattern with a no lock status field is detected, transitions 533 and 534 occur so that the logic increments the local lock history count. When the local lock history count is incremented, the logic can tolerate single-bit errors in the idle pattern match test.

[0048] The remote locked state can be reached via transitions 542-545. In each case, the logic sets the local idle locked and remote idle locked signals to true. When an expected idle mode is detected, transition 542 occurs, causing the local lock counter to reach a predetermined target and the status field accompanying the idle mode indicates that a remote lock is achieved. The logic sets the remote lock counter to zero, sets the local lock history count to one, and sets the remote lock history count to zero. When an expected idle mode with a lock status field is detected, transition 543 occurs, causing the logic to update the local lock history count and set the remote lock history count to zero and set the remote lock counter to zero. When an expected idle mode with a lock status field is detected and the remote lock counter has not yet reached the minimum target value, transition 544 occurs. The logic increments the remote lock counter and updates the remote lock history count. As with the local lock history count, the controller can tolerate single-bit errors in the idle mode when determining whether to increment the remote lock history count. Transition 545 occurs when the local lock history count remains above the local lock threshold but the remote lock history count falls below the remote lock threshold. The logic updates the local lock history count but resets the remote lock history count.

[0049] The idle locked state can be reached via transitions 554, 555, 557. For each of these transitions, the local idle locked signal is set to one and the remote idle locked is set to one. Transition 554 occurs when the logic detects an expected idle pattern with a locked state field and the remote lock counter reaches a minimum target value. The local lock history count is updated and the remote lock history count is set to one. If the receive message buffer has not been read or the message slot has not saved a message preamble, transition 555 occurs, assuming that the local lock history count and the remote lock history count remain above the local lock threshold and the remote lock threshold, respectively. The logic updates the local lock history count and the remote lock history count. Transition 557 occurs when the message counter hits a predetermined message length.

[0050] The spatial locked state may be reached via transitions 565-567. Transition 565 occurs when the message buffer has been read and a new message preamble is received. The intra-message idle counter is set to zero. Transition 566 occurs when the intra-message idle counter is less than a preset value and the local lock history count remains above the local lock threshold. The logic increments the intra-message idle counter and updates the local lock history count. Transition 567 occurs when the message word counter has not yet reached a predetermined message length.

[0051] The message locked state can only be reached via transition 576, which occurs when the in-message idle counter hits a preset value. The logic resets the in-message counter value and updates the local lock history count.

[0052] In summary, the controller uses a finite state machine to acquire and maintain indicators for both local lock and remote lock by seeking and verifying the occurrence of idle patterns and status fields at expected intervals. During the seek state, the logic scans the data stream to find a match with a predetermined idle pattern, and in the tentative state, the logic verifies that the logic pattern repeats at the expected interval before setting the local lock indicator. In the found state, the logic checks the status field of the additional word to verify that the lock status field occurs at least a predetermined number of times before setting the remote lock indicator. In the idle state, the logic maintains a history of detected idle patterns and only reverts to an earlier state when the history falls below a predetermined threshold. The threshold is less than the minimum target value, providing hysteresis for both the local and remote lock indicators. In the space locked and message word locked states, the logic relies on the space within the message to maintain the lock indicator during message reception. The status field of the space word within the message can be ignored to avoid inadvertent truncation of the message payload.

[0053] Figure 6An illustrative finite state machine for message reception is shown, having five states: an initial (INIT) state, a no lock (NO_LOCK) state, an idle (IDLE) state, a space (SPACE) state, and a message word (WORD) state. The initial state represents the case where the extraction logic is disabled, either due to a reset or de-assertion of the enable signal. The no lock state represents the case where the logic has been enabled but the lock detection logic has not yet asserted the idle lock signal. The idle state represents the case where the idle signal is asserted and the extraction logic is waiting for a message preamble or waiting for the receive message buffer to be read. The space state represents the case where the logic expects space within a message, and the message word state represents the case where the logic expects a message word.

[0054] The initial state is a state that can be reached via transitions 600-602, 604. Each of these transitions may be triggered when the finite state machine is in the corresponding initial state and the enable signal is deasserted and / or the reset signal is asserted.

[0055] The unlocked state may be reached via transitions 610 - 614. Each of these transitions may be triggered from the corresponding origination state if the detection logic deasserts the idle lock signal.

[0056] The idle state may be reached via transitions 621, 622, 624. Transition 621 occurs when the idle lock signal is asserted. Transition 622 occurs as long as an unread message resides in the receive message buffer or as long as no new message preamble is received. Transition 624 occurs when the message word counter reaches a predetermined message length. The message ready signal is asserted and the message word counter is incremented.

[0057] The space state can be reached via transitions 632-634. Assuming the idle lock signal remains asserted and there are no unread messages in the receive message buffer, transition 632 occurs when a new message preamble is received. When a preamble is detected, the logic can accommodate single-bit errors. The in-message space counter and the message word counter are reset to zero. Transition 633 occurs as long as the in-message space counter remains less than the expected number of in-message spaces and the in-message space counter is incremented. Transition 634 occurs after each message word as long as the message word counter is less than the predetermined message length. The controller stores the message word in the receive buffer and increments the message word counter.

[0058] The message word state can only be reached via transition 643 and this transition occurs when the in-message space counter reaches the expected amount of in-message space. The in-message space counter is set to zero.

[0059] In summary, the controller uses the finite state machine to monitor the extra words of the message preamble and thereafter stores a predetermined number of message words as message packets in the receive buffer. The controller then sets the message ready signal to indicate that the message packets can be read from the receive buffer. The space state is used to discard the intra-message space from the data stream.

[0060] In some contemplated implementations, each message packet consists of 2 10 bits, which can be sent as 32 words (32 bits per word). Each packet can optionally include a checksum field, and the controller can be configured to implement a packet numbering scheme and / or other suitable error detection and correction techniques to ensure reliable operation. As an example, the format of the message block can be similar to the format described in clause 82.2 of the IEEE 802.3 standard for 100G Base-R PCS, supporting the 66b block lock synchronization technique described in clause 82.2.12. The transceiver can further implement an acknowledgment or non-acknowledgment protocol to ensure that damaged message packets are retransmitted.

[0061] The default idle mode may preferably be selected to avoid any special protocol modes that the standard communication protocol may use, so as to avoid unduly impairing the operation of the standard communication protocol before synchronization is achieved or when synchronization is lost.

[0062] Once the above disclosure is fully understood, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, a 1:1 cable is used in the foregoing description, but the principles disclosed below also apply to other applications of optical modules, stand-alone transceivers, branch cables, and SerDes devices. The transceiver may also provide bit multiplexing to convert between a first number of channels on the host side and a second number of channels on the line side. Although it is advantageous to determine the line side clock frequency based on the fill level, this is not necessary because the line side clock frequency can be determined by other means, such as using bit filling to compensate for insufficient buffer filling. It is intended that the claims be interpreted as covering all such alternatives, equivalents, and modifications that are included within the scope of the appended claims.

Claims

1. An in-band communication method, the in-band communication method comprising in a local transceiver: buffering an outbound data stream from a host-side receiver using a data stream buffer, the outbound data stream having a first bit rate; and providing a line-side data stream having a second bit rate greater than the first bit rate, the line-side data stream representing the outbound data stream having an additional word after every N words of the outbound data stream, The additional words include message words.

2. The in-band communication method according to claim 1, wherein: The second bit rate is derived from a fill level of the data stream buffer.

3. The in-band communication method according to claim 1, wherein: The additional words further include a predetermined number of idle words separating adjacent message words, the predetermined number being greater than zero.

4. The in-band communication method according to claim 3, wherein: The idle word includes synchronization information.

5. The in-band communication method according to claim 3, further comprising: storing a group of message words in a transmit buffer, the group including a first message word, The additional word comprises a message preamble separated from the first message word by the predetermined number of idle words.

6. The in-band communication method according to claim 3, wherein: The predetermined number of free words is greater than one.

7. The in-band communication method according to claim 3, wherein: N is 10 4 or larger.

8. The in-band communication method of claim 3, further comprising, in the local transceiver: receiving a line-side data stream representing an inbound data stream having additional words after every N words of the inbound data stream, the additional words comprising receive message words and idle words, wherein adjacent receive message words are separated by the predetermined number of idle words; storing the received message word in a receive buffer; as well as A host-side data stream representing the inbound data stream without the additional words is provided to a host-side transmitter.

9. The in-band communication method according to claim 8, wherein: Each of the idle words in the line-side data stream representing the inbound data stream includes a status field indicating whether a remote transceiver is synchronized with the additional word, and wherein each of the idle words in the line-side data stream representing the outbound data stream includes a status field indicating whether the local transceiver is synchronized with the additional word.

10. The in-band communication method according to claim 9, further comprising: Synchronization with the extra words is established using a finite state machine by scanning the line side data stream for an idle word that occurs after every N words of the inbound data stream.

11. An in-band communication transceiver, comprising: a data stream buffer configured to buffer an outbound data stream from a host-side receiver, the outbound data stream having a first bit rate; insertion logic configured to create a line-side data stream representing the outbound data stream by inserting additional words after every N words of the outbound data stream, the additional words forming a sequence including message words and idle words, wherein adjacent message words are separated by a predetermined number of idle words, the predetermined number being greater than zero; as well as A line-side transmitter is configured to transmit the line-side data stream at a second bit rate, the second bit rate being derived from a fill level of the data stream buffer.

12. The in-band communication transceiver of claim 11, further comprising: a transmit buffer configured to store a group of message words, the group comprising a first message word, The sequence of additional words includes a message preamble separated from the first message word by the predetermined number of idle words.

13. The in-band communication transceiver of claim 11, wherein: The predetermined number of free words is greater than one.

14. The in-band communication transceiver of claim 11, wherein: N is 10 4 or larger.

15. The in-band communication transceiver of claim 11, further comprising: a line side receiver configured to receive a line side data stream representing an inbound data stream having additional words after every N words of the inbound data stream, the additional words comprising received message words and idle words, wherein adjacent received message words are separated by the predetermined number of idle words; extraction logic configured to store the received message word in a receive buffer and to store the inbound data stream in the data stream buffer; as well as A host-side transmitter is configured to transmit the inbound data stream without the additional words.

16. The in-band communication transceiver of claim 15, wherein: Each of the idle words in the line-side data stream representing the inbound data stream includes a status field indicating whether a remote transceiver is synchronized with the additional word, and wherein each of the idle words in the line-side data stream representing the outbound data stream includes a status field indicating whether the extraction logic is synchronized with the additional word.

17. The in-band communication transceiver of claim 16, wherein: The extraction logic is configured to pause a write clock of the data stream buffer while storing a received message word in the receive buffer.

18. The in-band communication transceiver of claim 16, wherein: The extraction logic is configured to implement a finite state machine for implementing and maintaining synchronization with the additional word.

19. The in-band communication transceiver of claim 11, wherein: The insertion logic is configured to pause a read clock of the data stream buffer while inserting the additional word.

20. The in-band communication transceiver of claim 11, wherein: The insertion logic is configured to implement a finite state machine for transmitting a grouping of message words with the predetermined number of idle words between adjacent message words.

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