Master-slave data transmission method, system and device and storage medium

Abstract

The invention discloses a master-slave data transmission method, system and device and a storage medium. The method comprises the following steps: acquiring a first aggregation frame constructed by a host according to an idle buffer area; the first aggregation frame comprises an aggregation frame header; analyzing and verifying an aggregation frame header according to the first aggregation frame, and determining a second aggregation frame; the second aggregation frame comprises a plurality of subframes; the plurality of subframes are subframes with different serial numbers; and carrying the plurality of subframes to the idle buffer area. According to the method, the aggregation frame can be constructed according to the idle buffer area, the aggregation frame with a plurality of subframes with different serial numbers is determined according to the aggregation frame, and the aggregation frame with a plurality of subframes with different serial numbers is carried to the idle buffer area to complete transmission of the master machine and the slave machine. The repeated frames are prevented from being carried to a buffer area, and the data transmission speed can be increased. The method can be widely applied to the technical field of data transmission.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a master-slave data transmission method, system, device and storage medium. Background Art

[0002] As a secure digital transmission interface specification, the SDIO protocol is widely used in products such as GPS cameras, Wi-Fi chips, and card readers. However, as digital products have higher and higher requirements for data transmission throughput, the existing data transmission methods are difficult to meet the needs. Therefore, a new master-slave data transmission method is urgently needed. Summary of the invention

[0003] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present application is to provide a master-slave data transmission method, system, device and storage medium, which can increase the speed of data transmission.

[0005] In order to achieve the above-mentioned technical objectives, the technical solution adopted in the embodiment of the present application includes: obtaining a first aggregate frame constructed by the host according to an idle buffer; the first aggregate frame includes an aggregate frame header; according to the first aggregate frame, parsing and verifying the aggregate frame header to determine the second aggregate frame; the second aggregate frame is the second aggregate frame including a plurality of subframes; the plurality of subframes are subframes with different sequence numbers; and moving the plurality of subframes to the idle buffer.

[0006] In addition, the master-slave data transmission method according to the above embodiment of the present invention may also have the following additional technical features:

[0007] Furthermore, in an embodiment of the present application, the master-slave data transmission method also includes: reading out the several subframes from the to-be-read buffer, wherein reading out the several subframes from the idle buffer includes: hanging the several subframes in a descriptor table, the descriptor table being used to characterize the address and length information of each to-be-read buffer; receiving a slave read start signal sent by the host, updating the address and length information of the to-be-read buffer into a register, and moving the corresponding several subframe data to the FIFO of the master-slave interface, so that the host deaggregates the several subframes and sends the deaggregated subframes to the upper-layer network protocol or forwards them through the MAC driver until a read end interrupt is triggered; according to the end of the read interrupt, reading the descriptor table from the register.

[0008] Furthermore, in an embodiment of the present application, the transmission method further includes: determining that the number of subframes continuously transported exceeds a preset number or all aggregated subframes are transported, and generating an interrupt to notify the CPU.

[0009] Furthermore, in an embodiment of the present application, the step of obtaining the first aggregate frame constructed by the host based on the free buffer also includes: constructing the first aggregate frame; wherein the host constructs the first aggregate frame based on the free buffer, including querying the number of free buffers of the slave; and copying the aggregatable frame data to a continuous memory according to the number of free buffers to obtain the first aggregate frame, and the first aggregate frame includes an aggregate frame header.

[0010] Further, in the embodiment of the present application, the step of parsing and verifying the aggregate frame header according to the first aggregate frame to determine the second aggregate frame specifically includes:

[0011] Parsing the frame header information of the first aggregated frame to obtain the first frame sequence number, the length of each subframe, and the aggregated frame header checksum of the first aggregated frame;

[0012] Determine an aggregate frame in which the first frame sequence number, the length of each subframe, and the aggregate frame header checksum are all the same as preset values ​​as a second aggregate frame.

[0013] On the other hand, an embodiment of the present application also provides a master-slave data transmission system for executing the master-slave data transmission method described in any of the above embodiments, including a host, a slave and a HIF controller; the host is connected to the HIF controller; the slave is connected to the HIF controller.

[0014] On the other hand, an embodiment of the present application also provides another master-slave data transmission system, including: an acquisition unit, used for the host to construct a first aggregate frame based on an idle buffer; a first processing unit, used to parse and verify the aggregate frame header based on the first aggregate frame, and determine a second aggregate frame; a second processing unit, used to move the several subframes to the idle buffer.

[0015] Furthermore, in an embodiment of the present application, the system also includes a reading unit, and the reading unit is used to read the plurality of subframes from the to-be-read buffer.

[0016] On the other hand, the present application also provides a master-slave data transmission device, comprising:

[0017] at least one processor;

[0018] at least one memory for storing at least one program;

[0019] When the at least one program is executed by the at least one processor, the at least one processor implements a master-slave data transmission method as described in any one of the invention contents.

[0020] In addition, the present application also provides a storage medium, in which processor-executable instructions are stored. When the processor-executable instructions are executed by the processor, they are used to execute a master-slave data transmission method as described in any one of the above items.

[0021] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0022] The present application can construct an aggregate frame based on an idle buffer, determine an aggregate frame having multiple subframes with different sequence numbers based on the aggregate frame, and move the aggregate frame having multiple subframes with different sequence numbers to the idle buffer to complete the transmission between the master and the slave. The present application can improve the speed of data transmission by avoiding moving duplicate frames to the buffer by using subframes with different sequence numbers. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of SDIO CMD53 transmission in the prior art;

[0024] Figure 2 A schematic diagram of the steps of a master-slave data transmission method in a specific embodiment of the present invention;

[0025] Figure 3 Write a block diagram of the aggregation principle for a specific embodiment of the present invention;

[0026] Figure 4 Write a polymerization flow chart for a specific embodiment of the present invention;

[0027] Figure 5 A schematic diagram of the read aggregation principle in a specific embodiment of the present invention;

[0028] Figure 6 A schematic diagram of a slave descriptor table in a specific embodiment of the present invention;

[0029] Figure 7 This is a diagram of the master-slave interaction interface of the RX path HIF controller in a specific embodiment of the present invention;

[0030] Figure 8 This is a software flow chart of the RX path slave in a specific embodiment of the present invention;

[0031] Fig. 9 This is a flow chart of a RX path HIF controller in a specific embodiment of the present invention;

[0032] Fig.10 This is a software flow chart of the RX path host side in a specific embodiment of the present invention;

[0033] Fig.11 It is a software flow chart of the host side under the piggy back mechanism in a specific embodiment of the present invention;

[0034] Fig.12 It is a structural schematic diagram of a master-slave data transmission system in a specific embodiment of the present invention;

[0035] Fig.13 It is a structural schematic diagram of another master-slave data transmission system in a specific embodiment of the present invention;

[0036] Fig.14 It is a structural schematic diagram of a master-slave data transmission device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0037] The embodiments of the present invention are described in detail below with reference to the accompanying drawings to illustrate the principles and processes of the master-slave data transmission method, system, device and storage medium in the embodiments of the present invention.

[0038] First, combine Figure 1 Explain the defects of existing technology

[0039] The defects of SDIO transmission in the prior art mainly include:

[0040] 1) SDIO transmission efficiency is limited by the host CPU scheduling, and each data transmission time includes a CMD53 command protocol overhead. Figure 1 The SDIO CMD53 transmission diagram shows that each SDIO CMD53 data transmission includes CMD53 command sending, R5 (CMD53 Response), and actual data transmission. The time from CMD53 issuance to the completion of all data transmission is relatively stable in accordance with the SDIO protocol, and the interval between two CMD53 is controlled by the host CPU scheduling.

[0041] 2) It does not support aggregate read and write operations. If multiple data need to be read and written separately, and each read and write has the overhead of the SDIO protocol (such as the interaction between CMD53 and R5), the overall efficiency is not high.

[0042] 3) The address range of the operation is limited to only 17 bits, and the size range that can be represented is 0-(128KByte-1).

[0043] 4) The host's read / write access to the slave information on the SDIO protocol depends on the cooperation of the slave CPU. When the slave CPU works abnormally, it is impossible to upload some key slave log information, download the slave execution program, etc., and the system debuggability is low.

[0044] In view of the defects of the above-mentioned prior art, Figure 2 The present invention provides a master-slave data transmission method, comprising the following steps:

[0045] S1. Obtain a first aggregate frame constructed by a host according to an idle buffer; the first aggregate frame includes an aggregate frame header.

[0046] S2. According to the first aggregate frame, parse and verify the aggregate frame header to determine a second aggregate frame. The second aggregate frame is the second aggregate frame including a plurality of subframes; the plurality of subframes are subframes with different sequence numbers;

[0047] S3. Moving the plurality of subframes to the idle buffer.

[0048] Further, in some embodiments of the present application, the master-slave data transmission method may further include:

[0049] S4, reading the plurality of subframes from the to-be-read buffer. Reading the plurality of subframes from the idle buffer includes:

[0050] S41, hanging the plurality of sub-frames in a descriptor table, wherein the descriptor table is used to represent the address and length information of each buffer to be read.

[0051] S42, receiving the slave read start signal sent by the host, updating the address and length information of the to-be-read buffer into the register, and moving the corresponding sub-frame data into the FIFO of the master-slave interface, so that the host deaggregates the sub-frames and sends the deaggregated sub-frames to the upper-layer network protocol or forwards them through the MAC driver until the read end interrupt is triggered.

[0052] S43: According to the end of the read interrupt, the descriptor table is read from the register.

[0053] Furthermore, in some embodiments of the present application, the transmission method may further include: S5, determining that the number of subframes continuously transported exceeds a preset number or all aggregated subframes are transported, and generating an interrupt to notify the CPU.

[0054] Furthermore, in some embodiments of the present application, the step of obtaining a first aggregate frame constructed by the host according to the free buffer may also include: constructing the first aggregate frame.

[0055] The host constructs the first aggregate frame according to the free buffer, including:

[0056] S51, query the number of idle buffers of the slave;

[0057] S52: Copy the aggregatable frame data to a continuous memory according to the number of free buffers to obtain a first aggregated frame, where the first aggregated frame includes an aggregated frame header.

[0058] Further, in some embodiments of the present application, the step of parsing and verifying the aggregate frame header according to the first aggregate frame to determine the second aggregate frame may specifically include:

[0059] S61. Parse the frame header information of the first aggregated frame to obtain the first frame sequence number of the first aggregated frame, the length of each subframe, and the aggregated frame header checksum;

[0060] S62: Determine that an aggregate frame in which the first frame sequence number, the length of each subframe, and the aggregate frame header checksum are all the same as preset values ​​is a second aggregate frame.

[0061] The data transmission method of the present application is described below in conjunction with this specific embodiment.

[0062] First, for the data writing process, refer to Figure 3 and Figure 4 The TX write path is mainly to aggregate the frame data of the host Wi-Fi, and send multiple Wi-Fi frames with only one SDIO CMD53 write command, reducing the SDIO protocol overhead and the impact of the host and slave CPU scheduling. The specific process is as follows

[0063] 1) The host queries the number of idle TX buffers of the slave.

[0064] 2) The host copies the aggregatable frame data to a continuous memory according to the number of idle TX buffers of the slave.

[0065] 3) The host constructs an aggregate frame header based on the aggregated frame information, and the aggregate frame header is used by the SDIO Slave hardware to parse the aggregate frame information. The aggregate frame header information includes the first frame sequence number, the length of each subframe, the aggregate frame header checksum, etc.

[0066] 4) The host sends an aggregate frame via an SDIO CMD53 command.

[0067] 5) The SDIO Slave hardware receives the aggregate frame, starts parsing the aggregate frame header information and verifies the aggregate frame header to confirm that it is a compliant aggregate frame.

[0068] 6) The slave SDIO Slave hardware records the first frame number of the aggregate frame header, which is used to compare and analyze whether it is a duplicate frame when each subframe is subsequently transferred. Duplicate frames will not be transferred to the TX memory. The analysis principle is to compare the subframe number to be transferred and the previous subframe number recorded by the slave SDIO Slave hardware. If the subframe number to be transferred is not greater than the previous subframe number recorded by the slave SDIO Slave hardware, the subframe to be transferred is determined to be a duplicate frame.

[0069] 7) The slave SDIO Slave hardware moves each subframe data to an idle TX memory buffer. The TX memory buffer can be a continuous buffer or a discrete buffer.

[0070] 8) If the number of subframes transported continuously exceeds the set number or all aggregated subframes are transported, the SDIO Slave hardware will notify the slave CPU through an interrupt. The number of subframes transported continuously can be freely set by the slave, which can effectively balance the relationship between throughput rate and processing delay.

[0071] 9) The slave CPU reads from the register to find out where the frame data to be processed is in the TX memory and processes the data.

[0072] For the data reading process, refer to Figure 5 , the RX read path is described as follows:

[0073] The data buf of the slave (Device) is Device RX BUF, and the data buf of the host (Host) is Host RX BUF. When the host and the slave interact, data is transmitted through the HIF (Host interface) controller (based on the SDIO3.0 protocol). Each transmission corresponds to an RX process. A data can contain multiple subframes. During transmission, scatter-gather DMA (SG DMA for short) is used for data transfer. SG DMA can be configured to transfer multiple bufs of discontinuous addresses to a continuous destination address area. Therefore, the overall RX process refers to Figure X ; Figure X Each subframe corresponds to a MAC frame, and the hdr (HIF header) of the subframe is the frame header of the HIF; the PL (HIF Payload) is the actual frame content. When used for the WiFi protocol stack, the PL of each subframe includes MAC Header and MAC Data, etc.):

[0074] 1. The slave software prepares the subframes to be uploaded in the Device RX BUF in advance and hangs them on a descriptor table (ADMA_desc_table1). This descriptor table is mainly used to indicate the address and length information of each RX BUF of the slave. For example, the first data is recorded using the descriptor table DMA_desc_tab le1, which contains information about 4 subframes. The starting address of the first frame is addr1 and the length is len1. The starting address of the second frame is addr2 and the length is len2. The starting address of the i-th frame is addr i and the length is len i. The memory address of each subframe may not be continuous.

[0075] 2. During transmission, the slave configures the total length to the read transfer length register and enables the RX transmission of the HIF controller.

[0076] 3. After the HIF controller receives the RX enable signal, it executes according to the original process of the SDIO3.0 protocol (such as triggering an interrupt to the host, waiting for the host to send a CMD53 read data instruction, triggering the slave read start signal, etc.), until the slave read start signal is generated, the slave responds to this signal, and the slave updates the subframe address, length and other information to be transmitted in the form of a descriptor table to the corresponding register of SGDMA. After the HIF controller checks the update, it starts SG DMA to move each subframe data to the FIFO of the master-slave interface.

[0077] 4. At this time, the host takes the data from the FIFO through the SDIO data line and stores it in a continuous memory of the host.

[0078] 5. When a single data (multiple subframes) is completely fetched into the host RX BUF, the host will perform HIF deaggregation on the data, and copy it to skbufs according to the subframe length indicated by each subframe header (hdr) for MAC driver processing. The MAC driver can send it to a higher-level network protocol or forward it (forwarding will be queued and sent through the TX channel) and other processing; at the same time, once the HIF controller sends the data of the last subframe in the descriptor table to the FIFO of the master-slave interface, it will trigger a read end interrupt to the slave and stop the SG DMA.

[0079] 6. After receiving the read completion interrupt, the slave reads the currently processed descriptor table information (including the address and length of each subframe, etc.) from the corresponding register of SG DMA to release the corresponding Device RX BUF. At the same time, repeat the process in step 2 and continue to configure the total length of the second data into the read transfer length register to enable the RX transmission of the HIF controller.

[0080] 7. Same as step 3, after the HIF controller receives the enable signal again, it continues to execute according to the SDIO3.0 protocol process, triggers an interrupt to the host, and waits for the host to send the CMD53 read data instruction. The HIF controller continues to try to read the start interrupt to the slave. The slave responds and updates the subframe address, length and other information to be transmitted to the register corresponding to the SG DMA. After the controller detects the update, it starts the SG DMA to continue to move the subframes corresponding to this data in the description table 2 (DMA_desc_table2) to the FIFO of the master-slave interface.

[0081] 8. Same as step 4, the host takes away the data.

[0082] 9. Same as step 5, the host performs HIF deaggregation processing; once the HIF controller sends the data of the last subframe in the descriptor table to the master-slave interface FIFO, it triggers the read end interrupt to the slave and stops the SG DMA.

[0083] 10. Same as step 6, after the slave receives the read completion interrupt sent by the HIF controller, it reads the currently processed descriptor table information from the register corresponding to the SG DMA, thereby releasing the LMAC RX BUF, and continues to configure the total length of the descriptor table 3 (DMA_desc_table 3), and starts the next data transmission again, and repeats this process.

[0084] According to the above overall process description, it can be seen that the management of the descriptor table in the RX path is mainly completed by the software on the slave side. Therefore, on the slave software, two SG DMA descriptor tables (implemented in the form of linked lists) are mainly maintained. The purpose is that when the first descriptor table is being processed, other data can be hung on the second descriptor table when it is ready at a later time. After the data transmission on the first descriptor table is completed, the HIF controller switches to descriptor table 2 for processing in the read end interrupt processing given by the HIF controller, ensuring that multiple subframes in the second data can also be uploaded at one time, ensuring the overall efficiency of RX (read path). Specifically, the slave software manages the descriptor table as follows Figure 6 As shown:

[0085] The HIF controller mainly contains registers needed by the slave side during RX; the slave side manages the descriptor table base address through a dual table. Descriptor table 1 is hif_rx_table1, and descriptor table 2 is hif_rx_table2. Each descriptor node in the table corresponds to a subframe in the slave memory. Due to the SG DMA functional characteristics, the subframe addresses indicated by the descriptor nodes in the descriptor table can be discontinuous. You only need to configure the registers according to the SG DMA rules, so that the HIF controller can process the next descriptor node after processing one descriptor node.

[0086] For the RX path, the overall interaction interface between the slave and the HIF controller, and between the HIF controller and the host is as follows Figure 7 As shown (the red 1 to 9 in the figure correspond to the following steps 1 to 9). During RX (i.e., host read), after the slave is ready to upload the descriptor table corresponding to the subframe, the slave and host use the HIF controller register as follows (the steps correspond to 1 to 9 in the figure; in the figure, the "read transfer length register" accessed by the host in step 4 and the "read transfer length register" accessed by the slave in step 1 are mapped to each other, and their values ​​are the same):

[0087] 1. The slave CPU configures the read transfer length register and writes the actual total length of this transfer (before block_size alignment);

[0088] 2. The slave CPU configures the read transfer enable register to enable transmission.

[0089] 3. The HIF controller generates a read data ready interrupt to the host. The host enters the interrupt response, obtains the current SDIO interrupt type from the read interrupt register, and clears / restores this interrupt indication bit.

[0090] 4. The host also reads the read transfer length register in the interrupt response to obtain the length of the data currently to be received, and sends a CMD53 read data command to the HIF controller.

[0091] 5. After receiving the CMD53 read command, the HIF controller triggers the SDIO read start interrupt signal to the slave CPU. The slave CPU responds to the interrupt, reads the read start register to check whether the interrupt subtype is indeed the SDIO read start interrupt, and clears / restores this interrupt indication bit.

[0092] 6. The slave CPU also configures the pre-prepared descriptor table information (hif_rx_table) into the SGDMA base address register in the interrupt response, and clears the read transfer length register. After the HIF controller detects that the SGDMA base address register has been updated, it starts to process the content pointed to by the descriptor table and moves the data into the FIFO;

[0093] 7. The host reads the data interface register and successively fetches data from the SDIO data line into its own BUF.

[0094] 8. When the data of the last subframe in the descriptor table (hif_rx_table) is uploaded, the HIF controller triggers a read completion interrupt to the slave CPU. The slave responds to the interrupt and clears / restores the corresponding interrupt indication bit in the read completion register.

[0095] 9. At the same time, the slave configures the Block count register in the interrupt response, clears the block count, obtains the descriptor table information from the SGDMA base address register, and releases the slave memory corresponding to each subframe of the descriptor table.

[0096] In addition, when RX reads data, the slave software process, HIF controller process, and host software process are as follows: Figure 8-Figure 10 As shown, when there is a frame to be uploaded, the interaction with the host is completed through the slave configuration descriptor table node and the register of the HIF controller and the read start and read end interrupts of the HIF controller. Figure 8 "Waiting for SDIO read start terminal of HIF controller", Fig. 9 "Send a read transfer ready interrupt to the host", "Send an SDIO read start interrupt to the slave CPU", and "Send an SDIO read end interrupt to the slave CPU after data transfer is completed" and Fig.10 The steps of "waiting for the read transfer ready interrupt of the HIF controller", "sending CMD53 (block mode), reading slave data (HIF aggregation frame) from the data interface register" are the interaction steps between the interrupts and interrupt responses of each module.

[0097] In addition, based on the RX descriptor configuration process, this embodiment designs the following piggy back mechanism to improve the RX throughput: each time the table is switched to the HIF controller for use, a special descriptor node is constructed at the end of the table, and the content of the node is configured as the total length of the next data transmission. The first transmission is started, and when the host reads the first data, the length information of the next data can be obtained at the same time. Therefore, the host's CMD53 read length register command can be omitted during the next RX interaction, thereby improving the RX interaction efficiency.

[0098] Specifically, refer to Fig.11 , if there are 6 data stored in table le1, before uploading these 6 subframes, it is found that there are 6 subframes ready in table 2. Therefore, when uploading the 6 subframes in table le1, a piggyback descriptor node can be added after the 6 subframe descriptor node in table le1 to notify the host that there are 6 subframes after the 6 subframes are uploaded. After the host receives the first 6 subframes, it reads the total length of the next data (6 subframes), then applies for memory of the corresponding length, and then directly sends the CMD53 command to read the next 6 subframes.

[0099] In addition, for the "read" path, it is also necessary to consider the "read" solution when the slave CPU status is abnormal.

[0100] The data upload / download operation in the abnormal state of the slave CPU is the Abnormal mode operation, which is mainly aimed at the scenario where part of the information in the slave's memory needs to be read by the host when the slave CPU is in an abnormal state.

[0101] First, the slave CPU is abnormal, which can be divided into two situations:

[0102] One is that before the slave CPU hangs itself due to an exception, it is still in the Active state and can control itself to run an exception handling program. For example, when the slave CPU executes the program, if there are hardware exceptions such as undefined instructions, data abort, pre-fetch abort, etc., it will jump to the exception handling program to run. For the sake of universality, the general process of this program is: turn off all interrupts, print exception context information, and hang the CPU. However, before hanging itself, the CPU can still run a piece of code.

[0103] The other is that the slave CPU inexplicably runs away, and the CPU itself does not know why it runs away. In this case, we can consider that the CPU is in a non-Active state, and the CPU cannot interact with the HIF controller.

[0104] Therefore, it is necessary to consider uploading the memory information (including debug information and slave abnormal information) under the above two slave CPU states.

[0105] Note: The debug information is stored in the slave memory and organized in the form of debug structure variables, which can contain various customized slave memory information such as firmware SRAM usage, firmware T / RX queue usage, etc., for WI FI debugging.

[0106] The slave exception information mainly includes the stack pointer, context, task running status and other information when the slave CPU has a hardware exception. This is the general exception printing information and is also stored in the slave memory.

[0107] For abnormal types of slave CPU under Active, uploading abnormal information is relatively simple. It is only necessary to perform a "read" operation in normal working mode before the slave CPU hangs itself. The steps are as follows:

[0108] 1) If the current HIF controller is still transmitting, then the current HIF controller path that is transmitting normally is stopped.

[0109] 2) Configure the debug structure, slave exception information, etc. as a data packet into the descriptor table node, and calculate the total length of this data.

[0110] 3) The slave CPU configures the read transfer length register and writes the total length of this transfer (after SDIO block size alignment).

[0111] 4) The slave CPU configures the HIF controller to enable “read” transmission.

[0112] 5) The slave CPU responds to the HIF controller read start interrupt and configures the debug information to be uploaded to the SG DMA base address register in the form of a descriptor table, and the data is uploaded to the host.

[0113] Abnormal information upload in non-Active state: When the slave is in non-Active state, data upload is realized. The main idea is that the HIF controller waits for the host to send a command to read debug information, and then the HIF controller takes data from the information register left in advance by the slave CPU and uploads it to the host.

[0114] The basic steps are as follows:

[0115] a) First, when the slave is initialized, an exception descriptor table tab le_except ion[tb l_len] is defined. The slave first obtains the address and length of each structure of the debug information to be uploaded, and configures them in the descriptor node of tab le_exception[tb l_len]] in sequence.

[0116] b) The slave calculates the total length of the data to be uploaded involved in the exception descriptor table table_except ion and backs it up to the exception information length register.

[0117] c) The slave backs up the base address of the exception information descriptor table table_except ion to the exception information base address register. The above two registers serve as a "death" will to tell the HIF controller in advance.

[0118] d) If the slave CPU runs away, the host will find that the slave does not respond to the instructions sent by the host on time, and the host will trigger the exception upload function by accessing the read exception information register. After the controller receives the host's exception information upload signal, the controller will update the content in the exception information length register to the read transfer length register, and then update the content in the exception information base address register to the SG DMA base address register, and then trigger the read transfer enable, and start SG DMA to upload the debug information in the "will" of the slave CPU.

[0119] e) The host still follows the normal process at this time, by reading the content of the transfer length register, obtaining the total length of the debug information, and then applying for memory to take away the debug information and then print it out.

[0120] In summary, this application has the following advantages:

[0121] 1. Support TX hardware write aggregation mechanism. The host can write multiple Wi-Fi frame data into the slave chip TX memory at one time through a single SDIOCMD command.

[0122] 2. Support TX write aggregation repeated subframe filtering and aggregation frame header verification, which ensures the reliability of the aggregation function and greatly improves the TX throughput of the interface channel; repeated subframe filtering can be compatible with the host's partial block retransmission and full block retransmission behavior, effectively avoiding the slave receiving duplicate data.

[0123] 3. Supports setting to notify the slave CPU in advance that the host's frame data has been received, which can effectively reduce data processing delays. When the number of frames written in a single time exceeds the set value, an interrupt is immediately generated to notify the slave CPU. The address range of the write is larger and can far exceed the address range of the SDIO protocol. The maximum address range of the SDIO CMD53 write command is 128KByte-1. The present invention does not limit the address range of the write, and the specific write address is set by the slave CPU.

[0124] 4. Support RX channel read aggregation mechanism, high "read" operation throughput. Adopt SG DMA mechanism to transmit data, while reducing the slave CPU handling overhead, data packets with discontinuous addresses can be sent from the slave to the host at one time, greatly improving the RX throughput.

[0125] 5. Support software piggy back mechanism of RX channel to improve the ultimate throughput of "read" operation. When the transmission buffer is limited, when the slave sends out the first data, the tail will carry the length of the next data packet, indicating that the host can continue to receive the next data, thereby saving the overhead generated by the host using CMD53 to read the next data through the SDIO protocol, and improving the ultimate throughput of the RX channel.

[0126] 6. Supports asynchronous operation of slaves when "reading" data, and the overall system efficiency is high. When executing the RX path, the slave CPU operation is simple, and some of the interactive work with the host is completed by the HIF controller hardware (such as the register update operation after the fn1_rd_start signal), thereby reducing the blocking overhead of the slave CPU. After enabling the RX path, the slave CPU can asynchronously execute other software programs, improving the overall system efficiency.

[0127] 7. Supports abnormal log information upload and program download of slaves, and the system is highly debuggable. Regardless of whether the slave is in normal working state or abnormal working state, the host can use the controller to perform "read / write" operations on the slave, thereby completing special functions such as abnormal log information upload and slave program download, and also increases the debuggability of the master-slave interface system.

[0128] In addition, refer to Fig.12 ,and Figure 1 Corresponding to the method, an embodiment of the present application also provides a master-slave data transmission system, which can be used to execute the master-slave data transmission method described in any of the above embodiments, including a host 1, a slave 2 and a HIF controller 3; the host 1 is connected to the HIF controller 3; the slave 2 is connected to the HIF controller 3.

[0129] The contents of the above-mentioned master-slave data transmission method embodiment are all applicable to the present master-slave data transmission system embodiment. The functions specifically implemented by the present master-slave data transmission system embodiment are the same as those of the above-mentioned master-slave data transmission method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned master-slave data transmission method embodiment.

[0130] In addition, refer to Fig.13 ,and Figure 1 Corresponding to the method, another master-slave data transmission system is also provided in an embodiment of the present application. The system may include an acquisition unit 101, a first processing unit 102 and a second processing unit 103. The acquisition unit 101 can be used to acquire a first aggregate frame constructed by the host according to an idle buffer; the first processing unit 102 can be used to parse and verify the aggregate frame header according to the first aggregate frame to determine a second aggregate frame; the second processing unit 103 can be used to move the several subframes to the idle buffer. Furthermore, the system may also include a third processing unit 104, which is used to read the several subframes from the buffer to be read.

[0131] and Figure 1 Corresponding to the method, the embodiment of the present application also provides a master-slave data transmission device, the specific structure of which can be referred to Fig.14 ,include:

[0132] at least one processor;

[0133] at least one memory for storing at least one program;

[0134] When the at least one program is executed by the at least one processor, the at least one processor implements the master-slave data transmission method.

[0135] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0136] and Figure 1 Corresponding to the method, an embodiment of the present application further provides a storage medium, in which processor-executable instructions are stored, and the processor-executable instructions are used to execute the master-slave data transmission method when executed by the processor.

[0137] The contents of the above-mentioned master-slave data transmission method embodiment are all applicable to the present storage medium embodiment. The functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned master-slave data transmission method embodiment, and the beneficial effects achieved are also the same as those achieved by the above-mentioned master-slave data transmission method embodiment.

[0138] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0139] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents. The functions, if implemented in the form of software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several programs to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-On lyMemory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0140] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0141] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0142] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0143] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0144] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0145] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field may make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A master-slave data transmission method, characterized in that: The following steps are involved: Acquire a first aggregate frame constructed by the host according to the free buffer; the first aggregate frame includes an aggregate frame header; According to the first aggregate frame, the aggregate frame header is parsed and verified to determine a second aggregate frame; the second aggregate frame is the second aggregate frame including a plurality of subframes; the plurality of subframes are subframes with different sequence numbers; The plurality of subframes are transferred to the idle buffer.

2. A master-slave data transmission method according to claim 1, characterized in that: The master-slave data transmission method further includes: reading the plurality of subframes from the to-be-read buffer, wherein reading the plurality of subframes from the idle buffer includes: Hanging the plurality of subframes in a descriptor table, wherein the descriptor table is used to represent the address and length information of each buffer to be read; Receiving a slave read start signal sent by the host, updating the address and length information of the to-be-read buffer into the register, and moving the corresponding sub-frame data into the FIFO of the master-slave interface, so that the host deaggregates the sub-frames and sends the deaggregated sub-frames to the upper layer network protocol or forwards them through the MAC driver until a read end interrupt is triggered; According to the end of the read interruption, the descriptor table is read from the register.

3. A master-slave data transmission method according to claim 1, characterized in that: The transmission method further includes: determining that the number of subframes continuously transported exceeds a preset number or all aggregated subframes are transported, and generating an interrupt to notify the CPU.

4. A master-slave data transmission method according to claim 1, characterized in that: The step of obtaining the first aggregate frame constructed by the host according to the free buffer also includes: constructing the first aggregate frame; wherein the host constructs the first aggregate frame according to the free buffer including Query the number of free buffers on the slave; The aggregatable frame data is copied to a continuous memory according to the number of the free buffers to obtain a first aggregate frame, where the first aggregate frame includes an aggregate frame header.

5. A master-slave data transmission method according to claim 1, characterized in that: The step of parsing and verifying the aggregate frame header according to the first aggregate frame to determine the second aggregate frame specifically includes: Parsing the frame header information of the first aggregated frame to obtain the first frame sequence number, the length of each subframe, and the aggregated frame header checksum of the first aggregated frame; Determine that an aggregate frame in which the first frame sequence number, the length of each subframe, and the aggregate frame header checksum are all the same as preset values ​​is a second aggregate frame.

6. A master-slave data transmission system, characterized in that: The method for transmitting data from a master to a slave machine according to any one of claims 1 to 5 above comprises a master machine, a slave machine and a HIF controller; the master machine is connected to the HIF controller; the slave machine is connected to the HIF controller.

7. A master-slave data transmission system, characterized in that: include: An acquisition unit, configured to acquire a first aggregate frame constructed by the host according to the free buffer; A first processing unit, configured to parse and verify the aggregate frame header according to the first aggregate frame to determine a second aggregate frame; The second processing unit is used to transfer the plurality of subframes to the idle buffer.

8. A master-slave data transmission system according to claim 7, characterized in that: The system also includes a reading unit, which is used to read the plurality of subframes from the to-be-read buffer.

9. A master-slave data transmission device, characterized in that include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the master-slave data transmission method as described in any one of claims 1 to 5.

10. A storage medium storing instructions executable by a processor, characterized in that: The processor-executable instructions are used to execute a master-slave data transmission method as described in any one of claims 1-5 when executed by the processor.

Images