A request message processing method, device, equipment and medium

Abstract

The application discloses a request message processing method and device, equipment and medium, and relates to the request processing field, and comprises the following steps: obtaining a newly received request message; performing a shift operation on the message addresses pre-stored in a preset address memory to generate a target message address storage area; the position sequence of each message address storage area in the preset address memory represents the receiving sequence of each request message corresponding to each message address; saving the non-message address information of the new request message to a preset message memory, and saving the message address of the new request message to the target message address storage area in the preset address memory; based on the position sequence of each message address storage area in the preset address memory, sequentially obtaining the message address saved on the message address storage area and the non-message address information of the corresponding request message in the preset message memory, and processing the obtained message information, thereby realizing low-latency ordered output of message information.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of request processing, in particular to a request message processing method and device, equipment and medium. BACKGROUND

[0002] With the advent of the big data era, high-performance computing, intelligent multimedia and many other fields have put forward higher requirements on the performance of computer systems. In order to meet the performance requirements, computer systems have gradually developed from single-core to multi-core, from multi-core to multi-chip, and the transmission efficiency of inter-chip interconnection interface has also gradually highlighted the influence on system performance. When multiple processors initiate requests, the requests received by the inter-chip interconnection processing module may be conflict requests that cannot be processed simultaneously, have the same address and can cause monitoring, or may be requests that can be processed simultaneously. In some related technologies, a piece of information is specially opened to save the sequence information corresponding to each message, and the sequence information is updated after each new message is received. The sequence information is compared each time the message is sent. In this way, when multiple processor requests arrive, additional sequence information needs to be opened, which increases resources; comparison algorithms need to be implemented, and different comparison algorithms have different time delays.

[0003] Therefore, how to ensure that the required message information is output in order with lower latency and lower power consumption is a problem to be solved by those skilled in the art. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a request message processing method, device, equipment and medium, which can ensure that the required message information is output in order with lower latency and lower power consumption. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a request message processing method, comprising:

[0006] obtaining a new request message currently received;

[0007] performing a shift operation on the message addresses pre-stored in the preset address storage to generate a target message address storage area; wherein the position order of each message address storage area in the preset address storage represents the receiving order of each request message corresponding to each message address;

[0008] saving the non-message address information of the new request message to the preset message storage, and saving the message address of the new request message to the target message address storage area in the preset address storage;

[0009] based on the position order of each message address storage area in the preset address storage, sequentially obtaining the message address saved on the message address storage area and the non-message address information of the corresponding request message in the preset message storage, and processing the obtained message information.

[0010] Optionally, after obtaining the newly received new request message, the method further comprises:

[0011] determining whether the new request message is valid according to a storage state of the preset message storage;

[0012] if the new request message is valid, performing a step of shifting the pre-stored message addresses in the preset address storage.

[0013] Optionally, before shifting the pre-stored message addresses in the preset address storage, the method further comprises:

[0014] determining whether the preset address storage has available space for storing message addresses;

[0015] if the preset address storage does not have available space, outputting a first signal indication representing that the preset address storage does not have available space to the backend, and storing the new request message to the preset first-in-first-out queue until the preset address storage has available space for storing message addresses;

[0016] if the preset address storage has available space, determining whether the preset address storage has pre-stored message addresses;

[0017] if the preset address storage has pre-stored message addresses, determining the position of the available space according to the positions of the pre-stored message addresses;

[0018] if the preset address storage does not have pre-stored message addresses, directly storing the message address of the new request message to the preset address storage, and outputting a second signal indication representing that the preset address storage does not have pre-stored message addresses to the backend;

[0019] Correspondingly, the shifting of the pre-stored message addresses in the preset address storage comprises:

[0020] shifting the pre-stored message addresses in the preset address storage according to the position of the available space.

[0021] Optionally, after saving the non-message address information of the new request message to the preset message storage, the method further comprises:

[0022] determining the storage position of the non-message address information of the new request message in the preset message storage;

[0023] saving the storage position to a target message address storage area in the preset address storage.

[0024] Optionally, after saving the message address of the new request message to the target message address storage area in the preset address storage, the method further comprises:

[0025] Retrieve the message address of the request message being processed in the protocol from the preset request address cache;

[0026] Compare the message address of the new request message with the message address of the request message that is currently being processed by the protocol;

[0027] If the message address of the new request message is the same as the message address of the request message that is being processed in the protocol, then the address flag corresponding to the message address of the new request message will be set to invalid.

[0028] If the message address of the new request message is different from the message address of the request message that is being processed in the protocol, then the address flag corresponding to the message address of the new request message will be set to valid.

[0029] Optionally, based on the positional order of each message address storage area in the preset address memory, the message addresses stored in the message address storage areas and the non-message address information of the corresponding request messages in the preset message memory are obtained sequentially, including:

[0030] Based on the address tags corresponding to each message address stored in the message address storage area, determine whether each message address stored in the message address storage area can be processed by the protocol;

[0031] If the address is marked as valid, it is determined that the message address stored in the message address storage area can be processed by the protocol.

[0032] If the address is marked as invalid, it is determined that the message address stored in the message address storage area cannot be processed by the protocol.

[0033] Based on the address markers and the positional order of each message address storage area in the preset address memory, the message addresses that can be processed by the protocol stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are obtained sequentially.

[0034] Optionally, after processing the acquired message information, the process may also include:

[0035] Determine whether the backend can receive and process the acquired message information, and obtain the corresponding judgment result;

[0036] Based on the judgment result, the corresponding third signal indication sent by the backend is received so as to determine the processing status of the acquired message information based on the third signal indication.

[0037] In a second aspect, the present invention provides a request message processing apparatus, comprising:

[0038] The message acquisition module is used to acquire newly received request messages.

[0039] The shift module is used for shifting the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the receiving sequence of each request message corresponding to each message address.

[0040] The save module is used for saving the non-message address information of the new request message to the preset message memory and saving the message address of the new request message to the target message address storage area in the preset address memory.

[0041] The message information processing module is used for sequentially obtaining the message address saved in the message address storage area and the non-message address information of the corresponding request message in the preset message memory based on the position sequence of each message address storage area in the preset address memory, and processing the obtained message information.

[0042] In a third aspect, the present application provides an electronic device, comprising:

[0043] The memory is used for storing the computer program.

[0044] The processor is used for executing the computer program to realize the aforementioned request message processing method.

[0045] In a fourth aspect, the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the aforementioned request message processing method.

[0046] In the present application, a new request message currently received is obtained; a shift operation is performed on the message addresses pre-stored in the preset address memory to generate a target message address storage area; wherein the position sequence of each message address storage area in the preset address memory represents the receiving sequence of each request message corresponding to each message address; the non-message address information of the new request message is saved to the preset message memory, and the message address of the new request message is saved to the target message address storage area in the preset address memory; based on the position sequence of each message address storage area in the preset address memory, the message address saved in the message address storage area and the non-message address information of the corresponding request message in the preset message memory are sequentially obtained, and the obtained message information is processed.

[0047] Beneficial effects: the present application obtains the address storage area of the new request message address by shifting the message address, and separately stores the non-message address information and the address information, and finally outputs the message information according to the position sequence of the address storage area. In this way, the present application can output the message information in the first-in first-out sequence by shifting instead of maintaining the sequence information table, reduce the time delay, and output the required message information in sequence. At the same time, the address information and the non-address information are separately stored, and only the address information is shifted, reducing the logic resources. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0049] Figure 1 A request message processing method flow chart is provided for the embodiments of the present application.

[0050] Figure 2 A request message preprocessing module schematic diagram is provided for the embodiments of the present application.

[0051] Figure 3 A multi-processor request processing system schematic diagram is provided for the embodiments of the present application.

[0052] Figure 4 A shift comparator control flow chart is provided for the embodiments of the present application.

[0053] Figure 5 A request message processing device structure schematic diagram is provided for the embodiments of the present application.

[0054] Figure 6 An electronic equipment structure diagram is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0056] The terms "include", "includes" and "including", as well as any forms of these terms used in the specification and in the accompanying claims, are intended to be inclusive in a manner similar to the term "comprising" as an open transition term without precluding any additional or omissions "comprising" term, for example, a process, method, system, product or apparatus that includes a list of steps or elements is not necessarily limited to those steps or elements specifically listed, but can include additional steps or elements not expressly listed or inherent to such process, method, system, product or apparatus.

[0057] For those skilled in the art to better understand the technical scheme of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0058] In some related technologies, a piece of information is specially opened to save the sequence information corresponding to each message, and the sequence information is updated after each new message is received. The sequence information is compared each time the message is sent. In this way, when the multi-processor request arrives, additional sequence information needs to be opened to increase resources, and a comparison algorithm needs to be implemented, and different comparison algorithms have different time delays. Therefore, the present application provides a request message processing method, device, equipment and medium, which can ensure that the required message information is output in order with lower power consumption and shorter time delay.

[0059] Referring to Figure 1 The embodiment of the present application provides a request message processing method, which comprises the following steps:

[0060] Step S11, obtaining a new request message currently received.

[0061] In the embodiment of the present application, the new request message currently received is first obtained, and then it is determined whether the new request message is valid according to the storage state of the preset message storage. If the new request message is valid, the step of performing a shift operation on the message address pre-stored in the preset address storage is executed. Specifically, the request message processing of the present application mainly uses the request message receiving preprocessing module as shown in Figure 2 When the new request message information is received, the request message receiving preprocessing module also receives a request message valid indication, which indicates that the new request message is valid. When there is an external message input and the request message preprocessing module outputs a non-full state, the external logic will set the signal to be valid, otherwise it will be invalid. At the same time, the new request message currently received can be customized according to the specific requirements of the project or the message packet format can be determined according to the bus protocol, which contains the request address information.

[0062] Step S12, performing a shift operation on the message address pre-stored in the preset address storage to generate a target message address storage area; wherein the position order of each message address storage area in the preset address storage represents the receiving order of each request message corresponding to each message address.

[0063] In the embodiment of the present application, the step of performing the shifting operation on the pre-stored message addresses in the preset address storage is executed only when the new request message is valid. However, before performing the shifting operation on the pre-stored message addresses in the preset address storage, the present application first determines whether the message address of the new request message can be stored in the preset address storage, i.e., whether the pre-stored message addresses in the preset address storage need to be shifted to provide a storage area for the message address of the new request message.

[0064] In this process, the present application first determines whether there is available space for storing message addresses in the preset address storage. If there is no available space in the preset address storage, a first signal indicating that there is no available space in the preset address storage is output to the back end, and the new request message is stored in the preset first-in-first-out queue until there is available space for storing message addresses in the preset address storage. If there is available space in the preset address storage, it is determined whether there are pre-stored message addresses in the preset address storage. If there are pre-stored message addresses, the position of the available space is determined according to the positions of the pre-stored message addresses. If there are no pre-stored message addresses, the message address of the new request message is directly stored in the preset address storage, and a second signal indicating that there are no pre-stored message addresses in the preset address storage is output to the back end. Specifically, if there is no available space for storing message addresses in the preset address storage, i.e., the preset address storage is full, a full signal is output. At this time, the new request message is first stored in the request FIFO (First Input First Output) cache after being read. Then, if the request message preprocessing module cache is not full, the message in the request FIFO cache is read to the request message preprocessing module. However, if the preset address storage of the current request message preprocessing module is full, the message is temporarily stored in the request FIFO cache, and the available space is obtained after the pre-stored message address in the preset address storage is selected and output. In addition, if there is available space for storing message addresses in the preset address storage, it is first determined whether the preset address storage is empty and has no pre-stored message addresses. If the preset address storage is empty, an empty signal is output, indicating that the current message storage is empty. At this time, the preset address storage is empty, so the pre-stored message addresses do not need to be shifted, and the message address of the new request message can be directly placed in the preset address storage. If the preset address storage is not empty and has some pre-stored message addresses, the position of the available space is determined according to the positions of the pre-stored message addresses. Then, when the shifting operation is performed on the pre-stored message addresses in the preset address storage, the shifting operation is performed on the pre-stored message addresses in the preset address storage according to the position of the available space.

[0065] Specifically, for the pre-stored message address, the preset address memory has 4 rows in total, the 3rd row has been selected and output, the next time a new message comes in, the 4th row judges itself as the highest row and does not shift; the 3rd row is invalid and does not shift; the message in the 2nd row is shifted to the 3rd row, and the previous 1st row is shifted to the 2nd row. In this way, the storage area of the 1st row is emptied, and the newly incoming message address can be placed in the first row. In this way, the first input message information is ensured to be in the storage area with a larger row number.

[0066] In step S13, the non-message address information of the new request message is saved to the preset message memory, and the message address of the new request message is saved to the target message address storage area in the preset address memory.

[0067] In the implementation of the present application, the internal logic of the request message preprocessing module mainly includes a two-dimensional array memory, M shift comparators, and an output information module. The depth of the two-dimensional array memory is M, and the width is the bit width of the input request message information. In order to reduce the number of logic, the two-dimensional array memory is stored in two parts, namely the preset message memory and the preset address memory. When shifting, only the message address is shifted, and the remaining information in the message is stored in the message memory. Therefore, after saving the non-message address information of the new request message to the preset message memory, the storage position of the non-message address information of the new request message in the preset message memory is determined; the storage position is saved to the target message address storage area in the preset address memory.

[0068] Specifically, when the request message valid indication is valid, the message information in the request message information except the address information is stored in the message memory. The address memory contains the following two information: 1, the address information of the request message 2, the storage row information of the message memory (i.e. the current message information is stored in the 2nd row of the two-dimensional array). The value of the message storage row information is: when each valid message is input, the current row information is processed by 1, and the value range is 0~M-1. That is, the storage information of each row in the address memory is {message address information, message storage row information}. It should be noted that if the message address of the new request message is saved to the target message address storage area in the preset address memory, the address memory valid mark corresponding to the message address of the new request message will be set to valid. The address memory valid mark: indicates whether the address in the address memory is valid, i.e. whether the message stored in the current row is valid. The bit width is M, and each bit represents the valid indication of a row, 1 for valid and 0 for invalid. In this way, when the request message valid indication is valid and the xth bit of the address memory valid mark is valid, it indicates that there is a valid message in the xth row of the address memory. In this way, it is clear whether the message address stored in the address memory is valid.

[0069] Meanwhile, the M shift controller modules in the application are used to select the information in the address memory corresponding to the earliest received message with an address different from the address in the protocol processing through logical judgment. Therefore, after the message address of the new request message is saved in the target message address storage area in the preset address memory, the message address of the request message being processed in the protocol is obtained from the preset request address cache area; the message address of the new request message is compared with the message address of the request message being processed in the protocol; if the message address of the new request message is the same as the message address of the request message being processed in the protocol, the address mark corresponding to the message address of the new request message is set as invalid; if the message address of the new request message is different from the message address of the request message being processed in the protocol, the address mark corresponding to the message address of the new request message is set as valid.

[0070] Specifically, the address information in each shift register needs to be compared with the address comparison information input by the request message preprocessing module. The address comparison information here represents the message address of the request message being processed in the protocol, and is combined as {addrn, ……addr1, addr0}. The bit width of the address comparison information = the request address bit width x the number of storage table entries; wherein the number of storage table entries = the maximum number of requests allowed to be initiated by a single processor x the number of processors. Meanwhile, the address comparison information also corresponds to an address valid flag. The address valid flag represents whether the address information corresponding to the above address comparison information is valid (i.e. if addr1 in the above address comparison information is invalid, the value is {1……01}). The bit width is M, and if valid, the message entering the request message preprocessing module needs to be compared with the address, otherwise, it does not need to be compared with the address. The preset request address cache area stores the message addresses of all request messages being processed in the protocol. When the request message is selected from the request message preprocessing module and starts to be processed in the protocol, the request address is recorded in the request address cache module (the bit width is the request message address bit width, and the depth is a two-dimensional array of M), and the output is the address comparison information address and the valid flag. For example, if addr0 and addr1 are stored, the output address comparison information is {00……addr1, addr0}, and the address valid flag is {00……11}. When the entire request processing flow corresponding to the address ends, the corresponding bit position is invalid, for example, when the addr0 request processing ends, the address valid flag output becomes {00……10}.

[0071] When comparing the packet address of the new request packet with the packet address of the request packet being processed, if the packet address of the new request packet is the same as the packet address of the request packet being processed, the address mark corresponding to the packet address of the new request packet is set as invalid; if the packet address of the new request packet is not the same as the packet address of the request packet being processed, the address mark corresponding to the packet address of the new request packet is set as valid. The address mark here can be named as the same address mark, indicating whether there is the same address as the address comparison information in the address storage, the bit width is M, and each bit represents the same address indication of one row, and the judgment is needed when the new packet or the address valid flag changes. Setting 1 indicates that there is no same address in the current comparison, and the request packet processing can be performed. The M shift comparators sequentially compare the packet address of the new request packet with the packet address of the request packet being processed in the same clock. For each shift comparator: if there is the same address, the corresponding position of the same address mark is set as 0, otherwise, it is set as 1.

[0072] In step S14, based on the position sequence of each packet address storage area in the preset address storage, the packet address stored in the packet address storage area and the non-packet address information of the corresponding request packet in the preset packet storage are sequentially acquired, and the acquired packet information is processed.

[0073] In the embodiment of the application, when the packet request is output, whether each packet address stored in the packet address storage area can be processed according to the address mark corresponding to each packet address stored in the packet address storage area; if the address mark is valid, it is determined that the packet address stored in the packet address storage area can be processed; if the address mark is invalid, it is determined that the packet address stored in the packet address storage area cannot be processed; finally, based on the address mark and the position sequence of each packet address storage area in the preset address storage, the packet address stored in the packet address storage area which can be processed and the non-packet address information of the corresponding request packet in the preset packet storage are sequentially acquired. It is also determined whether the packet address can be output for protocol processing according to the address mark.

[0074] In the process of processing the obtained message information, the generation of the processable message flag and the generation of the output message information are involved, wherein the processable message flag generation process is as follows: a register with a signal bit width of M is designed, and an optional message indication signal indicator is obtained, and a bit-by-bit or of the valid address marker and the same address marker of the address storage is obtained, which represents the current optional message indication signal. Then, the optional message indication signal is processed by logical judgment, and the bit width is M, and each bit represents whether the current row of the address storage can be selected and output, and the highest bit represents the earliest arriving message, and the lowest bit represents the latest arriving message. The request message is guaranteed to be processed in order according to the principle of high-bit validity priority. The final output of the processable message flag is the bit-by-bit or result of the optional message indication signal indicator, that is, as long as there is a non-same address message in the address storage, the processable message flag can be output.

[0075] When the selected message is output, the i-th row of the address storage that does not have the same address and arrives first in the processing process is selected by the shift controller. Since the i-th row contains the message address information and the storage row information of the message storage, the message storage row information j in the i-th row can be obtained, and the selected message is the j-th row information of the message storage through the message storage row information j. Therefore, the final output message information is the address information of the i-th row of the address storage and the selected message information. That is, based on the address marker and the position sequence of each message address storage area in the preset address storage, the message address stored in the message address storage area that can be processed by the protocol and the non-message address information of the corresponding request message in the preset message storage are obtained in sequence, and then the final output message address and non-message address information are obtained.

[0076] In addition, it should be noted that after the obtained message information is processed, it is necessary to determine whether the backend can receive and process the obtained message information to obtain a corresponding determination result; and a corresponding third signal indication sent by the backend is received according to the determination result, so as to determine the processing state of the obtained message information based on the third signal indication. The third indication signal is an external optional message indication, which indicates that the backend can process the currently selected message. The generation logic is as follows: when it is detected that the request message preprocessing module outputs the processable message flag, and it is determined whether the backend can receive the message processing, if yes, 1 is set, otherwise, 0 is set. The minimum delay can be effective at the same time as the processable message flag, that is, the 0 delay output indication is realized. Moreover, the request message processing of the present application is not limited to the request message address conflict determination, and when the input information needs to be determined for conflict, the method can be used.

[0077] In order to prevent data loss and data loss during the output process, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage can be packaged and encapsulated according to the self-defined request packet format or the request message packet format specified by the bus protocol to obtain a message packet, and a hash operation is performed according to the message packet to obtain a hash value, and finally the hash value and the message packet are sent to the backend together, so that the backend can verify the message packet according to the hash value after receiving the message packet, determine whether the message information in the message packet is complete, if not, directly return a signal that cannot be processed, and no other processing is performed, if complete, protocol processing is performed again, and the integrity of the message information for protocol processing is ensured.

[0078] Beneficial effects: The application obtains the address storage area for storing the new request message address by performing a shift operation on the message address, and separately stores the non-message address information and the address information, and finally outputs the message information in order according to the position sequence of the address storage area. In this way, the application can output the message information in the first-in first-out order by shifting instead of maintaining the sequence information table, reduce the time delay, and output the required message information in order. At the same time, the address information and the non-address information are stored separately, and only the address information is shifted, so that the logic resources are reduced.

[0079] The flow of protocol processing of the multi-processor request is shown in Figure 3 When the request of the multi-processor arrives, the request message preprocessing module is used to select the request message to be processed, and then the request message starts protocol processing. The request processing process mentioned in the application takes the CCIX (Cache Coherent Interconnect for Accelerators, Cache Coherent Interconnect for Accelerators) protocol as an example, which refers to all processes from starting to process the request to receiving the request response or ACK (Acknowledgement) response. Next, the processing of the request message preprocessing module for the message will be mainly described.

[0080] Referring to Figure 2As shown, the internal logic of the request message preprocessing module mainly includes a two-dimensional array memory, M shift controller modules, and an output information module. The depth of the two-dimensional array memory is M, and the width is the bit width of the input request message information. In order to reduce the number of logic, the two-dimensional array memory is stored in two parts, namely the message memory and the address memory. When shifting, only the address of the message is shifted, and the remaining information in the message is stored in the message memory. As shown, when a new message is input and the request message valid indication is valid, the message information in the request message information except the address information is stored in the message memory. The address memory includes the following two information: 1. address information of the request message 2. storage row information of the message memory (i.e. the current message information is stored in the first row of the two-dimensional array). The value of the message storage row information is obtained in the following manner: when each valid message is input, the current row information is incremented by 1, and the value range is 0~M-1. That is, the storage information in each row of the address memory is {message address information, storage row information of the message memory}.

[0081] The function of the M shift controller modules is to select the information in the address memory corresponding to the message received earliest and different from the address in the protocol processing through logical judgment. The address information in each shift register needs to be compared with the address comparison information input by the request message preprocessing module, and the M shift comparators are sequentially executed in the same clock. For each shift comparator: if the same address is found, the corresponding position of the same address marker is set to 0, otherwise, it is set to 1. At the same time, when the request message valid indication is valid and the address memory valid marker is valid, it indicates that there is a valid message in the xth row of the address memory. At this time, the data in the xth row of the address memory needs to be shifted to the x+1th row of the address memory, and the xth bit of the address memory valid marker needs to be moved to the x+1th bit. If the message address information corresponding to the x+1th row is selected and output, the xth bit of the address memory valid marker is set to 0. For example, if there is a valid message in the third row of the address memory, and a valid message is currently input, the shift register 3 judges that a new message is input, and the information in the third row of the address memory is shifted to the fourth row, and the address memory valid marker in the third row is shifted to the fourth row. At the same time, the comparison result of the address comparison information input by the module is recorded in the same address marker of the fourth row. In this way, the logic control of each shift comparator is the same. In this way, it is ensured that the message information input earliest is in the storage area with a larger row number. In summary, when the address information in the address memory is shifted, the corresponding address valid marker and same address marker are also shifted. At the same time, if there is no new message input, it is judged whether the address valid flag changes. If it changes, a new same address marker will be generated. If it does not change, the same address marker remains unchanged.

[0082] For the output information module, state output and message output are realized. It includes the generation of processable message flag and the generation of output message information. The generation process of processable message flag is as follows: a register with a signal bit width of M is designed, and an optional message indicator is generated, which is the bit-by-bit or of the valid address marker and the same address marker of the address storage, indicating the current optional message indicator. Then, logical judgment processing is performed on the optional message indicator, and the bit width is M, and each bit represents whether the current row of the address storage can be selected and output, and the highest bit represents the earliest arriving message, and the lowest bit represents the latest arriving message. The principle of high bit priority is used to ensure the ordered processing of the request message. The final output of the processable message flag is the bit-by-bit or result of the optional message indicator, that is, as long as there is a non-same address message in the address storage, the processable message flag can be output. Finally, based on the address marker and the position order of each message address storage area in the preset address storage, the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage are obtained in sequence, and then the final output message address and non-message address information are output.

[0083] Beneficial effects: The application outputs the request message in the order of first-in first-out by shifting instead of maintaining the order information table, and if there is data in the storage, the selected message can be output without time delay, thereby guaranteeing that the low-latency ordered output of the required message information meets the requirements. At the same time, by splitting the input message, the comparison information and the message information that does not need to be compared are stored separately, and the logic resources are reduced.

[0084] Referring to Figure 5 The embodiment of the application provides a request message processing device, which comprises:

[0085] A message acquisition module 11 is configured to acquire a new request message currently received;

[0086] A shifting module 12 is configured to perform a shifting operation on the message addresses pre-stored in the preset address storage to generate a target message address storage area; wherein the position order of each message address storage area in the preset address storage represents the receiving order of each request message corresponding to each message address;

[0087] A saving module 13 is configured to save the non-message address information of the new request message to the preset message storage, and save the message address of the new request message to the target message address storage area in the preset address storage;

[0088] The message information processing module 14 is configured to sequentially acquire the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage according to the position sequence of each message address storage area in the preset address storage, and process the acquired message information.

[0089] Since the embodiments of the device part correspond to the above-mentioned embodiments, the embodiments of the device part are described with reference to the embodiments of the method part, and will not be described here.

[0090] Beneficial effects: the application acquires the address storage area storing the new request message address by performing the shift operation on the message address, and separately stores the non-message address information and the address information, and finally sequentially outputs the message information according to the position sequence of the address storage area. In this way, the application can output the message information in the first-in first-out sequence by the shift operation instead of maintaining the sequence information table, reduce the time delay, and output the required message information in sequence. Meanwhile, the address information and the non-address information are separately stored, and only the address information is shifted, so as to reduce the logic resources.

[0091] Further, the embodiment of the application further discloses an electronic device, Figure 6 is an electronic device structure diagram according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the use range of the application. The electronic device can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is used for storing a computer program, and the computer program is loaded and executed by the processor 21 to realize the related steps in the request message processing method disclosed in any of the preceding embodiments. In addition, the electronic device in the embodiment can be an electronic computer.

[0092] In the embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and the external device, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the application, which will not be limited here; the input / output interface 25 is used to acquire external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which will not be limited here.

[0093] In addition, the memory 22 as the carrier of resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0094] The operating system 221 is configured to manage and control each hardware device on the electronic device and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. The computer program 222 can further include computer programs capable of performing other specific work in addition to the computer programs capable of performing the request message processing method disclosed by the electronic device in any of the foregoing embodiments.

[0095] Further, the present application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the request message processing method disclosed above. The specific steps of the method can refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0096] Further, the present application also discloses a computer program product comprising computer programs / instructions; wherein the computer programs / instructions are executed by a processor to implement the request message processing method disclosed above. The specific steps of the method can refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0097] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can refer to the method part.

[0098] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware, computer software or a combination of both. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized by hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0099] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0100] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be intended to distinguish one entity or operation from another entity or operation without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the stated element.

[0101] The above detailed description of the technical solutions provided by the present application has been made, and the principles and implementation modes of the present application are described by applying specific examples. The above description of the examples is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A request message processing method, characterized by, The method comprises the following steps: acquiring a newly received request message; performing a shift operation on the pre-stored message addresses in the preset address storage to generate a target message address storage area; the position sequence of each message address storage area in the preset address storage represents the receiving sequence of the corresponding request message; storing the non-message address information of the new request message in a preset message storage, and storing the message address of the new request message in the target message address storage area in the preset address storage; based on the position sequence of each message address storage area in the preset address storage, sequentially acquiring the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message storage, and processing the acquired message information.

2. The request message processing method of claim 1, wherein, After acquiring the newly received request message, the method further comprises the following steps: determining whether the new request message is valid according to the storage state of the preset message storage; if the new request message is valid, performing the shift operation on the pre-stored message addresses in the preset address storage.

3. The request message processing method of claim 1, wherein, Before performing the shift operation on the pre-stored message addresses in the preset address storage, the method further comprises the following steps: determining whether there is available space for storing message addresses in the preset address storage; if there is no available space in the preset address storage, outputting a first signal indicating that there is no available space in the preset address storage to the back end, and storing the new request message in a preset first-in-first-out queue until there is available space for storing message addresses in the preset address storage; if there is available space in the preset address storage, determining whether there are pre-stored message addresses in the preset address storage; if there are pre-stored message addresses, determining the position of the available space according to the position of each pre-stored message address; if there are no pre-stored message addresses, directly storing the message address of the new request message in the preset address storage, and outputting a second signal indicating that there are no pre-stored message addresses in the preset address storage to the back end; Correspondingly, the shift operation on the pre-stored message addresses in the preset address storage comprises the following steps: performing a shift operation on the pre-stored message addresses in the preset address storage according to the position of the available space.

4. The request message processing method of claim 1, wherein, After storing the non-message address information of the new request message in the preset message storage, the method further comprises the following steps: determining the storage position of the non-message address information of the new request message in the preset message storage; storing the storage position in the target message address storage area in the preset address storage.

5. The request message processing method of claim 1, wherein, After storing the message address of the new request message in the target message address storage area in the preset address storage, the method further comprises the following steps: acquiring the message address of the request message being processed in a protocol from a preset request address cache area; comparing the message address of the new request message with the message address of the request message being processed in a protocol; If the message address of the new request message is the same as the message address of the request message being processed, the address mark corresponding to the message address of the new request message is set as invalid; If the message address of the new request message is not the same as the message address of the request message being processed, the address mark corresponding to the message address of the new request message is set as valid.

6. The request message processing method of claim 5, wherein, The position order of each message address storage area in the preset address memory is used to sequentially acquire the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory. It is judged whether each message address stored in the message address storage area can be processed according to the address mark corresponding to each message address stored in the message address storage area. If the address mark is valid, it is determined that the message address stored in the message address storage area can be processed. If the address mark is invalid, it is determined that the message address stored in the message address storage area cannot be processed. The position order of each message address storage area in the preset address memory is used to sequentially acquire the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory.

7. The request message processing method according to any one of claims 1 to 6, characterized by, After the acquired message information is processed, the following steps are further included: It is judged whether the backend can receive and process the acquired message information to acquire a corresponding judgment result; According to the judgment result, a corresponding third signal indication sent by the backend is received, so as to determine the processing state of the acquired message information based on the third signal indication.

8. A request message processing apparatus characterized by comprising: It includes: A message acquisition module is used to acquire a new request message currently received; A shift module is used to perform a shift operation on the message address pre-stored in the preset address memory to generate a target message address storage area; wherein the position order of each message address storage area in the preset address memory represents the receiving order of each request message corresponding to each message address; A storage module is used to save the non-message address information of the new request message to a preset message memory and save the message address of the new request message to the target message address storage area in the preset address memory; A message information processing module is used to sequentially acquire the message address stored in the message address storage area and the non-message address information of the corresponding request message in the preset message memory based on the position order of each message address storage area in the preset address memory, and process the acquired message information.

9. An electronic device, comprising: It includes: A memory is used to store a computer program; A processor is used to execute the computer program to realize the steps of the request message processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to realize the steps of the request message processing method according to any one of claims 1 to 7.

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