N-polarity enhanced HEMT device and preparation method thereof

Abstract

The invention discloses an N-polarity enhanced HEMT device and a preparation method thereof, the device comprises a first substrate, the first substrate comprises a first region and a second region which are alternately arranged in sequence, and an isolation groove is formed between the first region and the second region; a SiO2 layer, a first passivation layer, a back barrier layer and a GaN layer are sequentially arranged on the first region, and a first source electrode, a first drain electrode and a first gate electrode are arranged on the GaN layer; the second region comprises source and drain regions and a substrate region, and the source and drain regions are arranged on the two sides of the substrate region and are isolated through the substrate region; a SiO2 layer is arranged on the substrate region, a second source electrode and a second drain electrode are arranged on the source and drain region, and a second gate electrode is arranged on the SiO2 layer; the first gate electrode is electrically connected with the second source electrode, the first source electrode is electrically connected with the second drain electrode, the metal electrode is used for replacing a lead, stray capacitance can be reduced, conduction loss of the device in a switching circuit is reduced, meanwhile, the metal electrode can also serve as a field plate, an electric field is dispersed, and voltage resistance and stability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an N-polarity enhanced HEMT device and a preparation method thereof. Background Art

[0002] Nitrogen-polar (N-polar) GaN materials, with the opposite polarity to traditional gallium-polar (Ga-polar) GaN materials, have shown potential advantages in high-frequency, high-power microwave transistors, enhanced devices and sensors with low contact resistance and high two-dimensional electron gas (2DEG) threshold. Low contact resistance, good surface morphology, high contour definition and stable and reliable ohmic contact are the key to its application, but the preparation of N-polar GaN materials and the control of polar epitaxy are very technically challenging.

[0003] High-quality substrates are the underlying basic materials for achieving high-quality GaN epitaxy. Si substrates have good heat dissipation, are easy to integrate, and are inexpensive, and are widely used as GaN epitaxial substrates. However, there is a large lattice mismatch between Si substrates and GaN materials, and epitaxial GaN has many dislocations, which is a considerable challenge for the application of GaN materials in high-voltage circuits. In comparison, sapphire and GaN have the same wurtzite crystal structure. Sapphire has good thermal stability and is easier to achieve high-quality, large-size, and high-voltage GaN epitaxy. Although sapphire-based GaN epitaxy has high quality, the process lags behind Si-based materials, and there are certain difficulties in preparing small linewidth devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an N-polarity enhancement mode HEMT device and a preparation method thereof, which are more compatible with the CMOS preparation process, more easily realize the preparation of small line width devices, and improve the process yield.

[0005] In order to solve the above technical problem, the first aspect of the present invention provides an N-polarity enhancement mode HEMT device, comprising a first substrate, wherein the first substrate comprises a first region and a second region alternately arranged in sequence, and an isolation trench is formed between the first region and the second region;

[0006] A SiO2 layer, a first passivation layer, a back barrier layer, and a GaN layer are sequentially arranged on the first region of the first substrate, and a first source electrode, a first drain electrode, and a first gate electrode are arranged on the GaN layer;

[0007] The second region of the first substrate comprises a source-drain region and a substrate region, wherein the source-drain region is disposed on both sides of the substrate region and isolated from each other by the substrate region; a SiO2 layer is disposed on the substrate region, a second source electrode and a second drain electrode are disposed on the source-drain region, and a second gate electrode is disposed on the SiO2 layer;

[0008] The first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode, so that the first drain electrode serves as the drain electrode of the N-polarity enhancement-mode HEMT device, the second gate electrode serves as the gate electrode of the N-polarity enhancement-mode HEMT device, and the second source electrode serves as the source electrode of the N-polarity enhancement-mode HEMT device.

[0009] As an improvement of the above solution, the thickness of the SiO2 layer provided on the first region is 200nm-500nm; the thickness of the SiO2 layer provided on the second region is 200nm-500nm;

[0010] As an improvement of the above solution, the distance between the first source electrode and the first drain electrode is 10 μm-15 μm;

[0011] The distance between the first source electrode and the first gate electrode is 1 μm-3 μm;

[0012] The length of the first gate electrode is 0.8 μm-1.3 μm.

[0013] As an improvement of the above solution, the doping concentration in the source and drain regions is 1×10 12 ions / cm 2 -1×10 15 ions / cm 2 ;

[0014] The depth of the isolation groove is 90nm-110nm.

[0015] As an improvement of the above solution, the first passivation layer is an AlN layer, and the thickness of the first passivation layer is 500nm-800nm;

[0016] The back barrier layer is Al x Ga 1-x N layer, wherein x=0.18-0.30, and the thickness of the back barrier layer is 20nm-30nm.

[0017] A second aspect of the present invention provides a method for preparing an N-polarity enhancement mode HEMT device, comprising:

[0018] providing a first substrate;

[0019] Providing a second substrate and growing a heterostructure on the surface of the second substrate, wherein the heterostructure includes a nucleation layer, a GaN layer, a back barrier layer and a first passivation layer deposited in sequence;

[0020] Depositing SiO2 layers on the heterostructure and the first substrate respectively;

[0021] Performing a hot pressing process on the SiO2 layer on the heterostructure and the SiO2 layer on the first substrate;

[0022] removing the second substrate and the nucleation layer to expose the N-polar surface of the GaN layer, and reducing the thickness of the GaN layer;

[0023] Etching part of the GaN layer downward to form a plurality of groove structures arranged at intervals, wherein the groove structures expose the SiO2 layer, and forming a plurality of protruding structures between the groove structures, and then etching the sidewalls of the GaN layer in the protruding structures and part of the sidewalls of the back barrier layer to form a mesa isolation region;

[0024] A first source electrode, a first drain electrode, and a first gate electrode are correspondingly manufactured on the surface of the GaN layer in the protruding structure;

[0025] Etching a portion of the SiO2 layer in the groove structure downward to the inside of the first substrate to form an isolation groove, wherein the isolation groove divides the first substrate into a first region and a second region that are alternately arranged, the protruding structure is located on the first region, and the groove structure is located on the second region;

[0026] Etching a portion of the SiO2 layer of the groove structure downwards until the first substrate is exposed, forming at least two ion implantation windows separated by the SiO2 layer, and doping the ion implantation windows to form source and drain regions;

[0027] A second source electrode and a second drain electrode are fabricated on the source and drain regions, and a second gate electrode is correspondingly fabricated on the SiO2 layer in the groove structure;

[0028] The first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode.

[0029] As an improvement of the above solution, the hot pressing treatment includes:

[0030] The SiO2 layer on the heterostructure and the SiO2 layer on the first substrate are pressed together at 300°C-450°C and a pressure of 1MPa-10MPa for 20min-60min, and then annealed at a high temperature of 450°C-600°C.

[0031] As an improvement of the above solution, the hot pressing treatment includes:

[0032] Before the hot pressing treatment, the SiO2 layer deposited on the heterostructure and / or the first substrate is subjected to micro-roughening treatment to make the roughness of the SiO2 layer less than 0.5 nm.

[0033] As an improvement of the above solution, the deposition thickness of the GaN layer is 2 μm-3 μm, and the thickness of the GaN layer after thinning is 50 nm-80 nm;

[0034] And / or, the method of removing the second substrate and the nucleation layer in the heterostructure comprises laser lift-off;

[0035] The nucleation layer is an AlN layer, and the thickness of the nucleation layer is 20nm-50nm.

[0036] As an improvement of the above solution, the first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode, including:

[0037] Depositing a second passivation layer, then forming openings in the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode corresponding regions, depositing a metal material at the openings, so that the first gate electrode is electrically connected to the second source electrode through the metal material;

[0038] A second passivation layer is deposited, and then openings are formed in the regions corresponding to the first source electrode and the second gate electrode, and a metal material is deposited in the openings, so that the first source electrode is electrically connected to the second drain electrode through the metal material.

[0039] The implementation of the present invention has the following beneficial effects:

[0040] (1) The present application provides an N-polarity enhancement mode HEMT device, which is a cascode HEMT device formed by cascading a HEMT and a MOSFET with the aid of a first substrate, wherein the first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode, and a metal electrode is used to replace the lead arrangement between the source, drain and gate electrodes, thereby reducing parasitic capacitance, which is beneficial to reducing the conduction loss of the device in a switching circuit. At the same time, the metal electrode can also serve as a field plate to disperse the electric field and improve the voltage resistance and stability of the device.

[0041] (2) The novel Cascode N-polarity enhancement-mode HEMT device prepared in the present application reduces parasitic effects on the basis of realizing enhancement-mode HEMT, facilitates integration, broadens the integration possibilities of HEMT, reduces the volume and conduction loss of power devices, and better exerts the high-frequency performance advantages of HEMT.

[0042] (3) The present application provides a method for easily integrated preparation of Cascode HEMT, which specifically uses an inverted bonding and substrate peeling method to achieve the preparation of Si-based N-polar HEMT, which is more compatible with CMOS preparation process, easier to achieve the preparation of small line width devices, and improves the process yield.

[0043] (4) This application provides a GaN device integration idea, and provides more preparation solutions for analog integrated circuits through the preparation and metal interconnection of GaN and Si-based MOSFETs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 : A schematic structural diagram of an N-polarity enhancement mode HEMT device in the present invention;

[0045] Figure 2 : A top view of an N-polarity enhancement mode HEMT device in the present invention;

[0046] Figure 3 : A schematic structural diagram of the first substrate in the present invention;

[0047] Figure 4 : A schematic diagram of the structure obtained in step (2);

[0048] Figure 5 : Schematic diagram of the structure of the SiO2 layer deposited on the surface of the heterostructure obtained in step (2);

[0049] Figure 6 : Schematic diagram of the structure of depositing SiO2 layer on the surface of the first substrate;

[0050] Figure 7 : A schematic diagram of the structure obtained in step (4);

[0051] Figure 8 : A schematic structural diagram of the structure obtained by removing the second substrate and the nucleation layer in step (5);

[0052] Fig. 9 : A schematic diagram of the structure obtained after the thickness of the GaN layer is reduced in step (5);

[0053] Fig.10 : A top view of the structure obtained in step (61);

[0054] Fig.11 : A schematic structural diagram of the structure obtained in step (61);

[0055] Fig.12 : A schematic structural diagram of the structure obtained in step (62);

[0056] Fig.13 : A schematic diagram of the structure obtained in step (71);

[0057] Fig.14 : A schematic structural diagram of the structure obtained in step (72);

[0058] Fig.15 : A top view of region A in the structure obtained in step (72);

[0059] Fig.16 : A schematic diagram of the structure obtained in step (8);

[0060] Fig.17 : A schematic structural diagram of the structure obtained by forming the ion implantation window in step (9);

[0061] Fig.18 : A schematic structural diagram of the structure obtained after the source and drain regions are formed in step (9);

[0062] Fig.19 : A schematic diagram of the structure obtained in step (10);

[0063] Fig. 20 : A schematic structural diagram of the structure obtained after the first deposition of the second passivation layer in step (111);

[0064] Fig.21 : A schematic structural diagram of the structure obtained after the opening is formed in step (111);

[0065] Fig. 22 : A schematic structural diagram of the structure obtained after the first deposition of metal material in step (111);

[0066] Fig.23 : A schematic structural diagram of the structure obtained after the second passivation layer is deposited for the second time in step (112);

[0067] Fig.24 : A schematic structural diagram of the structure obtained after the opening is formed in step (112);

[0068] Fig.25 : A schematic structural diagram of the structure obtained after the second deposition of metal material in step (112);

[0069] Fig.26 : A schematic structural diagram of the structure obtained after the second passivation layer is deposited for the third time in step (113);

[0070] Fig. 27 : Energy band diagram of GaN and AlGaN at the N-polar interface in the N-polar enhancement mode HEMT device obtained in Example 1 of the present invention;

[0071] Fig.28 : Energy band diagram of GaN and AlGaN at the Ga polar interface in the N polar enhancement mode HEMT device obtained in Comparative Example 1 of the present invention.

[0072] Reference numerals:

[0073] 1-first substrate; 2-second substrate; 3-nucleation layer; 4-GaN layer; 5-back barrier layer; 6-first passivation layer; 7-SiO2 layer; 8-first source electrode; 9-first drain electrode; 10-first gate electrode; 11-isolation groove; 12-ion implantation window; 13-substrate region; 14-source and drain region; 15-second source electrode; 16-second drain electrode; 17-second gate electrode; 18-second passivation layer; 19-metal material; 20-groove structure; 21-protrusion structure. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with specific embodiments below.

[0075] Conventional Si-based HEMT (high electron mobility transistor) has a higher lattice mismatch between Si and GaN, and a large number of dislocations will be generated by epitaxy. Therefore, an additional stress regulation layer needs to be grown to neutralize and increase the thickness of the epitaxial layer. Sapphire and GaN have the same wurtzite crystal structure. Therefore, the dislocation density of sapphire-based GaN is 1×10 19 cm -2 , which is much smaller than the dislocation density of Si-based GaN (3×10 18 cm -2 ), and sapphire has good thermal stability, and it is easier to achieve high quality and large size. The process of preparing GaN materials using sapphire substrates is mature and has been widely used in the LED industry. Sapphire-based GaN has certain difficulties in preparing small line width devices. It can be understood that the stress regulation layer can be a GaN layer or an AlGaN layer (the Al component accounts for 0.1 to 0.8), and the thickness of the stress regulation layer can be 500nm-1000nm.

[0076] In order to solve the above problems, the present invention provides an N-polarity enhancement mode HEMT device in a first aspect. Figure 1 and Figure 2 , comprising a first substrate 1, wherein the first substrate 1 comprises first regions and second regions alternately arranged in sequence, and an isolation groove 11 is formed between the first region and the second region;

[0077] A SiO2 layer 7, a first passivation layer 6, a back barrier layer 5, and a GaN layer 4 are sequentially provided on the first region of the first substrate 1, and a first source electrode 8, a first drain electrode 9, and a first gate electrode 10 are provided on the GaN layer 4;

[0078] The second region of the first substrate 1 includes a source-drain region 14 and a substrate region 13, wherein the source-drain region 14 is disposed on both sides of the substrate region 13 and is isolated by the substrate region 13; a SiO2 layer 7 is disposed on the substrate region 13, a second source electrode 15 and a second drain electrode 16 are disposed on the source-drain region 14, and a second gate electrode 17 is disposed on the SiO2 layer 7;

[0079] The first gate electrode 10 is electrically connected to the second source electrode 15, the first source electrode 8 is electrically connected to the second drain electrode 16, the first drain electrode 9 serves as the drain electrode of the N-polarity enhancement-mode HEMT device, the second gate electrode 17 serves as the gate electrode of the N-polarity enhancement-mode HEMT device, and the second source electrode 15 serves as the source electrode of the N-polarity enhancement-mode HEMT device.

[0080] In the present invention, the cascade preparation of MOSFET and HEMT is realized by means of the first substrate, and the metal electrode is used instead of the lead, which can reduce the parasitic capacitance and reduce the conduction loss of the device in the switching circuit. At the same time, the metal electrode can also be used as a field plate to disperse the electric field and improve the withstand voltage and stability of the device. In addition, the new Cascode N-polarity enhanced HEMT device in the present application is conducive to integration on the basis of realizing the enhanced HEMT, broadens the integration possibility of HEMT, and better exerts the high-frequency performance advantages of HEMT.

[0081] Furthermore, the N-polarity enhancement-mode HEMT device also includes a second passivation layer 18, which covers the surface of the protrusion structure 21, the surface of the recess structure 20 and the isolation groove 11. The first source electrode 8, the first drain electrode 9 and the first gate electrode 10 are arranged on the GaN layer 4 after penetrating the second passivation layer 18, the second source electrode 15 and the second drain electrode 16 are arranged on the source and drain region 14 after penetrating the second passivation layer 18, and the second gate electrode 17 is arranged on the SiO2 layer 7 after penetrating the second passivation layer 18.

[0082] Optionally, the thickness of the SiO2 layer 7 provided on the first region is 200nm-500nm; the thickness of the SiO2 layer 7 provided on the second region is 200nm-500nm, and the thickness of the SiO2 layer 7 provided on the first region may be equal to or different from the thickness of the SiO2 layer 7 provided on the second region.

[0083] Optionally, the thickness of the GaN layer 4 is 2 μm-3 μm; the back barrier layer 5 is Al x Ga 1-xN layer, wherein x=0.18-0.30, the thickness of the back barrier layer 5 is 20nm-30nm, which can better limit 2DEG and reduce leakage; the first passivation layer 6 is an AlN layer, and the thickness of the first passivation layer 6 is 500nm-800nm. Further depositing an AlN layer on the back barrier layer 5 can serve as a heat dissipation layer, which can cooperate with the back barrier layer 5 to further reduce the possibility of device leakage and improve the withstand voltage performance. Of course, the aforementioned structural layers can also be composed of other materials, and the present invention is not limited thereto. The implementation form of the material of any corresponding structural layer is within the protection scope of the present invention.

[0084] Optionally, the distance between the first source electrode 8 and the first drain electrode 9 is 10 μm-15 μm; the distance between the first source electrode 9 and the first gate electrode 10 is 1 μm-3 μm; and the length of the first gate electrode is 0.8 μm-1.3 μm.

[0085] Optionally, the doping concentration in the source and drain regions is 1×10 12 ions / cm 2 -1×10 15 ions / cm 2 .

[0086] Optionally, the depth of the isolation trench 11 is 90 nm-110 nm, which is convenient for filling with a passivation material later and prevents Si in the SiO2 layer formed by bonding from affecting the performance of the Si-based MOSFET.

[0087] Accordingly, the present invention also provides a method for preparing an N-polarity enhancement mode HEMT device, comprising:

[0088] (1) providing a first substrate 1;

[0089] (2) providing a second substrate 2, and growing a heterostructure on the surface thereof, wherein the heterostructure includes a nucleation layer 3, a GaN layer 4, a back barrier layer 5, and a first passivation layer 6 deposited in sequence;

[0090] (3) depositing a SiO2 layer 7 on the heterostructure and the first substrate 1 respectively;

[0091] (4) subjecting the SiO2 layer 7 on the heterostructure and the SiO2 layer 7 on the first substrate 1 to a hot pressing treatment;

[0092] (5) removing the second substrate 2 and the nucleation layer 3 to expose the N-polar surface of the GaN layer 4, and reducing the thickness of the GaN layer 4;

[0093] (6) etching a portion of the GaN layer 4 downward to form a plurality of groove structures 20 arranged at intervals, wherein the groove structures 20 expose the SiO2 layer 4, and forming a plurality of protruding structures 21 between the groove structures 20, and then etching a portion of the sidewalls of the GaN layer 4 and the back barrier layer 5 in the protruding structures 21 to form a mesa isolation region;

[0094] (7) A first source electrode 8, a first drain electrode 9, and a first gate electrode 10 are formed on the surface of the GaN layer 4 in the protruding structure 21;

[0095] (8) etching a portion of the SiO2 layer 4 in the groove structure 20 downward to the inside of the first substrate 1 to form an isolation groove 11, wherein the isolation groove 11 divides the first substrate 1 into a first region and a second region that are alternately arranged, wherein the protruding structure 21 is located on the first region, and the groove structure 20 is located on the second region;

[0096] (9) etching a portion of the SiO2 layer 7 of the groove structure 20 downward until the first substrate 1 is exposed, forming at least two ion implantation windows 12 separated by the SiO2 layer 7, and doping the ion implantation windows 12 to form source and drain regions 14;

[0097] (10) A second source electrode 15 and a second drain electrode 16 are formed on the source and drain regions 14, and a second gate electrode 17 is formed on the SiO2 layer 7 in the groove structure 20;

[0098] (11) The first gate electrode 10 is electrically connected to the second source electrode 15, and the first source electrode 8 is electrically connected to the second drain electrode 16, so that the first drain electrode 9 serves as the drain electrode of the N-polarity enhancement-mode HEMT device, the second gate electrode 17 serves as the gate electrode of the N-polarity enhancement-mode HEMT device, and the second source electrode 15 serves as the source electrode of the N-polarity enhancement-mode HEMT device.

[0099] In the present application, an inverted bonding and substrate peeling method is used to realize the preparation of Si-based N-polarity HEMT, which is more compatible with the CMOS (complementary metal oxide semiconductor) preparation process, easier to realize the preparation of small line width devices, and improve the process yield. At the same time, a new type of Cascode (common source and common gate) N-polarity enhancement HEMT device is prepared. On the basis of realizing the enhancement HEMT, the parasitic effect is reduced, which is conducive to integration, broadens the integration possibility of HEMT, reduces the volume and conduction loss of power devices, and better exerts the high-frequency performance advantages of HEMT.

[0100] Each step is described in detail below. Figure 3-Figure 26 .

[0101] Regarding (1), providing a first substrate 1;

[0102] Preferably, the first substrate 1 is a Si substrate, which has good heat dissipation, is easy to integrate, and is low in price. Figure 3 As shown. Of course, the first substrate 1 can also be replaced with any suitable semiconductor substrate according to actual conditions. Optionally, the first substrate 1 is a P-type Si substrate or an N-type Si substrate.

[0103] Regarding (2), providing a second substrate 2, and growing a heterostructure on the surface thereof, wherein the heterostructure comprises a nucleation layer 3, a GaN layer 4, a back barrier layer 5, and a first passivation layer 6 deposited in sequence;

[0104] Preferably, the second substrate 2 is a sapphire substrate. The sapphire substrate has the same wurtzite crystal structure as GaN, has good thermal stability, and is easier to achieve high-quality, large-size, and high-voltage GaN epitaxy. The structure after the heterostructure is grown on the sapphire substrate is as follows: Figure 4 Of course, the second substrate 2 can also be replaced with any suitable semiconductor substrate according to actual conditions.

[0105] Preferably, the nucleation layer 3 is an AlN layer, and the deposition thickness of the nucleation layer 3 is 20nm-50nm, more preferably 30nm-50nm; the deposition thickness of the GaN layer 4 is 2μm-3μm; the back barrier layer 5 is Al x Ga 1-x N layer, wherein x=0.18-0.30, the deposition thickness of the back barrier layer 5 is 20nm-30nm, which can better limit 2DEG and reduce leakage; the first passivation layer 6 is an AlN layer, and the deposition thickness of the first passivation layer 6 is 500nm-800nm. Further deposition of an AlN layer on the back barrier layer 5 can serve as a heat dissipation layer, and cooperate with the back barrier layer 5 to further reduce device leakage and improve withstand voltage. Of course, the aforementioned structural layers can also be composed of other materials, and the present invention is not limited thereto. The implementation form of the material of any corresponding structural layer is within the protection scope of the present invention.

[0106] Optionally, the heterostructure can be obtained by conventional epitaxial growth technology. Exemplarily, the nucleation layer 3, GaN layer 4, and back barrier layer 5 in the heterostructure include but are not limited to metal organic chemical vapor deposition (MOCVD), and the first passivation layer 6 can be obtained by magnetron sputtering; more preferably, the deposition method of the first passivation layer 6 includes: depositing a first passivation material on the back barrier layer 5 by magnetron sputtering, and then performing annealing at a high temperature of 650°C-900°C to further improve the quality of the first passivation layer 6.

[0107] Regarding (3), depositing a SiO2 layer 7 on the heterostructure and on the first substrate 1 respectively;

[0108] The deposition of the SiO2 layer 7 can not only be used for SiO2-SiO2 direct bonding, so that the wafer surface direct bonding process replaces the metal melt bonding, realizes low-temperature direct bonding, reduces costs, and prevents leakage, but can also be used as a barrier layer during flip-chip HEMT to prevent the channel 2DEG from leaking to the Si substrate bonding layer and affecting the device performance.

[0109] Preferably, the deposition thickness of the SiO2 layer 7 on the heterostructure is 200nm-500nm, and the structure formed is as follows: Figure 5 As shown, the deposition thickness of the SiO2 layer 7 on the first substrate 1 is 200nm-500nm, and the structure formed is as follows Figure 6 The SiO2 layer 7 can be deposited by a CVD process, or by other deposition processes in the art. The deposition process of the SiO2 layer 7 is not specifically limited in this application.

[0110] Regarding (4), the SiO2 layer 7 on the heterostructure and the SiO2 layer 7 on the first substrate 1 are subjected to hot pressing treatment;

[0111] Compared with Si-based epitaxial, sapphire-based GaN HEMT has lower dislocation density, higher reliability and better voltage resistance. By bonding with Si substrate, a HEMT device compatible with CMOS process is realized. By using advanced IC process, the line width and stability of the prepared device are improved.

[0112] Specifically include:

[0113] (41) performing micro-roughening treatment on the SiO2 layer 7 deposited on the heterostructure and / or the first substrate 1, so that the roughness of the SiO2 layer 7 is less than 0.5 nm;

[0114] The micro-roughening treatment of the SiO2 layer 7 can promote the bonding strength when the first substrate 1 and the second substrate 2 are directly bonded, and the roughness of the SiO2 layer 7 can be higher than 0.5nm in some cases, depending on the process conditions during bonding. The method selected for the micro-roughening treatment of the SiO2 layer 7 can be a conventional operation in the art, and an exemplary method is chemical mechanical polishing (CMP).

[0115] Furthermore, the SiO2 layer 7 deposited on the heterostructure and the first substrate 1 is micro-roughened so that the roughness of the SiO2 layer 7 is maintained at about 0.1 nm, which is conducive to direct bonding between the heterostructure and the first substrate 1 based on the SiO2 layer 7.

[0116] (42) Pressing the SiO2 layer 7 on the heterostructure and the SiO2 layer 7 on the first substrate 1 under pressure of 1 MPa-10 MPa at 300° C.-450° C. for 20 min-60 min, and then annealing at a high temperature of 450° C.-600° C.;

[0117] The bonding between the heterostructure and the first substrate 1 can be achieved by hot pressing the SiO2 layer 7. Under the hot pressing conditions of 20 min to 60 min, the SiO2 interface formed by the SiO2 layer 7 can be connected by the van der Waals force. After high temperature annealing, the hydrogen bonds between the connected SiO2 interfaces can be further dehydrated to form covalent bonds, thereby improving the bonding strength. The structure after bonding is as follows: Figure 7 shown.

[0118] Regarding (5), removing the second substrate 2 and the nucleation layer 3 to expose the N-polar surface of the GaN layer 4, and reducing the thickness of the GaN layer 4;

[0119] Conventional N-polar epitaxy is difficult to prepare. In this application, the inverted GaN layer 4 in the uppermost layer is exposed by removing the second substrate 2 and the nucleation layer 3 in the heterostructure, thereby obtaining a Si substrate HEMT epitaxy. Moreover, because the Ga polarity surface of the GaN layer 4 is 180° different from the N polarity surface, the N polarity surface of the GaN layer 4 is ingeniously exposed by an inverted method. The structure is as follows: Figure 8 As shown, bonding peeling realizes a simple preparation method of N-polarity HEMT. N-polarity HEMT epitaxy is obtained by bonding peeling, which has low difficulty and good quality.

[0120] Preferably, the method adopted includes laser stripping, specifically, after polishing the back side of the second substrate 2, the nucleation layer 3 and the GaN layer 4 are separated by means of laser stripping. During laser stripping, the laser energy is not absorbed by the second substrate 2 and the nucleation layer 3, and can smoothly penetrate the second substrate 2 and the nucleation layer 3 to reach the GaN layer 4, thereby removing the second substrate 2 and the nucleation layer 3 and exposing the GaN layer 4. However, it is not limited to using other processes to remove the second substrate 2 and the nucleation layer 3.

[0121] Conventional epitaxy must consider the growth quality of the upper core channel region. If the lower GaN layer 4 is too thin, a large number of dislocations will be generated, affecting the quality of the upper region. However, if the first source electrode 8, the first drain electrode 9, and the first gate electrode 10 are prepared on the conventional epitaxial structure, the first gate electrode 10 will be far away from the channel carriers. Therefore, in this step, part of the GaN layer 4 is removed to reduce its thickness, reduce the thickness of the N-polar surface of the GaN layer 4, and reduce the distance between the N-polar surface of the GaN layer 4 and the 2DEG channel, so as to better achieve the gate control effect. Its structure is as follows: Fig. 9 As shown, the thickness of the GaN layer after thinning is 50nm-80nm.

[0122] Furthermore, part of the GaN layer 4 may be removed by etching, including but not limited to ICP etching. The specific process for removing part of the GaN layer 4 is not specifically limited in the present application.

[0123] Regarding (6), etching a portion of the GaN layer 4 downward to form a plurality of groove structures 20 arranged at intervals, wherein the groove structures 20 expose the SiO2 layer 4, and forming a plurality of protruding structures 21 between the groove structures 20, and then etching a portion of the sidewalls of the GaN layer 4 and the back barrier layer 5 in the protruding structures 21 to form a mesa isolation region;

[0124] Specifically include:

[0125] (61) etching a portion of the GaN layer 4 downward until the SiO2 layer 7 is exposed, so as to form a plurality of groove structures 20 arranged at intervals, and a plurality of protrusion structures 21 are formed between the groove structures 20;

[0126] Specifically, a portion of the stacked GaN layer 4, the back barrier layer 5 and the first passivation layer 6 is removed to form the groove structure 20, and the remaining unremoved GaN layer 4, the back barrier layer 5 and the first passivation layer 6 are formed into a protrusion structure 21. Further, in this step, a combination of yellow light process and etching process is used to obtain a plurality of groove structures 20 arranged at intervals. First, a uniform coating process is performed on the GaN layer 4 to form a desired grid pattern on the wafer, such as Fig.10 As shown (the pink part is the groove structure 20 formed after etching, and the gray part is the protruding structure 21), wherein the size of a single gray part is 200μm*250μm, and the size of a single pink part is 200μm*120μm, and then photolithography is performed, using the pattern formed on the photoresist as a mask, and the pattern is transferred to the wafer; finally, the pink area is etched to expose the SiO2 layer 7, and the structure formed is as shown Fig.11 As shown, the etching method includes but is not limited to ICP dry etching, and the etching process is not specifically limited in this application.

[0127] (62) etching the sidewalls of the GaN layer 4 and part of the sidewalls of the back barrier layer 5 in the protruding structure 21 to form mesa isolation regions at both ends of the back barrier layer 5;

[0128] In this step, a combination of yellow light process and etching process is used to achieve the mesa isolation of the epitaxial structure in the HEMT region. Specifically, a photoresist process is performed on the GaN layer 4 to form a desired pattern on the wafer, and then a photolithography process is performed, using the pattern formed on the photoresist as a mask, and the pattern is transferred to the wafer; finally, the side wall of the GaN layer 4 and part of the side wall of the back barrier layer 5 are removed by etching until the back barrier layer 5 is exposed, so as to form a mesa isolation region at both ends of the back barrier layer 5, and the structure formed is as follows: Fig.12 As shown, the etching method includes but is not limited to ICP dry etching, and the etching process is not specifically limited in this application.

[0129] Regarding (7), a first source electrode 8, a first drain electrode 9, and a first gate electrode 10 are formed on the surface of the GaN layer 4 in the protruding structure 21;

[0130] Specifically include:

[0131] (71) depositing materials of the first source electrode 8 and the first drain electrode 9 at both ends of the surface of the GaN layer 4 in the protruding structure 21 to form the first source electrode 8 and the first drain electrode 9;

[0132] The material of the first source electrode 8 and the first drain electrode 9 is Ti / Al / Ni / Pt, that is, a Ti layer, an Al layer, a Ni layer and a Pt layer are deposited on the table in sequence, and a gold-free process is used to prevent Au from contaminating the CMOS production line process, wherein the thickness of the Ti layer is 15nm-25nm, the thickness of the Al layer is 145nm-155nm, the thickness of the Ni layer is 25nm-35nm, and the thickness of the Pt layer is 95nm-105nm. The deposition method of the material of the first source electrode 8 and the first drain electrode 9 includes but is not limited to evaporation. Specifically, the first source electrode 8 and the first drain electrode 9 region can be formed by a coating and photolithography process, and then the material can be deposited. The structure formed is as follows Fig.13 More preferably, annealing may be performed in a protective gas atmosphere at 400° C. to 600° C. for 30s to 60s to further promote the formation of a good ohmic contact.

[0133] Further, the size of the first source electrode 8 is 80 μm*100 μm, the size of the first drain electrode 9 is 80 μm*100 μm, and the distance L1 between the first source electrode 8 and the first drain electrode 9 is 10 μm-15 μm.

[0134] (72) depositing the material of the first gate electrode 10 on the surface of the GaN layer 4 in the protruding structure 21 to form the first gate electrode 10;

[0135] In this step, the first gate electrode 10 is deposited between the first source electrode 8 and the first drain electrode 9. The material of the first gate electrode 10 is Ni / Pt, that is, the Ni layer and the Pt layer are deposited on the table in sequence, wherein the thickness of the Ni layer is 25nm-35nm, the thickness of the Pt layer is 95nm-105nm, and the size of the first gate electrode 10 is 80μm*80μm. The deposition method of the first gate electrode 10 includes but is not limited to electron beam evaporation. Specifically, the material deposition can be performed after the first gate electrode 10 region is formed by coating and photolithography processes. The structure formed is as follows Fig.14 shown.

[0136] Furthermore, the width L3 of the first gate electrode 10 is 0.8 μm-1.3 μm, and the distance L2 between the first source electrode 8 and the first gate electrode 10 is 1 μm-3 μm. Fig.15 shown.

[0137] Regarding (8), a portion of the SiO2 layer 4 in the groove structure 20 is etched downward to the inside of the first substrate 1 to form an isolation groove 11, wherein the isolation groove 11 divides the first substrate 1 into a first region and a second region that are alternately arranged, wherein the protruding structure 21 is located on the first region, and the groove structure 20 is located on the second region;

[0138] In this step, the isolation groove 11 divides the first substrate 1 into a first area and a second area, the protruding structure 21 is located on the first area, and the groove structure 20 is located on the second area, so that the first source electrode 8, the first drain electrode 9, and the first gate electrode 10 are located in the first area, and the shallow trench isolation of the MOSFET area is realized, and different circuit units are separated to form different circuit units, which can also play a role in circuit insulation protection. The structure formed is as follows Fig.16 As shown. The first region can be regarded as a HEMT region, and the second region can be regarded as a MOSFET region. By way of example, the isolation groove 11 can be obtained by processing through photolithography, etching processes, wherein the etching process includes but is not limited to ICP dry etching, and the etching process is not specifically limited in this application.

[0139] Furthermore, the etching depth of the isolation groove inside the first substrate 1 is 90nm-110nm, and the width of the isolation groove 11 is greater than 10μm, which is convenient for filling with passivation materials later and prevents Si in the SiO2 layer 7 formed by bonding from affecting the performance of Si-based MOSFET.

[0140] Regarding (9), a portion of the SiO2 layer 7 of the groove structure 20 is etched downward to expose the first substrate 1, to form at least two ion implantation windows 12 separated by the SiO2 layer 7, and the ion implantation windows 12 are doped to form source and drain regions 14;

[0141] In this step, etching the SiO2 layer 7 in the second region can form at least two ion implantation windows 12 in the second region, which is convenient for the formation of the source and drain regions 14 later, and the Si in the first substrate 1 is exposed by etching, which is convenient for polarity doping. For example, two ion implantation windows 12 insulated from each other by the SiO2 layer 7 can be obtained by processing through the process of photolithography and etching, and the structure thereof is as follows: Fig.17 As shown, the etching process includes but is not limited to ICP dry etching, and the etching process is not specifically limited in this application.

[0142] Further, after doping the ion implantation window 12, at least two source and drain regions 14 are formed in the second region of the first substrate 1, and the first substrate is divided into a substrate region 13 and a source and drain region 14, and the source and drain regions 14 are arranged on both sides of the substrate region 13 and isolated by the substrate region 13. Specifically, by injecting dopants into the ion implantation window 12 to achieve polarity doping, and then activating the dopants to achieve a doping well process, the structure of which is as follows: Fig.18 Here, the polarity of the selected dopant is opposite to that of the first substrate 1, so that the first substrate 1 is in contact with the doped well and forms a PN junction, wherein the doping concentration is 1×10 12 ions / cm 2 -1×10 15 ions / cm 2 Exemplarily, the first substrate 1 shown is a P-type Si substrate, and the dopant here is an N-type dopant, including but not limited to P (phosphorus) ions; the first substrate 1 is an N-type Si substrate, and the dopant here is a P-type, including but not limited to boron (B), and the dopant can be a conventional choice in the art, and the present invention is not limited thereto.

[0143] Optionally, dopants may be implanted using ion implantation equipment, and then may be performed at a high temperature of 600°C-1000°C to repair lattice damage and activate dopants to achieve a doped well process, with the depth of the doped well being 45nm-55nm.

[0144] Regarding (10), a second source electrode 15 and a second drain electrode 16 are formed on the source and drain regions 14, and a second gate electrode 17 is formed on the SiO2 layer 7 in the groove structure 20;

[0145] In this step, a second source electrode 15 and a second drain electrode 16 are formed on the surfaces of the two source and drain regions 14, respectively, and a second gate electrode 17 is formed on the surface of the SiO2 layer 7. The structure is as follows: Fig.19 The electrode material includes but is not limited to Al, and the deposition method of the second source electrode 15, the second drain electrode 16, and the second gate electrode 17 includes but is not limited to evaporation.

[0146] Further, the thickness of the second source electrode 15 is 500nm-800nm, the thickness of the second drain electrode 16 is 500nm-800nm, and the thickness of the second gate electrode 17 is 500nm-800nm.

[0147] Regarding (11), the first gate electrode 10 is electrically connected to the second source electrode 15, and the first source electrode 8 is electrically connected to the second drain electrode 16;

[0148] In this step, by depositing a second passivation layer 18 and a metal material 19 on the surface of the structure, the first gate electrode 10 is connected to the second source electrode 15 through the metal material 19, and the first source electrode 8 is connected to the second drain electrode 16 through the metal material 19, so that the first drain electrode 9 serves as the drain electrode of the N-polarity enhancement-mode HEMT device, the second gate electrode 17 serves as the gate electrode of the N-polarity enhancement-mode HEMT device, and the second source electrode 15 serves as the source electrode of the N-polarity enhancement-mode HEMT device.

[0149] Specifically include:

[0150] (111) depositing the second passivation layer 18 for the first time, then forming openings in the regions corresponding to the first gate electrode 10, the second source electrode 15, the second drain electrode 16, and the second gate electrode 17, and depositing the metal material 19 at the openings for the first time, so that the first gate electrode 10 is connected to the second source electrode 15 through the metal material 19;

[0151] In this step, a second passivation layer 18 is deposited on the structure obtained in step (10) to cover the first region, the second region and the isolation trench 11. Fig. 20 As shown, more preferably, the deposition thickness of the second passivation layer 18 on the first gate electrode 10 is 450nm-550nm. Subsequently, a plurality of openings are formed in the second passivation layer 18, and the openings penetrate the first gate electrode 10, the second source electrode 15, the second drain electrode 16, and the second gate electrode 17, as shown in FIG. Fig.21 As shown, the openings can be realized by conventional operations in the art, including but not limited to ICP etching; finally, a metal material 19 is deposited to fill the openings with the metal material 19, so that the first gate electrode 10 is connected to the second source electrode 15 through the metal material 19, as shown in FIG. Fig. 22 shown.

[0152] Optionally, the material of the second passivation layer 18 formed after the first deposition of the second passivation layer 18 is SiN xThe second passivation layer 18 can be deposited by conventional epitaxial growth technology, exemplarily low pressure chemical vapor deposition (LPCVD); the metal material 19 is Ti / Al, that is, the Ti layer and the Al layer are deposited in sequence, wherein the deposition thickness of the Ti layer is 25nm-35nm, and the deposition thickness of the Al layer is 450nm-500nm.

[0153] (112) depositing the second passivation layer 18 for a second time, then forming openings in the regions corresponding to the first source electrode 8 and the second drain electrode 16, and depositing the metal material 19 at the openings for a second time, so that the first source electrode 8 is connected to the second drain electrode 16 through the metal material 19;

[0154] In this step, a second passivation layer 18 is deposited for a second time on the structure obtained in step (111) so that it completely covers the metal material 19. Fig.23 As shown, more preferably, the deposition thickness of the second passivation layer 18 on the metal material 19 is 180nm-230nm. Subsequently, a plurality of openings are formed in the second passivation layer 18, and the openings penetrate to the first source electrode 8 and the second drain electrode 16, as shown in FIG. Fig.24 Finally, a metal material 19 is deposited to fill the plurality of openings with the metal material 19, so that the first source electrode 8 is connected to the second drain electrode 16 through the metal material 19, as shown in FIG. Fig.25 shown.

[0155] Optionally, the metal material 19 is Ti / Al, that is, a Ti layer and an Al layer are deposited in sequence, wherein the deposition thickness of the Ti layer is 25nm-35nm, and the deposition thickness of the Al layer is 150nm-200nm.

[0156] (113) depositing the second passivation layer 18 for the third time, forming openings in the second passivation layer 18 to expose the first drain electrode 9, the second gate electrode 17, and the second source electrode 15, which serve as the drain electrode, gate electrode, and source electrode of the N-polarity enhancement mode HEMT device, respectively;

[0157] In this step, a second passivation layer 18 is deposited again on the structure obtained in step (112) to completely cover the metal material 19. Fig.26 Subsequently, an opening is formed in the second passivation layer 18 to expose the first drain electrode 9, the second gate electrode 17, the second source electrode 15, as shown Figure 1 shown.

[0158] The present invention will be further described below with specific embodiments:

[0159] Example 1

[0160] This embodiment provides an N-polarity enhancement mode HEMT device, and the preparation method thereof includes:

[0161] (1) providing a first substrate, wherein the first substrate is a P-type Si substrate;

[0162] (2) Providing a second substrate, which is a sapphire substrate, on the surface of which an AlN nucleation layer, a GaN layer and an AlN layer are sequentially deposited by MOCVD x Ga 1-x N layer (x = 0.25), wherein the deposition thickness of the AlN nucleation layer is 40nm, the deposition thickness of the GaN layer is 2.5μm, and the Al x Ga 1-x The deposition thickness of the N layer is 25 nm;

[0163] Subsequently, a first passivation layer of AlN layer is deposited by magnetron sputtering, and high-temperature annealing is performed at 800° C. to form a first passivation layer of high-quality AlN layer with a deposition thickness of 650 nm.

[0164] (3) depositing a SiO2 layer with a thickness of 350 nm on the first passivation layer of the AlN layer by LPCVD; depositing a SiO2 layer with a thickness of 350 nm on the P-type Si substrate by LPCVD; finally, polishing both deposited SiO2 layers by CMP to maintain a roughness of about 0.1 nm;

[0165] (4) The two SiO2 layers after treatment are bonded by hot pressing at 370°C and 5MP pressure for 40 min, followed by high temperature annealing at 520°C;

[0166] (5) After polishing the back side of the sapphire substrate, laser lift-off was used to separate the interface between the AlN nucleation layer and the GaN layer to obtain the Si substrate HEMT epitaxy, and the N-polar surface of the GaN layer was exposed by inversion; then, Cl2 and BCl3 were used as etching gases to perform ICP etching on the GaN layer to reduce its thickness to 65 nm;

[0167] (6) Performing a photoresist treatment on the GaN layer to form Fig.10 The alternating grid structure shown in the figure is subjected to photolithography, and finally Cl2 and BCl3 are used as etching gases to perform ICP etching on the pink area until the SiO2 layer is exposed to form an alternately arranged groove structure, and the remaining unremoved upper and lower stacked GaN layers, back barrier layers and first passivation layers form a protruding structure;

[0168] Subsequently, the side wall of the GaN layer and part of the side wall of the back barrier layer are etched through the processes of photoresist, photolithography and etching until the back barrier layer is exposed, so as to form a mesa isolation region at both ends of the back barrier layer.

[0169] (7) After negative photoresist photolithography was performed on the surface of the GaN layer in the protruding structure, Ti / Al / Ni / Pt was evaporated to form a first source electrode (80 μm*100 μm) and a first drain electrode (80 μm*100 μm) at both ends of the surface of the GaN layer, and annealed at 500°C for 45 seconds in an N2 atmosphere. Among them, in the first source electrode and the first drain electrode, the thickness of the Ti layer is 20 nm, the thickness of the Al layer is 150 nm, the thickness of the Ni layer is 30 nm, and the thickness of the Pt layer is 100 nm. The distance L1 between the first source electrode and the first drain electrode is 13 μm;

[0170] Subsequently, Ni / Pt is electron-beam evaporated on the surface of the GaN layer to form a first gate electrode (80 μm*80 μm) between the first source electrode and the first drain electrode. The thickness of the Ni layer in the first gate electrode is 30 nm, the thickness of the Pt layer is 170 nm, the width L3 of the first gate electrode is 1 μm, and the distance L2 between the first source electrode and the first gate electrode is 2 μm.

[0171] (8) After performing photolithography and photolithography on the SiO2 layer in the groove structure, CF4 is used as the etching gas ICP etching to the inside of the first substrate to form an isolation groove, wherein the isolation groove divides the first substrate into a first region and a second region that are alternately arranged, the protruding structure is located on the first region, and the groove structure is located on the second region. The etching depth of the isolation groove in the first substrate is 100 nm, and the width of the isolation groove is 15 μm;

[0172] (9) After photolithography and photolithography, a portion of the SiO2 layer in the groove structure is subjected to ICP etching using CF4 as an etching gas until the first substrate is exposed, so as to form at least an ion implantation window isolated by the SiO2 layer;

[0173] The N-type dopant phosphorus (P) ions were implanted into the ion implantation window using an ion implantation device with a doping concentration of 5×10 13 ions / cm 2 , after diffusing 50nm with 10ev energy, it is carried out at a high temperature of 800℃ to repair lattice damage and activate dopants to form source and drain regions;

[0174] (10) Al is deposited on the surfaces of the two source and drain regions to form a second source electrode and a second drain electrode; Al is deposited on the surface of the SiO2 layer to form a second gate electrode, and the thickness of the second source electrode, the second drain electrode, and the second gate electrode are all 650 nm;

[0175] (11) Depositing SiN on the structure obtained in step (10) by LPCVD xA second passivation layer is deposited to cover the first region, the second region and the isolation groove, and the deposition thickness of the second passivation layer on the first gate electrode is 500nm; then, CF4 is used as an etching gas to perform ICP etching on the second passivation layer to form a plurality of openings, and the openings penetrate the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode; finally, a metal material Ti / Al is deposited to fill the metal material in the plurality of openings, so that the first gate electrode is connected to the second source electrode through the metal material, and the deposition thickness of the Ti layer is 30nm, and the deposition thickness of the Al layer is 470nm;

[0176] Subsequently, SiN was deposited on the resulting structure a second time using LPCVD. x A second passivation layer is formed to completely cover the metal material, and the deposition thickness of the second passivation layer on the metal material is 200nm; then, CF4 is used as an etching gas to perform ICP etching on the second passivation layer to form a plurality of openings, and the openings penetrate to the first source electrode and the second drain electrode; finally, metal material Ti / Al is deposited to fill the plurality of openings, so that the first source electrode is connected to the second drain electrode through the metal material, and the deposition thickness of the Ti layer is 30nm, and the deposition thickness of the Al layer is 470nm.

[0177] Finally, a second passivation layer is deposited again on the obtained structure using LPCVD to completely cover the metal material; then, CF4 is used as an etching gas to perform ICP etching in the second passivation layer to form a number of openings to expose the first drain electrode, the second gate electrode, and the second source electrode, which serve as the drain electrode, gate electrode, and source electrode of the N-polarity enhancement mode HEMT device, respectively.

[0178] Comparative Example 1

[0179] This comparative example provides an N-polarity enhancement mode HEMT device, and the preparation method is basically the same as that of Example 1, except that:

[0180] (1) A first substrate is provided, and a second substrate is a P-type Si substrate, on the surface of which an AlN nucleation layer, a GaN stress regulation layer, a GaN layer and an AlN layer are sequentially deposited by MOCVD x Ga 1-x N layer (x = 0.25), wherein the deposition thickness of the AlN nucleation layer is 40nm, the thickness of the GaN stress regulation layer is 700nm, the deposition thickness of the GaN layer is 2.5μm, and the Al x Ga 1-x The deposition thickness of the N layer is 25 nm;

[0181] (2) The Ga-polar GaN surface is exposed on the surface, and Cl2 and BCl3 are used as etching gases to perform ICP etching on the GaN layer to reduce its thickness to 65 nm;

[0182] Then, prepare according to steps (6) to (11) in Example 1.

[0183] The energy band diagram of GaN and AlGaN at the N-polar interface in the N-polar enhancement mode HEMT device obtained in Example 1 is shown in FIG. Fig. 27 As shown in FIG. 1 , GaN and AlGaN have a high back barrier at a depth of 30-50 nm at the N-polar interface, and a naturally localized 2DEG. The energy band diagram of GaN and AlGaN at the Ga-polar interface in the enhanced HEMT device obtained in comparative example 1 is shown in FIG. Fig.28 As shown in the figure, GaN and AlGaN have a very small back barrier at a depth of 20-30nm at the Ga polar interface, and the localization effect is poor. Comparative analysis shows that the height of the back barrier formed at the N polar interface is significantly higher than that formed at the Ga polar interface, indicating that the N polar surface naturally has an AlGaN back barrier, which can better localize channel electrons and prevent leakage. In addition, compared with AlGaN, the bandgap is narrower, it is easier to form ohmic contact, control the channel, and have low contact resistance.

[0184] The drain resistance Rc of the N-polarity enhancement-mode HEMT devices obtained in Example 1 and Comparative Example 1 was tested. In Example 1, Rc=0.39Ωmm; in Comparative Example 1, Rc=0.5Ωmm, indicating that the resistance of the ohmic contact formed by the Ga-polarity enhancement-mode HEMT device is greater than the resistance of the ohmic contact formed by the N-polarity enhancement-mode HEMT device.

[0185] Example 2

[0186] This embodiment provides an N-polarity enhancement mode HEMT device, and the preparation method is basically the same as that of Embodiment 1, except that:

[0187] (4) The two SiO2 layers after treatment are bonded by hot pressing at 300°C and 1MP pressure for 60 minutes, followed by high temperature annealing at 600°C.

[0188] Example 3

[0189] This embodiment provides an N-polarity enhancement mode HEMT device, and the preparation method is basically the same as that of Embodiment 1, except that:

[0190] (4) The two treated SiO2 layers are bonded by hot pressing at 370°C and a pressure of 5MP, and the specific pressure application time is 40 minutes.

[0191] The drain resistance Rc of the N-polarity enhancement-mode HEMT devices obtained in Example 2 and Example 3 was tested. In Example 2, Rc=0.33Ωmm; in Example 3, Rc=31Ωmm. It can be seen that adjusting the hot-pressing bonding process of the SiO2 layer will affect the combination of the first substrate and the heterostructure, change the stress state, obtain different bonding layer products, and affect the drain resistance of the N-polarity enhancement-mode HEMT device, thereby affecting the performance of the N-polarity enhancement-mode HEMT device.

[0192] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An N-polarity enhancement mode HEMT device, characterized in that: The method comprises a first substrate, wherein the first substrate comprises first regions and second regions which are alternately arranged in sequence, and an isolation groove is formed between the first regions and the second regions; A SiO2 layer, a first passivation layer, a back barrier layer, and a GaN layer are sequentially arranged on the first region of the first substrate, and a first source electrode, a first drain electrode, and a first gate electrode are arranged on the GaN layer; The second region of the first substrate comprises a source-drain region and a substrate region, wherein the source-drain region is disposed on both sides of the substrate region and isolated from each other by the substrate region; a SiO2 layer is disposed on the substrate region, a second source electrode and a second drain electrode are disposed on the source-drain region, and a second gate electrode is disposed on the SiO2 layer; The first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode.

2. The N-polarity enhancement-mode HEMT device according to claim 1, characterized in that: The thickness of the SiO2 layer provided on the first region is 200nm-500nm; the thickness of the SiO2 layer provided on the second region is 200nm-500nm.

3. The N-polarity enhancement-mode HEMT device according to claim 1, characterized in that: The distance between the first source electrode and the first drain electrode is 10 μm-15 μm; The distance between the first source electrode and the first gate electrode is 1 μm-3 μm; The length of the first gate electrode is 0.8 μm-1.3 μm.

4. The N-polarity enhancement mode HEMT device according to claim 1, characterized in that: The doping concentration in the source and drain regions is 1×10 12 ions / cm 2 -1×10 15 ions / cm 2 ; The depth of the isolation groove is 90nm-110nm.

5. The N-polarity enhancement-mode HEMT device according to claim 1, characterized in that: The first passivation layer is an AlN layer, and the thickness of the first passivation layer is 500nm-800nm; The back barrier layer is Al x Ga 1-x N layer, wherein x=0.18-0.30, and the thickness of the back barrier layer is 20nm-30nm.

6. A method for preparing an N-polarity enhancement mode HEMT device according to any one of claims 1 to 5, characterized in that: include: providing a first substrate; Providing a second substrate and growing a heterostructure on the surface of the second substrate, wherein the heterostructure includes a nucleation layer, a GaN layer, a back barrier layer and a first passivation layer deposited in sequence; Depositing SiO2 layers on the heterostructure and the first substrate respectively; Performing a hot pressing process on the SiO2 layer on the heterostructure and the SiO2 layer on the first substrate; removing the second substrate and the nucleation layer to expose the N-polar surface of the GaN layer, and reducing the thickness of the GaN layer; Etching part of the GaN layer downward to form a plurality of groove structures arranged at intervals, wherein the groove structures expose the SiO2 layer, and forming a plurality of protruding structures between the groove structures, and then etching the sidewalls of the GaN layer in the protruding structures and part of the sidewalls of the back barrier layer to form a mesa isolation region; A first source electrode, a first drain electrode, and a first gate electrode are correspondingly manufactured on the surface of the GaN layer in the protruding structure; Etching a portion of the SiO2 layer in the groove structure downward to the inside of the first substrate to form an isolation groove, wherein the isolation groove divides the first substrate into a first region and a second region that are alternately arranged, the protruding structure is located on the first region, and the groove structure is located on the second region; Etching a portion of the SiO2 layer of the groove structure downwards until the first substrate is exposed, forming at least two ion implantation windows separated by the SiO2 layer, and doping the ion implantation windows to form source and drain regions; A second source electrode and a second drain electrode are fabricated on the source and drain regions, and a second gate electrode is correspondingly fabricated on the SiO2 layer in the groove structure; The first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode.

7. The method for preparing an N-polarity enhancement mode HEMT device according to claim 6, characterized in that: The hot pressing treatment comprises: The SiO2 layer on the heterostructure and the SiO2 layer on the first substrate are pressed together at 300°C-450°C and a pressure of 1MPa-10MPa for 20min-60min, and then annealed at a high temperature of 450°C-600°C.

8. The method for preparing an N-polarity enhancement mode HEMT device according to claim 6, characterized in that: The hot pressing treatment comprises: Before the hot pressing treatment, the SiO2 layer deposited on the heterostructure and / or the first substrate is subjected to micro-roughening treatment to make the roughness of the SiO2 layer less than 0.5 nm.

9. The method for preparing an N-polarity enhancement mode HEMT device according to any one of claims 6 to 8, characterized in that: The deposited thickness of the GaN layer is 2 μm-3 μm, and the thickness of the GaN layer after thinning is 50 nm-80 nm; And / or, the method of removing the second substrate and the nucleation layer in the heterostructure comprises laser lift-off; The nucleation layer is an AlN layer, and the thickness of the nucleation layer is 20nm-50nm.

10. The method for preparing an N-polarity enhancement mode HEMT device according to claim 6, characterized in that: The first gate electrode is electrically connected to the second source electrode, and the first source electrode is electrically connected to the second drain electrode, comprising: Depositing a second passivation layer, then forming openings in the first gate electrode, the second source electrode, the second drain electrode, and the second gate electrode corresponding regions, depositing a metal material at the openings, so that the first gate electrode is electrically connected to the second source electrode through the metal material; A second passivation layer is deposited, and then openings are formed in the regions corresponding to the first source electrode and the second gate electrode, and a metal material is deposited in the openings, so that the first source electrode is electrically connected to the second drain electrode through the metal material.

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