Display panel and display device

Abstract

The application provides a display panel and a display device. An active layer of a first initialization transistor of a first pixel circuit is connected with an active layer of a second initialization transistor of a second pixel circuit through a first connecting line, so as to connect the active layers of the initialization transistors in different regions together. After one of the initialization transistors is connected to an initialization signal, the initialization signal can be transmitted to the other initialization transistor through the first connecting line, thereby avoiding the problem that the initialization signal is transmitted only through a signal line with a voltage drop, and the problem that the initialization signals input by the initialization transistors in different regions are greatly different. The uniformity of the initialization signals input by the initialization transistors in different regions of the display panel is high.

Description

[0001] This application is a divisional application of application number 202111075596.8, filed on September 14, 2021, entitled "Display Panel and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0003] Existing display devices include peripheral driving circuitry in their bezel area to provide driving signals to the pixel units in the display area. In a display device, multiple pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuitry in the bezel area. The peripheral driving circuitry provides scanning control signals and light emission control signals to the pixel circuitry to control the pixel circuitry to provide driving current to the light-emitting element.

[0004] The pixel circuit also includes an initialization transistor. When initializing the pixel circuit, an initialization signal needs to be applied to the initialization transistor, which then selectively transmits the initialization signal to a preset node in the pixel circuit. Therefore, a separate signal line is required in the display device to apply the initialization signal to the initialization transistor. In existing display devices, the initialization signal is generally provided by an integrated circuit chip (IC). Considering the voltage drop on the signal line, the initialization signal is inconsistent between the points near and far from the IC. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and display device, which effectively solves the technical problems existing in the prior art and ensures high uniformity of the initialization signals connected to the initialization transistors in different areas of the display panel.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0007] A display panel, comprising:

[0008] Pixel circuits and light-emitting elements;

[0009] The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is used to provide an initialization signal for a preset node, which is either the gate of the driving transistor or the anode of the light-emitting element.

[0010] The pixel circuit includes an oxide semiconductor transistor and a silicon transistor, wherein the active layer of the oxide semiconductor transistor comprises oxide semiconductor and the active layer of the silicon transistor comprises silicon.

[0011] The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor, and the second pixel circuit includes a second initialization transistor. The active layer of the first initialization transistor and the active layer of the second initialization transistor are connected by a first connection line. At least a portion of the first connection line is located on the same layer as the active layer of the oxide semiconductor transistor.

[0012] Accordingly, the present invention also provides a display device including the display panel described above.

[0013] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0014] This invention provides a display panel and a display device. The active layer of the first initialization transistor of the first pixel circuit is connected to the active layer of the second initialization transistor of the second pixel circuit through a first connecting line, so as to connect the active layers of the initialization transistors in different areas together. Thus, after one initialization transistor receives an initialization signal, the initialization signal can be transmitted to the other initialization transistor through the first connecting line. This avoids the problem of large differences in the initialization signals received by the initialization transistors in different areas due to transmitting the initialization signal only through a signal line with a voltage drop, and ensures high uniformity of the initialization signals received by the initialization transistors in different areas of the display panel.

[0015] Meanwhile, connecting the active layers of the first initialization transistor and the second initialization transistor via the first connection line can appropriately reduce the number of signal lines transmitting the initialization signal, which helps to reduce the line density of the display panel and thus improve resolution. Furthermore, in the event of a break in the signal line transmitting the initialization signal, the initialization signal can still be transmitted to the connected initialization transistor via the first connection line, improving the flexibility and reliability of the circuit.

[0016] Furthermore, at least a portion of the first connection line provided by the present invention is located on the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connection line, the first connection line can be used as a trace to connect the two active layers, thereby eliminating the need to separately prepare a conductive thin film for making the first connection line, reducing the process flow for preparing the display panel, and avoiding increasing the trace layout burden of other conductive film layers. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0028] Figure 11 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0029] Figure 12 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0030] Figure 13 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0031] Figure 14This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0032] Figure 15 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0033] Figure 16 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0034] Figure 17 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0035] Figure 18 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0036] Figure 19 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0037] Figure 20 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0038] Figure 21 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present invention;

[0039] Figure 22 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] As described in the background section, the pixel circuit also includes an initialization transistor. When initializing the pixel circuit, an initialization signal needs to be applied to the initialization transistor, which then selectively transmits the initialization signal to a preset node in the pixel circuit. Therefore, a separate signal line is required in the display device to apply the initialization signal to the initialization transistor. In existing display devices, the initialization signal is generally provided by an integrated circuit chip (IC). Considering the voltage drop on the signal line, the initialization signal exhibits inconsistencies between the points near and far from the IC.

[0042] Based on this, embodiments of the present invention provide a display panel and a display device, which effectively solves the technical problems existing in the prior art and ensures high uniformity of the initialization signals connected to the initialization transistors in different areas of the display panel.

[0043] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 22 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0044] Combination Figures 1 to 4 As shown, Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 4 A schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, wherein the display panel includes:

[0045] The display area AA and the border area NA surrounding the display area AA include a pixel circuit 10 and a light-emitting element 20.

[0046] The pixel circuit 10 includes a driving transistor T0 and an initialization transistor Tx. The initialization transistor Tx is used to provide an initialization signal to a preset node Q, where the preset node Q is the gate of the driving transistor T0 (e.g., ...). Figure 3 (as shown) or the anode of the light-emitting element 20 (such as Figure 4 (As shown).

[0047] The pixel circuit 10 includes an oxide semiconductor transistor (IGZO) and a silicon TFT (SiTFT). The active layer of the IGZO comprises an oxide semiconductor, and the active layer of the SiTFT comprises silicon. The display panel includes a substrate 100; a silicon semiconductor layer 211 on the substrate 100, the silicon semiconductor layer 211 including the active layer of the SiTFT; a first insulating layer 212 on the side of the silicon semiconductor layer 211 facing away from the substrate 100; a first gate metal layer 213 on the side of the first insulating layer 212 facing away from the substrate 100, the first gate metal layer 213 including the gate of the SiTFT; a second insulating layer 214 on the side of the first gate metal layer 213 facing away from the substrate 100; a capacitor metal layer 215 on the side of the second insulating layer 214 facing away from the substrate 100, the capacitor metal layer 215 including one electrode of a storage capacitor C, the other electrode of the storage capacitor C may be made of the first gate metal layer 213 or other conductive layers; and a capacitor metal layer 215 on the side of the second insulating layer 214 facing away from the substrate 100, the capacitor metal layer 215 including one electrode of a storage capacitor C, the other electrode of the storage capacitor C may be made of the first gate metal layer 213 or other conductive layers; and a capacitor metal layer 215 on the side of the capacitor metal layer 215 facing away from the substrate 100. A third insulating layer 216 on one side of the substrate 100; an oxide semiconductor layer 217 on the side of the third insulating layer 216 away from the substrate 100, the oxide semiconductor layer 217 including an active layer of an oxide semiconductor transistor IGZO; a fourth insulating layer 218 on the side of the oxide semiconductor layer 217 away from the substrate 100; a second gate metal layer 219 on the side of the fourth insulating layer 218 away from the substrate 100, the second gate metal layer 219 including a gate of an oxide semiconductor transistor IGZO; a fifth insulating layer 220 on the side of the second gate metal layer 219 away from the substrate 100; a source / drain metal layer 221 on the side of the fifth insulating layer 220 away from the substrate 100, the source / drain metal layer 221 including the source and drain of an oxide semiconductor transistor IGZO and a silicon TFT.

[0048] The pixel circuit 10 includes a first pixel circuit 11 and a second pixel circuit 12. The first pixel circuit 11 includes a first initialization transistor, and the second pixel circuit 12 includes a second initialization transistor. The active layer of the first initialization transistor and the active layer of the second initialization transistor are connected by a first connection line 30. At least a portion of the first connection line 30 is located on the same layer as the active layer of the oxide semiconductor transistor.

[0049] It is understood that the active layer of the first initialization transistor of the first pixel circuit provided in the embodiments of the present invention is connected to the active layer of the second initialization transistor of the second pixel circuit through a first connection line, so as to connect the active layers of the initialization transistors in different regions together. In this way, after one initialization transistor receives an initialization signal, the initialization signal can be transmitted to the other initialization transistor through the first connection line, thereby avoiding the problem of large differences in the initialization signals received by the initialization transistors in different regions due to transmitting the initialization signal only through a signal line with a voltage drop. This ensures high uniformity of the initialization signals received by the initialization transistors in different regions of the display panel.

[0050] Meanwhile, connecting the active layers of the first initialization transistor and the second initialization transistor via the first connection line can appropriately reduce the number of signal lines transmitting the initialization signal, which helps to reduce the line density of the display panel and thus improve resolution. Furthermore, in the event of a break in the signal line transmitting the initialization signal, the initialization signal can still be transmitted to the connected initialization transistor via the first connection line, improving the flexibility and reliability of the circuit.

[0051] Furthermore, at least a portion of the first connection line provided in this embodiment of the invention is located on the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connection line, the first connection line can be used as a trace to connect the two active layers, thereby eliminating the need to separately prepare a conductive film for fabricating the first connection line, reducing the process flow for fabricating the display panel, and avoiding increasing the trace layout burden of other conductive film layers.

[0052] like Figure 3 or Figure 4As shown, the pixel circuit 10 provided in this embodiment of the invention includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor T0, an initialization transistor Mx, and a holding capacitor C. The driving transistor T0 is used to provide driving current to the light-emitting element 20; the initialization transistor Mx is used to initialize and reset the pixel circuit 10. The first electrode of the first transistor T1 is connected to the data signal Vdata, the second electrode of the first transistor T1 is connected to the first electrode of the driving transistor T0, and the gate of the first transistor T1 is connected to the first scan signal K1. The first electrode of the second transistor T2 is connected to the second electrode of the driving transistor T0, the second electrode of the second transistor T2 is connected to the gate of the driving transistor T0, and the gate of the second transistor T2 is connected to the second scan signal K2. The gates of the third transistor T3 and the fourth transistor T4 are connected to the light-emitting control signal EM. The first electrode of the third transistor T3 is connected to the first power supply signal PVDD. The second electrode of the third transistor T3 is connected to the source of the driving transistor T0. The first electrode of the fourth transistor T4 is connected to the drain of the driving transistor T0. The second electrode of the fourth transistor T4 is connected to one end of the light-emitting element 20, and the other end of the light-emitting element 20 is connected to the second power supply signal PVEE. The light-emitting control signal EM is a pulse signal. During a valid pulse, the light-emitting control signal EM controls the third transistor T3 and the fourth transistor T4 to conduct, and the light-emitting element 20 is in the light-emitting stage. During an invalid pulse, the light-emitting control signal EM controls the third transistor T3 and the fourth transistor T4 to turn off, and the light-emitting element 20 is in the non-light-emitting stage. A holding capacitor C is also included, which maintains the node potential. The first end of the holding capacitor C is connected to the first power supply signal PVDD, and the second end of the holding capacitor C is connected to the gate of the driving transistor T0.

[0053] like Figure 3As shown, in this embodiment of the invention, the gate of the initialization transistor Tx is connected to the initialization control signal Kx, the first electrode of the initialization transistor Tx is connected to the initialization signal Vref, and the second electrode of the initialization transistor Tx is electrically connected to the gate of the driving transistor T0, wherein the preset node Q is the gate of the driving transistor T0. The operation of the pixel circuit 10 includes an initialization stage, a data writing stage, and a light-emitting stage. In the initialization stage, the initialization transistor Tx transmits the initialization signal Vref to the gate of the driving transistor T0 to perform initialization and reset processing on the driving transistor T0. At the same time, the first transistor T1 to the fourth transistor T4 are in the off state. Then, in the data writing stage, the first transistor T1 and the second transistor T2 are turned on. The first transistor T1 transmits the data signal Vdata to the first electrode of the driving transistor T0. The second transistor T2 connects the gate and the second electrode of the driving transistor T0. At the same time, the initialization transistor Tx, the third transistor T3, and the fourth transistor T4 are in the off state. Finally, in the light-emitting stage, the third transistor T3 and the fourth transistor T4 are turned on, opening the path from the driving transistor T0 to the light-emitting element 20, driving the light-emitting element 20 to emit light. The light-emitting element 20 can be a light-emitting diode.

[0054] like Figure 4 As shown, in this embodiment of the invention, the gate of the initialization transistor Tx is connected to the initialization control signal Kx, the first electrode of the initialization transistor Tx is connected to the initialization signal Vref, and the second electrode of the initialization transistor Tx is electrically connected to the anode of the light-emitting element 20, wherein the preset node Q is the anode of the light-emitting element 20. The operation of the pixel circuit 10 includes an initialization stage, a data writing stage, and a light-emitting stage. In the initialization stage, the initialization transistor Tx transmits the initialization signal Vref to the anode of the light-emitting element 20 to initialize and reset the pixel circuit 10. At the same time, the first transistor T1 to the fourth transistor T4 are in the off state. Then, in the data writing stage, the first transistor T1 and the second transistor T2 are turned on. The first transistor T1 transmits the data signal Vdata to the first electrode of the driving transistor T0. The second transistor T2 connects the gate and the second electrode of the driving transistor T0. At the same time, the initialization transistor Tx, the third transistor T3, and the fourth transistor T4 are in the off state. Finally, in the light-emitting stage, the third transistor T3 and the fourth transistor T4 are turned on, opening the path from the driving current generated by the driving transistor T0 to the light-emitting element 20, driving the light-emitting element 20 to emit light. The light-emitting element 20 can be a light-emitting diode.

[0055] It should be noted that the pixel circuit provided by this invention is not limited to... Figure 2 and Figure 3 The two shown can also be other circuit structures, and the specific selection should be based on the actual application.

[0056] In one embodiment of the present invention, the initialization transistor provided by the present invention can be an oxide semiconductor transistor. Optionally, both the first connection line and the active layer of the initialization transistor comprise oxide semiconductor; and the conductivity of the first connection line is greater than the conductivity of the channel region of the active layer of the initialization transistor. Figure 5 As shown, the first initialization transistor Mx1 and the second initialization transistor Mx2 provided in this embodiment of the invention are both oxide semiconductor transistors. The active layers of the first initialization transistor Mx1 and the second initialization transistor Mx2 are connected by a first connection line 30, and the first connection line 30 is located on the same layer as the active layer of the oxide semiconductor transistor. Furthermore, the conductivity of the first connection line 30 is controlled during its fabrication to ensure that the conductivity of the first connection line 30 is greater than the conductivity of the channel region of the active layer of the initialization transistor, thereby guaranteeing high signal transmission performance of the first connection line 30.

[0057] like Figure 6 The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 provided in this embodiment are arranged along a first direction X. The first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuits provided in this embodiment can be arranged in a multi-row * multi-column array, where the first direction X can be the extension direction of the pixel circuit rows (i.e., the arrangement direction of multiple pixel circuit columns). Therefore, when one of the first pixel circuit 11 and the second pixel circuit 12 receives an initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits in the same row are connected together, when one of them receives an initialization signal, all pixel circuits in that row receive the initialization signal, further reducing the number of signal lines.

[0058] Alternatively, the first direction provided in this embodiment of the invention can also be the extending direction of the pixel circuit array. For example... Figure 7The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X. The first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuits provided in this embodiment can be arranged in a multi-row * multi-column array, where the first direction X can be the extension direction of a column of pixel circuits (i.e., the arrangement direction of multiple rows of pixel circuits). Therefore, when one of the first pixel circuit 11 and the second pixel circuit 12 receives an initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits in the same column are connected together, when one of them receives an initialization signal, all pixel circuits in that column receive the initialization signal, further reducing the number of signal lines.

[0059] Alternatively, the first direction provided in the embodiments of the present invention can also be oblique. For example... Figure 8 The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X. The first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuits provided in this embodiment can be arranged in a multi-row * multi-column array. The first direction X can be an oblique direction intersecting the row or column direction at an angle less than 90 degrees. Therefore, when one of the first pixel circuit 11 and the second pixel circuit 12 receives an initialization signal, the other pixel circuit also receives the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits along the first direction X are connected together, when one of them receives an initialization signal, all connected pixel circuits receive the initialization signal, further reducing the number of signal lines.

[0060] like Figure 9 The diagram shows a structural schematic of another display panel provided in an embodiment of the present invention. The display panel includes a first signal line 41 extending along the first direction X, and the first signal line 41 provides a control signal or input signal to the pixel circuit 10. The first signal line 41 does not overlap with the first connecting line 30. This avoids parasitic capacitance between the first signal line 41 and the first connecting line 30, ensuring high signal transmission stability between the first signal line 41 and the first connecting line 30.

[0061] It should be noted that the first signal line provided in this embodiment of the invention can transmit control signals generated by the driving circuit of the display panel, such as... Figure 2 and 3 The pixel circuit 10 shown is connected to the first control signal K1, the second control signal K2, the initialization control signal Kx, the light emission control signal EM, etc., or the first signal line can transmit input signals, such as... Figure 2 and 3 The pixel circuit 10 shown is connected to power signals, initialization signals Vref, data signals Vdata, etc.

[0062] In one embodiment of the present invention, the display panel provided by the present invention can not only connect the active layers of the initialization transistors of pixel circuits in the same direction, but also connect the active layers of the initialization transistors of pixel circuits in different directions. For example... Figure 10 The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X. The first connecting line 30 extends from the active layer Mx10 of the first initialization transistor along the first direction X to the active layer Mx20 of the second initialization transistor. The pixel circuit also includes a third pixel circuit 13, which includes a third initialization transistor. The first pixel circuit 11 and the third pixel circuit 13 are arranged along a second direction Y, where the first direction X intersects the second direction Y. The active layer Mx10 of the first initialization transistor and the active layer Mx30 of the third initialization transistor are connected by a second connecting line 32 extending along the second direction Y, and at least a portion of the second connecting line 32 is located on the same layer as the active layer of the initialization transistor.

[0063] Optionally, the pixel circuits provided in this embodiment of the invention can be arranged in a multi-row * multi-column array, where the first direction X can be the extension direction of the pixel circuit rows (i.e., the arrangement direction of multiple pixel circuit columns), and the second direction Y can be the extension direction of the pixel circuit columns. Thus, when one of the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 receives an initialization signal, the other two pixel circuits also receive the initialization signal, thereby reducing the number of signal lines. Furthermore, when the active layers of the initialization transistors of all pixel circuits are connected together, when one of them receives an initialization signal, all pixel circuits receive the initialization signal, transmitting the initialization signal to the pixel circuits of the entire display panel, further reducing the number of signal lines.

[0064] like Figure 11The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The display panel includes an integrated circuit (IC), located on one side of the display area AA of the display panel along the second direction Y. The IC provides the initialization signal to the pixel circuit 10. The width of the second connecting line 32 is greater than the width of the first connecting line 30. Since the extension direction of the second connecting line 32 is the same as the second direction Y, the second connecting line 32 includes a near-IC end and a far-IC end. Therefore, by making the width of the second connecting line 32 greater than the width of the first connecting line 30, the present invention ensures a lower impedance for the second connecting line 32, reducing voltage drop on the second connecting line 32 and ensuring high signal consistency. Simultaneously, narrowing the line width of the first connecting line 30 reduces the area occupied by the line, ensuring high resolution of the display panel.

[0065] like Figure 12 The diagram shows a structural schematic of another display panel provided in an embodiment of the present invention. The display panel includes a second signal line 42 extending along the second direction Y, and the second signal line 42 provides a control signal or input signal to the pixel circuit 10. The second connecting line 32 and the second signal line 42 do not overlap. This avoids parasitic capacitance between the second signal line 42 and the second connecting line 32, ensuring high signal transmission stability between the second signal line 42 and the second connecting line 32. The signals transmitted by the first and second signal lines provided in this embodiment can be specifically selected according to actual applications, and the present invention does not impose specific limitations on this.

[0066] like Figure 13The diagram shows a schematic representation of another display panel according to an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X. At least a portion of the first connecting line 30 is a curve or a broken line. The first connecting line 30 includes a first sub-connecting line segment 301, which extends along the first direction X. The display panel includes a signal line 43 that provides control signals or input signals to the pixel circuit 10 and extends along the first direction X. The first sub-connecting line 301 and the signal line 43 do not overlap. The display panel provided by this embodiment can configure the first connecting line 30 as a broken line or curve to optimize the overlap area between the first connecting line 30 and the signal line 43 to be smaller. For example, the first sub-connecting line 301 extends in the same direction as the signal line 43, while another line segment overlaps with the signal line 43 in a cross-shaped manner, ensuring a small overlap area between the first connecting line 30 and the signal line 43 and thus a small parasitic capacitance between them.

[0067] like Figure 14 The diagram shows a schematic representation of another display panel according to an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X. The display panel also includes an initialization signal line 44 extending along the first direction X, used to provide the initialization signal to the initialization transistor. The initialization signal line 44 at least partially overlaps with the first connecting line 30. Both the initialization signal line 44 and the first connecting line 30 are used to transmit the initialization signal. Their overlapping arrangement is equivalent to connecting a line in parallel with the initialization signal line to transmit the same signal. This saves panel space, reduces the voltage drop on the initialization signal line 44, and ensures high stability of the transmitted signal.

[0068] Or such as Figure 15The diagram shows a schematic representation of another display panel according to an embodiment of the present invention. The first pixel circuit 11 and the second pixel circuit 12 are arranged along a first direction X, and the first connecting line 30 extends along the first direction X. The display panel also includes an initialization signal line 44 extending along a second direction Y, used to provide initialization signals to the initialization transistors. The first direction X and the second direction Y intersect. The pixel circuits provided in this embodiment can be arranged in a multi-row * multi-column array, where the first direction X can be the extension direction of a row of pixel circuits (i.e., the arrangement direction of multiple columns of pixel circuits), and the second direction Y can be the extension direction of a column of pixel circuits. In this embodiment, the active layers of the initialization transistors in the pixel circuit 10 along the first direction X are connected via the first connecting line 30, and the initialization transistors in the pixel circuit 10 along the second direction Y are connected to the initialization signal line 44. Thus, the active layers of all the initialization transistors are formed into a connectivity grid through the first connecting line 30 and the initialization signal line 44. When the initialization signal line 44 provides an initialization signal, the initialization signal is transmitted in both the first direction X and the second direction Y, improving the consistency of initialization signal reception across the display panel.

[0069] In one embodiment of the present invention, such as Figure 3 As shown, the preset node Q provided by the present invention is the gate of the driving transistor; wherein, the driving transistor T0 is a PMOS type transistor, and there is no overlap between the first connection line 30 and the active layer of the silicon transistor SiTFT in the pixel circuit 10; specifically, the silicon transistor SiTFT is generally a PMOS type transistor. When the driving transistor T0 is a PMOS type transistor, the initialization signal is a low level signal to initialize it. At this time, a low level signal is transmitted on the first connection line 30. If it overlaps with the active layer of the PMOS type silicon transistor SiTFT, it will cause the PMOS type silicon transistor SiTFT, which was originally in the off state, to turn on, affecting the normal operation of the circuit.

[0070] Alternatively, the driving transistor T0 may be an NMOS transistor, and there may be no overlap between the first connection line 30 and the active layer of the oxide semiconductor transistor IGZO in the pixel circuit 10. Specifically, the oxide semiconductor transistor IGZO is generally an NMOS transistor. When the driving transistor T0 is an NMOS transistor, the initialization signal is a high-level signal for initialization processing. At this time, a high-level signal is transmitted on the first connection line 30. If it overlaps with the active layer of the NMOS type oxide semiconductor transistor IGZO, it will cause the NMOS type oxide semiconductor transistor IGZO, which was originally in the off state, to turn on, affecting the normal operation of the circuit.

[0071] In one embodiment of the present invention, such as Figure 4 As shown in the embodiment of the present invention, the preset node Q is the anode of the light-emitting element 20; there is no overlap between the first connection line 30 and the active layer of the silicon TFT in the pixel circuit 10. Specifically, the anode of the light-emitting element 20 is initialized with a low-level signal. At this time, a low-level signal is transmitted on the first connection line 30. If it overlaps with the active layer of the PMOS silicon TFT, it will cause the PMOS silicon TFT, which was originally in the off state, to turn on, affecting the normal operation of the circuit.

[0072] like Figure 16 The diagram shows a structural schematic of another display panel provided by an embodiment of the present invention. In the active layer of the initialization transistor provided by the embodiment of the present invention, its connection position is fixed. The portion 311 of the active layer Mx10 of the first initialization transistor and the active layer Mx20 of the second initialization transistor connected to the first connection line 30 extends along a third direction S, and the remaining portion 312 of the first connection line 30 extends along a fourth direction Z. The third direction S intersects with the fourth direction Z. Therefore, it is possible to avoid the situation where the first connection line 30 covers the active layer when it extends in the same direction as the active layer, thus avoiding the generation of additional parasitic capacitance and facilitating the connection between the active layer and the first connection line 30.

[0073] like Figure 17 The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The pixel circuit 10 includes pixel circuit groups 101 arranged repeatedly along a fifth direction H. Each pixel circuit group 101 includes a first pixel circuit 11 and a second pixel circuit 12 arranged adjacent to each other. Along the fifth direction H, the distance d1 between the active layers of the initialization transistors of two adjacent pixel circuit groups 101 is greater than the distance d2 between the active layers of the initialization transistors in the first pixel circuit 11 and the second pixel circuit 12 within the pixel circuit group 101. The active layers of the initialization transistors of the pixel circuits in two adjacent pixel circuit groups 101 are not connected by the first connecting line 30.

[0074] like Figure 18The diagram shown is a structural schematic of another display panel provided in an embodiment of the present invention. The display panel provided in this embodiment includes a first voltage signal line and a data signal line. The first voltage signal line is used to provide a first voltage signal PVDD to the pixel circuit 10, and the data signal line is used to provide a data signal Vdata to the pixel circuit. The first connecting line 30 extends in the same direction as the first voltage signal line and the data signal line, and there is no overlap between the first connecting line 30 and the first voltage signal line and the data signal line.

[0075] It is understood that the first connecting line provided in the embodiments of the present invention does not overlap with the first voltage signal line and the data signal line, thereby avoiding the formation of parasitic capacitance between the first connecting line and the first voltage signal line and the data signal line, and ensuring the stability of signal transmission of each line.

[0076] Alternatively, in one embodiment of the present invention, the overlap area S1 between the first connecting line and the first voltage signal line is greater than the overlap area S2 between the first connecting line and the data signal line, where S2 ≥ 0. The signal PVDD transmitted by the first voltage signal line is a fixed potential signal and is relatively stable, while the signal Vdata transmitted by the data signal line is variable. The parasitic capacitance generated by the overlap between the first connecting line and the data signal line will cause interference, affecting the stability of the signal Vdata that determines the magnitude of the drive current. Therefore, the overlap area between the first connecting line and the first voltage signal line is designed to be greater than the overlap area between the first connecting line and the data signal line.

[0077] like Figure 19 The diagram shows a schematic representation of another display panel according to an embodiment of the present invention. The first connecting line 30 provided in this embodiment includes a first sub-segment 313 and a second sub-segment 314. The first sub-segment 313 is directly connected to the active layer Mx10 of the first initialization transistor, and also includes a portion connected to the active layer Mx20 of the second initialization transistor. The second sub-segment 314 is located on the side of the first sub-segment 313 away from the active layer Mx10 of the first initialization transistor. The width of the second sub-segment 314 is greater than the width of the first sub-segment 313. Furthermore, by setting the width of the second sub-segment 314 to be greater than the width of the first sub-segment 313, the impedance of the first connecting line 30 can be reduced, and the area of ​​the pixel circuit 10 can be avoided from being increased.

[0078] like Figure 20The diagram shows a schematic representation of another display panel provided in an embodiment of the present invention. The pixel circuit provided in this embodiment further includes a first conductive layer 50, located on the side of the active layer of the silicon TFT (SiTFT) facing the substrate 100 of the display panel. The first connecting line 30 is interconnected with the first conductive layer 50. In the display panel provided in this embodiment, the first conductive layer 50 is disposed below the active layer of the silicon TFT. A fixed signal can be applied to the first conductive layer 50, thereby improving the stability of the silicon TFT. Therefore, this embodiment connects the first connecting line 30 to the first conductive layer 50 to transmit a fixed potential initialization signal to the first conductive layer 50, avoiding the need for a separate trace for signal transmission on the first conductive layer 50. In particular, a metal trace for signal transmission would affect the transmittance of the display panel.

[0079] like Figure 21 The diagram shown illustrates the structure of another display panel according to an embodiment of the present invention. The display panel includes a first display area AA1 and a second display area AA2. The second display area AA2 is correspondingly equipped with a camera element or a light-sensitive fingerprint recognition element. The first pixel circuit 11 and the second pixel circuit 12 are located in the second display area AA2. The display panel provided by this embodiment includes an under-display camera area or an under-display fingerprint recognition area. Since this area requires high transmittance, it is necessary to reduce the number of traces. To address this, a light-transmitting first connecting line can be used to replace the existing signal line transmitting the initialization signal, thereby increasing the transmittance of this area.

[0080] like Figure 21 As shown, the first display area AA1 includes an initialization signal line 44 that provides an initialization signal for the initialization transistor. The initialization signal line 44 is connected to the active layer Mx10 of the first initialization transistor, and the active layer Mx10 of the first initialization transistor is connected to the active layer Mx20 of the second initialization transistor through the first connection line 30.

[0081] Accordingly, embodiments of the present invention also provide a display device, including the display panel provided in any of the above embodiments.

[0082] like Figure 22 The diagram shown is a structural schematic of a display device provided in an embodiment of the present invention, wherein the display device 1000 provided in the embodiment of the present invention can be a mobile terminal device.

[0083] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, computer, or vehicle terminal, and the present invention does not impose specific limitations on it.

[0084] This invention provides a display panel and a display device. The active layer of the first initialization transistor of the first pixel circuit and the active layer of the second initialization transistor of the second pixel circuit are connected by a first connecting line to connect the active layers of the initialization transistors in different areas. Thus, after one initialization transistor receives an initialization signal, the initialization signal can be transmitted to the other initialization transistor through the first connecting line. This avoids the problem of large differences in the initialization signals received by the initialization transistors in different areas due to transmitting the initialization signal only through a signal line with a voltage drop, and ensures high uniformity of the initialization signals received by the initialization transistors in different areas of the display panel.

[0085] Meanwhile, connecting the active layers of the first initialization transistor and the second initialization transistor via the first connection line can appropriately reduce the number of signal lines transmitting the initialization signal, which helps to reduce the line density of the display panel and thus improve resolution. Furthermore, in the event of a break in the signal line transmitting the initialization signal, the initialization signal can still be transmitted to the connected initialization transistor via the first connection line, improving the flexibility and reliability of the circuit.

[0086] Furthermore, at least a portion of the first connection line provided in this embodiment of the invention is located on the same layer as the active layer of the oxide semiconductor transistor. By adjusting the conductivity of the first connection line, the first connection line can be used as a trace to connect the two active layers, thereby eliminating the need to separately prepare a conductive film for fabricating the first connection line, reducing the process flow for fabricating the display panel, and avoiding increasing the trace layout burden of other conductive film layers.

[0087] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving transistor and an initialization transistor. The first terminal of the initialization transistor is connected to an initialization signal, and the second terminal of the initialization transistor is connected to a preset node, which is either the gate of the driving transistor or the anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor, wherein the active layer of the oxide semiconductor transistor comprises oxide semiconductor and the active layer of the silicon transistor comprises silicon. The pixel circuit of the display panel includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor, and the second pixel circuit includes a second initialization transistor. The active layer of the first initialization transistor in the first pixel circuit and the active layer of the second initialization transistor in the second pixel circuit are connected by a first connection line. At least a portion of the first connection line is located on the same layer as the active layer of the oxide semiconductor transistor. The portion of the first connection line that connects to the active layer of the first initialization transistor and the active layer of the second initialization transistor extends along a third direction, and the remaining portion of the first connection line extends along a fourth direction, the third direction intersecting the fourth direction.

2. The display panel according to claim 1, characterized in that, Both the first connection line and the active layer of the initialization transistor contain oxide semiconductor.

3. The display panel according to claim 2, characterized in that, The conductivity of the first connection line is greater than the conductivity of the channel region of the active layer of the initialization transistor.

4. The display panel according to claim 1, characterized in that, The active layers of the initialization transistors for all pixel circuits in the same row are connected.

5. The display panel according to claim 1, characterized in that, The first pixel circuit and the second pixel circuit are arranged along a first direction, and the first connecting line extends along the first direction.

6. The display panel according to claim 5, characterized in that, The display panel includes a first signal line extending along the first direction, and the first signal line provides control signals or input signals to the pixel circuit; wherein... There is no overlap between the first signal line and the first connection line.

7. The display panel according to claim 5, characterized in that, The pixel circuit further includes a third pixel circuit, which includes a third initialization transistor. The first pixel circuit and the third pixel circuit are arranged along a second direction, which intersects the second direction. The active layer of the first initialization transistor and the active layer of the third initialization transistor are connected by a second connection line extending along the second direction, and at least a portion of the second connection line is located on the same layer as the active layer of the initialization transistor.

8. The display panel according to claim 7, characterized in that, The display panel includes an integrated chip located on one side bezel of the display area of ​​the display panel along the second direction. The integrated chip provides the initialization signal to the pixel circuit. The width of the second connecting line is greater than the width of the first connecting line.

9. The display panel according to claim 7, characterized in that, The display panel includes a second signal line extending along the second direction, and the second signal line provides control signals or input signals to the pixel circuit; wherein... There is no overlap between the second connecting line and the second signal line.

10. The display panel according to claim 1, characterized in that, The first pixel circuit and the second pixel circuit are arranged along a first direction, and the display panel further includes an initialization signal line extending along the first direction for providing the initialization signal to the initialization transistor; wherein, The initialization signal line overlaps at least partially with the first connection line.

11. The display panel according to claim 1, characterized in that, The first pixel circuit and the second pixel circuit are arranged along a first direction, and the first connecting line extends along the first direction; wherein... The display panel also includes an initialization signal line extending along a second direction for providing an initialization signal to the initialization transistor, wherein the first direction and the second direction intersect.

12. The display panel according to claim 1, characterized in that, The preset node is the gate of the driving transistor; The driving transistor is a PMOS transistor, and there is no overlap between the first connection line and the active layer of the silicon transistor in the pixel circuit; or, the driving transistor is an NMOS transistor, and there is no overlap between the first connection line and the active layer of the oxide semiconductor transistor in the pixel circuit.

13. The display panel according to claim 1, characterized in that, The preset node is the anode of the light-emitting element; The first connection line does not overlap with the active layer of the silicon transistor in the pixel circuit.

14. The display panel according to claim 1, characterized in that, The pixel circuit includes a group of pixel circuits arranged repeatedly along the fifth direction, and the pixel circuit group includes the first pixel circuit and the second pixel circuit arranged adjacent to each other. The spacing between the active layers of the initialization transistors in two adjacent pixel circuit groups is greater than the spacing between the active layers of the initialization transistors in the first pixel circuit and the second pixel circuit within the pixel circuit group; wherein, The active layers of the initialization transistors of two adjacent pixel circuit groups are not connected through the first connection line.

15. The display panel according to claim 1, characterized in that, The display panel includes a first voltage signal line and a data signal line. The first voltage signal line is used to provide a first voltage signal to the pixel circuit, and the data signal line is used to provide a data signal to the pixel circuit. The first connecting line extends in the same direction as the first voltage signal line and the data signal line, and there is no overlap between the first connecting line and the first voltage signal line and the data signal line. Alternatively, the overlap area S1 between the first connecting line and the first voltage signal line is greater than the overlap area S2 between the first connecting line and the data signal line, and S2≥0.

16. The display panel according to claim 1, characterized in that, The pixel circuit further includes a first conductive layer, which is located on the side of the active layer of the silicon transistor facing the substrate of the display panel; wherein, The first connecting line is interconnected with the first conductive layer.

17. The display panel according to claim 1, characterized in that, The display panel includes a first display area and a second display area, wherein the second display area is correspondingly provided with a camera element or a light-sensitive fingerprint recognition element; wherein... The first pixel circuit and the second pixel circuit are located in the second display area.

18. The display panel according to claim 17, characterized in that, The first display area includes an initialization signal line that provides an initialization signal to the initialization transistor. The initialization signal line is connected to the active layer of the first initialization transistor, and the active layer of the first initialization transistor is connected to the active layer of the second initialization transistor through the first connection line.

19. The display panel according to claim 1, characterized in that, The preset node of the first pixel circuit and the preset node of the second pixel circuit are the gates of the corresponding driving transistors; and / or, the preset node of the first pixel circuit and the preset node of the second pixel circuit are the anodes of the corresponding light-emitting elements.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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