Method and apparatus for executing rules

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed. An apparatus for executing a rule includes: at least one memory; a machine readable instruction; and a processor circuit to at least one of instantiate or execute the machine-readable instructions to: access an attribute value from the data collector, the attribute value including an operational value of a workstation within the process control system; creating a data model instance representing the workstation; applying the attribute value to the data model instance; identifying a rule associated with the data model instance; causing an executable package associated with the rule to be executed using the data model instance; and recording a result of execution of the executable package.

Description

Related Applications

[0001] This patent application claims the benefit of U.S. Patent Application No. 17 / 945,624, entitled “METHODS AND APPARATUS FOR EXECUTING RULES,” filed on September 15, 2022. U.S. Patent Application No. 17 / 945,624 is incorporated herein by reference in its entirety. Priority to U.S. Patent Application No. 17 / 945,624 is hereby claimed. Technical Field

[0002] The present disclosure relates generally to process control systems and, more particularly, to methods and apparatus for executing rules. Background Art

[0003] Process control systems are used in manufacturing and / or industrial settings to control processes (e.g., manufacturing processes). During such processes, machines are operated to produce outputs. Operators of such process control systems wish to know when a particular element in the process control system is operating out of tolerance and / or malfunctioning. Such out of tolerance operation and / or malfunctioning may require operator intervention to correct the error in the process control system. Summary of the invention

[0004] In order to effectively operate a process within a process control system, components of the process control system (e.g., workstations) must function and / or operate within normal operating limits. In existing process control systems, workstations within the process control system each execute their own logic for determining whether the workstation is functioning and / or operating within normal operating limits. If a workstation is not operating within its operating limits, an operator may be notified so the operator can intervene and resolve the problem before the system becomes catastrophic.

[0005] In existing implementations, rules for evaluating the operational status of a workstation are executed separately within each respective workstation. Some of those rules for evaluating the operational status of a workstation may be the same for multiple workstations within a process control system. For example, if a rule common to multiple workstations is to be updated, potential errors may occur when updating each workstation separately, and thus, the likelihood of errors occurring increases due to the number of potential error sources.

[0006] For example, a workstation may execute rules against a defined list of parameters to determine if any parameter has exceeded a defined threshold. The output of the execution of the rules is an indication (e.g., a report) indicating that each parameter has passed (the parameter is within the operating range) or failed (the parameter is not within the operating range). In this example, the list of parameters and the logic for checking the parameters against the thresholds are embedded in the workstation itself. If the rule logic needs to be changed on this workstation, such as updating a threshold value or changing a parameter, the operator will have to make these changes on this single workstation, and no other workstation within the workstation system will receive the change. Therefore, it is not possible to leverage work done for one product (e.g., a workstation) and use it in another product, and it is expensive to maintain these products.

[0007] To further exacerbate the risk of errors, existing rules are deployed as executable constructs. In other words, the rules are stored at each workstation as compiled executable files to be executed at the workstation. Because the rules are compiled, changes to the rules require recompilation. Process control system operators typically adopt strict quality control measures that require full validation testing of the executable files before they are deployed to the workstations. For example, before a supplier of a process control system installs an executable file at a workstation, the executable file must undergo multiple tests to verify that it operates correctly under different potential conditions that may occur at the workstation (e.g., the workstation executes a specific operating system and / or applies specific updates and / or other configurations). Such testing may cause delays in the deployment of updated rules, even when the changes to such rules are minor (e.g., adjusting the expected temperature range).

[0008] Therefore, there is a need for a process control system in which rules to be executed are stored and / or executed in a common location. There is also a need for a process control system in which a common rule executor is implemented, in which the logic used to execute a series of rules does not need to be modified after the rules are modified. Implementing such a system greatly reduces maintenance costs and the probability of errors when updating individual rules. Examples disclosed herein are rule executors used by one or more workstations to execute one or more rules. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of a process control system.

[0010] Figure 2 is a schematic diagram of an exemplary workstation of a process control system.

[0011] Figure 3 Yes means Figure 1 and / or Figure 2 A block diagram of an exemplary implementation of an exemplary rule engine circuit.

[0012] Figure 4 It can be done by Figure 1 , Figure 2 and / or Figure 3 Representation of an exemplary rule configuration file used by an exemplary rule engine circuit.

[0013] Figure 5 is a representation that can be executed and / or instantiated by an exemplary processor circuit to implement Figure 3 Flowcharts of example machine-readable instructions and / or example operations of example script generator circuits and rule compilation circuits.

[0014] Figure 6 is a representation that can be executed and / or instantiated by an exemplary processor circuit to implement Figure 3 Example machine readable instructions and / or a flowchart of example operations of example rule engine circuits.

[0015] Figure 7 It can be done by Figure 3 A representation of an exemplary graphical user interface of an exemplary rule editor circuit display.

[0016] Figure 8 is a representation that can be executed and / or instantiated by an exemplary processor circuit to implement Figure 3 A flowchart of example machine readable instructions and / or example operations of example rule editor circuits.

[0017] Fig. 9 is a block diagram of an exemplary processing platform including a processor circuit configured to perform Figure 5 , Figure 6 and / or Figure 8 Example machine readable instructions and / or example operations to implement Figure 3 An exemplary rules engine circuit of FIG.

[0018] Fig.10 yes Fig. 9 A block diagram of an exemplary implementation of a processor circuit.

[0019] Fig.11 yes Fig. 9 A block diagram of another exemplary implementation of a processor circuit.

[0020] Fig.12 is a block diagram of an exemplary software distribution platform (eg, one or more servers) for distributing software (eg, Figure 5 , Figure 6 and / or Figure 8The software corresponding to the exemplary machine-readable instructions of the present invention is distributed to client devices associated with end users and / or consumers (e.g., for licensing, sale, and / or use), retailers (e.g., for sale, resale, licensing, and / or sublicensing), and / or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers and / or other end users such as direct purchasing customers).

[0021] Generally, the same reference numbers will be used throughout the drawings and accompanying written description to refer to the same or like parts.The drawings are not drawn to scale. DETAILED DESCRIPTION

[0022] Unless otherwise expressly stated, descriptors such as "first", "second", "third", etc., are used herein and do not indicate priority, physical order, arrangement in a list, and / or ordering in any manner by any implication or otherwise, but are merely used as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to reference an element in a specific embodiment, while the same element may be referenced in the claims with a different descriptor (such as "second" or "third"). In such cases, it should be understood that such descriptors are only used to clearly identify those elements that may, for example, otherwise share the same name.

[0023] As used herein, "approximately" and "about" modify their objects / values ​​to recognize that there may be variations in real-world applications. For example, as will be understood by one of ordinary skill in the art, "approximately" and "about" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. For example, "approximately" and "approximately" may indicate that such a dimension may be within a tolerance range of + / - 10%, unless otherwise specified in the description below. As used herein, "substantially real time" means occurring in a near instantaneous manner, recognizing that there may be real-world delays in computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + / - 1 second.

[0024] As used herein, the phrase "in communication" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0025] As used herein, "processor circuitry" is defined as including: (i) one or more special-purpose circuits that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuits include programmable microprocessors, field programmable gate arrays (FPGAs) that can instantiate instructions, central processor units (CPUs), graphics processor units (GPUs), digital signal processors (DSPs), XPUs, or microcontrollers, and integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of processor circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and / or combinations thereof) and (one or more) application programming interfaces (APIs) that can assign (one or more) computing tasks to any one or more processor circuits of the multiple types of processor circuits that are most suitable for performing the computing task.

[0026] Figure 1 is a schematic diagram of a process control system 100. The exemplary process control system 100 includes a plurality of workstations 110, a network 115, a rule engine circuit host 120, and a remote device 140. The rule engine circuit host 120 communicates with the plurality of workstations 110 via the network 115. In some examples, the process control system 100 enables communication with the remote device 140. The remote device 140 may be operated by an operator to, for example, control the operation of the process control system 100, receive and / or display alarms from the rule engine circuit 130, and the like.

[0027] Network 115 may be any one or combination of a public network, a virtual private network (VPN), a private network, or any other similar communication platform that enables two or more computing devices to communicate.

[0028] The example rule engine circuit host 120 includes an example rule engine circuit 130 and an example storage device 135. The rule engine circuit 130 controls the management and execution of rules within the process control system 100. The rule engine circuit 130 creates a workstation instance (e.g., a data model instance) for each of the plurality of workstations 110, determines which rules need to be executed, where the rules are stored, whether the rules are executable, executes the rules, and reports the results of the rule execution to a web-based interface and / or a graphical user interface (GUI). In some examples, the rule engine circuit 130 stores the results of the rule execution in the storage device 135.

[0029] Figure 1 The storage device 135 of the illustrated example stores one or more of rules, executable files, results, etc. to be accessed by the rule engine circuit 130. The storage device 135 can be implemented by one or more non-transitory computer-readable storage media, such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., any type of random access memory (RAM), etc.) or a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, HDD, SSD, etc.). In some examples, the rule engine circuit 130 is executed by the rule engine circuit 130 instructions and / or is configured to perform such as by Figure 5 , Figure 6 and / or Figure 8 The flowcharts represent processor circuit instantiations of those operations.

[0030] The rule engine circuit 130 identifies the plurality of workstations 110 from data transmitted over the network 115 from the data collector circuit 150. The data collector circuit 150 stores information about the workstation(s) 110 that the rule engine circuit 130 requests to execute a rule. In some examples, the information (e.g., attribute values) obtained by the rule engine circuit 130 from the data collector circuit 150 may include parameters such as CPU utilization, storage utilization, temperature readings, or any other information related to workstation system health and performance. In some examples, the attribute values ​​may include parameters that define a data model instance (e.g., Internet Protocol (IP) addresses, workstation identification information, etc.).

[0031] As used herein, a rule includes one or more instructions to be executed by the rule engine circuitry 130 during execution. A rule defines which parameters the rule engine circuitry 130 obtains from the data collector circuitry 150 as attribute values ​​and then analyzes those obtained attribute values ​​against thresholds also defined in the rule. The output of the rule contains information that includes the health of the system and / or any other combination of information required to analyze the health of the system. Figure 4 Exemplary rules are discussed further.

[0032] The rule engine circuitry 130 processes the rules to create (one or more) executable constructs representing the rules that can be executed against the data provided by the data collector circuitry 150 of the workstation 110. In response to evaluating the rules (e.g., by executing (one or more) executable constructs representing the rules), the rule engine circuitry 130 can present alarms and / or other notifications to an operator of the process control system 100. Figure 3 An exemplary implementation of the rules engine circuit 130 is further disclosed.

[0033] The workstation 112 processes the rule execution instructions passed from the rule engine circuit 130 to read the attribute values ​​from one or more I / O devices 165 and create outputs that are sent back to the rule engine circuit 130. Communications to / from the rule engine circuit 130 are handled by the communication circuit 155. For example, the rule engine circuit 130 may request the workstation 112 to store the attribute value of utilization. In this example, the rule engine circuit 130 sends a command to the data collector circuit 150 to access the workstation 112 to store the utilization, and passes the result back to the rule engine circuit 130 to analyze the attribute value against the threshold defined in the rule. As another example, the rule engine circuit 130 may request actuator health information from the workstation 112. In this example, the data collector circuit 150 receives a command to activate the actuator from the rule engine circuit 130, which causes the data collector circuit 150 to send a command to the actuator to activate. The resulting response from the actuator is then sent to the rule engine circuit 130 for analyzing the health of the actuator.

[0034] Figure 1The data collector circuit 150 of the illustrated example aggregates device information from an I / O controller 160 that controls the operation of an I / O device 165. The data collector circuit 150 accesses information about the health of the process control system 100 and then communicates the information to the rule engine circuit 130 via the network 115. In some examples, the data collector circuit 130 may store the information accessed from the I / O controller 160 on an internal storage device housed within the data collector circuit 150. The rule engine circuit 130 may then access the information from the internal storage device via the network 115. In some examples, the data collector circuit 150 may send the information accessed from the I / O controller 160 to the rule engine circuit 130 via the network 115 without storing the information. In this example, the rule engine circuit 130 determines whether to store the information. Determining whether to store the information may include whether the rule engine circuit 130 may need to access the information multiple times, whether the rule engine circuit 130 may need to keep a record of the results, etc.

[0035] Figure 1 The communication circuit 155 of the illustrated example is a communication link between the rule engine circuit 130 and the data collector circuit 150. In some examples, the communication circuit 155 can access information stored on the data collector circuit 150 and send the information to the rule engine 130 via the network 115. In this example, the communication circuit 155 can also receive information (e.g., rule execution commands, which parameters to obtain their property values, etc.) from the rule engine circuit 130 and pass the information to the data collector circuit 150.

[0036] Figure 1 The I / O controller 160 of the illustrated example controls the operation of the I / O device 165 and reads the property value of the I / O device 165. In some examples, the I / O controller 160 can receive instructions from the data collector circuit 150 for accessing the CPU utilization (I / O device 165) of the workstation 112. The I / O controller 160, through its own instruction set, can read the CPU utilization of the workstation 112 and pass the property value back to the data collector circuit 150. For example, the I / O controller 160 can receive instructions from the data collector circuit 150 to open and close a valve (I / O device 165) to verify the operating state of the valve. The I / O controller 160 can command the valve to open and close, and then read a value associated with the operation check (such as whether the valve is open, whether the valve is closed, the percentage of the valve being open, etc.) from the valve to pass back to the data collector circuit 150.

[0037] Figure 1The I / O devices 165 of the illustrated example may include any type of physical sensors, actuators, components, etc. that are operated and / or read by the data collector circuitry 150 on the workstation 112. The I / O devices 165 include physical property values ​​that the data collector circuitry 150 may access and send to the rule engine circuitry 130 to execute rules on those property values ​​to determine the health of the process control system 100.

[0038] Figure 1 The remote device 140 of the illustrated example communicates with the process control system 100 to control the operation of the process control system 100 and / or display an alarm at the request of the rule engine circuit 130. Figure 1 In the illustrated example of , the remote device 140 is permitted to communicate via the network 115. However, in some examples, a separate network may be provided to enable communications with elements of the process control system 100.

[0039] Figure 2 is a block diagram of a workstation 212 of the process control system 100. The workstation 212 executes Figure 1 The same operation as the workstation 112 of FIG. However, in this example, the rule engine circuitry 130 and the storage device 135 are located within the workstation 212. In this example, the rule engine circuitry 130 communicates directly with the data collector circuitry 150 via the communication circuitry 155 (e.g., without requiring an external communication medium such as a wired or wireless Ethernet connection). This example allows the workstation 212 to access the rule engine circuitry 130 without requiring an external communication medium, while still maintaining the benefits of a common or shared rule engine circuitry 130 for managing and executing rules.

[0040] Similar to Figure 1 The storage device 135, Figure 2 The storage device 135 of the illustrated example stores one or more of rules, executable files, results, etc. to be accessed by the rule engine circuit 130. The storage device 135 can be implemented by one or more non-transitory computer-readable storage media, such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., any type of random access memory (RAM), etc.) or a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, HDD, SSD, etc.). The storage device 135 provides the ability to transfer rules from the workstation 212 to any other workstation in the plurality of workstations 110.

[0041] Figure 3 Yes means Figure 1 and / or Figure 2 1 is a block diagram of an exemplary implementation of the rules engine circuit 130. Figure 3 The rule engine circuit 130 of can be instantiated (e.g., create an instance of it, make it exist for any length of time, materialize, realize, etc.) by a processor circuit such as a central processing unit that executes instructions. Additionally or alternatively, Figure 3 The rule engine circuit 130 may be instantiated (e.g., create an instance of it, cause it to be in any length of time, materialize, implement, etc.) by an ASIC or FPGA configured to perform operations corresponding to the instructions. It should be understood that Figure 3 Some or all of the circuits may thus be instantiated at the same or different times. Some or all of the circuits may be instantiated, for example, in one or more threads that are executed simultaneously on hardware and / or in series on hardware. Furthermore, in some examples, Figure 3 Some or all of the circuitry may be implemented by a microprocessor circuit that executes instructions to implement one or more virtual machines and / or containers.

[0042] Figure 3 The rule engine circuit 130 of the illustrated example includes an I / O interface 310 , a data interface circuit 320 , a rule management circuit 330 , a model instance circuit 340 , a script generator circuit 350 , a rule compilation circuit 355 , a rule result circuit 360 , and a rule editor circuit 370 .

[0043] Figure 3 The data interface circuit 320 of the illustrated example identifies a plurality of workstations 110, accesses attribute values ​​stored in the data collector circuit 150 from the workstation 112 through the I / O interface 310, and records the attribute values. The data interface circuit 320 interfaces with the data collector circuit 150 through the I / O interface 310. The I / O interface 310 communicates with the communication circuit 155 within the workstation 112 to send / retrieve data to / from the data collector circuit 150. The data collector circuit 150 sends / receives data to / from the I / O device 165 through the I / O controller 160, and the data includes instructions for controlling the operation of the I / O device 165. In some examples, the data interface circuit 320 is configured to execute data interface instructions and / or is configured to perform operations such as by Figure 6 The flowcharts represent processor circuit instantiations of those operations.

[0044] In some examples, the process control system 100 includes means for identifying the plurality of workstations 110, accessing attribute values ​​stored in the data collector circuit 150 from the workstations 112 through the I / O interface 310, and recording those attribute values. For example, the means for identifying the plurality of workstations 110, accessing attribute values ​​stored in the data collector circuit 150 from the workstations 112 through the I / O interface 310, and recording the attribute values ​​may be implemented by the data interface circuit 320. In some examples, the data interface circuit 320 may be implemented by, for example, Fig. 9 For example, the data interface circuit 320 may be implemented by executing machine executable instructions (such as at least Figure 6 those implemented by blocks 610, 620, and 640 of Fig.10 In some examples, the data interface circuit 320 may be instantiated by a hardware logic circuit that may be configured to perform operations corresponding to machine-readable instructions. Fig.11 The data interface circuit 320 may be implemented by any other combination of hardware, software, and / or firmware. In addition or alternatively, the data interface circuit 320 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the data interface circuit 320 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all machine-readable instructions and / or to execute some or all operations corresponding to machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0045] Figure 3 The rule management circuit 330 of the illustrated example manages the rule database and executes the machine-readable instructions contained in the rules. In some examples, the rule management circuit 330 is configured to execute rule management instructions and / or to perform operations such as Figure 5 and / or Figure 6 The flowcharts represent processor circuit instantiations of those operations.

[0046] In some examples, the process control system 100 includes a unit for managing a rule database and executing machine-readable instructions contained in (one or more) rules. For example, the unit for managing a rule database and executing machine-readable instructions contained in (one or more) rules can be implemented by the rule management circuit 330. In some examples, the rule management circuit 330 can be implemented by, for example, Fig. 9 For example, the rule management circuit 330 may be implemented by executing machine executable instructions (such as at least Figure 5 The frame 510 and Figure 6 those implemented by blocks 650, 660, 670, 672, 674, and 690) Fig.10 In some examples, the rule management circuit 330 may be instantiated by a hardware logic circuit that may be configured to perform operations corresponding to machine-readable instructions. Fig.11The rule management circuit 330 may be implemented by any other combination of hardware, software, and / or firmware. Additionally or alternatively, the rule management circuit 330 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the rule management circuit 330 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0047] Figure 3 The model instantiation circuit 340 of the illustrated example creates a data model instance for the example workstation 112 based on the identification of the plurality of workstations 110. In some examples, the model instantiation circuit 340 is configured to execute model instantiation instructions and / or to perform operations such as by Figure 6 The flowcharts represent processor circuit instantiations of those operations.

[0048] In some examples, the process control system 100 includes means for creating a data model instance for the workstation 112 based on the identification of the plurality of workstations 110. For example, the means for creating a data model instance for the workstation 112 based on the identification of the plurality of workstations 110 may be implemented by the model instance circuit 340. In some examples, the model instance circuit 340 may be instantiated by a processor circuit (such as the processor circuit 912 of FIG. 1 ). For example, the model instance circuit 340 may be instantiated by executing machine executable instructions (such as by Figure 6 At least those instructions implemented by block 630) Fig.10 In some examples, the model instance circuit 340 may be instantiated by a hardware logic circuit that is configured to perform operations corresponding to machine-readable instructions. Fig.11 ASIC, XPU or FPGA circuit 1100. Additionally or alternatively, the model instance circuit 340 may be instantiated by any other combination of hardware, software and / or firmware. For example, the model instance circuit 340 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0049] Figure 3 The script generator circuit 350 of the illustrated example is derived from the rule configuration file 400 ( Figure 4 ) generates a machine-readable instruction script. In some examples, the script generator circuit 350 is configured to execute script generator instructions and / or to perform operations such as Figure 5 The flowcharts represent processor circuit instantiations of those operations.

[0050] In some examples, the process control system 100 includes means for generating a machine-readable instruction script from the rule configuration file 400. For example, the means for generating a machine-readable instruction script from the rule configuration file 400 may be implemented by the script generator circuit 350. In some examples, the script generator circuit 350 may be implemented by a program such as Fig. 9 For example, the script generator circuit 350 may be instantiated by a processor circuit such as the processor circuit 912 of FIG. Figure 5 At least those instructions implemented by block 520) Fig.10 In some examples, the script generator circuit 350 may be instantiated by a hardware logic circuit that may be configured to perform operations corresponding to machine-readable instructions. Fig.11 ASIC, XPU or FPGA circuit 1100. Additionally or alternatively, the script generator circuit 350 may be instantiated by any other combination of hardware, software and / or firmware. For example, the script generator circuit 350 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0051] Figure 3 The rule compilation circuitry 355 of the illustrated example creates an executable package based on the machine-readable instruction file generated from the script generator circuitry 350. In some examples, the rule compilation circuitry 355 is configured to execute rule compilation instructions and / or to perform operations such as Figure 5 The flowcharts represent processor circuit instantiations of those operations.

[0052] In some examples, the process control system 100 includes means for creating an executable package based on a machine-readable instruction file generated from the script generator circuit 350. For example, the means for creating an executable package based on a machine-readable instruction file generated from the script generator circuit 350 may be implemented by the rule compilation circuit 355. In some examples, the rule compilation circuit 355 may be implemented by, for example, Fig. 9 For example, the rule compilation circuit 355 may be implemented by executing machine executable instructions (such as at least Figure 5 530 and 540 of the implementation of those instructions) Fig.10 In some examples, the rule compilation circuit 355 may be instantiated by a hardware logic circuit, which may be configured to perform operations corresponding to machine-readable instructions. Fig.11 ASIC, XPU or FPGA circuit 1100. Additionally or alternatively, the rule compilation circuit system 355 may be instantiated by any other combination of hardware, software and / or firmware. For example, the rule compilation circuit 355 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all of the machine-readable instructions and / or execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0053] Figure 3 The rule result circuit 360 of the illustrated example reports the result of the rule execution. The report of the rule execution may include a pass or fail result, attribute values, and / or any other information collected through the execution of the rule. In some examples, the rule result circuit 360 communicates with the exemplary graphical user interface (GUI) 700 ( Figure 7 ) or a web-based interface to display the results of the rule execution. In some examples, the rule result circuit 360 stores the results of the rule execution in the storage device 135 through the I / O interface 310 to maintain a history of the rule execution results. In some examples, the rule result circuit 360 is executed by executing rule result instructions and / or is configured to perform such as by Figure 6 The flowcharts represent processor circuit instantiations of those operations.

[0054] In some examples, the process control system 100 includes a unit for reporting the results of the rule execution. For example, the unit for reporting the results of the rule execution can be implemented by the rule result circuit 360. In some examples, the rule result circuit 360 can be implemented by a system such as Fig. 9 For example, rule result circuit 360 may be implemented by executing machine executable instructions (such as by Figure 6 at least those instructions implemented by block 680) Fig.10 In some examples, the rule result circuit 360 may be instantiated by a hardware logic circuit, which may be configured to perform operations corresponding to machine-readable instructions. Fig.11 The rule result circuit 360 may be implemented by an ASIC, XPU, or FPGA circuit 1100. Additionally or alternatively, the rule result circuit 360 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the rule result circuit 360 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0055] Figure 3 The rule editor circuit 370 of the illustrated example applies the edits to the rule parameter file 400. In some examples, the rule editor circuit 370 is configured to execute rule editor instructions and / or to perform operations such as by Figure 8 The flowcharts represent processor circuit instantiations of those operations.

[0056] In some examples, the process control system 100 includes means for applying edits to the rule parameter file 400. For example, the means for applying edits to the rule parameter file 400 may be implemented by the rule editor circuit 370. In some examples, the rule editor circuit 370 may be implemented by, for example, Fig. 9 For example, the rule editor circuit 370 may be instantiated by a processor circuit such as the processor circuit 912 of FIG. Figure 8 those implemented by blocks 810, 820, 822, 824, 826, 830, 832, 834, 840, 842, 844, and 850) Fig.10 In some examples, the rule editor circuit 370 may be instantiated by a hardware logic circuit that may be configured to perform operations corresponding to machine-readable instructions. Fig.11The rule editor circuit 370 may be implemented by an ASIC, XPU, or FPGA circuit 1100. Additionally or alternatively, the rule editor circuit 370 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the rule editor circuit 370 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally appropriate.

[0057] Although in Figure 3 An exemplary manner of implementing the rule engine circuit 130 is shown in FIG. Figure 3 One or more of the elements, processes and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. In addition, I / O interface 310, data interface circuit 320, rule management circuit 330, model instance circuit 340, script generator circuit 350, rule compilation circuit 355, rule result circuit 360, rule editor circuit 370 and / or more generally Figure 3 The rule engine circuit 130 may be implemented by hardware alone, or by a combination of hardware and software and / or firmware. Thus, for example, the I / O interface 310, the data interface circuit 320, the rule management circuit 330, the model instance circuit 340, the script generator circuit 350, the rule compilation circuit 355, the rule result circuit 360, the rule editor circuit 370 and / or more generally any one of the rule engine circuit 130 may be implemented by a processor circuit, an analog circuit, a digital circuit, a logic circuit, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) and / or a field programmable logic device (FPLD) such as a field programmable gate array (FPGA). In addition, Figure 3 The rule engine circuit 130 may include in addition to Figure 3 In addition to or in lieu of those shown in Figure 3 One or more of the elements, processes and / or devices shown in the drawings, and / or may include more than one of any or all of the elements, processes and devices shown.

[0058] exist Figure 5 , Figure 6 and / or Figure 8 A flowchart representing exemplary machine readable instructions is shown in Figure 3 The machine-readable instructions may be one or more executable programs or portions of executable programs for execution by a processor circuit, such as the following in combination with Fig. 9 The processor circuit 912 shown in the exemplary processor platform 900 discussed below and / or in combination with Fig.10 and / or Fig.11 Exemplary processor circuits discussed. The program may be embodied in software stored on one or more non-transitory computer-readable storage media, such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., any type of random access memory (RAM), etc.) or a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, HDD, SSD, etc.), associated with a processor circuit located in one or more hardware devices, but the entire program and / or portions thereof may alternatively be executed by one or more hardware devices other than the processor circuit and / or embodied in firmware or dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN)) gateway that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media located in one or more hardware devices. In addition, although the reference Figure 5 , Figure 6 and / or Figure 8The flowchart shown describes an exemplary procedure, but many other methods of implementing the rule engine circuit 130 may be used instead. For example, the order of execution of the boxes may be changed, and / or some of the boxes described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the boxes may be implemented by one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are configured to perform corresponding operations without executing software or firmware. The processor circuits may be distributed in different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core central processor units (CPUs)), multi-core processors in a single machine (e.g., multi-core CPUs, XPUs, etc.), multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, CPUs and / or FPGAs in the same package (e.g., the same integrated circuit (IC) package or two or more separate housings, etc.).

[0059] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data or data structures (e.g., as instructions, codes, portions of code representations, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers) located at the same or different locations of a network or a collection of networks (e.g., in the cloud, in edge devices, etc.). The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts form a set of machine-executable instructions when decrypted, decompressed, and / or combined, and these instruction implementations may together form one or more operations of a program such as described herein.

[0060] In another example, the machine-readable instructions may be stored in a state in which they can be read by a processor circuit, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, a machine-readable medium may include machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transit.

[0061] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0062] As mentioned above, Figure 5 , Figure 6 and / or Figure 8The exemplary operations of can be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on one or more non-transitory computer and / or machine readable media, such as optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, and / or any other storage device or storage disk, where information is stored for any duration (e.g., for an extended period of time, permanently, transiently, temporarily buffering and / or caching information). As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine readable medium, and non-transitory machine readable storage medium are expressly defined to include any type of computer readable storage device and / or storage disk, and exclude propagating signals and exclude transmission media. As used herein, the terms "computer readable storage device" and "machine readable storage device" are defined to include any physical (mechanical and / or electrical) structure to store information, but exclude propagating signals and exclude transmission media. Examples of computer-readable storage devices and machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuit, that may or may not be configured by computer-readable instructions, machine-readable instructions, etc. and / or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0063] "Include" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprising" (e.g., includes, including, contains, includes, has, etc.) as a preamble or within any type of claim narrative, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or narrative. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended in the same manner as the terms "include" and "comprising" are open-ended. When used, for example, in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to embodiments that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0064] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the object. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. In addition, although listed separately, multiple units, elements, or method actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0065] Figure 4 It can be done by Figure 1 , Figure 23. A representation of an exemplary rule configuration file 400 for use by the rule engine circuit 130 of FIG. 3. The rule configuration file 400 includes exemplary rule file execution attributes 410, exemplary rule execution commands 420, exemplary inputs 430, and exemplary outputs 440.

[0066] Figure 4 The rule file execution attributes 410 of the illustrated example rule configuration file 400 include information about the rule. In some examples, the rule file execution attributes 410 may include the name of the rule, the target node and / or asset type on which the rule may be executed, a description of the rule, an execution rate of the rule, or any other combination of information that may be included to describe the properties of the rule.

[0067] Figure 4 The rule execution commands 420 of the illustrated example rule configuration file 400 include core logic / machine-readable instructions that the rule engine circuit 130 executes to determine the success or failure of a rule. For example, the rule execution commands 420 may include instructions that instruct the rule engine circuit 130 to query the CPU utilization of the workstation 112 and determine whether the CPU utilization of the workstation 112 is above the exemplary threshold value of 85%. The rule execution commands 420 may then instruct the rule engine circuit 130 to output a fail if the CPU utilization reads above the threshold value of 85%, or to output a pass if the CPU utilization reads below the threshold value of 85%.

[0068] Figure 4 Inputs 430 of rule configuration file 400 include parameters by which rule engine circuitry 130 may request attribute values ​​from data collector circuitry 150. In some examples, inputs 430 may also include threshold(s) against which rule execution commands 420 may check (e.g., compare against) attribute values ​​received from data collector circuitry 150. In some examples, the threshold(s) against which rule execution commands 420 may check attribute values ​​received from data collector circuitry 150 are stored in an external file.

[0069] Figure 4 The output 440 of the rule configuration file 400 includes the results of the rule execution command 420. In some examples, the output 440 includes alert information about the results of the rule execution command 420 to be sent to the web-based interface and / or graphical user interface (GUI) 700. The output 440 is not limited to reporting only the results of the rule execution command 420. Any relevant information about the execution of the rule may be included in the output 440. Examples of relevant information about the execution of the rule may include, but are not limited to, the time that elapsed before a failure occurred, the number of execution cycle failures, etc.

[0070] Any one or combination of the rule file execution attributes 410, rule execution commands 420, inputs 430, and / or outputs 440 may be separated and / or combined in any number of ways that maintain the core functionality of the rule configuration file 400. In some examples, each of the rule file execution attributes 410, rule execution commands 420, inputs 430, and outputs 440 may be separate files, and the combination of each of these files may create the example rule configuration file 400. The rule configuration file 400 is not limited to a single file, nor is it limited to a single file type (e.g., a text file, JavaScript Object Notation (JSON), etc.).

[0071] Figure 5 is a representation that can be executed and / or instantiated by a processor circuit to implement Figure 3 Flowcharts of example machine readable instructions and / or example operations of the script generator circuit 350 and the rule compilation circuit 355. Figure 5 The script generation and rule compilation process 500 begins at block 510, where the rule management circuit 330 accesses the rule configuration file 400. In some examples, the rule configuration file 400 may be located on the rule engine circuit host 120 stored in the storage device 135 and may be retrieved by the rule engine circuit 130. In some examples, the rule configuration file 400 may be located on the workstation 212 stored in the storage device 135 and may be retrieved by the rule engine circuit 130. In some examples, the rule configuration file 400 may be located at a remote location (e.g., a remote server) and may be retrieved by the rule engine circuit 130 via the network 115.

[0072] The script generator circuit 350 generates a machine-readable instruction script from the rule configuration file 400 (box 520). An example method for generating a machine-readable instruction script is to use the Roslyn.NET compiler platform for dynamic script generation. In some examples, the script generator circuit 350 (e.g., the Roslyn.NET compiler platform) reads a JavaScript object representation (JSON) rule configuration file 400 and generates a machine-readable instruction script. In some examples, the machine-readable instruction script is a C# file. However, any other programming language and / or programming syntax may be used additionally or alternatively. In some examples, the generation of a machine-readable instruction script is referred to as refactoring, wherein the JSON rule configuration file 400 is reconstructed into a machine-readable instruction script.

[0073] The rule compilation circuit 355 compiles the machine-readable instruction script generated from the rule configuration file 400 into an executable package (block 530). The executable package may be a single executable program file (e.g., .exe file) or any combination of executable package files necessary to instruct a machine to execute the rule execution commands 420 in the rule configuration file 400. An example method of compiling the machine-readable instruction script into an executable package is to utilize the Roslyn.NET compiler platform to compile the generated machine-readable instruction script into an executable package.

[0074] In some examples, the rule compilation circuitry 355 stores / saves the executable package for the rule engine circuitry 130 to execute the instructions stored therein (block 540). The executable package may be stored on the rule engine circuitry host 120 in the storage device 135 and may be retrieved by the rule engine circuitry 130 for execution. In some examples, the executable package may be stored on the workstation 212 in the storage device 135 and may be retrieved by the rule engine circuitry 130 for execution. In some examples, the rule management circuitry 330 may also store the executable package for the rule engine circuitry 130 to execute the instructions stored therein.

[0075] Figure 6 is a representation that can be executed and / or instantiated by a processor circuit to implement Figure 3 Flowcharts of example machine-readable instructions and / or example operations of the rules engine circuit 130. Figure 6 The rule engine execution process 600 begins at block 610, where the data interface circuit 320 accesses attribute values ​​stored within the data collector circuit 150 via the I / O interface 310. In some examples, the data interface circuit 320 can access attribute values ​​such as CPU utilization, storage utilization, temperature readings, or any other information related to workstation system health and performance from the data collector circuit 150. In some examples, the data interface circuit 320 can access attribute values ​​that define a data model instance (e.g., Internet Protocol (IP) address, workstation identification information, etc.).

[0076] In some examples, the data interface circuitry 320 identifies a workstation 112 on which the example rule profile 400 may be executed (block 620). In some examples, the rule management circuitry 330 may also identify a workstation 112 on which the example rule profile 400 may be executed.

[0077] Model instance circuitry 340 creates an instance (eg, a virtual representation of attributes) (eg, a data model instance) of workstation 112 based on the identification of workstation 112 from block 620 (block 630). Creation of an instance allows rule management circuitry 330 to execute rules in parallel or serially.

[0078] The data interface circuit 320 then records the attribute values ​​collected from the data collector circuit 150 via the I / O interface 310 to each data model instance created by the model instance circuit 340 (block 640). As described above, in some examples, the attribute values ​​include parameters such as CPU utilization, storage utilization, temperature readings, or any other information related to workstation system operation, health, and / or performance. In some examples, the attribute values ​​may include parameters that define the data model instance (e.g., Internet Protocol (IP) address, workstation identification information, etc.).

[0079] The rule management circuitry 330 identifies rules associated with each data model instance created by the model instance circuitry 340 (block 650). In some examples, the rule management circuitry 330 retrieves the rule(s) stored in storage 135 on the rule engine circuitry host 120. In some examples, the rule management circuitry 330 may also retrieve the rule(s) stored in storage 135 on the workstation 212.

[0080] The rule management circuitry 330 then selects a rule to execute based on the identification of the rule from block 650 (block 660). As described above, the rule management circuitry 330 may execute the rules in parallel or serially.

[0081] Then, the rule management circuit 330 determines whether there is an executable package for the rule (block 670). For example, the rule management circuit 330 can determine whether there is an executable package by querying the storage device 135 for one or more identifiers of the rule (e.g., file name, file extension, file location, file content, etc.).

[0082] When the rule management circuit 330 determines that there is no executable package for the rule (e.g., block 670 returns a "no" result), the rule management circuit 330 generates an executable package for the rule (block 672). In some examples, the exemplary instructions of block 672 are based on Figure 5 The script generation and rule compilation process 500 is implemented.

[0083] When an executable package is created by the script generation and rule compilation process 500 from block 672, or when the rule management circuitry 330 determines that an executable package for the rule already exists (e.g., block 670 returns a "yes" result), the rule management circuitry 330 then causes execution of the rule (block 674).

[0084] When the rule management circuit 330 completes execution of the rule, the rule result circuit 360 transmits the result of the rule execution command 420 (block 680). The result may include a pass or fail indication, a property value, or any other information collected during execution of the rule. In some examples, the rule result circuit 360 may report the result to a web-based interface or graphical user interface (GUI) 700 via the I / O interface 310.

[0085] In some examples, rule result circuitry 360 may store the results of rule execution commands 420 on storage device 135 or any form of internal or external storage medium to maintain a history of the results by communicating with storage device 135 via I / O interface 310. Storage of the results allows for analysis of historical trend data that may be relevant to system health and performance analysis.

[0086] The rule management circuitry 330 then determines whether there are any more rules that need to be executed (block 690). In some examples, the rule management circuitry 330 may determine whether there are any more rules that need to be run by accessing the list of rules identified by block 650. When the rule management circuitry 330 determines that there are additional rules that need to be executed (e.g., block 690 returns a "yes" result), the rule management circuitry 330 returns to block 660 to select the next rule to execute. The rule engine execution process 600 of blocks 660 to 690 is repeated until the rule management circuitry 330 determines that there are no additional rules to execute.

[0087] Figure 7 It can be done by Figure 3 7. A representation of a graphical user interface (GUI) 700 displayed by the rule editor circuit 370 of FIG. GUI 700 includes an exemplary core logic field 710, an exemplary editable parameter field 720, and an exemplary editable threshold field 730.

[0088] Figure 7 The core logic field 710 of the GUI 700 displays the rule execution command 420 executed by the rule engine circuit 130. In some examples, the core logic field 710 is not editable. In this example, prohibiting editing of the core logic field 710 ensures that the rule does not need to be recompiled and revalidated, thereby saving maintenance costs and reducing the probability of errors. In addition, in this example, the rule includes a list of possible variations of the core logic field 710 that can be executed by the rule engine circuit 130 when it is created. In some examples, the core logic field 710 can be editable, thereby allowing the rule execution command 420 executed by the rule engine circuit 130 to be modified.

[0089] Figure 7The editable parameter fields 720 of the GUI 700 allow for customization of the inputs 430 and outputs 440 of the rule configuration file 400. In some examples, the editable parameter fields 720 include an array of parameters available within the workstation 112 that can be analyzed by the rule engine circuitry 130 based on the rule execution command 420. For example, when the rule engine circuitry 130 selects to run the rule execution command to check the health of the CPU of the workstation 112, the array of parameters in the editable parameter field 720 may only include a list of parameters related to the health of the CPU. In some examples, the parameters available in the editable parameter field 720 may include a comprehensive list of all parameters available within the process control system 100 and / or the workstation 112.

[0090] Figure 7 The editable threshold value field 730 of the GUI 700 allows for customization of the threshold value against which the rule engine circuit 130 can compare the input 430 to determine the health of the system. In some examples, the threshold value can be included in the input 430 of the rule configuration file 400, which is read by the GUI 700 to populate the editable threshold value field 730. In some examples, the threshold value can be in a separate file and read by the GUI 700 to populate the editable threshold value field 730.

[0091] Figure 8 is a representation that can be executed and / or instantiated by a processor circuit to implement Figure 3 Example machine readable instructions and / or a flowchart of example operations of the rule editor circuit 370. Figure 8 The rule editor process 800 begins at block 810, where the rule editor circuitry 370 identifies a rule to be edited. In some examples, the rules may be stored in a rule dictionary that contains a list of rules available within the system that the rule editor circuitry 370 can access. In some examples, the rules may be stored in a separate file on the workstation 112 within the storage device 135. The rules may be stored in any one or more of a comma separated value (CSV) file, a text file, a JSON file, or any other file extension.

[0092] The rule editor circuitry 370 then identifies the rule execution commands 420 (e.g., core logic) (block 820). The rule execution commands 420 include instructions for the rule engine circuitry 130 to execute. In some examples, the rule editor circuitry 370 may identify the rule execution commands 420 by analyzing the format of the rule parameter file 400 and extracting information identifying the rule execution commands 420. One method of identification may include searching for patterns such as string phrases and / or sub-categories of the file identification information (e.g., decomposing the rule configuration file 400 into its individual components, such as the rule execution commands 420, inputs 430, outputs 440, etc.).

[0093] The rule editor circuitry 370 then determines whether the rule execution command 420 has been edited (block 822). The rule editor circuitry 370 may determine whether the rule execution command 420 has been edited, for example, by determining whether the rule configuration file 400 has been modified via file save information, version control history, or any other means of determining whether a file or a particular portion of a file has been modified.

[0094] When the rule editor circuitry 370 determines that the rule execution command 420 has been edited (e.g., block 822 returns a "yes" result), the rule editor circuitry 370 then determines whether editing the rule execution command 420 is permitted (e.g., by accessing management rules associated with the rule configuration file 400) (block 824). In some examples, the management rules of the rule configuration file 400 may prohibit editing of the rule execution command 420. When editing of the rule execution command 420 is prohibited, the validation process of the rule may be reduced or even eliminated because recompilation is not required, which reduces maintenance costs. In some examples, the rule execution command 420 may be edited to change the rule being executed and / or optimize the execution of the rule.

[0095] When the rule editor circuitry 370 determines that editing the rule execution command 420 is permitted (eg, block 824 returns a "yes" result), the rule editor circuitry 370 applies the changes to the rule execution command 420 to the rule configuration file 400 and saves the resulting rule configuration file 400 (block 826).

[0096] When the rule editor circuitry 370 determines that the rule execution command 420 has not been edited (e.g., block 822 returns a result of "no"), editing of the rule execution command 420 is not permitted (e.g., block 824 returns a result of "no"), or the rule editor 370 has applied changes to the rule execution command 420 to the rule configuration file 400, the rule editor circuitry 370 then identifies inputs 430 and / or outputs 430 (e.g., parameters) to be collected during execution of the rule (block 830). In some examples, the rule editor circuitry 370 may identify the inputs 430 and / or outputs 430 by analyzing the format of the rule parameter file 400 and extracting information identifying the inputs 430 and / or outputs 440. One method of identification may include searching for patterns such as string phrases and / or sub-categories of file identification information (e.g., decomposing the rule configuration file 400 into its individual components, such as the rule execution command 420, the inputs 430, the outputs 440, etc.).

[0097] The rule editor circuit 370 then determines whether the input 430 and / or the output 430 have been edited (block 832). The rule editor circuit 370 may determine whether the input 430 and / or the output 430 have been edited, for example, by determining whether the rule configuration file 400 has been modified via file save information, version control history, or any other means of determining whether a file or a particular portion of a file has been modified.

[0098] When the rule editor circuit 370 determines that the input 430 and / or output 430 has been edited (e.g., box 832 returns a "yes" result), the rule editor circuit 370 applies the changes to the input 430 and / or output 440 to the rule configuration file 400 and saves the resulting rule configuration file 400 (box 834).

[0099] When the rule editor circuitry 370 determines that the input 430 and / or output 430 has not been edited (e.g., block 832 returns a “no” result) or the rule editor circuitry 370 has applied changes to the input 430 and / or output 430 to the rule configuration file 400, the rule editor circuitry 370 then identifies a threshold against which the input 430 may be evaluated during execution of the rule (block 840). In some examples, the rule editor circuitry 370 may identify the threshold by analyzing the format of the rule parameter file 400 and extracting information identifying the threshold from the input 430. One method of identification may include searching for patterns such as string phrases and / or sub-categories of file identification information (e.g., decomposing the rule configuration file 400 into its individual components, such as the rule execution command 420, the input 430, the output 440, etc.).

[0100] In this example, the threshold value is included in the input 430 of the rule parameter file 400. In some examples, the threshold value can be stored in a threshold value file separate from the rule configuration file 400. The threshold value file can be in the form of, but not limited to, a database (db) file, a JSON file, and / or a CSV file. Keeping the threshold value file separate from the rule configuration file 400 can greatly reduce the maintenance cost of the rule engine circuit 130 and the verification cost.

[0101] The rule editor circuitry 370 then determines whether the thresholds have been edited (block 842). In some examples, the rule editor circuitry 370 may determine whether the thresholds have been edited by determining whether the rule configuration file 400 has been modified through file save information, version control history, or any other means of determining whether a file or a particular portion of a file has been modified. In some examples, the rule editor circuitry 370 may read a threshold file separate from the rule configuration file 400 and determine whether any thresholds have been edited.

[0102] When the rule editor circuit 370 determines that the threshold has been edited (e.g., block 842 returns a "yes" result), the rule editor circuit 370 applies the change in the threshold to the input 430 of the rule configuration file 400 and saves the resulting rule configuration file 400 (block 844). In some examples, the rule editor circuit 370 may alternatively apply the change in the threshold to a threshold file separate from the rule configuration file 400.

[0103] When the rule editor circuit 370 determines that the threshold has not been edited (e.g., block 842 returns a "no" result) or the rule editor circuit 370 has applied the change of the threshold to the file containing the threshold information (rule configuration file 400 or threshold file), the rule editor circuit 370 saves the final updated rule configuration file 400 (block 850). In some examples, the rule configuration file 400 can be saved on the rule engine circuit host 120 and stored in the storage device 135. In some examples, the rule configuration file 400 can be saved on the workstation 212 and stored in the storage device 135. In some examples, the rule configuration file 400 can alternatively be saved to a remote location (e.g., a remote server) via the network 115.

[0104] In some examples, the rule editor circuitry 370 allows creation and modification of rules through the GUI 700. In some examples, the rule editor circuitry 370 allows importing external files containing rule parameter information to be applied to rules or batch creation of multiple rule configuration files 400.

[0105] Fig. 9 is constructed to execute and / or instantiate Figure 5 , Figure 6and / or Figure 8 Machine readable instructions and / or operations to implement Figure 3 The processor platform 900 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cellular phone, a smart phone, an iPad, etc.). TM tablet computer), personal digital assistant (PDA), Internet appliance, or any other type of computing device.

[0106] The processor platform 900 of the illustrated example includes a processor circuit 912. The processor circuit 912 of the illustrated example is hardware. For example, the processor circuit 912 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired series or manufacturer. The processor circuit 912 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuit 912 implements the data interface circuit 320, the rule management circuit 330, the model instance circuit 340, the script generator circuit 350, the rule compilation circuit 355, the rule result circuit 360, and the rule editor circuit 370.

[0107] The processor circuit 912 of the illustrated example includes a local memory 913 (e.g., cache, registers, etc.). The processor circuit 912 of the illustrated example communicates with a main memory including a volatile memory 914 and a non-volatile memory 916 via a bus 918. The volatile memory 914 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 916 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 914, 916 of the illustrated example is controlled by a memory controller 917.

[0108] The processor platform 900 of the illustrated example also includes an interface circuit 920. The interface circuit 920 may be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0109] In the example shown, one or more input devices 922 are connected to the interface circuit 920. The input devices 922 allow a user to input data and / or commands into the processor circuit 912. The input devices 922 may be implemented by, for example, a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, and / or a pointing device.

[0110] One or more output devices 924 are also connected to the interface circuit 920 of the illustrated example. The output device 924 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-plane switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit 920 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit, such as a GPU.

[0111] The interface circuitry 920 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any kind of computing device) over the network 926. Communications may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0112] The processor platform 900 of the illustrated example also includes one or more mass storage devices 928 to store software and / or data. Examples of such mass storage devices 928 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant arrays of independent disks (RAID) systems, solid-state storage devices (e.g., flash memory devices and / or SSDs), and DVD drives.

[0113] Can be Figure 5 , Figure 6 and / or Figure 8 The machine-readable instructions 932 implemented by the machine-readable instructions may be stored in the mass storage device 928, in the volatile memory 914, in the non-volatile memory 916, and / or on a removable, non-transitory computer-readable storage medium such as a CD or DVD.

[0114] Fig.10 yes Figure 4 912 of the processor circuit 912. In this example, Figure 4 The processor circuit 912 is implemented by the microprocessor 1000. For example, the microprocessor 1000 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit). The microprocessor 1000 executes Figure 5 , Figure 6 and / or Figure 8 Some or all of the machine readable instructions of a flowchart to effectively Figure 3 The rule engine circuit 130 is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such examples, Figure 3 The rule engine circuit 130 is instantiated by the hardware circuit of the microprocessor 1000 in combination with instructions. For example, the microprocessor 1000 can be implemented by a multi-core hardware circuit, such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of exemplary cores 1002 (for example, 1 core), the microprocessor 1000 of this example is a multi-core semiconductor device including N cores. The cores 1002 of the microprocessor 1000 can operate independently or can cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 1002, or can be executed by multiple of the cores 1002 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more cores 1002. The software program may correspond to a program executed by Figure 5 , Figure 6 and / or Figure 8 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0115] The core 1002 can communicate via a first exemplary bus 1004. In some examples, the first bus 1004 can be implemented by a communication bus to implement communications associated with one (or more) of the cores 1002. For example, the first bus 1004 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1004 can be implemented by any other type of computing or electrical bus. The core 1002 can obtain data, instructions, and / or signals from one or more external devices via an exemplary interface circuit 1006. The core 1002 can output data, instructions, and / or signals to one or more external devices via the interface circuit 1006. Although the cores 1002 of this example include an exemplary local memory 1020 (e.g., a level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes an exemplary shared memory 1010 (e.g., a level 2 (L2) cache) that may be shared by the cores for high-speed access to data and / or instructions. Data and / or instructions may be transferred by writing to and / or reading from the shared memory 1010. The local memory 1020 and the shared memory 1010 of each of the cores 1002 may be a plurality of levels of cache memory and a main memory (e.g., Fig. 9 A cache memory is a memory device that is part of a hierarchy of storage devices (main memory 914, 916). Typically, higher levels of memory in the hierarchy exhibit lower access times and have smaller storage capacities than lower levels of memory. Changes to various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0116] Each core 1002 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit. Each core 1002 includes a control unit circuit 1014, an arithmetic and logic (AL) circuit (sometimes referred to as an ALU) 1016, a plurality of registers 1018, a local memory 1020, and a second exemplary bus 1022. Other structures may exist. For example, each core 1002 may include a vector unit circuit, a single instruction multiple data (SIMD) unit circuit, a load / store unit (LSU) circuit, a branch / jump unit circuit, a floating point unit (FPU) circuit, etc. The control unit circuit 1014 includes a semiconductor-based circuit configured to control (e.g., coordinate) data movement within the corresponding core 1002. The AL circuit 1016 includes a semiconductor-based circuit configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1002. The AL circuit 1016 of some examples performs integer-based operations. In other examples, the AL circuit 1016 also performs floating-point operations. In other examples, AL circuit 1016 may include a first AL circuit that performs integer-based operations and a second AL circuit that performs floating-point operations. In some examples, AL circuit 1016 may be referred to as an arithmetic logic unit (ALU). Register 1018 is a semiconductor-based structure for storing data and / or instructions, such as the results of one or more operations performed by AL circuit 1016 of corresponding core 1002. For example, register 1018 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Register 1018 may be arranged in a manner such as Fig.10 1002. Alternatively, registers 1018 may be organized in any other arrangement, format, or structure, including being distributed throughout core 1002 to reduce access time. Second bus 1022 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0117] Each core 1002 and / or more generally the microprocessor 1000 may include additional and / or alternative structures to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHA), one or more aggregation / common grid stations (CMS), one or more shifters (e.g., barrel shifters) and / or other circuits. The microprocessor 1000 is a semiconductor device manufactured to include many interconnected transistors to implement the above structure in one or more integrated circuits (ICs) contained in one or more packages. The processor circuit may include one or more accelerators and / or collaborate with one or more accelerators. In some examples, the accelerator is implemented by a logic circuit to perform certain tasks faster and / or more efficiently than a general-purpose processor can accomplish. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU or other programmable device may also be an accelerator. The accelerator may be onboard the processor circuit, in the same chip package as the processor circuit, and / or in one or more packages separated from the processor circuit.

[0118] Fig.11 yes Fig. 9 1 is a block diagram of another exemplary implementation of the processor circuit 912 of FIG. In this example, the processor circuit 912 is implemented by an FPGA circuit 1100. For example, the FPGA circuit 1100 can be implemented by an FPGA. The FPGA circuit 1100 can be used, for example, to execute a program that can be executed by executing corresponding machine-readable instructions. Fig.10 However, once configured, the FPGA circuit 1100 instantiates machine-readable instructions in hardware and can therefore typically perform operations faster than a general-purpose microprocessor executing corresponding software.

[0119] More specifically, Fig.10 The microprocessor 1000 (which is a general-purpose device that can be programmed to perform the Figure 5 , Figure 6 and / or 8, which are flowcharts representing some or all of the machine-readable instructions, but whose interconnections and logic circuits are fixed once they are manufactured), Fig.11 The example FPGA circuit 1100 includes interconnects and logic circuits that can be configured and / or interconnected in different ways after fabrication to instantiate, for example, Figure 5 , Figure 6 and / or Figure 8In particular, FPGA circuit 1100 can be considered as an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit 1100 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on the data received by the input circuits. These operations can correspond to Figure 5 , Figure 6 and / or Figure 8 In this way, FPGA circuit 1100 can be constructed to effectively Figure 5 , Figure 6 and / or Figure 8 Some or all of the machine-readable instructions of the flowchart of FIG. 1100 are instantiated as dedicated logic circuits to perform operations corresponding to those software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit 1100 can execute operations corresponding to those software instructions faster than a general-purpose microprocessor. Figure 5 , Figure 6 and / or Figure 8 Operations corresponding to some or all of the machine-readable instructions.

[0120] exist Fig.11 In the example of FPGA circuit 1100, FPGA circuit 1100 is configured to be programmed (and / or reprogrammed one or more times) by an end user via a hardware description language (HDL) such as Verilog. Fig.11 The FPGA circuit 1100 includes an exemplary input / output (I / O) circuit 1102 to obtain and / or output data to / from an exemplary configuration circuit 1104 and / or external hardware 1106. For example, the configuration circuit 1104 can be implemented by an interface circuit that can obtain machine-readable instructions to configure the FPGA circuit 1100 or (one or more) portions thereof. In some such examples, the configuration circuit 1104 can obtain machine-readable instructions from a user, a machine (e.g., a hardware circuit (e.g., a programmed or dedicated circuit) that can implement an artificial intelligence / machine learning (AI / ML) model to generate instructions), etc. In some examples, the external hardware 1106 can be implemented by an external hardware circuit. For example, the external hardware 1106 can be implemented by Fig.10 FPGA circuit 1100 also includes an array of exemplary logic gate circuits 1108, a plurality of exemplary configurable interconnects 1110, and exemplary storage circuits 1112. Logic gate circuits 1108 and configurable interconnects 1110 may be configured to instantiate Figure 5 , Figure 6 and / or Figure 8One or more operations of at least some of the machine-readable instructions and / or other desired operations. Fig.11 The logic gate circuits 1108 shown in are manufactured in groups or blocks. Each block includes a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. An electrically controllable switch (e.g., a transistor) is present in each of the logic gate circuits 1108 to enable the electrical structure and / or the logic gate to be configured to form a circuit that performs the desired operation. The logic gate circuits 1108 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0121] The configurable interconnect 1110 of the illustrated example is a conductive path, trace, via, etc., which may include an electrically controllable switch (e.g., a transistor) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuits 1108 to program the desired logic circuit.

[0122] The storage circuit 1112 of the illustrated example is configured to store the result(s) of one or more operations performed by the corresponding logic gates. The storage circuit 1112 may be implemented by a register, etc. In the illustrated example, the storage circuit 1112 is distributed between the logic gate circuits 1108 to facilitate access and increase execution speed.

[0123] Fig.11 The exemplary FPGA circuit 1100 also includes an exemplary special operation circuit 1114. In this example, the special operation circuit 1114 includes a dedicated circuit 1116, which can be called to implement common functions to avoid the need to program these functions on site. Examples of such dedicated circuits 1116 include memory (e.g., DRAM) controller circuits, PCIe controller circuits, clock circuits, transceiver circuits, memories, and multiplier-accumulator circuit systems. There may be other types of dedicated circuits. In some examples, the FPGA circuit system 1100 may also include an exemplary general-purpose programmable circuit 1118, such as an exemplary CPU 1120 and / or an exemplary DSP 1122. There may be other general-purpose programmable circuits 1118 that can be programmed to perform other operations, such as GPUs, XPUs, etc., in addition or alternatively.

[0124] although Fig.10 and Fig.11 Shows Fig. 9 These are two exemplary implementations of the processor circuit 912, but many other approaches are contemplated. For example, as described above, modern FPGA circuits may include an onboard CPU, such as Fig.11 One or more of the exemplary CPUs 1120. Thus, Fig. 9 The processor circuit 912 may additionally be combined by Fig.10 The exemplary microprocessor 1000 and Fig.11 In some such hybrid examples, the exemplary FPGA circuit 1100 is implemented by Figure 5 , Figure 6 and / or Figure 8 The first portion of the machine-readable instructions represented by the flowchart may be represented by Fig.10 One or more of the cores 1002 are executed by Figure 5 , Figure 6 and / or Figure 8 The second portion of the machine-readable instructions represented by Fig.11 FPGA circuit 1100 performs, and / or is performed by Figure 5 , Figure 6 and / or Figure 8 The third portion of the machine-readable instructions represented by the flowchart may be executed by the ASIC. It should be understood that Figure 3 Some or all of the rule engine circuitry 130 may therefore be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads that execute simultaneously and / or serially. Furthermore, in some examples, Figure 3 Some or all of the rules engine circuitry 130 may be implemented within one or more virtual machines and / or containers executing on a microprocessor.

[0125] In some examples, Fig. 9 The processor circuit 912 may be in one or more packages. For example, Fig.10 The microprocessor 1000 and / or Fig.11 The FPGA circuit 1100 can be in one or more packages. In some examples, the XPU can be composed of Fig. 9 The XPU may be implemented in a processor circuit 912, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in yet another package.

[0126] exist Fig.12 A diagram is shown for converting Fig. 9932 to a hardware device owned and / or operated by a third party. The software distribution platform 1205 can be implemented by any computer server, data facility, cloud service, etc. that can store software and transfer software to other computing devices. The third party can be a customer of the entity that owns and / or operates the software distribution platform 1205. For example, the entity that owns and / or operates the software distribution platform 1205 can be a software (such as Fig. 9 The third party may be a consumer, user, retailer, OEM, etc. who purchases and / or licenses the software for use and / or resale and / or sub-license. In the example shown, the software distribution platform 1205 includes one or more servers and one or more storage devices. The storage device stores the machine-readable instructions 932, which may correspond to the above-described Figure 5 , Figure 6 and / or Figure 8 The one or more servers of the software distribution platform 1205 communicate with the exemplary network 1210, which may correspond to any one or more of the Internet and / or any of the networks 926 described above. In some examples, the one or more servers respond to a request to send software to a requesting party as part of a commercial transaction. The delivery, sale, and / or payment of the license for the software may be processed by one or more servers of the software distribution platform and / or by a third-party payment entity. The server enables a purchaser and / or licensee to download the machine-readable instructions 932 from the software distribution platform 1205. For example, the one or more servers may correspond to Figure 5 , Figure 6 and / or Figure 8 The software of the machine-readable instructions 500, 600 and / or 800 can be downloaded to the processor platform 900, which is used to execute the machine-readable instructions 932 to implement the rule engine circuit 130. In some examples, one or more servers of the software distribution platform 1205 periodically provide, transmit and / or force updates of the software (e.g., Fig. 9 932) to ensure that improvements, patches, updates, etc. are distributed and applied to the software at the end-user device.

[0127] In light of the foregoing, it should be appreciated that exemplary systems, methods, apparatus, and articles of manufacture have been disclosed that implement one or more checks and check actuators that are used by one or more workstations to reduce maintenance costs associated with system health and performance verification checks. The disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using computing devices by implementing a rule engine circuit 130 that can be independent of any individual workstation, which enables the use of the rule engine circuit 130 commonly or shared across a control system 100 at any of a plurality of workstations 110. Such an implementation allows for reduced maintenance costs and reduced risk of errors due to verification of system health and performance checks. Thus, the disclosed systems, methods, apparatus, and articles of manufacture relate to one or more improvements in the operation of a machine such as a computer or other electronic and / or mechanical device.

[0128] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for implementing one or more checks and check actuators used by one or more workstations to reduce maintenance costs associated with system health and performance verification checks. Other examples and combinations thereof include the following:

[0129] Example 1 includes a device for executing rules, the device including at least one memory, machine-readable instructions, and a processor circuit, the processor circuit being used to: instantiate or execute at least one of the machine-readable instructions to: access attribute values ​​from a data collector, the attribute values ​​including operation values ​​of a workstation within a process control system; create a data model instance representing the workstation; apply the attribute values ​​to the data model instance; identify a rule associated with the data model instance; cause an executable package associated with the rule to be executed using the data model instance; and record the results of the execution of the executable package.

[0130] Example 2 includes an apparatus as described in Example 1, wherein the processor circuit also instantiates or executes at least one of the machine-readable instructions to: access a rule configuration file that defines rule execution instructions; generate a computer-readable script based on the rule configuration file, compile the computer-readable script into an executable package, and store the executable package to a storage device.

[0131] Example 3 includes an apparatus as described in Example 1, wherein the processor circuit further instantiates or executes at least one of the machine-readable instructions to: apply updates to the core logic of the rule, parameters to be utilized during execution of the rule, or at least one of thresholds to be utilized during execution of the rule; and store a rule profile.

[0132] Example 4 includes the apparatus of Example 3, wherein the threshold is in a file separate from the rule.

[0133] Example 5 includes the apparatus of Example 1, wherein the data collector is to receive instructions for obtaining attribute values ​​via a network connection.

[0134] Example 6 includes the apparatus of Example 1, wherein the results of the rule execution are presented using a web-based interface.

[0135] Example 7 includes the apparatus of Example 1, wherein the result of the rule execution is stored to a storage device.

[0136] Example 8 includes the apparatus of Example 1, wherein the remote device is to instruct the processor circuit to at least one of instantiate or execute the machine-readable instructions.

[0137] Example 9 includes a non-transitory machine-readable storage medium that includes instructions that, when executed, cause a processor circuit to at least: access attribute values ​​from a data collector that include operational values ​​of a workstation within a process control system; create a data model instance representing the workstation; apply the attribute values ​​to the data model instance; identify a rule associated with the data model instance; cause an executable package associated with the rule to be executed using the data model instance; and record results of the execution of the executable package.

[0138] Example 10 includes the non-transitory machine-readable storage medium as described in Example 9, wherein the instructions, when executed, cause the processor circuit to at least: access a rule configuration file that defines rule execution instructions; generate a computer-readable script based on the rule configuration file; compile the computer-readable script into an executable package; and store the executable package to a storage device.

[0139] Example 11 includes a non-transitory machine-readable storage medium as described in Example 9, wherein the instructions, when executed, cause the processor circuit to at least: apply updates to the core logic of the rule, parameters to be utilized during execution of the rule, or at least one of thresholds to be utilized during execution of the rule; and store a rule profile.

[0140] Example 12 includes the non-transitory machine-readable storage medium of Example 11, wherein the threshold is compiled in a file separate from the rule.

[0141] Example 13 includes the non-transitory machine-readable storage medium of Example 9, wherein the instructions, when executed, cause the processor circuit to receive instructions for obtaining a property value via a network connection.

[0142] Example 14 includes the non-transitory machine-readable storage medium of Example 9, wherein the instructions, when executed, display results of the rule execution via a graphical user interface.

[0143] Example 15 includes a method for executing a rule, the method comprising: accessing attribute values ​​from a data collector, the attribute values ​​including operation values ​​of a workstation within a process control system; creating a data model instance representing the workstation; applying the attribute values ​​to the data model instance; identifying a rule associated with the data model instance; causing an executable package associated with the rule to be executed using the data model instance; and recording the execution results of the executable package.

[0144] Example 16 includes the method as described in Example 15, further comprising: accessing a rule configuration file that defines rule execution instructions; generating a computer-readable script based on the rule configuration file; compiling the computer-readable script into an executable package; and storing the executable package to a storage device.

[0145] Example 17 includes the method as described in Example 15, further comprising: applying updates to at least one of the core logic of the rule, the parameters to be utilized during the execution of the rule, or the thresholds to be utilized during the execution of the rule; and storing the rule configuration file.

[0146] Example 18 includes the method of Example 17, wherein the thresholds are edited in a file separate from the rules.

[0147] Example 19 includes the method of Example 15, wherein the data collector receives the instruction to obtain the attribute value via a network connection.

[0148] Example 20 includes the method of Example 15, wherein the results of the rule execution are displayed to at least one of a web-based interface or a graphical user interface.

[0149] Example 21 includes the method of Example 15, wherein the result of the rule execution is stored to a storage device.

[0150] Example 22 includes the method of Example 21, further comprising: querying the stored results; and analyzing the results to identify trend information.

[0151] Example 23 includes a device for executing rules, the device comprising: a unit for accessing attribute values ​​from a data collector, the attribute values ​​including operation values ​​of a workstation within a process control system; a unit for creating a data model instance representing the workstation; a unit for applying the attribute values ​​to the data model instance; a unit for identifying a rule associated with the data model instance; a unit for causing an executable package associated with the rule to be executed using the data model instance; and a unit for recording the execution results of the executable package.

[0152] Example 24 includes an apparatus as described in Example 23, wherein the unit for accessing is a first unit for accessing, and the apparatus further includes a second unit for accessing a rule configuration file defining rule execution instructions, a unit for generating a computer-readable script based on the rule configuration file, a unit for compiling the computer-readable script into an executable package, and a unit for storing the executable package to a storage device.

[0153] Example 25 includes an apparatus as described in Example 23, wherein the unit for applying is a first unit for applying, and the apparatus further includes a second unit for applying updates to at least one of core logic for applying rules, parameters to be utilized during execution of rules, or thresholds to be utilized during execution of rules, and a unit for storing rule profiles.

[0154] Example 26 includes the apparatus of Example 23, further comprising means for receiving, via a network connection, an instruction for obtaining a property value.

[0155] Example 27 includes the apparatus of Example 23, further comprising means for reporting results of the rule execution to a graphical user interface.

[0156] The attached claims are hereby incorporated by reference into this detailed description. Although certain example systems, methods, devices, and articles have been disclosed herein, the coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, devices, and articles that fully fall within the scope of the claims of this patent.

Claims

1. A device for executing a rule, comprising: at least one memory; machine-readable instructions; as well as Processor circuitry configured to at least one of instantiate or execute the machine-readable instructions to: accessing attribute values ​​from a data collector, the attribute values ​​comprising operational values ​​of a workstation within a process control system; creating a data model instance representing the workstation; applying the attribute value to the data model instance; identifying rules associated with the data model instance; causing execution of an executable package associated with the rule using the data model instance; and The result of executing the executable package is recorded.

2. The device according to claim 1, wherein: The processor circuit further at least one of instantiates or executes the machine-readable instructions to: Access rule configuration files that define rule execution instructions; generating a computer-readable script based on the rule configuration file; compiling the computer readable script into the executable package; and The executable package is stored in a storage device.

3. The device according to claim 1, wherein: The processor circuit further at least one of instantiates or executes the machine-readable instructions to: applying an update to at least one of a core logic of the rule, a parameter to be utilized during execution of the rule, or a threshold to be utilized during execution of the rule; as well as Storage rule configuration files.

4. The device according to claim 3, wherein: The thresholds are in a separate file from the rules.

5. The device according to claim 1, wherein: The data collector receives instructions for obtaining the attribute value via a network connection.

6. The device according to claim 1, wherein: The results of the rule execution are presented using a web-based interface.

7. The device according to claim 1, wherein: The results of the rule execution are stored in a storage device.

8. The device according to claim 1, wherein: The remote device is used to instruct the processor circuit to at least one of instantiate or execute the machine-readable instructions.

9. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a processor circuit to at least: accessing attribute values ​​from a data collector, the attribute values ​​comprising operational values ​​of a workstation within a process control system; creating a data model instance representing the workstation; applying the attribute value to the data model instance; identifying rules associated with the data model instance; causing execution of an executable package associated with the rule using the data model instance; and The result of executing the executable package is recorded.

10. The non-transitory machine-readable storage medium of claim 9, wherein: The instructions, when executed, cause the processor circuit to at least perform the following operations: Access rule configuration files that define rule execution instructions; generating a computer-readable script based on the rule configuration file; compiling the computer readable script into the executable package; and The executable package is stored in a storage device.

11. The non-transitory machine-readable storage medium of claim 9, wherein: When executed, the instructions cause the processor circuit to at least perform the following operations: applying an update to at least one of a core logic of the rule, a parameter to be utilized during execution of the rule, or a threshold to be utilized during execution of the rule; as well as Storage rule configuration files.

12. The non-transitory machine-readable storage medium of claim 11, wherein: The thresholds are compiled in a separate file from the rules.

13. The non-transitory machine-readable storage medium of claim 9, wherein: The instructions, when executed, cause the processor circuit to perform the following operations: receiving, via a network connection, an instruction for obtaining the property value.

14. The non-transitory machine-readable storage medium of claim 9, wherein: When executed, the instructions display the result of the rule execution via a graphical user interface.

15. A method for executing a rule, the method comprising: accessing attribute values ​​from a data collector, the attribute values ​​comprising operational values ​​of a workstation within a process control system; creating a data model instance representing the workstation; applying the attribute value to the data model instance; identifying rules associated with the data model instance; causing execution of an executable package associated with the rule using the data model instance; and The result of executing the executable package is recorded.

16. The method according to claim 15, further comprising: Access rule configuration files that define rule execution instructions; generating a computer-readable script based on the rule configuration file; compiling the computer readable script into the executable package; as well as The executable package is stored in a storage device.

17. The method according to claim 15, further comprising: applying an update to at least one of a core logic of the rule, a parameter to be utilized during execution of the rule, or a threshold to be utilized during execution of the rule; as well as Storage rule configuration files.

18. The method according to claim 17, wherein: The thresholds are compiled in a separate file from the rules.

19. The method according to claim 15, wherein: The data collector receives instructions for obtaining the attribute value via a network connection.

20. The method according to claim 15, wherein: Results of the rule execution are displayed to at least one of a web-based interface or a graphical user interface.

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