Fast memory clear for system memory

Abstract

Various embodiments are provided herein for compressing data in a delay critical processor link of a computing system in a computing environment. The one or more cache lines may be dynamically compressed at a lowest level of a network stack based on one or more of a plurality of parameters prior to transmitting a single cache line, wherein the network stack includes a framer and a data link layer.

Description

Background Art

[0001] The present invention relates generally to computing systems and, more particularly, to various embodiments for compressing data in a latency critical processor link of a computing system in a computing environment using computing processors. Summary of the invention

[0002] According to an embodiment of the present invention, a method for compressing data in a latency critical processor link of a computing system in a computing environment using a computing processor is described. One or more cache lines can be dynamically compressed at the lowest level of a network stack based on one or more of a plurality of parameters before transmitting the single cache line, wherein the network stack includes a framer and a data link layer.

[0003] Embodiments include a computer usable program product. The computer usable program product includes a computer readable storage device and program instructions stored on the storage device.

[0004] An embodiment includes a computer system. The computer system includes a processor, a computer-readable memory and a computer-readable storage device, and program instructions stored on the storage device for execution by the processor via the memory.

[0005] Therefore, in addition to the foregoing exemplary method embodiments, other exemplary system and computer product embodiments are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram depicting an exemplary cloud computing node according to an embodiment of the present invention.

[0007] Figure 2 A cloud computing environment according to an embodiment of the present invention is depicted.

[0008] Figure 3 Abstract model layers according to an embodiment of the present invention are depicted.

[0009] Figure 4 are additional block diagrams that depict exemplary functional relationships between various aspects of the invention.

[0010] Figure 5 is a block diagram depicting operations for compressing data in a latency critical processor link of a computing system in a computing environment in accordance with an embodiment of the present invention.

[0011] Figure 6 is an additional block diagram depicting operations for compressing data in a latency critical processor link of a computing system in a computing environment in accordance with an embodiment of the present invention.

[0012] Figure 7is an additional block diagram depicting operations for compressing data in a latency critical processor link of a computing system in a computing environment in accordance with an embodiment of the present invention.

[0013] Figure 8 is an additional block diagram depicting operations for compressing data in a latency critical processor link of a computing system utilizing compression in a framer and decompression in a parser in a computing environment in accordance with an embodiment of the present invention.

[0014] Fig. 9 is a flow chart depicting an additional exemplary method for compressing data in a latency critical processor link of a computing system in a computing environment according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In modern computer systems, multiprocessor systems include multi-core central processing units (CPUs) in a single module. Typically, communication between processors in a multiprocessor system is via an inter-processor bus (also called a processor link). Processors coupled via a processor link (i.e., a driver processor and a destination processor) are typically associated with I / O parameters that govern analog characteristics of signals transmitted from the driver processor and corresponding signals received at the destination processor. Characterizing the processor link during the testing / validation phase can help identify optimal I / O parameters for reliably achieving the desired performance level.

[0016] In addition, a computer hardware cache is a temporary holding storage device for quickly accessing frequently used memory data. In other words, in order to reduce or avoid the time delay (or "wait time") for accessing data stored in the computer's main memory, modern computer processors include cache memory (or "cache"), which stores recently accessed data so that it can be quickly accessed by the processor again. Data stored in the cache can be quickly accessed by the processor without accessing the main memory (or "memory"), thereby improving the performance of the processor and the computer as a whole. The cache has a shorter access time than the computer system memory (e.g., often referred to as dynamic random access memory "DRAM"). The cache is usually composed of static random access memory ("SRAM"), which is faster than DRAM. However, the cache capacity is smaller than DRAM. The cache / memory access speed and capacity are inversely proportional.

[0017] Several different layers of cache may be provided in a computer system. For example, a Level 1 (or primary) cache is used to store data on behalf of the system memory (which includes random access memory, or RAM) for access by the processor. A Level 1 ("L1") cache may be built directly into the processor and may run at the same speed as the processor, providing the fastest possible access time. A Level 2 (or secondary) ("L2") cache is also used to store a portion of the system memory and may be included within the chip package but separate from the processor. A Level 2 cache has a larger capacity than a Level 1 cache, but is slower. Some systems may even include a Level 3 ("L3") cache with an even larger capacity than a Level 2 cache. However, a Level 3 cache is typically slower than a Level 2 cache, but still faster than primary storage, and may be located outside the chip package.

[0018] Data in a cache is stored in "lines," which are contiguous blocks of data (i.e., a power-of-two number of bytes long, aligned on boundaries corresponding to that size). That is, data is typically transferred and accessed in groups called cache lines, which may include more than one data item.

[0019] In a typical computing architecture, a processor core may be connected to a cache (e.g., an on-chip cache or "nest"), which in turn is connected to a processor link ("link"). The nest and link are designed to operate at a much lower speed than the processor core. The nest may be a computing infrastructure that handles data transfer between a core and other cores, main memory, and input / output ("I / O") devices. The nest is responsible for maintaining the coherence of data lines throughout the system. It is not an industry standard term, so perhaps we should define it better before using it. There are many data links in a computing system - processor-to-IO links (PCIe, Ethernet), processor-to-memory links, and processor-to-processor links. The nest includes all the infrastructure that handles these links. Therefore, a link may be a connection that facilitates data transfer to / from a processor. In other words, in a computer system configuration where a cache is shared between different processors connected together by an inter-processor link, there may be a coherent transfer of cache data lines between processors.

[0020] Typical computing systems have a handshake protocol for cache line transfers, and only a limited number of requests on a link can be outstanding. Requests for cache line transfers are satisfied, but are limited by the link speed. This provides computer system performance with reasonable power consumption, since not all processor core computations require nested or linked interactions. However, when processor cores request cache lines over a processor link, speed mismatches negatively impact the performance of the computer system. For example, physical limitations limit link speed, which is a combination of the number of serial lanes per link and the operating speed.

[0021] Therefore, the present invention provides for improving and optimizing the effective bandwidth and latency of such constrained processor links while reducing computational processor overhead to improve and provide increased computational efficiency.

[0022] In this manner, the present invention provides increased computing system performance through reduced latency of single cache line transfers via lossless compression.

[0023] Therefore, various embodiments are provided herein for compressing data in a delay-critical processor link of a computing system in a computing environment using a computing processor. One or more cache lines can be dynamically compressed at the lowest level of a network stack based on one or more of a plurality of parameters before transmitting a single cache line, wherein the network stack includes a framer and a data link layer. In some examples, a data packet created for transmission over a link may include header information, cache line data, and some control information. The cache line data may be compressed, while other parts of the data packet (e.g., header, control flags) are not compressed. Therefore, in practice, more cache line data may fit into a single data packet when compressed. That is, cache lines may be dynamically compressed at the lowest level (framer / DLL) of the network stack rather than at the application layer.

[0024] It should be noted that as used herein, a network stack may include the following layers; 1) Application Layer (the application layer may be the core and any software running), 2) Transport Layer (a layer that handles consistency of data transmission - creates packets from cache lines of data for transmission, and processes received packets for delivery to the application layer), 3) Data Link Layer (a layer responsible for ensuring error-free and in-order delivery of data packets), and 4) Physical Layer (the actual circuit). Thus, the core may be the application layer, the nest may be the transport layer, and the link may be the link layer and the physical layer.

[0025] Thus, the lower level of compression is that it is a purely hardware ("HW") driven mechanism without any intervention from the kernel or software application.

[0026] In one example, a framer may be defined as a component / module that frames data to transmit over a link by adding some additional information in a predefined organization to allow processing of the data at the receiving side. The DLL may be a data link layer.

[0027] In some examples, various embodiments provide for compressing data in the data link layer using framer feedforward. In some examples, various embodiments provide for compressing data in a framer with bus feedback. In some examples, various embodiments provide for dynamic compression switching based on cache line contention. For example, an attacker may attempt to create frequent transfers of cache lines between processors to obtain information about their compressibility. If a large number of transfers are observed in a particular address space, i.e., there is high contention for some cache lines, it is safer to disable compression to prevent any information leakage.

[0028] In this way, various embodiments provide pipelined compression at the data link layer and achieve compression in a computing system without any performance loss. That is, compared to compression only on the cache all the time, the present invention provides low latency compression on the data link without compromising security via side channels. By enabling dynamic compression operations on the data link, any real-time impact (positive or negative) of compression on performance can be evaluated, thereby enabling corrective actions / selections to adjust compression and reduce latency.

[0029] In some examples, various embodiments provide for compressing data at the data link layer by using control signals at the link layer. That is, data can be dynamically compressed by dynamically adapting to data link layer conditions to increase compression efficiency in terms of latency to be equal to or greater than the data link speed without compression.

[0030] In some examples, various embodiments provide for implementing compression at the link level to reduce link latency while not increasing the complexity of the cache implementation and keeping overall cache data access latency equal to or better than a system without compression.A cache line is considered the smallest entity to operate on and can therefore be implemented on link data.

[0031] It should be noted that one or more calculations may be performed using various mathematical operations or functions that may involve one or more mathematical operations (e.g., analytically or computationally solving differential equations or partial differential equations, using addition, subtraction, division, multiplication, standard deviations, means, averages, percentages, using statistical modeling of statistical distributions, by finding minimum, maximum, or similar thresholds of combined variables, etc.).

[0032] In general, as used herein, "optimization" may refer to and / or be defined as "maximizing," "minimizing," "optimizing," or achieving one or more specific goals, objectives, goals, or intentions. Optimization may also refer to maximizing benefit to a user (e.g., maximizing benefit to a trained machine learning scheduling agent). Optimization may also refer to making the most efficient or functional use of a situation, opportunity, or resource.

[0033] In addition, optimization need not refer to the best solution or result, but can refer to a solution or result that is "good enough" for a particular application, for example. In some implementations, the goal is to suggest the "best" combination of operations, scheduling, compression / decompression operations and / or framer / DLL manager options, but there may be various factors that can cause alternative suggestions for combinations of operations, scheduling, compression / decompression operations and / or framer / DLL manager options to produce better results. In this article, the term "optimization" can refer to such results based on minimum values ​​(or maximum values, depending on what parameters are considered in the optimization problem). In other aspects, the term "optimization" can refer to operations performed to achieve improved results (e.g., reduced execution costs or increased resource utilization), regardless of whether the optimal result is actually achieved. Similarly, the term "optimization" can refer to components used to perform such improved operations, and the term "optimization" can be used to describe the results of such improved operations.

[0034] It should be understood in advance that although the present disclosure includes detailed descriptions about cloud computing, the implementation of the teachings described herein is not limited to cloud computing environments. Instead, embodiments of the present invention can be implemented in conjunction with any other type of computing environment now known or later developed.

[0035] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage devices, applications, virtual machines, and services) that can be quickly provisioned and released with minimal management effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0036] Features are as follows:

[0037] On-demand self-service: Cloud consumers can automatically and unilaterally provision computing capabilities, such as server time and network storage, as needed, without requiring human interaction with the service provider.

[0038] Broad network access: Capabilities are available over the network and accessed through standard mechanisms that facilitate the use of heterogeneous thin-client platforms or thick-client platforms (eg, mobile phones, laptops, and PDAs).

[0039] Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated based on demand. There is a sense of location independence, as consumers generally have no control or knowledge of the exact location of the resources provided, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0040] Rapid elasticity: Capacity can be provisioned quickly and elastically, in some cases automatically, to scale up quickly and released quickly to scale out quickly. To the consumer, the capacity available for provisioning often appears to be unlimited and can be purchased in any quantity at any time.

[0041] Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the utilized services.

[0042] The service model is as follows:

[0043] Software as a Service (SaaS): The capability provided to the consumer is to use the provider's applications running on the cloud infrastructure. The applications can be accessed from a variety of client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage devices, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0044] Platform as a Service (PaaS): The capability provided to consumers is to deploy applications created or acquired by consumers onto the cloud infrastructure. Applications created or acquired by consumers are created using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but have control over deployed applications and possibly the configuration of the application hosting environment.

[0045] Infrastructure as a Service (IaaS): The capability provided to consumers is the provisioning of processing, storage, networking, and other basic computing resources, where consumers can deploy and run arbitrary software, which may include operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but have control over the operating system, storage, deployed applications, and may have limited control over select networking components (e.g., host firewalls).

[0046] The deployment model is as follows:

[0047] Private Cloud: Cloud infrastructure is operated for only one organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0048] Community cloud: The cloud infrastructure is shared by several organizations and supports a specific community with common concerns (e.g., mission, security requirements, policies, and compliance considerations). It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0049] Public cloud: Cloud infrastructure is available to the general public or large industry groups and is owned by an organization that sells cloud services.

[0050] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain distinct entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0051] The cloud computing environment is service-oriented, with characteristics centered on statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is the infrastructure consisting of a network of interconnected nodes.

[0052] Reference now Figure 1 , a schematic diagram of an example of a cloud computing node is shown. Cloud computing node 10 is only one example of a suitable cloud computing node and is not intended to impose any limitations on the scope of use or functionality of the embodiments of the present invention described herein. Regardless, cloud computing node 10 is capable of implementing and / or performing any of the functions set forth above.

[0053] In cloud computing node 10, there is a computer system / server 12, which can operate with many other general or special computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, fat clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, etc.

[0054] Computer system / server 12 may be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Computer system / server 12 may be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0055] like Figure 1 As shown, the computer system / server 12 in the cloud computing node 10 is shown in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18, which couples various system components including the system memory 28 to the processor 16.

[0056] Bus 18 represents any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0057] Computer system / server 12 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, and it includes volatile and nonvolatile media, removable and non-removable media.

[0058] The system memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may also include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 may be provided for reading and writing from a non-removable, non-volatile magnetic medium (not shown and generally referred to as a "hard drive"). Although not shown, a disk drive for reading from and writing to a removable non-volatile disk (e.g., a "floppy disk") may be provided, as well as an optical drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media). In this case, each may be connected to the bus 18 via one or more data media interfaces. As will be further depicted and described below, the system memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of an embodiment of the present invention.

[0059] By way of example and not limitation, a program / utility 40 having a set (at least one) of program modules 42, as well as an operating system, one or more application programs, other program modules, and program data, may be stored in system memory 28. Each or some combination of the operating system, one or more application programs, other program modules, and program data may include an implementation of a networking environment. Program modules 42 generally perform the functions and / or methods of embodiments of the present invention as described herein.

[0060] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, a pointing device, a display 24, etc.; one or more devices that enable a user to interact with the computer system / server 12; and / or any device that enables the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 22. In addition, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems, etc.

[0061] Reference now Figure 2, depicts an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 with which a local computing device used by a cloud computing consumer (e.g., a personal digital assistant (PDA) or cellular phone 54A, a desktop computer 54B, a laptop computer 54C, and / or an automobile computer system 54N) can communicate. The nodes 10 can communicate with each other. They can be physically or virtually grouped in one or more networks (not shown), such as a private cloud, community cloud, public cloud, or hybrid cloud as described above, or a combination thereof. This allows the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service that cloud consumers do not need to maintain resources on local computing devices. It should be understood that Figure 2 The types of computing devices 54A-N shown in are intended to be illustrative only, and computing node 10 and cloud computing environment 50 may communicate with any type of computerized device over any type of network and / or network addressable connection (eg, using a web browser).

[0062] Reference now Figure 3 , showing the cloud computing environment 50 ( Figure 2 ) provides a set of functional abstraction layers. First of all, it should be understood that Figure 3 The components, layers and functions shown in are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0063] The device layer 55 includes physical and / or virtual devices, embedded and / or independent electronic devices, sensors, actuators and other objects to perform various tasks in the cloud computing environment 50. Each device in the device layer 55 combines networking capabilities with other functional abstraction layers so that information obtained from the device can be provided to it, and / or information from other abstraction layers can be provided to the device. In one embodiment, the various devices comprising the device layer 55 can include a network of entities collectively referred to as the "Internet of Things" (IoT). As will be understood by those of ordinary skill in the art, such a network of entities allows for the mutual communication, collection and dissemination of data to achieve a variety of purposes.

[0064] The device layer 55 shown includes sensors 52, actuators 53, a "learning" thermostat 56 with integrated processing, sensors and networked electronics, a camera 57, a controllable household outlet / receptacle 58, and a controllable electrical switch 59 as shown. Other possible devices may include, but are not limited to, various additional sensor devices, networked devices, electronic devices (such as remote control devices), additional actuator devices, so-called "smart" appliances (such as refrigerators or washing machines / dryers), and a wide variety of other possible interconnected objects.

[0065] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: host 61; server 62 based on RISC (Reduced Instruction Set Computer) architecture; server 63; blade server 64; storage device 65; and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0066] Virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 71 ; virtual storage 72 ; virtual networks 73 , including virtual private networks; virtual applications and operating systems 74 ; and virtual clients 75 .

[0067] In one example, the management layer 80 may provide the functionality described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources for performing tasks within a cloud computing environment. Metering and pricing 82 provides cost tracking when utilizing resources within a cloud computing environment, as well as billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management so that the required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides pre-scheduling and procurement of cloud computing resources, anticipating future demand for cloud computing resources based on the SLA.

[0068] The workload layer 90 provides examples of functionality that can take advantage of a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and, in the context of the illustrated embodiment of the present invention, various workloads and functionality 96 for compressing data in latency-critical processor links of computing systems in a computing environment. In addition, the workloads and functionality 96 for compressing data in latency-critical processor links of computing systems in a computing environment may include operations such as interleaving and user and device management functionality as will be further described. One of ordinary skill in the art will appreciate that the workloads and functionality 96 for compressing data in latency-critical processor links of computing systems in a computing environment may also work in conjunction with other portions of various abstraction layers, such as abstraction layers in hardware and software 60, virtualization 70, management 80, and other workloads 90, such as data analytics processing 94, to achieve the various purposes of the illustrated embodiment of the present invention.

[0069] As previously described, the present invention provides novel solutions for improving and optimizing the effective bandwidth and latency of such constrained processor links while reducing computational processor overhead to improve and provide increased computational efficiency. Therefore, various embodiments are provided herein for using a computational processor to compress data in a latency-critical processor link of a computing system in a computing environment. One or more cache lines may be dynamically compressed at the lowest level of a network stack based on one or more of a plurality of parameters before transmitting a single cache line, wherein the network stack includes a framer and a data link layer. That is, cache lines may be dynamically compressed at the lowest level of the network stack (framer / DLL) rather than at the application layer.

[0070] In some examples, various embodiments are provided herein for dynamic compression of cache lines at the lowest level of a network stack (framer / DLL), rather than via an application layer where pipeline compression is performed, as described herein. In some examples, data is fed from the framer to the DLL using the feed data to determine the amount of compression to attempt. One or more queue levels in the framer may be monitored.

[0071] In some examples, various embodiments are provided herein for dynamically compressing by dynamically turning on or off dynamic compression, which may be based on rate matching, as described herein. Various embodiments provide compression operations designed to be aware of clock differences between links and nests using rate matching. In some examples, various embodiments are provided herein for dynamic compression, which prevent timing side channel attacks by dynamically controlling compression on hot cache lines (e.g., cache lines that are frequently transferred, such as, for example, more than other cache lines, transferred above a predetermined threshold, transferred at a defined percentage or above a defined percentage, and / or transferred above a defined percentage), and / or the number of times n is transferred within a specified time period, etc., where n is a positive integer. That is, an attack that may exploit the time taken to perform a particular operation to obtain additional information about the operation itself. Therefore, if a certain amount of data is observed to be transferred quickly between processors, it indicates that the data has low entropy, and an attacker can attempt to obtain further information based on the low entropy.

[0072] Now go to Figure 4 , a block diagram of exemplary functional components of a cache system 400 for compressing data in a latency-critical processor link of a computing system in a computing environment is shown depicting various mechanisms according to the illustrated embodiments. In one aspect, the cache system 400 may be configured to provide a cache memory for a computing system in a computing environment. Figure 4 Use in Figure 1-3 As will be seen, in conjunction with the previously described Figure 1-3In the same descriptive sense described in , many functional blocks can also be considered as functional "modules" or "components".

[0073] System 400 includes memory 410 , cache 420 (eg, a cache data array), and cache directory 430 , all of which may be in communication with processor 450 .

[0074] Data in cache 420 is stored in "lines", such as, for example, memory line 422, which is a contiguous block of data (i.e., a power of 2 number of bytes long, aligned on a boundary corresponding to that size). Cache lines 422 of memory data (typically in units of 64 to 256 bytes long) are stored in data array locations, and the corresponding memory addresses are stored in the directory, such as Figure 4 Processor 450 provides a memory address to a cache, such as cache data array 420. If the address is found in cache directory 430, processor 450 may access the corresponding data line in cache 420. If the address is not found in cache directory 430, processor 450 may access the corresponding data line in memory 410.

[0075] Now go to Figure 5 , a block diagram depicting exemplary functional components of a system 500 for compressing data in a latency-critical processor link of a computing system in a computing environment according to various mechanisms of the illustrated embodiments is shown. In one aspect, the Figure 5 Use in Figure 1-4 As will be seen, in conjunction with the previously described Figure 1-4 In the same descriptive sense described in , many functional blocks can also be considered as functional "modules" or "components".

[0076] Data compression service 510 is shown, which includes a processing unit 520 ("processor") to perform various computations, data processing, and other functions according to various aspects of the present invention. In one aspect, processor 520 and memory 530 can be internal and / or external to interleaving service 510, and internal and / or external to computing system / server 12. Interleaving service 510 can be included in computer system / server 12 and / or external to computer system / server 12, such as Figure 1 The processing unit 520 may be in communication with the memory 530 . The data compression service 510 may include a compression component 540 , a framer / data link layer (“DLL”) component 550 , a determination component 560 , and a decompression component 570 .

[0077] In one aspect, system 400 can provide virtualized computing services (ie, virtualized computing, virtualized storage, virtualized networking, etc.) More specifically, system 500 can provide virtualized computing, virtualized storage, virtualized networking, and other virtualized services executed on a hardware substrate.

[0078] The data compression service 510 may use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to determine to compress one or more cache lines based on one or more of a plurality of parameters, wherein the plurality of parameters include a number of pending data packets, quality of service ("QoS"), and a current packet type, wherein the current packet type is either a data packet or a control packet.

[0079] The data compression service 510 can use a compression component 540, a framer / DLL component 550, a determination component 560, and a decompression component 570 to dynamically compress one or more cache lines at the lowest level of a network stack, including a framer and a data link layer, based on one or more of a plurality of parameters before transmitting the single cache line.

[0080] The data compression service 510 can use the compression component 540, the framer / DLL component 550, the determination component 560 and the decompression component 570 to enable compression of one or more cache lines based on the data in the queue being above a defined threshold, or to disable compression of one or more cache lines based on the data in the queue being below a defined threshold.

[0081] Data compression service 510 may feed data from the framer to the data link layer using compression component 540, framer / DLL component 550, determination component 560, and decompression component 570 to determine the amount of data to compress based on one or more of a plurality of parameters.

[0082] Data compression service 510 may use compression component 540, framer / DLL component 550, determination component 560, and decompression component 570 to dynamically switch compression of one or more cache lines using a Bloom filter on a previously passed set of cache line addresses.

[0083] Data compression service 510 may use compression component 540, framer / DLL component 550, determination component 560, and decompression component 570 to dynamically compress one or more cache lines to match the data input rate.

[0084] Data compression service 510 may use compression component 540, framer / DLL component 550, determination component 560, and decompression component 570 to dynamically control compression of one or more cache lines based on the number of hot cache lines.

[0085] To explain further, Figure 6 is a block diagram depicting operations for compressing data in a latency-critical processor link of a computing system in a computing environment according to an embodiment of the present invention. Figure 6 Use in Figure 1-5 As shown, various blocks of functionality are depicted using arrows that specify the relationship of the blocks of system 600 to each other and illustrate process flow (e.g., steps or operations). In addition, descriptive information associated with each functional block of system 600 can also be seen. As will be seen, in the same manner as previously described in Figure 1-5 In the same descriptive sense described in the foregoing, many functional blocks may also be considered as "modules" of functionality. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted.

[0086] In view of the foregoing, the modules of system 600 may also be incorporated into various hardware and software components of a computing system, or in a cloud computing environment according to the present invention. Many functional blocks of system 600 may be executed as background processes on various components in a distributed computing component or elsewhere.

[0087] As depicted, in a first example of system 600, a framer 610A at a data link layer is depicted for receiving data packets (e.g., receiving data from a processor core that is not shown for ease of illustration). A queue 612A may exist in the framer 610A, where the queue 612A may be monitored. A determination operation may be performed in the queue 612A to determine whether the data (e.g., the number of data packets in the queue 612A) is below a threshold for disabling compression. If so, a decision to disable compression is determined, and a compressor 614A bypasses compression of the data in the queue 610A and transmits data 616A to a parser 618A, which receives uncompressed data, such as 620A and 622A. In one example, the threshold may be dynamically set to the average compressibility of previous packets multiplied by the number of clocks / times taken to compress a single packet.

[0088] In a second example of system 600, a framer 610B at a data link layer is depicted for receiving data packets (e.g., receiving data from a processor core that is not shown for ease of illustration). A queue 612B may exist in the framer 610B, where the queue 612B may be monitored. A determination operation may be performed in the queue 612B to determine whether the data (e.g., the number of data packets in the queue 612B) is above a threshold for enabling compression. If so, a decision is performed to enable compression, and the data may be sent to a compressor 614B, and a cache line may be dynamically compressed. The compressed cache line 616B may be transmitted to a parser 618B for decompressing one or more cache lines, such as, for example, 620B and 622B.

[0089] In this way, embodiments dynamically determine how much (if any) the next data should be compressed, which allows scaling computing system performance by transmitting more data using the same link bandwidth without compromising latency. While this change may add certain side channels, one or more protections against side channel attacks are provided.

[0090] Figure 7 is an additional block diagram depicting operations for compressing data in a latency-critical processor link of a computing system in a computing environment in accordance with an embodiment of the present invention. Figure 7 Use in Figure 1-6 One or more of the components, modules, services, applications and / or functions described in the present invention. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0091] A network stack 700 is depicted, which includes a framer 710, a compressor 720, and a data link layer (e.g., a data link adapter 730 ("DLA") or also referred to as a DLL), which may be associated with a processor core. It should be noted that "DLA" may be used interchangeably with "DLL." DLA 730A may communicate with additional DLAs such as DLA 730B, which is associated with a decompressor 740 and a parser 750. In some implementations, framer 710 and DLA 730A may communicate with one or more compression ("CMP") controls.

[0092] In operation, the framer 710 may receive incoming data (eg, from a processor core). That is, the incoming packet may be 30 bytes and include a packet identifier ("ID"), which may indicate the packet type.

[0093] The framer 710 can indicate various parameters to the DLL (e.g., DLA 730A) for compressing or not compressing data. In one example, the framer 710 indicates at least three parameters to the DLA 730A; 1) the number of pending data packets (e.g., pending data), 2) quality of service ("QoS"), and 3) the current packet type, where the current packet type is a data packet or a control packet. In some examples, a shutdown signal from the link layer to the framer can be used to allow the DLL to control the flow rate of data. In one example, due to some error conditions in the link, the link may not be ready to accept new packets, and the DLL will shut down the framer. In some implementations, a modified version of the shutdown signal can be used to indicate that the compression engine is busy processing packets and should not drive in new packets. Therefore, the modified shutdown signal is the original DLL shutdown and any reason that the compression engine may have.

[0094] Based on these parameters, the compressor 720 can perform at least two phases: 1) a compression phase or a non-compression phase. That is, in the non-compression phase, the compressor does not attempt to compress the current packet type indicated as a control packet. That is, the cache line indicated as control is not compressed. Instead, based on the assumption that the control packet is difficult to compress, the compressor 720 passes the data (e.g., cache line) to the DLA 730A.

[0095] Alternatively, during the compression phase, the compressor 720 attempts to compress the data based on the amount of pending data (e.g., pending data in the queue in the framer 710). For example, if the amount of pending data is greater than a threshold, the compressor 720 will attempt to compress more cache lines. Alternatively, if the amount of pending data is less than a threshold, the compressor 720 will compress and zero-fill to the packet size. For example, consider the case where there are three packets P0, P1, and P2. Ideally, if all three packets can be compressed together, only one packet is transmitted. After compressing P0 and P1, it can be observed that P2 cannot be compressed into the same packet and it overflows. At this point, the compressed form of P0 and P1 (e.g., P0+P1) together with the zeros added to reach the fixed packet size can be sent and transferred out. P2 can then be sent out separately.

[0096] The compressor 720 also considers the quality of service ("QoS") required for compression. The QoS is an indication of how much additional latency can be added to that particular data packet (e.g., cache line) without having a negative system impact. Higher latency indicates that the compressor 720 will try to pack more data (e.g., pack more cache lines) into the packet, otherwise the compressor 720 will compress, zero-fill to the packet size, and flush earlier.

[0097] For example, as previously described in the P0, P1, P2 scenario, another option for the compression engine is to put P0, P1, and P2 together and try to increase compression rather than processing them individually. Compressing packets individually is ideal for latency because multiple packets do not need to be buffered. However, compressing packets together improves efficiency and can result in more compression at the expense of latency. The QoS factor indicates whether the data can withstand a delay, even if only slightly, in order to identify a more efficient compression format. If latency is critical, a decision can be made to just send out the packet without processing it.

[0098] For example, as Figure 7 In an example of operation, the transmit core (eg, Tx side) bus may be released faster than a normal number of processor clock signals ("PCLKs") earlier (eg, 28 PCLKs). In addition, Figure 7 The operation can complete the cache line transfer (256 bytes) in the Nth plks earlier / faster (e.g., complete the cache line transfer 24PCLKs earlier). In addition, the bandwidth is increased on average, for example, the bandwidth is increased by 20%. On average, each oct word ("OW") (32 bytes) arrives multiple pclks faster, for example, each OW arrives 10 pclks earlier. In one aspect, the first OW is delayed by 2 pclks, and all other OWs arrive pclks earlier.

[0099] Figure 8 is an additional block diagram depicting operations for compressing data in a latency critical processor link of a computing system utilizing compression in a framer with bus feedback (e.g., compression in the framer and decompression in the parser) in a computing environment in accordance with an embodiment of the present invention. In one aspect, the Figure 8 Use in Figure 1-7 One or more of the components, modules, services, applications and / or functions described in the present invention. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0100] As depicted, the compressor in the framer 810 may receive a frame with tag (n+1) and data (n). The compressor may have a tag buffer and an 8-deep data buffer. Assume that the nesting clock is equal to the processor core clock divided by 2 to obtain the input flow rate (e.g., ), the link clock is equal to the processor core clock divided by 3 to get the output flow rate (for example, ). That is, the cache (e.g., nested) operates at half the speed of the processor core, and the link operates at one-third the speed of the processor core.

[0101] It should be noted that the threshold calculation may be similar to the previous case, and the maximum compression to attempt (eg, 2x, 4x, 8x) may be determined as the fill level divided by the output flow rate.

[0102] Therefore, given a packet that can be received at 37 bytes, only twenty (20) bytes can be flushed. That is, the DLL framer fill rate is equal to 37 bytes ("B") per nesting clock ( ). The DLL framer refresh rate is equal to twenty bytes per nesting clock (for example, ).

[0103] The compressor of the framer (eg, DLL compression) attempts to compress based on rate matching. That is, in some examples, the compressor of the framer 810 attempts to compress at a compression ratio (eg, eight times the compression ratio). ') dynamically compresses the cache line. If the fill level is equal to or greater than 180 bytes. In some examples, the compressor of the framer 810 attempts to compress the cache line at a compression ratio (e.g., four times the ' ') dynamically compresses the cache line. If the fill level is equal to or greater than 100 bytes. In some examples, the compressor of the framer 810 attempts to compress the cache line at a compression ratio (e.g., twice the ' ') Compress cache lines dynamically. If fill level is equal to or greater than 60 bytes.

[0104] In some examples, the compressor of the framer 810 does not compress the data and allows the data to pass through. In this way, various embodiments provide dynamic compression without increasing latency in the transfer of cache lines.

[0105] The framer 810 may send compressed or uncompressed data to the parser 820, and a decompressor of the parser 820 may decompress the data.

[0106] For further example, various embodiments of dynamic compression and transmission ("Tx") are provided to release 9 pclks early per cache line. Receive ("Rx") completes cache line transfers 4 pclks early (and the nominal latency of 1 cache line, assuming everything else is idle). In addition, transfers of zero to two OWs experience no additional delay at the parser 820 output. The third OW can be delayed by only 2 PCLKs. Transfers of OWs 4-7 can arrive 1, 2, 3, and 4 PCLKs early, respectively. Therefore, averaged over isolated cache lines, each OW arrives 1 pclks early. Averaged over multiple transactions, each OW arrives at least 7 pclks early.

[0107] Additionally, due to the compression of cache lines, an attacker can launch an attack that continually flushes and reloads sensitive lines. Based on the time taken to flush and reload, the attacker can determine the compressibility of the line that leaks entropy. To overcome this weakness, the present invention can implement a Bloom filter on a set of previously transmitted cache line addresses. If the same cache line is moved back and forth too many times (a programmable limit), compression can be turned off (e.g., dynamic compression is turned off). If the computing system does not have hot cache lines that have been flushed / reloaded too many times, dynamic compression can be turned on again. Compression can also be turned on again after a defined period of time (e.g., dynamic compression is toggled on).

[0108] Now turn to Fig. 9 , depicts a method 900 for using a processor to compress data in a latency-critical processor link of a computing system in a computing environment, in which aspects of the illustrated embodiments may be implemented. Function 900 may be implemented as a method executed as instructions on a machine (e.g., a computer-implemented method), where the instructions are included on at least one computer-readable medium or a non-transitory machine-readable storage medium. Function 900 may begin in block 902.

[0109] The one or more cache lines may be dynamically compressed at the lowest level of a network stack including a framer and a data link layer based on one or more of a plurality of parameters prior to transmitting the single cache line, as shown in block 904. Functionality 900 may end, as shown in block 906.

[0110] In one aspect, in combination Fig. 9 At least one box and / or as Fig. 9 The operations of method 900 may include each of the following: The operations of method 900 may enable compression of one or more cache lines based on data in the queue being above a defined threshold; or disable compression of one or more cache lines based on data in the queue being below a defined threshold.

[0111] The operations of method 900 may determine to compress one or more cache lines based on one or more of a plurality of parameters, wherein the plurality of parameters include a number of pending data packets, quality of service (“QoS”), and a current packet type, wherein the current packet type is a data packet or a control packet.

[0112] The operations of method 900 may feed data from a framer to a data link layer to determine an amount of data to be compressed based on one or more of a plurality of parameters. The operations of method 900 may dynamically switch compression of one or more cache lines over a set of previously passed cache line addresses using a Bloom filter. The operations of method 900 may dynamically compress one or more cache lines to match a data input rate. The operations of method 900 may dynamically control compression of one or more cache lines based on a number of hot cache lines.

[0113] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium (or medium) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.

[0114] A computer-readable storage medium may be a tangible device that can retain and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device (such as a punched card or a raised structure in a groove on which instructions are recorded), and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0115] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0116] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions to personalize the electronic circuits by utilizing the state information of the computer-readable program instructions so as to perform various aspects of the present invention.

[0117] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0118] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can instruct the computer, programmable data processing device, and / or other device to function in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0119] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device, so that a series of operational steps are performed on the computer, other programmable device, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0120] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing a specified logical function. In some alternative embodiments, the function annotated in the frame may not occur in the order annotated in the figure. For example, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the functions involved. It will also be noted that each frame of the block diagram and / or flow chart illustration and the combination of frames in the block diagram and / or flow chart illustration can be implemented by a system based on dedicated hardware that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0121] The description of the embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for compressing data in a delay-critical processor link of a computing system in a computing environment by one or more processors, comprising: One or more cache lines at a lowest level of a network stack including a framer and a data link layer are dynamically compressed based on one or more of a plurality of parameters prior to transmitting the single cache line.

2. The method according to claim 1, further comprising: enabling compression of the one or more cache lines based on data in the queue being above a defined threshold; or Compression of the one or more cache lines is disabled based on data in the queue being below a defined threshold.

3. The method of claim 1 , further comprising determining to compress the one or more cache lines based on one or more of the plurality of parameters, wherein the plurality of parameters comprises a number of pending data packets, quality of service (“QoS”), and a current packet type, wherein the current packet type is a data packet or a control packet.

4. The method according to claim 3, further comprising: Data is fed from the framer to the data link layer to determine an amount of data to be compressed based on one or more of the plurality of parameters.

5. The method according to claim 1, further comprising: Compression of the one or more cache lines is dynamically switched using a Bloom filter on a set of previously transmitted cache line addresses.

6. The method of claim 1, further comprising dynamically compressing the one or more cache lines to match a data input rate.

7. The method according to claim 1, further comprising: Compression of the one or more cache lines is dynamically controlled based on a number of hot cache lines.

8. A system for compressing data in a latency-critical processor link of a computing system in a computing environment, comprising: One or more computers having executable instructions that, when executed, cause the system to: One or more cache lines at a lowest level of a network stack including a framer and a data link layer are dynamically compressed based on one or more of a plurality of parameters prior to transmitting the single cache line.

9. The system of claim 8, wherein the executable instructions, when executed, cause the system to: enabling compression of the one or more cache lines based on data in the queue being above a defined threshold; or Compression of the one or more cache lines is disabled based on data in the queue being below a defined threshold.

10. The system of claim 8, wherein the executable instructions, when executed, cause the system to determine to compress the one or more cache lines based on the one or more parameters of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, quality of service ("QoS"), and a current packet type, wherein the current packet type is a data packet or a control packet.

11. The system of claim 10, wherein the executable instructions, when executed, cause the system to feed data from the framer to the data link layer to determine an amount of data to compress based on the one or more of the plurality of parameters.

12. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically switch the compression of the one or more cache lines using a Bloom filter on a set of previously transmitted cache line addresses.

13. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically compress the one or more cache lines to match a data input rate.

14. The system of claim 8, wherein the executable instructions, when executed, cause the system to dynamically control compression of the one or more cache lines based on a number of hot cache lines.

15. A computer program product for compressing data in a delay critical processor link of a computing system in a computing environment, the computer program product comprising: One or more computer-readable storage media, and program instructions stored together on the one or more computer-readable storage media, the program instructions comprising: Program instructions for dynamically compressing one or more cache lines at a lowest level of a network stack including a framer and a data link layer based on one or more of a plurality of parameters prior to transmitting the single cache line.

16. The computer program product of claim 15, further comprising program instructions for: enabling compression of the one or more cache lines based on data in the queue being above a defined threshold; or Compression of the one or more cache lines is disabled based on data in the queue being below a defined threshold.

17. The computer program product of claim 15, further comprising program instructions for determining: compressing the one or more cache lines based on one or more of the plurality of parameters, wherein the plurality of parameters include a number of pending data packets, quality of service ("QoS"), and a current packet type, wherein the current packet type is a data packet or a control packet; and Data is fed from the framer to the data link layer to determine an amount of data to be compressed based on one or more of the plurality of parameters.

18. The computer program product of claim 15, further comprising program instructions for dynamically switching the compression of the one or more cache lines using a Bloom filter on a set of previously transmitted cache line addresses.

19. The computer program product of claim 15, further comprising program instructions for dynamically compressing the one or more cache lines to match a data input rate.

20. The computer program product of claim 15, further comprising program instructions for dynamically controlling compression of the one or more cache lines based on a number of hot cache lines.

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