Array substrate and display device

Abstract

An array substrate includes a plurality of pixel driving circuits and a plurality of gate lines. Each pixel driving circuit includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Each gate line is configured to provide a gate scanning signal to the data writing transistor in a corresponding pixel driving circuit. A gate of the driving transistor is connected to the third capacitor electrode. The first node connection line connects a second electrode of the first reset transistor and the third capacitor electrode. A normal projection of the corresponding gate line on a substrate substrate substantially does not overlap a normal projection of the first node connection line on the substrate substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including a plurality of pixel driving circuits and a plurality of gate lines; wherein each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line; each of the plurality of gate lines is configured to provide a gate scan signal to the data writing transistor in the corresponding pixel driving circuit; the gate of the driving transistor is connected to the third capacitor electrode; the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode; and the orthographic projection of the corresponding gate line on the substrate substantially does not overlap with the orthographic projection of the first node connection line on the substrate.

[0004] Optionally, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the first node connection line on the substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

[0005] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor on the substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate, and does not substantially overlap with the orthographic projection of the first node connection line on the substrate.

[0006] Optionally, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the third capacitor electrode of the second capacitor on the substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

[0007] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor on the substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate, and also does not substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor on the substrate.

[0008] Optionally, the orthographic projection of the corresponding gate line on the substrate does not substantially overlap with the orthographic projection of the active layer of the first reset transistor and the second electrode on the substrate.

[0009] Optionally, the second electrode of the first reset transistor crosses the electrode of the second capacitor.

[0010] Optionally, the array substrate includes a plurality of second capacitor electrode lines extending in a direction substantially parallel to the second direction; wherein each of the plurality of second capacitor electrode lines includes second capacitor electrodes of pixel driving circuits connected together in the same row; wherein each pixel driving circuit further includes a light-emitting control transistor and a third reset transistor; wherein a connecting line in a corresponding second capacitor electrode line connecting two adjacent second capacitor electrodes of two adjacent pixel driving circuits in the same row spaces the second electrode of the light-emitting control transistor from the second electrode of the third reset transistor, and spaces the second electrode of the light-emitting control transistor from the first electrode of the driving transistor.

[0011] Optionally, each pixel driving circuit further includes a second node connection line, which is connected to the second electrode of the light-emitting control transistor through a third via, to the first electrode of the driving transistor through a fourth via, and to the second electrode of the third reset transistor through a fifth via; the second electrode of the light-emitting control transistor and the first electrode of the driving transistor are located in a first semiconductor material layer; the corresponding second capacitor electrode line is located in a first gate metal layer, which is located on the side of the first semiconductor material layer away from the substrate; the second electrode of the third reset transistor is located in a second semiconductor material layer, which is located on the side of the first gate metal layer away from the substrate; and the second node connection line is located in a first signal line layer, which is located on the side of the second semiconductor material layer away from the substrate.

[0012] Optionally, the second node connection line crosses the corresponding second capacitor electrode line.

[0013] Optionally, the array substrate further includes a plurality of voltage supply lines; wherein each pixel driving circuit further includes a light-emitting control transistor and a voltage supply connection line; a corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line through an eighth via; the voltage supply connection line is connected to the first electrode of two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row through a ninth via; the first electrode of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row is part of the overall structure; and the voltage supply connection lines are respectively connected to the second capacitor electrode of the first capacitor of the two adjacent pixel driving circuits in the same row through different vias.

[0014] Optionally, the voltage supply connection line includes a main line portion extending in a direction substantially parallel to the second direction; a first extension, a second extension, and a third extension extending away from the main line portion; the first extension, the second extension, and the third extension each extending in a direction substantially parallel to the first direction; a corresponding voltage supply line among the plurality of voltage supply lines connected to the first extension through the eighth via; the first extension connected to the first electrode of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row through the ninth via; the second extension connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit; and the third extension connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

[0015] Optionally, the voltage supply connection line has a substantially mirror symmetry with respect to a plane that is substantially parallel to the first direction and substantially perpendicular to the light-emitting surface of the array substrate.

[0016] Optionally, each pixel driving circuit further includes a compensation transistor; wherein the orthographic projection of the voltage supply connection line on the substrate at least partially surrounds the orthographic projection of two adjacent compensation transistors of two adjacent pixel driving circuits in the same row on the substrate; and the main line portion intersects the active layer of two adjacent data write transistors of two adjacent pixel driving circuits in the same row.

[0017] Optionally, each pixel driving circuit further includes a compensation transistor; wherein at least a portion of the orthographic projection of the second extension on the substrate spacers the orthographic projection of the at least active layer of the first reset transistor in the first adjacent pixel driving circuit on the substrate and the orthographic projection of the at least active layer of the compensation transistor in the first adjacent pixel driving circuit on the substrate; and at least a portion of the orthographic projection of the third extension on the substrate spacers the orthographic projection of the at least active layer of the first reset transistor in the second adjacent pixel driving circuit on the substrate and the orthographic projection of the at least active layer of the compensation transistor in the second adjacent pixel driving circuit on the substrate.

[0018] Optionally, the array substrate further includes a plurality of first reset signal lines and a plurality of data lines; wherein at least a portion of the orthographic projection of each of the plurality of first reset signal lines onto the substrate spaced apart from the orthographic projection of at least a portion of a first corresponding data line onto the substrate and the orthographic projection of at least a portion of a second corresponding data line onto the substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit.

[0019] Optionally, the array substrate further includes a plurality of first reset signal lines; wherein each of the plurality of first reset signal lines includes a plurality of loops arranged in a direction substantially parallel to a first direction; and each of the plurality of loops is connected to the first electrode of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

[0020] Optionally, the array substrate further includes an interconnect voltage supply network; wherein the interconnect voltage supply network includes a plurality of voltage supply lines, a plurality of second capacitor electrode lines, and a plurality of voltage supply connection lines; the plurality of voltage supply lines extend in a direction substantially parallel to a first direction; the plurality of second capacitor electrode lines extend in a direction substantially parallel to a second direction; each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in the same row; and each of the plurality of voltage supply connection lines connects a corresponding voltage supply line among the plurality of voltage supply lines to a corresponding second capacitor electrode line among the plurality of second capacitor electrode lines.

[0021] Optionally, each pixel driving circuit further includes a compensation transistor and a third node connection line; wherein the third node connection line is connected to the second electrode of the compensation transistor and the data writing transistor through a sixth via, and to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor through a seventh via; the orthographic projection of the third node connection line on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate; and the third node connection line extends in a direction substantially parallel to the extension direction of the active layer of the compensation transistor.

[0022] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of a display substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 4A The current path in a pixel driving circuit at stage t1 of an image frame is shown in some embodiments of the present disclosure.

[0029] Figure 4B The current path in a pixel driving circuit at stage t2 of an image frame is shown in some embodiments of the present disclosure.

[0030] Figure 4C The current path in a pixel driving circuit at stage t3 of an image frame is shown in some embodiments of the present disclosure.

[0031] Figure 4D The current path in the pixel driving circuit at stage t4 of the image frame is shown in some embodiments of the present disclosure.

[0032] Figure 4EThe current path in the pixel driving circuit at stage t5 of the image frame is shown in some embodiments of the present disclosure.

[0033] Figure 5A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0034] Figure 5B It is shown Figure 5A The diagram depicts the arrangement of pixel driving circuits in an array substrate.

[0035] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted.

[0036] Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0037] Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0038] Figure 5F It is shown Figure 5A A schematic diagram depicting a via extending through the first interlayer dielectric layer in an array substrate.

[0039] Figure 5G It is shown Figure 5A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted.

[0040] Figure 5H It is shown Figure 5A A schematic diagram depicting a via extending through a second interlayer dielectric layer in an array substrate.

[0041] Figure 5I It is shown Figure 5A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0042] Figure 5J It is shown Figure 5A A schematic diagram depicting a via extending through a passivation layer in an array substrate.

[0043] Figure 5K It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0044] Figure 5L It is shown Figure 5AA schematic diagram depicting a via extending through the first planarization layer in an array substrate.

[0045] Figure 5M It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0046] Figure 5N It is shown Figure 5A A schematic diagram depicting a via extending through the second planarization layer in an array substrate.

[0047] Figure 5O It is shown Figure 5A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0048] Figure 6A It is along Figure 5A A cross-sectional view of line A-A' in the diagram.

[0049] Figure 6B It is along Figure 5A A cross-sectional view of line B-B' in the diagram.

[0050] Figure 6C It is along Figure 5A A cross-sectional view of the C-C' line in the diagram.

[0051] Figure 6D It is along Figure 5A A cross-sectional view of the D-D' line in the diagram.

[0052] Figure 7A It is shown Figure 5A The diagram depicts the structure of the second semiconductor material layer and the first signal line layer in the array substrate.

[0053] Figure 7B This is a schematic diagram illustrating the structure of a reset signal line network according to some embodiments of the present disclosure.

[0054] Figure 7C This is a schematic diagram illustrating the structure of a voltage supply network according to some embodiments of the present disclosure.

[0055] Figure 7D This is a schematic diagram illustrating the structure of a second signal line layer in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure.

[0056] Figure 8A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0057] Figure 8B It is shown Figure 8AThe diagram depicts the arrangement of pixel driving circuits in an array substrate.

[0058] Figure 8C It is shown Figure 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted.

[0059] Figure 8D It is shown Figure 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted.

[0060] Figure 8E It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted.

[0061] Figure 8F It is shown Figure 8A A schematic diagram depicting a via extending through the first interlayer dielectric layer in an array substrate.

[0062] Figure 8G It is shown Figure 8A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted.

[0063] Figure 8H It is shown Figure 8A A schematic diagram depicting a via extending through a second interlayer dielectric layer in an array substrate.

[0064] Figure 8I It is shown Figure 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure.

[0065] Figure 8J It is shown Figure 8A A schematic diagram depicting a via extending through a passivation layer in an array substrate.

[0066] Figure 8K It is shown Figure 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0067] Figure 8L It is shown Figure 8A A schematic diagram depicting a via extending through the first planarization layer in an array substrate.

[0068] Figure 8M It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0069] Figure 8N It is shown Figure 8A A schematic diagram depicting a via extending through the second planarization layer in an array substrate.

[0070] Figure 8O It is shown Figure 8A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0071] Figure 9 It is shown Figure 5A or Figure 8A The diagram depicts the layout of the corresponding gate lines in the array substrate relative to the first node connection lines.

[0072] Figure 10 It is shown Figure 5A or Figure 8A A schematic diagram depicting the layout of the corresponding second capacitor electrode lines in the array substrate relative to the second node connection lines.

[0073] Figure 11 This is a schematic diagram illustrating the structure of a voltage supply connection line according to some embodiments of the present disclosure.

[0074] Figure 12 It is shown Figure 5A or Figure 8A The diagram depicts the layout of voltage supply connection lines in the array substrate relative to the second semiconductor material layer.

[0075] Figure 13 This is a schematic diagram illustrating the layout of multiple first reset signal lines relative to multiple data lines in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0076] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0077] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits and a plurality of gate lines. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Optionally, each of the plurality of gate lines is configured to provide a gate scan signal to the data writing transistor in the corresponding pixel driving circuit. Optionally, the gate of the driving transistor is connected to the third capacitor electrode. Optionally, the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode. Optionally, the orthographic projection of the corresponding gate line on the substrate substantially does not overlap with the orthographic projection of the first node connection line on the substrate.

[0078] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 7T2C driving circuit. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is an 8T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0079] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple voltage supply lines Vdd. Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via each of the multiple voltage supply lines Vdd; a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low-voltage supply line. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0080] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A In some embodiments, the pixel driving circuit includes: a driving transistor T3; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4; and a data writing transistor T4 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0081] In some embodiments, the pixel driving circuit further includes a compensation transistor T2 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a second electrode connected to a first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode of a data writing transistor T4.

[0082] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high-voltage signal line) among a plurality of voltage supply lines Vdd.

[0083] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate of the driving transistor T3.

[0084] In some embodiments, the pixel driving circuit further includes a light-emitting control transistor T5, which has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor T3 and the first electrode of the compensation transistor T2.

[0085] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1, which has a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the gate of the driving transistor T3 and a third capacitor electrode Ce3 of the second capacitor C2.

[0086] In some embodiments, the pixel driving circuit further includes a second reset transistor T7, which has a gate connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to a second electrode of the driving transistor T3 and the anode of the light-emitting element LE.

[0087] In some embodiments, the pixel driving circuit further includes a third reset transistor T6, which has a gate connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a third reset signal line Vint3, and a second electrode connected to a first electrode of the driving transistor T3, a second electrode of the light-emitting control transistor T5, and a second electrode of the compensation transistor T2.

[0088] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light-emitting control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1, and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the driving transistor T3, the second electrode of the second reset transistor T7, and the anode of the light-emitting element LE.

[0089] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0090] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2A The data writing transistor T4, compensation transistor T2, first reset transistor T1, and third reset transistor T6 are n-type transistors, such as metal-oxide-semiconductor transistors (MOSTs), while the driving transistor T3, light-emitting control transistor T5, and second reset transistor T7 are p-type transistors, such as polysilicon transistors (PSTs). For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0091] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2B The pixel driving circuit includes: a driving transistor T3; a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4; and a data writing transistor T4 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0092] In some embodiments, the pixel driving circuit further includes a compensation transistor T2 having a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a second electrode connected to a first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode of a data writing transistor T4.

[0093] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high-voltage signal line) among a plurality of voltage supply lines Vdd.

[0094] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate of the driving transistor T3.

[0095] In some embodiments, the pixel driving circuit further includes a light-emitting control transistor T5, which has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor T3 and the first electrode of the compensation transistor T2.

[0096] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1, which has a gate connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the gate of the driving transistor T3 and a third capacitor electrode Ce3 of the second capacitor C2.

[0097] In some embodiments, the pixel driving circuit further includes a control transistor T8 having a gate connected to a respective third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a second electrode of the driving transistor T3, and a second electrode connected to the anode of the light-emitting element LE.

[0098] The inventors of this disclosure discovered Figure 2A The invention describes a problem with leakage current through the driving transistor T3 in the pixel driving circuit. In one example, the reset signal provided by the corresponding third reset signal line Vint3 has a voltage level of 6V, and the reset signal provided by the corresponding first reset signal line Vint1 has a voltage level of -3V. The reset signal provided by the corresponding third reset signal line Vint3 can flow through the driving transistor T3 and the second reset transistor T7. The inventors of this disclosure have discovered that by configuring the control transistor T8, leakage current through the driving transistor T3 and the second reset transistor T7 can be prevented or avoided.

[0099] In some embodiments, the pixel driving circuit further includes a second reset transistor T7, which has a gate connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to a second electrode of a control transistor T8 and the anode of the light-emitting element LE.

[0100] In some embodiments, the pixel driving circuit further includes a third reset transistor T6, which has a gate connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a third reset signal line Vint3, and a second electrode connected to a first electrode of the driving transistor T3, a second electrode of the light-emitting control transistor T5, and a second electrode of the compensation transistor T2.

[0101] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light-emitting control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1, and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the control transistor T8, the second electrode of the second reset transistor T7, and the anode of the light-emitting element LE.

[0102] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2B The data writing transistor T4, compensation transistor T2, first reset transistor T1, and third reset transistor T6 are n-type transistors, such as metal-oxide-semiconductor transistors (MOSTs), while the driving transistor T3, light-emitting control transistor T5, second reset transistor T7, and control transistor T8 are p-type transistors, such as polysilicon transistors (PSTs). For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0103] Figure 3 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A , Figure 2B as well as Figure 3 During one frame of an image, the operation of the pixel driving circuit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5.

[0104] In the first stage t1, a turn-on control signal is provided to the gate of the first reset transistor T1 via a corresponding first control signal line among the plurality of first control signal lines SL1, turning on the first reset transistor T1. This allows the reset signal from the first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor T1 to the second electrode of the first reset transistor T1, and then to the third capacitor electrode Ce3 and the gate of the driving transistor T3. Node N1 (the gate of the driving transistor T3) is reset. The turn-on control signal is also provided to the gate of the compensation transistor T2 via a corresponding first control signal line among the plurality of first control signal lines SL1, turning on the compensation transistor T2. The turn-on control signal is provided to the gate of the second reset transistor T7 via a corresponding second control signal line among the plurality of second control signal lines SL2, turning on the second reset transistor T7. This allows the reset signal from the corresponding first reset signal line among the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the second reset transistor T7 to the second electrode of the second reset transistor T7, and then to the anode of the light-emitting element LE. Node N4 (the anode of the light-emitting element LE) is reset. The cutoff control signal is provided to the gate of the light-emitting control transistor T5 through each of the multiple light-emitting control signal lines em, thereby turning off the light-emitting control transistor T5. The cutoff control signal is provided to the gate of the third reset transistor T6 through the corresponding third control signal line SL3, thereby turning off the third reset transistor T6. The cutoff gate signal is provided to the gate of the data writing transistor T4 through the corresponding gate line GL, thereby turning off the data writing transistor T4. Figure 4A The current path in a pixel driving circuit at stage t1 of an image frame is shown in some embodiments of the present disclosure. Figure 4A The shaded arrow in the diagram represents the current at stage t1.

[0105] In the second stage t2, a turn-on control signal is provided to the gate of the first reset transistor T1 via a corresponding first control signal line among the plurality of first control signal lines SL1, to turn on the first reset transistor T1. It is also provided to the gate of the compensation transistor T2 via a corresponding first control signal line among the plurality of first control signal lines SL1, to turn on the compensation transistor T2. A turn-on control signal is provided to the gate of the second reset transistor T7 via a corresponding second control signal line among the plurality of second control signal lines SL2, to turn on the second reset transistor T7. A turn-on control signal is provided to the gate of the third reset transistor T6 via a corresponding third control signal line among the plurality of third control signal lines SL3, to turn on the third reset transistor T6. This allows the reset signal from the corresponding third reset signal line among the plurality of third reset signal lines Vint3 to be transmitted from the first electrode of the third reset transistor T6 to the second electrode of the third reset transistor T6, and further to the first electrode of the driving transistor T3, the second electrode of the light-emitting control transistor T5, and the second electrode of the compensation transistor T2. Node N2 (the first electrode of the driving transistor T3) is charged with the voltage of the corresponding third reset signal line among the plurality of third reset signal lines Vint3. In some embodiments, the voltage of the respective third reset signal line in the plurality of third reset signal lines Vint3 has a high voltage level (e.g., 6V) to ensure that Vgs < Vth, thereby ensuring that the drive transistor T3 remains in the on state. Figure 4B The current path in a pixel driving circuit at stage t2 of an image frame is shown in some embodiments of the present disclosure. Figure 4B The shaded arrow in the diagram represents the current at stage t2.

[0106] In the third stage t3 (Vth compensation stage), a cutoff control signal is provided to the gate of the third reset transistor T6 through the corresponding third control signal line among the multiple third control signal lines SL3, causing the third reset transistor T6 to be turned off. In the third stage t3, the first reset transistor T1, compensation transistor T2, drive transistor T3, second reset transistor T7, and control transistor T8 remain on. A first reset signal is provided through the corresponding first reset signal line among the multiple first reset signal lines Vint1. The first reset signal passes through the second reset transistor T7 and drive transistor T3, charging node N2 (the first electrode of drive transistor T3). When node N2 is charged to Vgs = Vth, drive transistor T3 is turned off. Vgs = VN1 - VN2, where VN1 is the voltage level of node N1, and VN2 is the voltage level of node N2. In the third stage t3, VN1 = the voltage level of the first reset signal provided by the first reset signal line Vint1. Therefore, VN2 = VN1 - Vgs = VN1 - Vth, which means VN2 = Vint1 - Vth. Since the compensation transistor T2 is turned on in the third stage t3, VN3 = VN2 = VN1 - Vth, where VN3 is the voltage level of node N3. Figure 4C The current path in the pixel driving circuit at stage t3 of the image frame is shown in some embodiments of the present disclosure. Figure 4C The shaded arrow in the figure represents the current at stage t3.

[0107] In stage t4 (data write stage), a cutoff control signal is provided to the gate of the first reset transistor T1 via a corresponding first control signal line among the multiple first control signal lines SL1, causing the first reset transistor T1 to turn off. It is also provided to the gate of the compensation transistor T2 via a corresponding first control signal line among the multiple first control signal lines SL1, causing the compensation transistor T2 to turn off. A cutoff control signal is provided to the gate of the second reset transistor T7 via a corresponding second control signal line among the multiple second control signal lines SL2, causing the second reset transistor T7 to turn off. A turn-on gate signal is provided to the gate of the data write transistor T4 via a corresponding gate line among the multiple gate lines GL, causing the data write transistor T4 to turn on, thereby allowing the data signal provided via the data line DL to be transmitted from the first electrode of the data write transistor T4 to the second electrode of the data write transistor T4, and then to node N3. In stage t3, VN1 = the voltage level of the first reset signal provided by the first reset signal line Vint1 (denoted as Vre1). In stage t4, the voltage level of node N3 changes from (Vre1 - Vth) to the voltage level of the data signal Vdata. The change is ΔVN3 = Vdata - Vre1 + Vth. The second capacitor C2 induces voltage coupling at node N1 through ΔVN3. Due to voltage coupling, VN1 changes to (Vre1 + ΔVN3) = (Vre1 + Vdata - Vre1 + Vth) = (Vdata + Vth), where Vdata is the voltage level of the data voltage signal, and Vth is the voltage level of the threshold voltage Th of the PN junction driving transistor T3. Figure 4D The current path in the pixel driving circuit at stage t4 of the image frame is shown in some embodiments of the present disclosure. Figure 4D The shaded arrow in the figure represents the current at stage t4.

[0108] In stage t5 (light emission stage), a light emission control signal is provided to the gate of the light emission control transistor T5 through a corresponding light emission control signal line among multiple light emission control signal lines em, causing the light emission control transistor T5 to conduct. This allows the voltage supply signal provided through a corresponding voltage supply line among multiple voltage supply lines Vdd to be transmitted from the first electrode of the light emission control transistor T5 to the second electrode of the light emission control transistor T5, then from the first electrode of the driving transistor T3 to the second electrode of the driving transistor T3, then from the first electrode of the control transistor T8 to the second electrode of the control transistor T8, and finally to the anode of the light-emitting element LE. The light-emitting element is configured to emit light. Figure 4E The current path in the pixel driving circuit at stage t5 of the image frame is shown in some embodiments of the present disclosure. Figure 4E The shaded arrow in the diagram represents the current at stage t5.

[0109] Figure 5A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 5B It is shown Figure 5A The diagram depicts the arrangement of pixel driving circuits in an array substrate. Figure 5A and Figure 5B A portion of the array substrate with two adjacent pixel driving circuits (including PDC1 and PDC2) is depicted.

[0110] Figure 5C It is shown Figure 5A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted. Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted. Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 5F It is shown Figure 5A A schematic diagram depicting a via extending through the first interlayer dielectric layer in an array substrate. Figure 5G It is shown Figure 5A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted. Figure 5H It is shown Figure 5A A schematic diagram depicting a via extending through a second interlayer dielectric layer in an array substrate. Figure 5I It is shown Figure 5A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 5J It is shown Figure 5A A schematic diagram depicting a via extending through a passivation layer in an array substrate. Figure 5K It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 5L It is shown Figure 5A A schematic diagram depicting a via extending through the first planarization layer in an array substrate. Figure 5M It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 5N It is shown Figure 5A A schematic diagram depicting a via extending through the second planarization layer in an array substrate. Figure 5O It is shown Figure 5A A schematic diagram of the structure of the anode layer in the array substrate is depicted. Figure 6A It is along Figure 5A A cross-sectional view of line A-A' in the diagram. Figure 6B It is along Figure 5A A cross-sectional view of line B-B' in the diagram. Figure 6C It is along Figure 5A A cross-sectional view of the C-C' line in the diagram. Figure 6D It is along Figure 5A A cross-sectional view of the D-D' line in the diagram.

[0111] Reference Figures 5A to 5O as well as Figures 6A to 6D In some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; and a second interlayer dielectric layer... The system comprises: an ILD2 layer located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; a third gate metal layer Gate3 located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; a passivation layer PVX located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; a first signal line layer SD1 located on the side of the passivation layer PVX away from the third gate metal layer Gate3; a first planarization layer PLN1 located on the side of the first signal line layer SD1 away from the passivation layer PVX; a second planarization layer SD2 located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; a second planarization layer PLN2 located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; and an anode layer ADL located on the side of the second planarization layer PLN2 away from the second signal line layer SD2.

[0112] Reference Figure 2B , Figure 5A , Figure 5C , Figures 6A to 6DIn some embodiments, the first semiconductor material layer SML1 includes at least an active layer of a plurality of transistors (including driving transistor T3, light-emitting control transistor T5, second reset transistor T7, and control transistor T8) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least a corresponding portion of the first electrode of the plurality of transistors (including driving transistor T3, light-emitting control transistor T5, second reset transistor T7, and control transistor T8) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least a corresponding portion of the second electrode of the plurality of transistors (including driving transistor T3, light-emitting control transistor T5, second reset transistor T7, and control transistor T8) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode of the plurality of transistors (including driving transistor T3, light-emitting control transistor T5, second reset transistor T7, and control transistor T8) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0113] exist Figure 5C In the middle, the corresponding numbers are marked. Figure 5B The pixel driving circuit of PDC2 is denoted by reference numerals, which denote components of each of the multiple transistors (T3, T5, T7, and T8) in the pixel driving circuit. For example, driving transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. Light-emitting control transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. Second reset transistor T7 includes an active layer ACT7, a first electrode S7, and a second electrode D7. Control transistor T8 includes an active layer ACT8, a first electrode S8, and a second electrode D8.

[0114] Optionally, the active layers (ACT3, ACT5, ACT7, and ACT8), the first electrodes (S3, S5, S7, and S8), and the second electrodes (D3, D5, D7, and D8) of each transistor (T3, T5, T7, and T8) are located on the same layer.

[0115] In some embodiments, at least a portion of the active layers (ACT3, ACT7, and ACT8), at least a portion of the first electrodes (S3, S7, and S8), and at least a portion of the second electrodes (D3, D7, and D8) of the plurality of transistors (T3, T7, and T8) in the pixel driving circuit are part of the overall structure. Optionally, in the same pixel driving circuit, the portion of the light-emitting control transistor T5 located in the first semiconductor material layer (ACT5, S5, and D5) is spaced apart from the overall structure (T3, T7, and T8).

[0116] In some embodiments, at least a portion of the active layer and the first electrode of two adjacent light-emitting control transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row) are part of an integral structure. Optionally, at least a portion of the active layer, the first electrode, and the second electrode of two adjacent light-emitting control transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row) are part of an integral structure. Optionally, the first electrodes of two adjacent light-emitting control transistors in two adjacent pixel driving circuits in the same row are directly connected to each other.

[0117] Reference Figure 2B , Figure 5A , Figure 5D and Figures 6A to 6D In some embodiments, the first gate metal layer Gate1 includes a plurality of light emission control signal lines em, a plurality of second control signal lines SL2, at least a portion of a plurality of third control signal lines (e.g., a first branch SL3-1 of a corresponding third control signal line), a second capacitor electrode Ce2 of the first capacitor C1, and a third capacitor electrode Ce3 of the second capacitor C2 in the pixel driving circuit.

[0118] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned by plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least a portion of the plurality of light-emitting control signal lines em, the plurality of second control signal lines SL2, the plurality of third control signal lines (e.g., the first branch SL3-1 of the corresponding third control signal lines), the second capacitor electrode Ce2 of the first capacitor C1, and the third capacitor electrode Ce3 of the second capacitor C2 are located in the same layer.

[0119] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple light-emitting control signal lines em and a second capacitor electrode Ce2 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple light-emitting control signal lines em and a second capacitor electrode Ce2 can be formed in the same layer by simultaneously performing the steps of forming multiple light-emitting control signal lines em and forming the second capacitor electrode Ce2. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0120] Reference Figure 5D In this invention, multiple second capacitor electrodes in multiple pixel driving circuits are interconnected and are part of an integral structure. By interconnecting the second capacitor electrodes, since the second capacitor electrodes are electrically connected to multiple voltage supply lines Vdd, the resistance of the multiple voltage supply lines Vdd can be reduced. The inventors of this disclosure have found that this structure improves the display uniformity of the array substrate.

[0121] Reference Figure 2B , Figure 5A , Figure 5E and Figures 6A to 6D In some embodiments, the second gate metal layer Gate2 includes at least portions of a plurality of gate lines in the pixel driving circuit (e.g., corresponding first branches of gate lines GL-1), at least portions of a plurality of first control signal lines (e.g., corresponding first branches of first control signal lines SL1-1), at least portions of a plurality of third control signal lines (e.g., corresponding second branches of third control signal lines SL3-2), a first capacitor electrode Ce1 of the first capacitor C1, and a fourth capacitor electrode Ce4 of the second capacitor C2. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second gate metal layer Gate2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least portions of a plurality of gate lines in the pixel driving circuit (e.g., the first branch GL-1 of the corresponding gate line), at least portions of a plurality of first control signal lines (e.g., the first branch SL1-1 of the corresponding first control signal line), at least portions of a plurality of third control signal lines (e.g., the second branch SL3-2 of the corresponding third control signal line), the first capacitor electrode Ce1 of the first capacitor C1, and the fourth capacitor electrode Ce4 of the second capacitor C2 are located on the same layer.

[0122] Optionally, the first capacitor electrode Ce1 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2 in the pixel driving circuit are part of the overall structure.

[0123] Figure 5F The image depicts a via extending through the first interlayer dielectric layer ILD1.

[0124] Reference Figure 2B , Figure 5A , Figure 5G as well as Figures 6A to 6DIn some embodiments, the second semiconductor material layer SML2 includes at least the active layer ACT1 of the first reset transistor T1, the active layer ACT2 of the compensation transistor T2, the active layer ACT4 of the data writing transistor T4, and the active layer ACT6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S1 of the first reset transistor T1, at least a portion of the first electrode S2 of the compensation transistor T2, at least a portion of the first electrode S4 of the data writing transistor T4, and at least a portion of the first electrode S6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D1 of the first reset transistor T1, at least a portion of the second electrode D2 of the compensation transistor T2, at least a portion of the second electrode D4 of the data writing transistor T4, and at least a portion of the second electrode D6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes: an active layer ACT1, a first electrode S1, and a second electrode D1 of the first reset transistor T1 in the pixel driving circuit; an active layer ACT2, a first electrode S2, and a second electrode D2 of the compensation transistor T2; an active layer ACT4, a first electrode S4, and a second electrode D4 of the data write transistor T4; and an active layer ACT6, a first electrode S6, and a second electrode D6 of the third reset transistor T6. In this array substrate, at least the active layer ACT1 of the first reset transistor T1, the active layer ACT2 of the compensation transistor T2, the active layer ACT4 of the data write transistor T4, and the active layer ACT6 of the third reset transistor T6 are located in layers different from at least the active layers of the other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0125] exist Figure 5G In the middle, the corresponding numbers are marked. Figure 5B The pixel driving circuit of PDC2 is denoted by reference numerals, which denote components of each of the multiple transistors (T1, T2, T4, and T6) in the pixel driving circuit. For example, the first reset transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The compensation transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The data write transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The third reset transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6.

[0126] In some embodiments, at least a portion of the active layers (ACT2, ACT4, and ACT6), at least a portion of the first electrodes (S2, S4, and S6), and at least a portion of the second electrodes (D2, D4, and D6) of the plurality of transistors (T2, T4, and T6) in the pixel driving circuit are part of the overall structure. Optionally, in the same pixel driving circuit, at least a portion (ACT1, S1, and D1) of the first reset transistor T1 located in the second semiconductor material layer is spaced apart from the overall structure (T2, T4, and T6).

[0127] In some embodiments, at least a portion of the active layer and the first electrode of two adjacent third reset transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row) are part of the overall structure. Optionally, at least a portion of the active layer, the first electrode, and the second electrode of two adjacent third reset transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row) are part of the overall structure. Optionally, in the overall structure, the first electrodes of two adjacent third reset transistors in two adjacent pixel driving circuits in the same row are directly connected to each other.

[0128] In some embodiments, the active layers, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent third reset transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row); the active layers, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent compensation transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row); and the active layers, at least a portion of the first electrode, and at least a portion of the second electrode of two adjacent data write transistors in two adjacent pixel driving circuits (e.g., two adjacent pixel driving circuits in the same row) are part of an overall structure. Optionally, in the overall structure, the first electrodes of two adjacent third reset transistors in two adjacent pixel driving circuits in the same row are directly connected to each other.

[0129] Figure 5H The image depicts a via extending through the second interlayer dielectric layer ILD2.

[0130] Reference Figure 2B , Figure 5A , Figure 5I , Figures 6A to 6DIn some embodiments, the third gate metal layer Gate3 includes at least portions of a plurality of gate lines (e.g., corresponding second branches of gate lines GL-2), at least portions of a plurality of first control signal lines (e.g., corresponding second branches of first control signals SL1-2), at least portions of a plurality of third control signal lines (e.g., corresponding third branches of third control signals SL3-3), a plurality of second reset signal lines Vint2, and a plurality of third reset signal lines Vint3. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third gate metal layer Gate3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0131] Figure 5J The image depicts vias extending through the passivation layer PVX.

[0132] Reference Figure 2B , Figure 5A , Figure 5K , Figures 6A to 6D In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines Vint1; a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a data connection line Cld, a voltage supply connection line Clv, a reset signal connection line Cli, and a relay electrode RE.

[0133] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple first reset signal lines Vint1, first node connection lines Cln1, second node connection lines Cln2, third node connection lines Cln3, data connection lines Cld, voltage supply connection lines Clv, reset signal connection lines Cli, and relay electrodes RE are located in the same layer.

[0134] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (Refer to...) Figure 6AIn the pixel driving circuit, the first node connection line Cln1 is connected to the third capacitor electrode Ce3 of the second capacitor C2 through the first via v1, and to the first reset transistor T1 (e.g., connected to the second electrode D1 of the first reset transistor T1) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2B The node N1 is depicted in the diagram. In one example, a first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, a second via v2 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0135] In some embodiments, the second node connection line Cln2 connects multiple components of the pixel driving circuit to node N2. (Refer to...) Figure 6B In the pixel driving circuit, the second node connection line Cln2 is connected to the second electrode D5 of the light-emitting control transistor T5 through the third via v3, to the first electrode S3 of the driving transistor T3 through the fourth via v4, and to the second electrode D6 of the third reset transistor T6 through the fifth via v5. Optionally, the second node connection line Cln2 corresponds to... Figure 2B The node N2 is depicted in the diagram. In one example, a third via v3 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, a fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In yet another example, a fifth via v5 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0136] In some embodiments, the third node connection line Cln3 connects multiple components of the pixel driving circuit to node N3. (Refer to...) Figure 6C In the pixel driving circuit, the third node connection line Cln3 is connected to the second electrode of the compensation transistor T2 and the data write transistor T4 through the sixth via v6, and is connected to the first capacitor electrode Ce1 of the first capacitor C1 and / or the fourth capacitor electrode Ce4 of the second capacitor C2 through the seventh via v7. Optionally, the third node connection line Cln3 corresponds to Figure 2B The node N3 is depicted in the diagram. In one example, the sixth via v6 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2. In another example, the seventh via v7 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1.

[0137] In some embodiments, voltage supply connection line Clv connects multiple components of the pixel driving circuit to corresponding voltage supply lines in multiple voltage supply connection lines Vdd. (See also...) Figure 6D In the pixel driving circuit, a corresponding voltage supply line among multiple voltage supply lines Vdd is connected to a voltage supply connection line Clv via an eighth via v8. The voltage supply connection line Clv is connected to the second electrode S5 of the light-emitting control transistor T5 via a ninth via v9, and to the second capacitor electrode Ce2 of the first capacitor C1 via a tenth via v10. In one example, the eighth via v8 extends through the first planarization layer PLN1. In another example, the ninth via v9 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In yet another example, the tenth via v10 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0138] In some embodiments, refer to Figure 6A The corresponding first reset signal line in the plurality of first reset signal lines Vint1 is connected to the first electrode S1 of the first reset transistor T1 through the eleventh via v11. In one example, the eleventh via v11 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0139] Figure 7A It is shown Figure 5A This is a schematic diagram depicting the structure of the second semiconductor material layer and the first signal line layer in an array substrate. In some embodiments, reference is made to… Figure 7A The orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps (e.g., at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) with the orthographic projection of the active layer ACT2 of the compensation transistor T2 on the substrate BS. Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the extension direction of the active layer ACT2 of the compensation transistor T2. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the first electrode S2 of the compensation transistor T2 on the substrate. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the second electrode D2 of the compensation transistor T2 on the substrate BS.

[0140] Reference Figure 5K and Figure 6D In some embodiments, the voltage supply connection line Clv connects multiple components of two adjacent pixel driving circuits in the same row to corresponding voltage supply lines in a plurality of voltage supply lines Vdd. In some embodiments, corresponding voltage supply lines in the plurality of voltage supply lines Vdd are connected to the voltage supply connection line Clv, for example, through an eighth via v8. The voltage supply connection line Clv is connected to the first electrodes of two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row through a ninth via v9. The first electrodes of the two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row are part of an integral structure. The voltage supply connection line Clv is connected to the second capacitor electrodes of the first capacitors of the two adjacent pixel driving circuits in the same row, respectively, through different vias.

[0141] Figure 7B This is a schematic diagram illustrating the structure of a reset signal line network according to some embodiments of the present disclosure. (Refer to...) Figure 7B In some embodiments, the array substrate includes an interconnect reset signal line network. In some embodiments, the interconnect reset signal line network includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2 interconnected together. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to a second direction DR2. Optionally, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are located on different layers. In one example, the plurality of first reset signal lines Vint1 are located on a first signal line layer, and the plurality of second reset signal lines Vint2 are located on a third gate metal layer. In some embodiments, each first reset signal line in the plurality of first reset signal lines Vint1 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2. In some embodiments, each second reset signal line in the plurality of second reset signal lines Vint2 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1, thereby forming an interconnect reset signal line network.

[0142] Reference Figure 7B In some embodiments, each of the plurality of first reset signal lines Vint1 includes a plurality of loops LP arranged in a direction substantially parallel to the first direction DR1. Each loop in the plurality of loops LP is connected to the first electrode of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

[0143] Reference Figure 5A , Figure 5G , Figure 5I and Figure 5KIn some embodiments, the reset signal connection line Cli in the first signal line layer is connected to a corresponding third reset signal line among the plurality of third reset signal lines Vint3 in the third gate metal layer, and is also connected to the first electrode S6 of the third reset transistor T6 in the second semiconductor material layer. Optionally, the reset signal connection line Cli is connected to the first electrodes of two adjacent third reset transistors in two adjacent pixel driving circuits in the same row.

[0144] Figure 5L The image depicts vias extending through the first planarization layer PLN1.

[0145] Reference Figure 2B , Figure 5A , Figure 5M and Figures 6A to 6D In some embodiments, the second signal line layer SD2 includes multiple voltage supply lines Vdd, multiple data lines DL, and an anode connection pad ACP. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the second signal line layer includes multiple sublayers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the multiple voltage supply lines Vdd, multiple data lines DL, and an anode connection pad ACP are located in the same layer.

[0146] Reference Figure 5A , Figure 5G , Figure 5K and Figure 5M In some embodiments, each of the multiple data lines DL in the second signal line layer is connected to the data connection line Cld in the first signal line layer, and the data connection line Cld is connected to the first electrode S4 of the data writing transistor T4 located in the second semiconductor material layer.

[0147] In some embodiments, each data line in a plurality of data lines DL includes a plurality of branches BL arranged in a direction substantially parallel to a first direction DR1. Each branch of the plurality of branches BL extends away from the body MB of the corresponding data line. In some embodiments, each branch of the plurality of branches BL is connected to a data connection line Cld in a first signal line layer. In some embodiments, the body MB of the corresponding data line extends in a direction substantially parallel to the first direction DR1, and each branch extends in a direction substantially parallel to a second direction DR2. The second direction DR2 is different from the first direction DR1. The second direction DR2 intersects the first direction DR1.

[0148] Reference Figure 5A , Figure 5C , Figure 5K as well as Figure 5M In some embodiments, the anode connection pad ACP in the second signal line layer is connected to the relay electrode RE in the first signal line layer, and the relay electrode RE is connected to the second electrode of the second reset transistor T7 and the control transistor T8. The anode connection pad ACP is connected to a corresponding anode among a plurality of anodes.

[0149] Figure 5N The image depicts vias extending through the second planarization layer PLN2.

[0150] Reference Figure 5A , Figure 5O as well as Figures 6A to 6D In some embodiments, the anode layer ADL includes multiple anodes AD.

[0151] Figure 7C This is a schematic diagram illustrating the structure of a voltage supply network according to some embodiments of the present disclosure. (Refer to...) Figure 7CIn some embodiments, the array substrate includes an interconnect voltage supply network. In some embodiments, the interconnect voltage supply network includes a plurality of voltage supply lines Vdd, a plurality of second capacitor electrode lines Ce2L, and a plurality of voltage supply connection lines Clvs. Optionally, the plurality of voltage supply lines Vdd extends in a direction substantially parallel to a first direction DR1. Optionally, the plurality of second capacitor electrode lines Ce2L extends in a direction substantially parallel to a second direction DR2. Each second capacitor electrode line in the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode of a pixel driving circuit in the same row. Each voltage supply connection line in the plurality of voltage supply connection lines Clvs connects a corresponding voltage supply line in the plurality of voltage supply lines Vdd to a corresponding second capacitor electrode line in the plurality of second capacitor electrode lines Ce2L. Optionally, the plurality of voltage supply lines Vdd, the plurality of second capacitor electrode lines Ce2L, and the plurality of voltage supply connection lines Clvs are located on different layers. In one example, the plurality of second capacitor electrode lines Ce2L are located on a first gate metal layer, the plurality of voltage supply connection lines Clvs are located on a first signal line layer, and the plurality of voltage supply lines Vdd are located on a second signal line layer. In some embodiments, each of the plurality of voltage supply lines Vdd is connected to one or more of the plurality of second capacitor electrode lines Ce2L via one or more of the plurality of voltage supply connection lines Clvs. In some embodiments, each of the plurality of second capacitor electrode lines Ce2L is connected to one or more of the plurality of voltage supply lines Vdd via one or more of the plurality of voltage supply connection lines Clvs.

[0152] Reference Figure 5A In some embodiments, the array substrate includes a transmissive region TR in which no conductive components of the pixel driving circuitry exist. (Refer to...) Figure 7B Each of the multiple loops in the first reset signal line surrounds the transmission region TR. An accessory may be mounted in the transmission region TR. Examples of accessories include a photoelectric sensor.

[0153] Reference Figure 5M Each data line in the multiple data lines DL includes a main MB and multiple branches BL extending away from the main MB. The main MB includes multiple first segments SG1 and multiple second segments SG2 alternately connected together. Figure 7D This is a schematic diagram illustrating the structure of the second signal line layer in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 5M and Figure 7DIn some embodiments, the second segment of two adjacent data lines configured to provide data signals to two adjacent pixel driving circuits in the same row substantially surrounds the transmission region TR. In some embodiments, the first segment SG1 is substantially straight, and the second segment SG2 is a curved segment that bends around the transmission region TR. In some embodiments, a virtual extension of the first segment SG1 passes through the transmission region TR.

[0154] Figure 8A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 8B It is shown Figure 8A The diagram depicts the arrangement of pixel driving circuits in the array substrate. Figure 8C It is shown Figure 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is depicted. Figure 8D It is shown Figure 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is depicted. Figure 8E It is shown Figure 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is depicted. Figure 8F It is shown Figure 8A A schematic diagram depicting a via extending through the first interlayer dielectric layer in an array substrate. Figure 8G It is shown Figure 8A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is depicted. Figure 8H It is shown Figure 8A A schematic diagram depicting a via extending through a second interlayer dielectric layer in an array substrate. Figure 8I It is shown Figure 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in the figure. Figure 8J It is shown Figure 8A A schematic diagram depicting a via extending through a passivation layer in an array substrate. Figure 8K It is shown Figure 8A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 8L It is shown Figure 8A A schematic diagram depicting a via extending through the first planarization layer in an array substrate. Figure 8M It is shown Figure 8A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 8N It is shown Figure 8A A schematic diagram depicting a via extending through the second planarization layer in an array substrate. Figure 8O It is shown Figure 8A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0155] Figures 8A to 8O The array substrate and depicted in Figures 5A to 5O The difference between the array substrates depicted in the text is: Figures 8A to 8O The main bodies (MB) of each data line in the array substrate depicted extend substantially straight along a direction substantially parallel to the first direction DR1. Optionally, Figures 8A to 8O The array substrate depicted does not include the transmission region TR.

[0156] The inventors of this disclosure have discovered that resistance-capacitance delay occurs in the associated array substrate due to the presence of resistance and parasitic capacitance in the signal lines. This resistance-capacitance delay is particularly significant when the signal transmission distance of the signal lines becomes long. The inventors of this disclosure have discovered that control signals (e.g., gate scan signals) output from the scan circuit to sub-pixel rows farther from the integrated circuit have a longer delay compared to control signals output to sub-pixel rows closer to the integrated circuit. The inventors of this disclosure have discovered that this is at least in part due to the resistance-capacitance delay in the signal lines that transmit signals (e.g., clock signals) from the integrated circuit to the multi-stage scan circuitry.

[0157] The inventors of this disclosure have discovered that, in a related array substrate, the falling edge duration of a signal varies with the signal transmission distance of the signal line. This variation in falling edge duration becomes particularly significant when the signal transmission distance of the signal line becomes longer. The inventors of this disclosure have also discovered that the gate scan signal output from the scan circuit to the sub-pixel farther from the scan circuit has a longer falling edge duration compared to the control signal output to the sub-pixel closer to the scan circuit. When the scan circuit outputs a cutoff gate scan signal, due to the variation in falling edge duration, the voltage of node N1 in the pixel driving circuit farther from the scan circuit is pulled down to a smaller extent compared to the voltage of node N1 in the pixel driving circuit closer to the scan circuit, resulting in poorer display uniformity between sub-pixels farther from and closer to the scan circuit.

[0158] The inventors of this disclosure have surprisingly and unexpectedly found that the array substrate according to this disclosure alleviates the problem of display non-uniformity. The inventors of this disclosure have found that reducing the parasitic capacitance between the corresponding gate lines and the N1 node successfully eliminates the problem of display non-uniformity. Figure 9 It is shown Figure 5A or Figure 8A The diagram depicts the layout of corresponding gate lines in the array substrate relative to the first node connection lines. (Refer to...) Figure 9 The inventors of this disclosure have discovered that reducing the parasitic capacitance between the corresponding gate line in the plurality of gate lines GL and the first node connection line Cln1 can successfully improve the problem of display non-uniformity.

[0159] Reference Figure 9In some embodiments, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the first node connection line Cln1 on the substrate are substantially non-overlapping (e.g., at least 80%, at least 90%, at least 95%, at least 99%, or completely non-overlapping). This can minimize the parasitic capacitance between the corresponding gate line in the plurality of gate lines GL and the first node connection line Cln1. The first node connection line Cln1 at least partially corresponds to node N1.

[0160] In some embodiments, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the first node connection line Cln1 on the substrate are separated by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate is substantially non-overlapping with the orthographic projection of the corresponding gate line on the substrate (e.g., at least 80%, at least 90%, at least 95%, at least 99%, or completely non-overlapping), and substantially non-overlapping with the orthographic projection of the first node connection line Cln1 on the substrate (e.g., at least 80%, at least 90%, at least 95%, at least 99%, or completely non-overlapping). By separating the orthographic projection of the corresponding gate line on the substrate from the orthographic projection of the first node connection line Cln1 on the substrate by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1, the parasitic capacitance (e.g., lateral parasitic capacitance) between the corresponding gate line and the node N1 in the plurality of gate lines GL can be further minimized.

[0161] In some embodiments, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 on the substrate are separated by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate is substantially non-overlapping with the orthographic projection of the corresponding gate line on the substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping), and substantially non-overlapping with the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 on the substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping).

[0162] Comparing the array substrate according to this disclosure with related array substrates, the parasitic capacitance between the corresponding gate line and node N1 is 1.33f in the array substrate according to this disclosure and 2.72f in the related array substrate. In the related array substrate, the orthographic projection of the third capacitor electrode Ce3 onto the substrate separates the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the substrate from the orthographic projection of the corresponding gate line onto the substrate (making node N1 closer to the corresponding gate line). The voltage difference between the first nodes in the pixel driving circuit located further away from the scanning circuit and the pixel driving circuit located closer to the scanning circuit is 0.08V in the array substrate according to this disclosure, while it is 0.16V in the related array substrate. In the array substrate according to this disclosure, display non-uniformity is significantly improved.

[0163] In some embodiments, the first node connection line Cln1 is connected to the second electrode D1 of the first reset transistor T1 through the second via v2. Because the first reset transistor T1 is connected to the first node connection line Cln1, the inventors of this disclosure have found that minimizing the parasitic capacitance between the first reset transistor T1 and the corresponding gate line further improves the problem of display non-uniformity.

[0164] In some embodiments, the orthographic projection of the corresponding gate line on the substrate is substantially non-overlapping with the orthographic projection of the second electrode D1 of the first reset transistor T1 on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projection of the corresponding gate line on the substrate is substantially non-overlapping with the orthographic projection of the active layer ACT1 and the second electrode D1 of the first reset transistor T1 on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projection of the corresponding gate line on the substrate is substantially non-overlapping with the orthographic projections of the first electrode S1, the active layer ACT1, and the second electrode D1 of the first reset transistor T1 on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap).

[0165] In some embodiments, the second electrode D1 of the first reset transistor T1 intersects with the second capacitor electrode Ce2. Optionally, the orthographic projection of the second electrode D1 of the first reset transistor T1 onto the substrate partially overlaps with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the substrate.

[0166] In some embodiments, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate are separated by the orthographic projections of the corresponding light-emitting control signal lines among the plurality of light-emitting control signal lines em on the substrate. Optionally, the orthographic projections of each of the plurality of light-emitting control signal lines em on the substrate are substantially non-overlapping with the orthographic projections of the corresponding gate lines on the substrate (e.g., at least 80%, at least 90%, at least 95%, at least 99%, or completely non-overlapping), and substantially non-overlapping with the orthographic projections of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate (e.g., at least 80%, at least 90%, at least 95%, at least 99%, or completely non-overlapping).

[0167] In some embodiments, the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate are separated by the orthographic projections of the corresponding first control signal lines among the plurality of first control signal lines SL1 on the substrate. Optionally, the orthographic projections of each of the plurality of first control signal lines SL1 on the substrate are substantially non-overlapping with the orthographic projections of the corresponding gate line on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlapping), and substantially non-overlapping with the orthographic projections of the second capacitor electrode Ce2 of the first capacitor C1 on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlapping).

[0168] As previously combined Figure 7C In some embodiments discussed, the array substrate includes a plurality of second capacitor electrode lines Ce2L, which serve as part of an interconnect voltage supply network. The plurality of second capacitor electrode lines Ce2L extend in a direction substantially parallel to the second direction DR2. Each of the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode of a pixel driving circuit connected together in the same row.

[0169] Figure 10 It is shown Figure 5A or Figure 8A A schematic diagram depicting the layout of the corresponding second capacitor electrode lines relative to the second node connection lines in the array substrate. (Refer to...) Figure 10 and Figure 6BThe connecting line CL, which connects the two adjacent second capacitor electrodes of two adjacent pixel driving circuits in the same row, separates the second electrode D5 of the light-emitting control transistor T5 from the second electrode D6 of the third reset transistor T6, and also separates the second electrode D5 of the light-emitting control transistor T5 from the first electrode S3 of the driving transistor T3. Because each second capacitor electrode line is located in the first gate metal layer, the second node connecting line Cln2 cannot be placed in the first gate metal layer.

[0170] In some embodiments, each of the second capacitor electrode lines is located in the first gate metal layer, the second electrode D5 of the light-emitting control transistor T5 and the first electrode S3 of the driving transistor T3 are located in the first semiconductor material layer, and the second electrode D6 of the third reset transistor T6 is located in the second semiconductor material layer. In some embodiments, in the pixel driving circuit, the second node connection line Cln2 is connected to the second electrode D5 of the light-emitting control transistor T5 through a third via v3, to the first electrode S3 of the driving transistor T3 through a fourth via v4, and to the second electrode D6 of the third reset transistor T6 through a fifth via v5. In one example, the third via v3 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. In another example, the fifth via v5 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0171] In some embodiments, the second node connection line Cln2 intersects with the corresponding second capacitor electrode line. Optionally, the orthographic projection of the second node connection line Cln2 on the substrate partially overlaps with the orthographic projection of the corresponding second capacitor electrode line on the substrate.

[0172] Reference Figures 5A to 5O , Figures 6A to 6D as well as Figures 8A to 8O In some embodiments, the first pixel driving circuits (e.g., directly adjacent to each other and located in the same row) Figure 5B The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 5B The corresponding layer of PDC2 in the array, for example, has a substantially mirror symmetry with respect to each other about a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines.

[0173] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a light-shielding layer or a first signal line layer. In one example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and a conductive layer of the second pixel driving circuit. In one specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. In another specific example, "corresponding layer" also includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, the "corresponding layer" includes a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, and a second signal line layer. In another specific example, the "corresponding layer" further includes a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer.

[0174] Reference Figures 5A to 5O , Figures 6A to 6D as well as Figures 8A to 8O In some embodiments, the voltage supply connection line Clv connects multiple components of two adjacent pixel driving circuits in the same row to corresponding voltage supply lines in a plurality of voltage supply lines Vdd. In some embodiments, each voltage supply line in the plurality of voltage supply lines Vdd is connected to the voltage supply connection line Clv, for example, through an eighth via v8. The voltage supply connection line Clv is connected to the first electrodes of two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row through a ninth via v9. The first electrodes of the two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row are part of the overall structure. The voltage supply connection line Clv is connected to the second capacitor electrodes of the first capacitors of the two adjacent pixel driving circuits in the same row, respectively, through different vias.

[0175] Figure 11 This is a schematic diagram illustrating the structure of a voltage supply connection line according to some embodiments of the present disclosure. (Refer to...) Figure 11In some embodiments, the voltage supply connection line includes: a main line portion MLP extending in a direction substantially parallel to the second direction DR2; and a first extension E1, a second extension E2, and a third extension E3 extending away from the main line portion MLP. The first extension E1, the second extension E2, and the third extension E3 each extend in a direction substantially parallel to the first direction DR1. In some embodiments, each of the plurality of voltage supply lines Vdd is connected to the first extension E1, for example, through an eighth via v8. The first extension E1 is connected to the first electrodes of two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row through a ninth via v9. The second extension E2 is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit, and the third extension E3 is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

[0176] In some embodiments, the voltage supply connection line Clv has substantially mirror symmetry with respect to a plane that is substantially parallel to the first direction DR1 and substantially perpendicular to the light-emitting surface of the array substrate. Optionally, this plane intersects with the first extension. Optionally, this plane intersects with the eighth via v8 and the ninth via v9.

[0177] Figure 12 It is shown Figure 5A or Figure 8A A schematic diagram depicting the layout of voltage supply interconnects in an array substrate relative to a second semiconductor material layer. (Refer to...) Figure 11 and Figure 12 In some embodiments, the orthographic projection of the voltage supply connection line Clv on the substrate at least partially surrounds the orthographic projections of two adjacent compensation transistors of two adjacent pixel driving circuits in the same row on the substrate. The main line portion MLP of the voltage supply connection line Clv intersects the active layers of two adjacent data write transistors of two adjacent pixel driving circuits in the same row. Optionally, the orthographic projection of the voltage supply connection line Clv on the substrate partially overlaps with the orthographic projections of the active layers of two adjacent data write transistors of two adjacent pixel driving circuits in the same row on the substrate.

[0178] In some embodiments, the orthographic projection of the first extension E1 onto the substrate separates the orthographic projection of the second electrode of the compensation transistor in the first adjacent pixel driving circuit onto the substrate from the orthographic projection of the second electrode of the compensation transistor in the second adjacent pixel driving circuit onto the substrate.

[0179] In some embodiments, at least a portion of the orthographic projection of the second extension E2 onto the substrate spaced the orthographic projection of the at least active layer of the first reset transistor in the first adjacent pixel driving circuit onto the substrate from the orthographic projection of the at least active layer of the compensation transistor in the first adjacent pixel driving circuit onto the substrate. Because the voltage supply connection line Clv is supplied with a constant voltage, this arrangement effectively prevents interference between the signals in the first reset transistor and the compensation transistor.

[0180] In some embodiments, at least a portion of the orthographic projection of the third extension E3 onto the substrate spaced the orthographic projection of the at least active layer of the first reset transistor in the second adjacent pixel driving circuit onto the substrate from the orthographic projection of the at least active layer of the compensation transistor in the second adjacent pixel driving circuit onto the substrate. Because the voltage supply connection line Clv is supplied with a constant voltage, this arrangement effectively prevents interference between the signals in the first reset transistor and the compensation transistor.

[0181] Figure 13 This is a schematic diagram illustrating the layout of multiple first reset signal lines relative to multiple data lines in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 13 , Figure 5K and Figure 5M In some embodiments, at least a portion of the orthographic projection of each of the plurality of first reset signal lines Vint1 onto the substrate spaced apart from at least a portion of the orthographic projection of a first corresponding data line among the plurality of data lines DL onto the substrate and from at least a portion of the orthographic projection of a second corresponding data line among the plurality of data lines DL onto the substrate. The first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit. Optionally, at least a portion of the orthographic projection of each of the plurality of first reset signal lines Vint1 onto the substrate spaced apart from the orthographic projection of a second segment of a first corresponding data line among the plurality of data lines DL onto the substrate and from the orthographic projection of a second segment of a second corresponding data line among the plurality of data lines DL onto the substrate. The first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit. Because each of the first reset signal lines is provided with a constant voltage, this layout can effectively prevent interference between the data signals of two adjacent data lines DL that are configured to provide data signals to two adjacent pixel drive circuits.

[0182] In some embodiments, each of the plurality of gate lines includes a plurality of branches. (See reference...) Figures 5A to 5O as well as Figures 8A to 8O In some embodiments, each gate line includes a corresponding first branch GL-1 and a corresponding second branch GL-2. Optionally, the orthographic projection of the corresponding first branch GL-1 onto the substrate and the orthographic projection of the corresponding second branch GL-2 onto the substrate at least partially overlap. In one example, the corresponding first branch GL-1 is located in a second gate metal layer. In another example, the corresponding second branch GL-2 is located in a third gate metal layer.

[0183] In some embodiments, each of the plurality of first control signal lines SL1 includes a plurality of branches. (Refer to...) Figures 5A to 5O as well as Figures 8A to 8O Each first control signal line includes a first branch SL1-1 and a second branch SL1-2. Optionally, the orthographic projection of the first branch SL1-1 on the substrate and the orthographic projection of the second branch SL1-2 on the substrate at least partially overlap. In one example, the first branch SL1-1 is located in the second gate metal layer. In another example, the second branch SL1-2 is located in the third gate metal layer.

[0184] In some embodiments, each of the plurality of third control signal lines includes multiple branches. (Refer to...) Figures 5A to 5O as well as Figures 8A to 8O Each third control signal line includes a first branch SL3-1, a second branch SL3-2, and a third branch SL3-3. Optionally, the orthographic projection of the first branch SL3-1 on the substrate at least partially overlaps with the orthographic projection of the second branch SL3-2 on the substrate, and at least partially overlaps with the orthographic projection of the third branch SL3-3 on the substrate. Optionally, the orthographic projection of the second branch SL3-2 on the substrate at least partially overlaps with the orthographic projection of the third branch SL3-3 on the substrate. In one example, the first branch SL3-1 is located in a first gate metal layer. In another example, the second branch SL3-2 is located in a second gate metal layer. In yet another example, the third branch SL3-3 is located in a third gate metal layer.

[0185] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0186] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel driving circuits and forming a plurality of gate lines. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes forming a driving transistor, forming a data writing transistor, forming a first reset transistor, forming a first capacitor having a first capacitor electrode and a second capacitor electrode, forming a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and forming a first node connection line. Optionally, each of the plurality of gate lines is configured to provide a gate scan signal to the data writing transistor in the corresponding pixel driving circuit. Optionally, the gate of the driving transistor is connected to the third capacitor electrode. Optionally, the first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode. Optionally, the orthographic projection of the corresponding gate line on the substrate does not substantially overlap with the orthographic projection of the first node connection line on the substrate.

[0187] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising multiple pixel driving circuits and multiple gate lines; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Each of the plurality of gate lines is configured to provide a gate scan signal to the data write transistor in the corresponding pixel driving circuit; The gate of the driving transistor is connected to the electrode of the third capacitor; The first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode; as well as The orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the first node connection line on the substrate do not substantially overlap; wherein the orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the first node connection line on the substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

2. The array substrate according to claim 1, wherein, The orthographic projection of the second capacitor electrode of the first capacitor on the substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate, and also does not substantially overlap with the orthographic projection of the first node connection line on the substrate.

3. The array substrate according to claim 2, wherein, The orthographic projection of the corresponding gate line on the substrate and the orthographic projection of the third capacitor electrode of the second capacitor on the substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

4. The array substrate according to claim 3, wherein, The orthographic projection of the second capacitor electrode of the first capacitor on the substrate does not substantially overlap with the orthographic projection of the corresponding gate line on the substrate, and also does not substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor on the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein, The orthographic projection of the corresponding gate line on the substrate does not substantially overlap with the orthographic projection of the active layer of the first reset transistor and the second electrode on the substrate.

6. The array substrate according to any one of claims 1 to 4, wherein, The second electrode of the first reset transistor intersects with the electrode of the second capacitor.

7. The array substrate according to any one of claims 1 to 4, comprising a plurality of second capacitor electrode lines extending in a direction substantially parallel to the second direction; in, Each of the plurality of second capacitor electrode lines includes second capacitor electrodes of pixel driving circuits connected together in the same row. Each pixel driving circuit further includes a light-emitting control transistor and a third reset transistor; Among them, the connecting line of the two adjacent second capacitor electrodes in the corresponding second capacitor electrode line that connects the two adjacent pixel driving circuits in the same row separates the second electrode of the light-emitting control transistor from the second electrode of the third reset transistor, and separates the second electrode of the light-emitting control transistor from the first electrode of the driving transistor.

8. The array substrate according to claim 7, wherein, Each pixel driving circuit further includes a second node connection line, which is connected to the second electrode of the light-emitting control transistor through a third via, to the first electrode of the driving transistor through a fourth via, and to the second electrode of the third reset transistor through a fifth via. The second electrode of the light-emitting control transistor and the first electrode of the driving transistor are located in the first semiconductor material layer; The corresponding second capacitor electrode line is located in the first gate metal layer, and the first gate metal layer is located on the side of the first semiconductor material layer away from the substrate. The second electrode of the third reset transistor is located in the second semiconductor material layer, which is located on the side of the first gate metal layer away from the substrate. as well as The second node connection line is located in the first signal line layer, which is located on the side of the second semiconductor material layer away from the substrate.

9. The array substrate according to claim 8, wherein, The second node connection line intersects with the corresponding second capacitor electrode line.

10. The array substrate according to any one of claims 1 to 4, further comprising a plurality of voltage supply lines; in, Each pixel driving circuit also includes a light-emitting control transistor and a voltage supply connection line; The corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line through the eighth via; The voltage supply connection line is connected to the first electrode of two adjacent light-emitting control transistors of two adjacent pixel driving circuits in the same row through the ninth via. The first electrode of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row is part of the overall structure. as well as The voltage supply connection lines are respectively connected to the second capacitor electrodes of the first capacitors of two adjacent pixel driving circuits in the same row through different vias.

11. The array substrate according to claim 10, wherein, The voltage supply connection line includes a main line portion extending in a direction substantially parallel to the second direction; and a first extension, a second extension, and a third extension extending away from the main line portion; The first extension, the second extension, and the third extension each extend in a direction substantially parallel to the first direction; The respective voltage supply line of the plurality of voltage supply lines is connected to the first extension through the eighth via; The first extension is connected to the first electrode of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row through the ninth via; The second extension is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit. as well as The third extension is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

12. The array substrate according to claim 11, wherein, The voltage supply connection line has a substantially mirror symmetry with respect to a plane that is substantially parallel to the first direction and substantially perpendicular to the light-emitting surface of the array substrate.

13. The array substrate according to claim 11, wherein, Each pixel driving circuit also includes a compensation transistor; Wherein, the orthographic projection of the voltage supply connection line on the substrate at least partially surrounds the orthographic projection of two adjacent compensation transistors of two adjacent pixel driving circuits in the same row on the substrate; and The main line section intersects with the active layers of two adjacent data write transistors of two adjacent pixel driving circuits in the same row.

14. The array substrate according to claim 11, wherein, Each pixel driving circuit also includes a compensation transistor; Wherein, at least a portion of the orthographic projection of the second extension onto the substrate spaced the orthographic projection of the at least active layer of the first reset transistor in the first adjacent pixel driving circuit onto the substrate from the orthographic projection of the at least active layer of the compensation transistor in the first adjacent pixel driving circuit onto the substrate; and At least a portion of the orthographic projection of the third extension onto the substrate spaced the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel driving circuit onto the substrate from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel driving circuit onto the substrate.

15. The array substrate according to any one of claims 1 to 4, further comprising a plurality of first reset signal lines and a plurality of data lines; in, At least a portion of the orthographic projection of each of the plurality of first reset signal lines on the substrate spaced apart from the orthographic projection of at least a portion of the first corresponding data line of the plurality of data lines on the substrate, wherein the first corresponding data line is configured to provide a data signal to a first adjacent pixel driving circuit, and the second corresponding data line is configured to provide a data signal to a second adjacent pixel driving circuit.

16. The array substrate according to any one of claims 1 to 4, further comprising a plurality of first reset signal lines; in, Each of the plurality of first reset signal lines includes a plurality of loops arranged in a direction substantially parallel to the first direction; as well as Each loop in the multiple loops is connected to the first electrode of two adjacent first reset transistors of two adjacent pixel driving circuits in the same row.

17. The array substrate according to any one of claims 1 to 4, further comprising an interconnect voltage supply network; in, The interconnected voltage supply network includes multiple voltage supply lines, multiple second capacitor electrode lines, and multiple voltage supply connection lines; The plurality of voltage supply lines extend in a direction substantially parallel to the first direction; The plurality of second capacitor electrode lines extend in a direction substantially parallel to the second direction; Each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in the same row. as well as Each of the plurality of voltage supply connection lines connects a corresponding voltage supply line among the plurality of voltage supply lines to a corresponding second capacitor electrode line among the plurality of second capacitor electrode lines.

18. The array substrate according to any one of claims 1 to 4, wherein, Each pixel driving circuit also includes a compensation transistor and a third node connection line; The third node connection line is connected to the second electrode of the compensation transistor and the data writing transistor through the sixth via, and is connected to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor through the seventh via. The orthographic projection of the third node connection line on the substrate at least partially overlaps with the orthographic projection of the active layer of the compensation transistor on the substrate; and The third node connection line extends in a direction substantially parallel to the extension direction of the active layer of the compensation transistor.

19. A display device comprising an array substrate according to any one of claims 1 to 18 and one or more integrated circuits connected to the array substrate.

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