Shifting register, gate driving circuit, display panel and driving method and device

Abstract

The invention relates to a shift register, a gate driving circuit, a display panel and a driving method and device, and relates to the technical field of display. The shift register comprises a driving module used for outputting an initial scanning signal; the control module is connected with the driving module and is used for at least receiving the initial scanning signal, the first power supply signal, the second power supply signal, the third power supply signal, the first frequency control signal and the second frequency control signal; the control module is also used for outputting a first power supply signal as a grid scanning signal under the condition that both the initial scanning signal and the first frequency control signal are valid and the second frequency control signal is invalid; or, under the condition that the first frequency control signal is invalid and the initial scanning signal and the second frequency control signal are valid, outputting the second power supply signal as the grid scanning signal. The first power supply signal or the second power supply signal can be output as the grid scanning signal, and the display uniformity can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display panel, and a driving method and device. Background Art

[0002] With the continuous advancement of display technology, the application scenarios of display devices are increasing, and users' demands for display devices are becoming more diverse. In some application scenarios, the use of zoned frequency-frequency display in display devices can effectively reduce power consumption and extend service life. However, existing display devices have the problem of uneven display when implementing zoned frequency-frequency display. Summary of the invention

[0003] The embodiments of the present application provide a shift register, a gate driving circuit, a display panel, and a driving method and device, which are helpful to improve display uniformity.

[0004] In a first aspect, an embodiment of the present application provides a shift register, comprising:

[0005] A driving module, used for outputting an initial scanning signal;

[0006] a control module connected to the driving module, and configured to receive at least the initial scanning signal, the first power signal, the second power signal, the third power signal, the first frequency control signal, and the second frequency control signal; the first power signal, the second power signal, and the third power signal are different from each other;

[0007] The control module is also used to output the first power signal as a gate scan signal when the initial scan signal and the first frequency control signal are both valid and the second frequency control signal is invalid; or to output the second power signal as a gate scan signal when the first frequency control signal is invalid and the initial scan signal and the second frequency control signal are both valid.

[0008] In a second aspect, an embodiment of the present application provides a gate drive circuit, comprising a plurality of cascaded shift registers as described above.

[0009] In a third aspect, an embodiment of the present application provides a display panel, comprising at least one gate driving circuit and a pixel circuit as described above, wherein the gate driving circuit is connected to the pixel circuit.

[0010] In a fourth aspect, an embodiment of the present application provides a method for driving a display panel, which is applied to the display panel as described above, wherein the display panel includes a first display area and a second display area, and the method includes:

[0011] By controlling part of the shift registers in the gate driving circuit to output a first power supply signal, the pixel circuit of the first display area is driven to drive the first display area to display at a first frequency;

[0012] The remaining shift registers in the gate drive circuit are controlled to output a second power supply signal to drive the pixel circuit of the second display area to drive the second display area to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power supply signal is different from the second power supply signal.

[0013] In a fifth aspect, an embodiment of the present application provides a display device, which includes the display panel as described above.

[0014] The shift register, gate drive circuit, display panel, and driving method and device provided in the embodiments of the present application control the shift register to select and output the first power signal or the second power signal as the gate scanning signal by controlling the first frequency control signal and the second frequency control signal. Since the first power signal is different from the second power signal, the present application can provide gate scanning signals of different potentials for pixel circuits of display areas of different frequencies. Specifically, by controlling the initial scanning signal and the first frequency control signal to be valid and the second frequency control signal to be invalid, the shift register outputs the first power signal as the gate scanning signal, and controls the first frequency control signal to be invalid and the initial scanning signal to be and the second frequency control signal are both valid, so that the shift register outputs the second power supply signal as the gate scanning signal, so that the same shift register can provide different power supply signals as gate scanning signals for different refresh frequencies or different display scenarios, and different shift registers can provide different power supply signals as gate scanning signals for display areas with different frequencies, that is, through gate scanning signals with different potentials, the characteristic drift difference of the transistor in the zoned frequency-determined display scenario is compensated, and then the display brightness difference between different display areas in the zoned frequency-determined display scenario can be compensated, so that the display brightness of different display areas is balanced, thereby achieving the purpose of improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of a shift register provided in an embodiment of the present application;

[0016] Figure 2 A timing diagram of multiple signals provided in an embodiment of the present application;

[0017] Figure 3 Another timing diagram of multiple signals provided in an embodiment of the present application;

[0018] Figure 4A timing diagram of multiple signals provided in another embodiment of the present application;

[0019] Figure 5 A timing diagram of multiple signals provided in another embodiment of the present application;

[0020] Figure 6 A schematic diagram of the structure of another shift register provided in an embodiment of the present application;

[0021] Figure 7 A schematic diagram of the structure of a control module provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of the structure of another control module provided in an embodiment of the present application;

[0023] Fig. 9 A schematic diagram of the structure of another control module provided in an embodiment of the present application;

[0024] Fig.10 A schematic diagram of the structure of another control module provided in an embodiment of the present application;

[0025] Fig.11 A schematic diagram of the structure of a driving module provided in an embodiment of the present application;

[0026] Fig.12 A schematic diagram of the structure of another driving module provided in an embodiment of the present application;

[0027] Fig.13 A schematic diagram of the structure of another driving module provided in an embodiment of the present application;

[0028] Fig.14 A schematic diagram of the structure of a shift register provided in an embodiment of the present application;

[0029] Fig.15 A timing diagram of multiple signals provided in an embodiment of the present application;

[0030] Fig.16 Another timing diagram of multiple signals provided in an embodiment of the present application;

[0031] Fig.17 A schematic diagram of the structure of a shift register provided in an embodiment of the present application;

[0032] Fig.18 A timing diagram of multiple signals provided in an embodiment of the present application;

[0033] Fig.19 A timing diagram of multiple signals provided in an embodiment of the present application;

[0034] Fig. 20 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application;

[0035] Fig.21 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0036] Fig. 22 A schematic diagram of the structure of a pixel circuit and a light-emitting element provided in an embodiment of the present application;

[0037] Fig.23 A schematic diagram of a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0038] Fig.24 A schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0039] Fig.25 A timing diagram of multiple signals provided in an embodiment of the present application;

[0040] Fig.26 A graph showing the relationship between a first power signal and a second power signal and time, respectively, provided in an embodiment of the present application;

[0041] Fig. 27 Another graph showing the relationship between a first power signal and a second power signal and time provided in an embodiment of the present application;

[0042] Fig.28 A schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0043] Description of reference numerals:

[0044] 1. First display area; 2. Second display area; 10. Driving module; 11. Input module; 12. First driving module; 13. Second driving module; 20. Control module; 21. First control module; 22. Second control module; 23. Output module; 210. First control unit; 211. First control unit; 212. First control unit; 220. Second control unit; 221. Second control unit; 222. Second control unit; 230. Third control unit; 231. Third control unit; 232. Third control unit; 240. Fourth control unit; 241. Fourth control unit; 242. Fourth control unit; 30. Gate driving circuit; 301. Shift register; 31. First gate driving circuit; 311. Shift register; 32. Second gate driving circuit; 321. Shift register; 40. Pixel circuit; 51. First display area; 52. Second display area; 60. Display panel; 70. Display device. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0047] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0048] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0049] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0050] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0051] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0052] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0053] As described in the background technology section, the display device has the problem of uneven display when displaying in different regions and frequencies. For example, the display brightness of the regions displaying at different frequencies (referred to as different display regions) is different, resulting in poor display effect. Figure 1 In the display panel shown, the display brightness of the first display area 1 is lower than the display brightness of the second display area 2, wherein the refresh frequencies of the first display area 1 and the second display area 2 are different.

[0054] It can be understood that the display panel is the core component of the display device to realize the display function. The display panel drives the light-emitting element to emit light through the pixel circuit to realize the display function. Based on the above technical problems, the inventors have found that when the display panel is divided into zones and frequency-controlled for a long time, there are differences in the characteristic drift of the transistors in the pixel circuits of different display areas, which leads to differences in the display brightness of different display areas, and then leads to the problem of uneven display, affecting the display effect. Taking the pixel circuit of the display panel including oxide thin film transistors as an example, when the display panel is divided into zones and frequency-controlled for a long time, due to the different refresh frequencies of the high-frequency and low-frequency display areas, the oxide thin film transistors in the high-frequency display area are more likely to drift than those in the low-frequency display area, resulting in differences in the display brightness between the high-frequency display area and the low-frequency display area, and the problem of split-screen display will occur.

[0055] Based on the above, the inventor further studied the technical solution of the embodiment of the present application. Specifically, the shift register provided in the embodiment of the present application includes a driving module and a control module, the driving module is used to output an initial scan signal; the control module is used to receive at least an initial scan signal, a first power signal, a second power signal, a third power signal, a first frequency control signal and a second frequency control signal; the control module is also used to output the first power signal as a gate scan signal when the initial scan signal and the first frequency control signal are both valid and the second frequency control signal is invalid; or, when the first frequency control signal is invalid and the initial scan signal and the second frequency control signal are both valid, the second power signal is output as a gate scan signal; wherein the first power signal, the second power signal and the third power signal are different. In this way, the present application controls the shift register to select the output of the first power signal or the second power signal as the gate scan signal by controlling the first frequency control signal and the second frequency control signal, so as to provide gate scan signals of different potentials for pixel circuits in different display areas, realize compensation for the drift difference of transistor characteristics in pixel circuits in different display areas, and then compensate for the display brightness difference in different display areas, which helps to improve display uniformity.

[0056] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] Figure 2 A schematic diagram of the structure of a shift register provided in an embodiment of the present application is shown in FIG. Figure 3 A timing diagram of multiple signals provided in an embodiment of the present application, Figure 4 Another timing diagram of multiple signals provided in an embodiment of the present application.

[0058] Combination Figures 2 to 4 As shown, in some embodiments, the present application provides a shift register, including a driving module 10 and a control module 20. The driving module 10 is used to output an initial scanning signal Next. The driving module 10 can receive a start signal STV, a first clock signal CK, a second clock signal XCK, a first power signal VGH1, and a third power signal VGL, and output an initial scanning signal Next.

[0059] The control module 20 is connected to the driving module 10. The control module 20 is used to receive at least an initial scanning signal Next, a first power signal VGH1, a second power signal VGH2, a third power signal VGL, a first frequency control signal Ctrl1, and a second frequency control signal Ctrl2. The first power signal VGH1, the second power signal VGH2, and the third power signal VGL are different. Exemplarily, the first power signal VGH1 is different from the second power signal VGH2, and the first power signal VGH1 and the second power signal VGH2 are respectively greater than the third power signal VGL. For example, the first power signal VGH1 and the second power signal VGH2 are both high-level signals, and the third power signal VGL is a low-level signal. The frequencies of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are different, and the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are respectively used to control the driving frequency of the pixel circuit corresponding to the shift register connected, thereby controlling the refresh frequency of the corresponding display area.

[0060] For the sake of convenience, in the embodiment of the present application, the first power signal VGH1 is greater than the second power signal VGH2, the second power signal VGH2 is greater than the third power signal VGL, and the frequency of the first frequency control signal Ctrl1 is greater than the frequency of the second frequency control signal Ctrl2. It should be noted that in some embodiments, the first power signal VGH1 may be less than the second power signal VGH2, and the first power signal VGH1 is greater than the third power signal VGL; the frequency of the first frequency control signal Ctrl1 may be less than the frequency of the second frequency control signal Ctrl2, and the relationship between each power signal and each frequency control signal may be set according to application requirements.

[0061] The control module 20 is further configured to output the first power signal VGH1 as the gate scan signal OUT when both the initial scan signal Next and the first frequency control signal Ctrl1 are valid and the second frequency control signal Ctrl2 is invalid; or, when the first frequency control signal Ctrl1 is invalid and both the initial scan signal Next and the second frequency control signal Ctrl2 are valid, output the second power signal VGH2 as the gate scan signal OUT. Figure 3 As shown, when the initial scan signal Next and the first frequency control signal Ctrl1 are valid pulses and the second frequency control signal Ctrl2 is an invalid pulse, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; Figure 4 As shown, when the first frequency control signal Ctrl1 is an invalid pulse and the initial scan signal Next and the second frequency control signal Ctrl2 are valid pulses, the gate scan signal OUT output by the control module 20 is the second power signal VGH2.

[0062] Exemplarily, the effective pulses of the initial scan signal Next and the first frequency control signal Ctrl1 are different, and the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are the same. For example, the effective pulse of the initial scan signal Next is high level, and the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both low level; correspondingly, when the first frequency control signal Ctrl1 is low level and the initial scan signal Next and the second frequency control signal Ctrl2 are both high level, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; when the initial scan signal Next and the first frequency control signal Ctrl1 are both high level and the second frequency control signal Ctrl2 is low level, the gate scan signal OUT output by the control module 20 is the second power supply signal VGH2.

[0063] In another exemplary embodiment, the effective pulses of the initial scan signal Next, the first frequency control signal Ctrl1, and the second frequency control signal Ctrl2 are all the same. For example, the effective pulses of the initial scan signal Next, the first frequency control signal Ctrl1, and the second frequency control signal Ctrl2 are all high level; correspondingly, when the initial scan signal Next and the first frequency control signal Ctrl1 are both high level, and the second frequency control signal Ctrl2 is low level, the gate scan signal OUT output by the control module 20 is the first power supply signal VGH1; when the first frequency control signal Ctrl1 is low level, and the initial scan signal Next and the second frequency control signal Ctrl2 are both high level, the gate scan signal OUT output by the control module 20 is the second power supply signal VGH2.

[0064] It should be noted that in some other examples, the effective pulse of the initial scanning signal Next may be at a low level. In applications, the level types of the effective pulses of the initial scanning signal Next, the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 may be set accordingly according to specific requirements, and are not limited in detail here.

[0065] When the initial scan signal Next and the first frequency control signal Ctrl1 are both valid pulses and the second frequency control signal Ctrl2 is an invalid pulse, the pixel circuit connected to the shift register drives the light-emitting element D to emit light at the first frequency under the action of the gate scan signal OUT, i.e., the first power signal VGH1, so that the display area driven by the pixel circuit is displayed at the first frequency. When the first frequency control signal Ctrl1 is an invalid pulse and the initial scan signal Next and the second frequency control signal Ctrl2 are both valid pulses, the pixel circuit connected to the shift register drives the light-emitting element D to emit light at the second frequency under the action of the gate scan signal OUT, i.e., the second power signal VGH2, so that the display area driven by the pixel circuit is displayed at the second frequency.

[0066] In the application, the control module 20 in the shift register is used to connect with the pixel circuit, and the pixel circuit is used to drive the light-emitting element D connected to the pixel circuit to emit light. When the display area corresponding to the pixel circuit connected to the shift register works in the first mode, that is, the refresh frequency of the display area is the first frequency, the initial scan signal Next and the first frequency control signal Ctrl1 can be set to valid and the second frequency control signal Ctrl2 can be set to invalid. In this case, the shift register outputs the first power signal VGH1 as the gate scan signal OUT to drive the pixel circuit, so that the pixel circuit drives the light-emitting element D to emit light at the first frequency, and then the corresponding display area is displayed at the first frequency. When the display area corresponding to the pixel circuit connected to the shift register works in the second mode, that is, in the application scenario where the refresh frequency of the display area is the second frequency, the first frequency control signal Ctrl1 can be set to invalid and the initial scan signal Next and the second frequency control signal Ctrl2 can be set to valid. In this case, the shift register outputs the second power signal VGH2 as the gate scan signal OUT to drive the pixel circuit, so that the pixel circuit drives the light-emitting element D to emit light at the second frequency, and then the corresponding display area is displayed at the second frequency.

[0067] It can be understood that, taking a display panel with a zoned frequency division function as an example, the display panel includes a first display area and a second display area. If the first display area of ​​the display panel operates in a first mode and the second display area operates in a second mode, correspondingly, the shift register connected to the pixel circuit of the first display area can output a first power signal VGH1 as a gate scan signal OUT, so that the pixel circuit of the first display area drives the first display area to display at a first frequency under the drive of the first power signal VGH1; the shift register connected to the pixel circuit of the second display area can output a second power signal VGH2 as a gate scan signal OUT, so that the pixel circuit of the second display area drives the second display area to display at a second frequency under the drive of the second power signal VGH2. For example, the first frequency is greater than the second frequency, that is, the first display area displayed at a higher frequency uses the first power signal VGH1 as the gate scan signal OUT, and the second display area displayed at a lower frequency uses the second power signal VGH2 as the gate scan signal OUT.

[0068] The shift register provided in the embodiment of the present application controls the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to control the shift register to select and output the first power signal VGH1 or the second power signal VGH2 as the gate scan signal OUT. Since the first power signal VGH1 is different from the second power signal VGH2, the present application can provide the pixel circuits in different display areas with gate scan signals OUT of different potentials. By controlling the initial scan signal Next and the first frequency control signal Ctrl1 to be valid and the second frequency control signal Ctrl2 to be invalid, the shift register outputs the first power signal VGH1 as the gate scan signal OUT, and controls the first frequency control signal Ctrl1 to be invalid and the initial scan signal Ctrl2 to be invalid. The scanning signal Next and the second frequency control signal Ctrl2 are both valid, so that the shift register outputs the second power supply signal VGH2 as the gate scanning signal OUT, so that the same shift register can provide different power supply signals as the gate scanning signal OUT for different refresh frequencies or different display modes, and different shift registers can provide different power supply signals as the gate scanning signal OUT for different display areas, that is, through the gate scanning signal OUT with different potentials, the characteristic drift difference of the transistor in the partitioned frequency-departure display scenario is compensated, and then the display brightness difference between different display areas in the partitioned frequency-departure scenario can be compensated, so that the display brightness of different display areas is balanced, thereby achieving the purpose of improving display uniformity.

[0069] Figure 5 A timing diagram of multiple signals provided in an embodiment of the present application. Figure 2 and Figure 5 As shown, in some embodiments, the control module 20 is further used to output the third power signal VGL as the gate scan signal OUT when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid. That is, when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, the gate scan signal OUT output by the control module 20 is the third power signal VGL. Wherein, when both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid pulses, no matter whether the initial scan signal Next is a valid pulse or an invalid pulse, the gate scan signal OUT output by the control module 20 is the third power signal VGL.

[0070] Exemplarily, the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are the same, for example, both are low level; correspondingly, when the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both low level, the gate scan signal OUT output by the control module 20 is the third power signal VGL. In this case, the control module 20 does not output the first power signal VGH1, nor does it output the second power signal VGH2. It can be understood that the control module 20 maintains the default low level state. Another exemplary embodiment, the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both high level; correspondingly, when the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both high level, the gate scan signal OUT output by the control module 20 is the third power signal VGL. It should be noted that in the application, the level type of the effective pulses of the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 can be set according to the specific application scenario, and no excessive restrictions are made here.

[0071] In the application, the control module 20 in the shift register is used to connect with the pixel circuit, and the pixel circuit is used to drive the light-emitting element D connected to the pixel circuit to emit light. When the display area corresponding to the pixel circuit connected to the shift register is in the maintenance stage, the gate scanning signal OUT output by the shift register remains unchanged by setting the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to invalid, so that the display area corresponding to the pixel circuit driven by the shift register maintains the display brightness unchanged.

[0072] The shift register provided in the embodiment of the present application controls the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 to be invalid, so that the control module 20 outputs the third power signal VGL as the gate scan signal OUT, thereby providing the third power signal VGL to the pixel circuit through the shift register, so that the pixel circuit drives the corresponding display area to keep the display brightness unchanged under the drive of the third power signal VGL, which helps to realize the zoned and frequency-determined display function of the display panel.

[0073] Figure 6 A schematic diagram of the structure of a shift register provided in an embodiment of the present application. Figures 3 to 6 As shown, in some embodiments, the control module 20 includes a first control module 21 , a second control module 22 and an output module 23 .

[0074] The first control module 21 is connected to the output module 23 and the driving module 10, respectively. The first control module 21 can be connected to the first output node SOUT of the output module 23 and the second output node NEXT of the driving module 10, respectively. The first control module 21 is used to receive at least the initial scan signal Next, the first power signal VGH1, the third power signal VGL and the first frequency control signal Ctrl1, and control the gate scan signal OUT outputted from the first output node SOUT of the output module 23. The first control module 21 can select to output the first power signal VGH1 under the action of the initial scan signal Next, the first power signal VGH1, the third power signal VGL and the first frequency control signal Ctrl1.

[0075] The second control module 22 is connected to the output module 23 and the driving module 10 respectively. The second control module 22 can be connected to the first output node SOUT of the output module 23 and the driving module 10 respectively. The second control module 22 is used to receive at least the second power signal VGH2, the third power signal VGL and the second frequency control signal Ctrl2, and control the gate scan signal OUT outputted by the first output node SOUT. The second control module 22 can select to output the second power signal VGH2 under the action of the initial scan signal Next, the second power signal VGH2, the third power signal VGL and the second frequency control signal Ctrl2.

[0076] The output module 23 is connected to the driving module 10. The output module 23 can be connected to the third node N3 of the driving module 10. The output module 23 is used to receive at least the third power signal VGL and control the gate scanning signal OUT output by the first output node SOUT. The output module 23 can receive the third node signal of the third node N3 and the third power signal VGL, and select to output the third power signal VGL.

[0077] When the initial scanning signal Next and the first frequency control signal Ctrl1 are both valid, and the second frequency control signal Ctrl2 is invalid, for example Figure 3 As shown, when the initial scanning signal Next and the second frequency control signal Ctrl2 are both high level, and the first frequency control signal Ctrl1 is low level, the first control module 21 outputs the first power signal VGH1, and the second control module 22 and the output module 23 do not output. In this case, the shift register outputs the first power signal VGH1 as the gate scanning signal OUT.

[0078] When the first frequency control signal Ctrl1 is invalid, and both the initial scanning signal Next and the second frequency control signal Ctrl2 are valid, for example Figure 4As shown, when the second frequency control signal Ctrl2 is at a low level, and the initial scan signal Next and the first frequency control signal Ctrl1 are both at high levels, the second control module 22 outputs the second power supply signal VGH2, and the first control module 21 and the output module 23 do not output. In this case, the shift register outputs the second power supply signal VGH2 as the gate scan signal OUT.

[0079] When both the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are invalid, for example Figure 5 As shown, when the second frequency control signal Ctrl2 and the first frequency control signal Ctrl1 are both at high levels, the output module 23 outputs the third power signal VGL, and the first control module 21 and the second control module 22 do not output. In this case, the shift register outputs the third power signal VGL as the gate scan signal OUT.

[0080] In the shift register provided in the embodiment of the present application, the control module 20 controls the gate scan signal OUT outputted from the first output node SOUT of the output module 23 through the first control module 21, the second control module 22 and the output module 23 respectively, thereby realizing the switching of the first power supply signal VGH1, the second power supply signal VGH2 or the third power supply signal VGL of the gate scan signal OUT output according to the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2, so as to compensate for the display brightness difference of different display areas through the gate scan signal OUT of different potentials, thereby achieving the purpose of balancing the display brightness and improving the display uniformity.

[0081] Figure 7 A schematic diagram of the structure of a control module 20 provided in an embodiment of the present application is shown in FIG. Figure 8 This is a schematic diagram of the structure of another control module 20 provided in an embodiment of the present application. Fig. 9 This is a schematic diagram of the structure of another control module 20 provided in an embodiment of the present application.

[0082] Combination Figures 7 to 9 As shown, in some embodiments, the first control module 21 and the second control module 22 both include a first control unit 210 and a second control unit 220, that is, the first control module 21 includes a first control unit 210 and a second control unit 220, and the second control module 22 includes a first control unit 210 and a second control unit 220.

[0083] The first control unit 210 is connected to the target node of the driving module 10. The first control unit 210 is used to receive the target node signal, the target frequency control signal and the third power signal VGL of the target node, and control the output of the first control signal. The first control unit 210 can control the output of the first control signal under the action of the target node signal, the target frequency control signal and the third power signal VGL.

[0084] The second control unit 220 is respectively connected to the first control unit 210, the first output node SOUT, the first node N1 of the driving module 10, and the second node N2 of the driving module 10. The second control unit 220 is used to receive the first control signal, the first node signal of the first node N1, the second node signal of the second node N2, and the target power signal, and control the gate scan signal OUT output by the first output node SOUT. The first control unit 210 can control the first output node SOUT to select the output of the first power signal VGH1 under the action of the first control signal, the first node signal, the second node signal, and the target power signal.

[0085] In the first control module 21, the target node is the second output node NEXT of the driving module 10, the target node signal is the initial scan signal Next, the target frequency control signal is the first frequency control signal Ctrl1, and the target power signal is the first power signal VGH1. Specifically, in the first control module 21, the first control unit 211 is connected to the second output node NEXT of the driving module 10, and the first control unit 211 is used to receive the initial scan signal Next, the first frequency control signal Ctrl1 and the third power signal VGL, and control the first control signal output by the first control node R1; the second control unit 221 is respectively connected to the first control node R1, the first output node SOUT, the first node N1 and the second node N2, and the second control unit 221 is used to receive the first control signal, the first node signal, the second node signal and the first power signal VGH1 output by the first control node R1, and control the gate scan signal OUT output by the first output node SOUT.

[0086] In the second control module 22, the target node is the first node N1, the target node signal is the first node signal, the target frequency control signal is the second frequency control signal Ctrl2, and the target power signal is the second power signal VGH2. Specifically, in the second control module 22, the first control unit 212 is connected to the first node N1, and the first control unit 212 is used to receive the first node signal, the second frequency control signal Ctrl2 and the third power signal VGL, and control the first control signal output by the second control node R2; the second control unit 222 is respectively connected to the second control node R2, the first output node SOUT, the first node N1 and the second node N2, and the second control unit 222 is used to receive the first control signal, the first node signal, the second node signal and the second power signal VGH2 output by the second control node R2, and control the gate scan signal OUT output by the first output node SOUT.

[0087] In the shift register provided in the embodiment of the present application, the first control module 21 realizes effective control of the gate scan signal OUT outputted from the first output node SOUT according to the first frequency control signal Ctrl1 through the first control unit 211 and the second control unit 221, and the second control module 22 realizes effective control of the gate scan signal OUT outputted from the first output node SOUT according to the second frequency control signal Ctrl2 through the first control unit 212 and the second control unit 222. In this way, the gate scan signal OUT can be switched between the first power supply signal VGH1 and the second power supply signal VGH2 to compensate for the difference in display brightness, thereby improving display uniformity.

[0088] Please continue reading Figures 7 to 9 In some embodiments, the first control unit 210 includes a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 is connected to the target node. The first electrode of the first transistor T1 is connected to the second control unit 220 and the first end of the first capacitor C1, respectively, and the first electrode of the first transistor T1 is used to output the first control signal. The second electrode of the first transistor T1 is used to receive the target frequency control signal. The second end of the first capacitor C1 is used to receive the third power supply signal VGL.

[0089] In the first control module 21, the first control unit 211 includes a first transistor T1_1 and a first capacitor C1_1, wherein the gate of the first transistor T1_1 is connected to the second output node NEXT, the first electrode of the first transistor T1_1 is connected to the first end of the first capacitor C1_1, the first electrode of the first transistor T1_1 serves as the first control node R1 of the first control module 21, the second electrode of the first transistor T1_1 is used to receive the first frequency control signal Ctrl1, and the second end of the first capacitor C1_1 is used to receive the third power supply signal VGL.

[0090] In the second control module 22, the first control unit 212 includes a first transistor T1_2 and a first capacitor C1_2, wherein the gate of the first transistor T1_2 is connected to the first node N1, the first electrode of the first transistor T1_2 is connected to the first end of the first capacitor C1_2, the first electrode of the first transistor T1_2 serves as the second control node R2 of the second control module 22, the second electrode of the first transistor T1_2 is used to receive the second frequency control signal Ctrl2, and the second end of the first capacitor C1_2 is used to receive the third power supply signal VGL.

[0091] In the shift register provided in the embodiment of the present application, the first control unit 210 realizes effective control of the first control signal through the first transistor T1 and the first capacitor C1 according to the target node signal, the target frequency control signal and the third power supply signal VGL, thereby combining with the second control unit 220 to realize the output switching of the gate scan signal OUT according to the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2, so as to achieve the purpose of compensating for the display brightness difference and improving the display uniformity.

[0092] Please continue reading Fig. 9 In some embodiments, the first transistor T1 includes a dual-gate transistor. Exemplarily, the first transistor T1 includes a first sub-transistor and a second sub-transistor, wherein the gate of the first sub-transistor and the gate of the second sub-transistor are respectively connected to the target node, the first electrode of the first sub-transistor is respectively connected to the second control unit 220 and the first end of the first capacitor C1, the second electrode of the first sub-transistor is connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is used to receive the target frequency control signal.

[0093] In the first control module 21, the first transistor T1_1 includes a first sub-transistor T1_11 and a second sub-transistor T1_12, wherein the gate of the first sub-transistor T1_11 and the gate of the second sub-transistor T1_12 are respectively connected to the second output node NEXT, the first electrode of the first sub-transistor T1_11 is connected to the first end of the first capacitor C1_1, the first electrode of the first sub-transistor T1_11 serves as the first control node R1 of the first control module 21, the second electrode of the first sub-transistor T1_11 is connected to the first electrode of the second sub-transistor T1_12 of the first control module 21, and the second electrode of the second sub-transistor T1_12 is used to receive the first frequency control signal Ctrl1.

[0094] In the second control module 22, the first transistor T1_2 includes a first sub-transistor T1_21 and a second sub-transistor T1_22, wherein the gate of the first sub-transistor T1_21 and the gate of the second sub-transistor T1_22 are respectively connected to the first node N1, the first electrode of the first sub-transistor T1_21 is connected to the first end of the first capacitor C1_2, and the first electrode of the first sub-transistor T1_21 serves as the second control node R2 of the second control module 22, the second electrode of the first sub-transistor T1_21 is connected to the first electrode of the second sub-transistor T1_22 of the second control module 22, and the second electrode of the second sub-transistor T1_22 is used to receive the second frequency control signal Ctrl2.

[0095] In the shift register provided in the embodiment of the present application, the first transistor T1 adopts a dual-gate transistor, which can prevent leakage and reduce the leakage of the target frequency control signal to the second control unit 220, thereby improving the reliability and stability of the shift register, thereby improving the reliability of the display panel using the shift register, and thus improving the display effect.

[0096] Please continue reading Figures 7 to 9 In some embodiments, the first transistor T1 is a P-type transistor. For example, the first transistor T1 is a P-type thin film transistor (TFT) or a P-type metal-oxide-semiconductor field-effect transistor (MOSFET / MOS). In this way, the valid pulse of the target node signal is a low-level signal, and the invalid pulse is a high-level signal. Based on this, when the target node signal is at a low level, the first transistor T1 is turned off; when the target node signal is at a high level, the first transistor T1 is turned on. Among them, the on-off of the first transistor T1, i.e., the first control unit 210, is controlled by the target node signal, thereby controlling the on-off state of the path for the target frequency control signal to be transmitted to the second control unit 220.

[0097] Please continue reading Figures 7 to 9 In some embodiments, the second control unit 220 includes a second transistor T2, a third transistor T3, and a fourth transistor T4. The gate of the second transistor T2 is connected to the first control unit 210. The first electrode of the second transistor T2 is connected to the second node N2. The second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the gate of the fourth transistor T4. The gate of the third transistor T3 is connected to the first node N1. The first electrode of the third transistor T3 and the first electrode of the fourth transistor T4 are respectively used to receive the target power supply signal. The second electrode of the fourth transistor T4 is connected to the first output node SOUT.

[0098] In the first control module 21, the second control unit 221 includes a second transistor T2_1, a third transistor T3_1 and a fourth transistor T4_1, wherein the gate of the second transistor T2_1 is connected to the first control node R1. The first electrode of the second transistor T2_1 is connected to the second node N2. The second electrode of the second transistor T2_1 is connected to the seventh control node R7, and the seventh control node R7 is respectively connected to the second electrode of the third transistor T3_1 and the gate of the fourth transistor T4_1. The gate of the third transistor T3_1 is connected to the first node N1. The first electrode of the third transistor T3_1 and the first electrode of the fourth transistor T4_1 are respectively used to receive the first power supply signal VGH1. The second electrode of the fourth transistor T4_1 is connected to the first output node SOUT.

[0099] In the second control module 22, the second control unit 222 includes a second transistor T2_2, a third transistor T3_2 and a fourth transistor T4_2, wherein the gate of the second transistor T2_2 is connected to the second control node R2. The first electrode of the second transistor T2_2 is connected to the second node N2. The second electrode of the second transistor T2_2 is connected to the eighth control node R8, and the eighth control node R8 is respectively connected to the second electrode of the third transistor T3_2 and the gate of the fourth transistor T4_2. The gate of the third transistor T3_2 is connected to the first node N1. The first electrode of the third transistor T3_2 and the first electrode of the fourth transistor T4_2 are respectively used to receive the second power supply signal VGH2. The second electrode of the fourth transistor T4_2 is connected to the first output node SOUT.

[0100] In the shift register provided in the embodiment of the present application, the second control unit 220 realizes effective control of the gate scan signal OUT output by the first output node SOUT through the second transistor T2, the third transistor T3 and the fourth transistor T4 to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0101] Please continue reading Figure 8 and Fig. 9 In some embodiments, the second control unit 220 further includes a second capacitor C2, which is connected to the first electrode of the fourth transistor T4 and the gate of the fourth transistor T4 respectively. The second capacitor C2 can improve the stability of the gate scanning signal OUT outputted by the first output node SOUT.

[0102] In the first control module 21, the second control unit 221 further includes a second capacitor C2_1, which is connected to the first electrode of the fourth transistor T4_1 and the gate of the fourth transistor T4_1 respectively. The second capacitor C2_1 helps to improve the stability of the first control module 21 controlling the first output node SOUT to output the first power signal VGH1 as the gate scanning signal OUT.

[0103] In the second control module 22, the second control unit 222 further includes a second capacitor C2_2, which is connected to the first electrode of the fourth transistor T4_2 and the gate of the fourth transistor T4_2 respectively. The second capacitor C2_2 helps to improve the stability of the second control module 22 controlling the first output node SOUT to output the second power signal VGH2 as the gate scanning signal OUT.

[0104] Please continue reading Figures 7 to 9 In some embodiments, the second transistor T2, the third transistor T3 and the fourth transistor T4 are P-type transistors, respectively. For example, the second transistor T2 may be a PTFT or a PMOS, the third transistor T3 may be a PTFT or a PMOS, and the fourth transistor T4 may be a PTFT or a PMOS. In this way, the valid pulses of the first node signal and the first control signal are low-level signals, and the invalid pulses are high-level signals. Based on this, when the first control signal is at a low level, the second transistor T2 is turned off; when the first control signal is at a high level, the second transistor T2 is turned on. When the first node signal is at a low level, the third transistor T3 is turned off; when the first node signal is at a high level, the third transistor T3 is turned on. Among them, the on-off of the second transistor T2 is controlled by the first control signal, and the on-off of the third transistor T3 is controlled by the first node signal, and combined with the fourth transistor T4, effective control of the gate scan signal OUT output by the first output node SOUT is achieved, thereby achieving switching of the first output node SOUT outputting the first power signal VGH1 or the second power signal VGH2, and then compensating for the difference in drift characteristics of transistors in the pixel circuit through the potential difference between the power signals, so as to balance the display brightness and achieve the purpose of improving display uniformity.

[0105] Fig.10 A schematic diagram of the structure of a control module 20 provided in an embodiment of the present application. Fig.10 As shown, in some embodiments, the first control module 21 and the second control module 22 both include a third control unit 230 and a fourth control unit 240, that is, the first control module 21 includes a third control unit 230 and a fourth control unit 240, and the second control module 22 includes a third control unit 230 and a fourth control unit 240.

[0106] The third control unit 230 is respectively connected to the second output node NEXT of the driving module 10 and the first output node SOUT of the output module 23. The third control unit 230 is used to receive the initial scanning signal Next, the target frequency control signal and the third power signal VGL, and control the output of the second control signal and the third control signal.

[0107] The fourth control unit 240 is connected to the third control unit 230, the first output node SOUT and the second output node NEXT respectively. The fourth control unit 240 is used to receive the second control signal, the third control signal, the initial scan signal Next and the target power signal, and control the gate scan signal OUT output by the first output node SOUT.

[0108] In the first control module 21, the target frequency control signal is the first frequency control signal Ctrl1, and the target power signal is the first power signal VGH1. Specifically, in the first control module 21, the third control unit 231 is connected to the second output node NEXT and the first output node SOUT respectively, and the third control unit 231 is used to receive the initial scan signal Next, the first frequency control signal Ctrl1 and the third power signal VGL, and control the second control signal output by the third control node R3 and the third control signal output by the fourth control node R4; the fourth control unit 241 is connected to the third control node R3, the fourth control node R4, the first output node SOUT and the second output node NEXT respectively, and the fourth control unit 241 is used to receive the second control signal output by the third control node R3, the third control signal output by the fourth control node R4, the initial scan signal Next and the first power signal VGH1, and control the gate scan signal OUT output by the first output node SOUT.

[0109] In the second control module 22, the target frequency control signal is the second frequency control signal Ctrl2, and the target power signal is the second power signal VGH2. Specifically, in the second control module 22, the third control unit 232 is connected to the second output node NEXT and the first output node SOUT respectively, and the third control unit 232 is used to receive the initial scan signal Next, the second frequency control signal Ctrl2 and the third power signal VGL, and control the second control signal output by the fifth control node R5 and the third control signal output by the sixth control node R6; the fourth control unit 242 is connected to the fifth control node R5, the sixth control node R6, the first output node SOUT and the second output node NEXT respectively, and the fourth control unit 242 is used to receive the second control signal output by the fifth control node R5, the third control signal output by the sixth control node R6, the initial scan signal Next and the second power signal VGH2, and control the gate scan signal OUT output by the first output node SOUT.

[0110] In the shift register provided in the embodiment of the present application, the first control module 21 realizes effective control of the gate scan signal OUT outputted from the first output node SOUT according to the first frequency control signal Ctrl1 through the third control unit 231 and the fourth control unit 241, and the second control module 22 realizes effective control of the gate scan signal OUT outputted from the first output node SOUT according to the second frequency control signal Ctrl2 through the third control unit 232 and the fourth control unit 242. In this way, the gate scan signal OUT can be switched between the first power supply signal VGH1 and the second power supply signal VGH2 to compensate for the difference in display brightness, thereby improving display uniformity.

[0111] Please continue reading Fig.10 In some embodiments, the third control unit 230 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is connected to the second output node NEXT and the gate of the seventh transistor T7, respectively. The first electrode of the fifth transistor T5 is connected to the gate of the sixth transistor T6 and the fourth control unit 240, respectively. The first electrode of the fifth transistor T5 is used to output the third control signal. The second electrode of the fifth transistor T5 is used to receive the target frequency control signal. The first electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7. The second electrode of the sixth transistor T6 is connected to the fourth control unit 240. The second electrode of the sixth transistor T6 is used to output the second control signal. The second electrode of the seventh transistor T7 is used to receive the third power supply signal VGL.

[0112] In the first control module 21, the third control unit 231 includes a fifth transistor T5_1, a sixth transistor T6_1 and a seventh transistor T7_1, wherein the gate of the fifth transistor T5_1 is respectively connected to the second output node NEXT and the gate of the seventh transistor T7_1, the first electrode of the fifth transistor T5_1 is respectively connected to the gate of the sixth transistor T6_1 and the fourth control node R4, the first electrode of the fifth transistor T5_1 serves as the fourth control node R4 and is used to output the third control signal, the second electrode of the fifth transistor T5_1 is used to receive the first frequency control signal Ctrl1, the first electrode of the sixth transistor T6_1 is connected to the first electrode of the seventh transistor T7_1, the second electrode of the sixth transistor T6_1 is connected to the fourth control unit 241, the second electrode of the sixth transistor T6_1 serves as the third control node R3 and is used to output the second control signal, and the second electrode of the seventh transistor T7_1 is used to receive the third power supply signal VGL.

[0113] In the second control module 22, the third control unit 232 includes a fifth transistor T5_2, a sixth transistor T6_2 and a seventh transistor T7_2, wherein the gate of the fifth transistor T5_2 is respectively connected to the second output node NEXT and the gate of the seventh transistor T7_2, the first electrode of the fifth transistor T5_2 is respectively connected to the gate of the sixth transistor T6_2 and the sixth control node R6, the first electrode of the fifth transistor T5_2 serves as the sixth control node R6 and is used to output the third control signal, the second electrode of the fifth transistor T5_2 is used to receive the second frequency control signal Ctrl2, the first electrode of the sixth transistor T6_2 is connected to the first electrode of the seventh transistor T7_2, the second electrode of the sixth transistor T6_2 is connected to the fourth control unit 242, the second electrode of the sixth transistor T6_2 serves as the fifth control node R5 and is used to output the second control signal, and the second electrode of the seventh transistor T7_2 is used to receive the third power supply signal VGL.

[0114] In the shift register provided in the embodiment of the present application, the third control unit 230 realizes effective control of the second control signal and the third control signal through the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0115] Please continue reading Fig.10 In some embodiments, the fifth transistor T5 is a P-type transistor, and the sixth transistor T6 and the seventh transistor T7 are respectively N-type transistors. For example, the fifth transistor T5 may be a PTFT or a PMOS, the sixth transistor T6 may be an NTFT or an NMOS, and the seventh transistor T7 may be an NTFT or an NMOS. In this way, when the initial scan signal Next is at a high level, the fifth transistor T5 is turned off and the seventh transistor T7 is turned on. When the initial scan signal Next is at a low level, the fifth transistor T5 is turned on and the seventh transistor T7 is turned off; in this case, when the target frequency control signal is at a low level, the sixth transistor T6 is turned on; when the target frequency control signal is at a high level, the sixth transistor T6 is turned off. Among them, the on-off state of the fifth transistor T5 and the seventh transistor T7 is controlled by the initial scan signal Next, and the on-off state of the sixth transistor T6 is controlled by the target frequency control signal, thereby realizing effective control of the second control signal and the third control signal output by the third control unit 230.

[0116] Please continue reading Fig.10In some embodiments, the fourth control unit 240 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10 and a third capacitor C3; wherein the gate of the eighth transistor T8 is connected to the second output node NEXT; the first electrode of the eighth transistor T8, the second electrode of the ninth transistor T9, the first electrode of the tenth transistor T10, and the first end of the third capacitor C3 are connected, and the first electrode of the eighth transistor T8 is used to receive the target power signal; the second electrode of the eighth transistor T8 is respectively connected to the third control unit 230, the first electrode of the ninth transistor T9 and the gate of the tenth transistor T10; the gate of the ninth transistor T9 is respectively connected to the third control unit 230 and the second end of the third capacitor C3; the second electrode of the tenth transistor T10 is connected to the first output node SOUT.

[0117] In the first control module 21, the fourth control unit 241 includes an eighth transistor T8_1, a ninth transistor T9_1, a tenth transistor T10_1 and a third capacitor C3_1, wherein the gate of the eighth transistor T8_1 is connected to the second output node NEXT; the first electrode of the eighth transistor T8_1, the second electrode of the ninth transistor T9_1, the first electrode of the tenth transistor T10_1, and the first end of the third capacitor C3_1 are connected, and the first electrode of the eighth transistor T8_1 is used to receive the first power supply signal VGH1; the second electrode of the eighth transistor T8_1 is respectively connected to the third control node R3, the first electrode of the ninth transistor T9_1 and the gate of the tenth transistor T10_1; the gate of the ninth transistor T9_1 is respectively connected to the fourth control node R4 and the second end of the third capacitor C3_1; the second electrode of the tenth transistor T10_1 is connected to the first output node SOUT.

[0118] In the second control module 22, the fourth control unit 242 includes an eighth transistor T8_2, a ninth transistor T9_2, a tenth transistor T10_2 and a third capacitor C3_2, wherein the gate of the eighth transistor T8_2 is connected to the second output node NEXT; the first electrode of the eighth transistor T8_2, the second electrode of the ninth transistor T9_2, the first electrode of the tenth transistor T10_2, and the first end of the third capacitor C3_2 are connected, and the first electrode of the eighth transistor T8_2 is used to receive the second power supply signal VGH2; the second electrode of the eighth transistor T8_2 is respectively connected to the fifth control node R5, the first electrode of the ninth transistor T9_2 and the gate of the tenth transistor T10_2; the gate of the ninth transistor T9_2 is respectively connected to the sixth control node R6 and the second end of the third capacitor C3_2; the second electrode of the tenth transistor T10_2 is connected to the first output node SOUT.

[0119] In the shift register provided in the embodiment of the present application, the fourth control unit 240, through the eighth transistor T8, the ninth transistor T9, the tenth transistor T10 and the third capacitor C3, combined with the third control unit 230, realizes effective control of the gate scan signal OUT output from the first output node SOUT to compensate for the difference in display brightness and achieve the purpose of improving display uniformity.

[0120] Please continue reading Fig.10 In some embodiments, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are P-type transistors, respectively. For example, the eighth transistor T8 may be a PTFT or a PMOS, the ninth transistor T9 may be a PTFT or a PMOS, and the tenth transistor T10 may be a PTFT or a PMOS. When the initial scan signal Next is at a high level, the eighth transistor T8 is turned off; when the initial scan signal Next is at a low level, the eighth transistor T8 is turned on. When the second control signal is at a high level, the tenth transistor T10 is turned off; when the second control signal is at a low level, the tenth transistor T10 is turned on. When the third control signal is at a high level, the ninth transistor T9 is turned off; when the third control signal is at a low level, the ninth transistor T9 is turned on. In this case, the fourth control unit 240 controls the first output node SOUT to output the target power supply signal. In this way, the on-off control of the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 is realized through the initial scan signal Next, the second control signal, and the third control signal, thereby realizing the effective control of the gate scan signal OUT by the fourth control unit 240.

[0121] Please continue reading Figures 7 to 10 In some embodiments, the output module 23 includes an eleventh transistor T11, the gate of the eleventh transistor T11 is connected to the third node N3 of the driving module 10, the first electrode of the eleventh transistor T11 is connected to the first output node SOUT, and the second electrode of the eleventh transistor T11 is used to receive the third power signal VGL. In this way, the output module 23 controls the gate scanning signal OUT of the first output node SOUT through the eleventh transistor T11, so that when the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both invalid, the first output node SOUT can output the third power signal VGL to ensure the normal output of the gate scanning signal OUT.

[0122] Please continue reading Figures 7 to 10In some embodiments, the eleventh transistor T11 is a P-type transistor. The eleventh transistor T11 can be a PTFT or a PMOS. In this way, when the third node signal of the third node N3 is at a high level, the eleventh transistor T11 is turned off; when the third node signal is at a low level, the eleventh transistor T11 is turned on. In this case, the output module 23 controls the first output node SOUT to output the third power signal VGL. In this way, the on-off of the eleventh transistor T11 is controlled by the third node signal, and the on-off of the path of the third power signal VGL to the first output node SOUT is effectively controlled, thereby ensuring that the first output node SOUT can effectively output the third power signal VGL.

[0123] Please continue reading Figures 7 to 10 In some embodiments, the output module 23 further includes a fourth capacitor C4, which is connected to the first electrode and the gate of the eleventh transistor T11, respectively. Thus, the stability of the gate scanning signal OUT can be improved by the fourth capacitor C4.

[0124] Fig.11 A schematic diagram of the structure of a driving module 10 provided in an embodiment of the present application. Fig.11 As shown, in some embodiments, the driving module 10 includes an input module 11, a first driving module 12 and a second driving module 13. The input module 11 is used to receive the start signal STV and the first clock signal CK, and control the first node signal of the first node N1 and the fourth node signal of the fourth node N4. The first driving module 12 is used to receive the first node signal, the fourth node signal, the first clock signal CK, the second clock signal XCK, the first power signal VGH1 and the third power signal VGL, and control the second node signal of the second node N2 and the third node signal of the third node N3. The second driving module 13 is used to receive the second node signal, the third node signal, the first power signal VGH1 and the third power signal VGL, and control the second output node NEXT to output the initial scan signal Next.

[0125] Fig.12 A schematic diagram of the structure of a driving module 10 provided in an embodiment of the present application is shown in FIG. Fig.13 This is a schematic diagram of the structure of another driving module 10 provided in an embodiment of the present application. Fig.12 and Fig.13As shown, in some embodiments, the second driving module 13 includes a twelfth transistor T12, a thirteenth transistor T13 and a fifth capacitor C5. The first electrode of the twelfth transistor T12 is used to receive the first power signal VGH1, the first electrode of the twelfth transistor T12 is connected to the first end of the fifth capacitor C5, the second electrode of the twelfth transistor T12 is connected to the first electrode of the thirteenth transistor T13, the second electrode of the twelfth transistor T12 serves as the second output node NEXT, the gate of the twelfth transistor T12 is respectively connected to the second end of the fifth capacitor C5 and the second node N2, the gate of the thirteenth transistor T13 is connected to the third node N3, and the second electrode of the thirteenth transistor T13 is used to receive the third power signal VGL.

[0126] Please continue reading Fig.12 and Fig.13 In some embodiments, the twelfth transistor T12 and the thirteenth transistor T13 are both P-type transistors. For example, the twelfth transistor T12 can be a PTFT or a PMOS; the thirteenth transistor T13 can be a PTFT or a PMOS. When the second node signal is at a high level, the twelfth transistor T12 is turned off; when the second node signal is at a low level, the twelfth transistor T12 is turned on, in which case, the first power signal VGH1 is transmitted to the second output node NEXT through the twelfth transistor T12; when the third node signal is at a high level, the thirteenth transistor T13 is turned off; when the third node signal is at a low level, the thirteenth transistor T13 is turned on, in which case, the third power signal VGL is transmitted to the second output node NEXT through the thirteenth transistor T13.

[0127] In the shift register provided in the embodiment of the present application, the second driving module 13 in the driving module 10 includes a twelfth transistor T12, a thirteenth transistor T13 and a fifth capacitor C5, and the on-off control of the twelfth transistor T12 is realized by the second node signal, and the on-off control of the thirteenth transistor T13 is realized by the third node signal, thereby realizing effective control of the gate scanning signal OUT output by the first output node SOUT; in addition, the fifth capacitor C5 can improve the stability of the gate scanning signal OUT output by the first output node SOUT.

[0128] Please continue reading Fig.12 and Fig.13In some embodiments, the input module 11 includes a fourteenth transistor T14 and a fifteenth transistor T15. The gate of the fourteenth transistor T14 and the gate of the fifteenth transistor T15 are respectively used to receive the first clock signal CK, the first electrode of the fourteenth transistor T14 and the second electrode of the fifteenth transistor T15 are respectively used to receive the start signal STV, the second electrode of the fourteenth transistor T14 is connected to the first node N1, and the first electrode of the fifteenth transistor T15 is connected to the fourth node N4.

[0129] Please continue reading Fig.12 and Fig.13 In some embodiments, the fourteenth transistor T14 and the fifteenth transistor T15 are both P-type transistors. For example, the fourteenth transistor T14 can be a PTFT or a PMOS; the fifteenth transistor T15 can be a PTFT or a PMOS. When the first clock signal CK is at a high level, the fourteenth transistor T14 and the fifteenth transistor T15 are both turned off; when the first clock signal CK is at a low level, the fourteenth transistor T14 and the fifteenth transistor T15 are both turned on. In this case, the start signal STV is transmitted to the first node N1 through the fourteenth transistor T14, and the start signal STV is transmitted to the fourth node through the fifteenth transistor T15.

[0130] In the shift register provided in the embodiment of the present application, the input module 11 in the driving module 10 includes a fourteenth transistor T14 and a fifteenth transistor T15, and the on-off control of the fourteenth transistor T14 and the fifteenth transistor T15 is realized by the first clock signal CK, thereby realizing effective control of outputting the first node signal of the first node N1 and the fourth node outputting the fourth node signal respectively.

[0131] Please continue reading Fig.12 and Fig.13 In some embodiments, the first driving module 12 includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, a sixth capacitor C6 and a seventh capacitor C7.

[0132] A first electrode of the sixteenth transistor T16 is connected to the fifth node N5, a second electrode of the sixteenth transistor T16 is used to receive the third power signal VGL, and a gate of the sixteenth transistor T16 is used to receive the first clock signal CK. A first electrode of the seventeenth transistor T17 is connected to the fifth node N5, a second electrode of the seventeenth transistor T17 is used to receive the first clock signal CK, and a gate of the seventeenth transistor T17 is connected to the first node N1. A first electrode of the eighteenth transistor T18 is connected to the sixth node N6, a second electrode of the eighteenth transistor T18 is connected to the fifth node N5, and a gate of the eighteenth transistor T18 is used to receive the third power signal VGL.

[0133] The first end of the sixth capacitor C6 is connected to the sixth node N6, and the second end of the sixth capacitor C6 is connected to the seventh node N7. The first electrode of the nineteenth transistor T19 is connected to the seventh node N7, the second electrode of the nineteenth transistor T19 is used to receive the second clock signal XCK, and the gate of the nineteenth transistor T19 is connected to the sixth node N6. The first electrode of the twentieth transistor T20 is connected to the seventh node N7, the second electrode of the twentieth transistor T20 is connected to the second node N2, and the gate of the twentieth transistor T20 is used to receive the second clock signal XCK. The first electrode of the twenty-first transistor T21 is connected to the second node N2, the second electrode of the twenty-first transistor T21 is used to receive the first power supply signal VGH1, and the gate of the twenty-first transistor T21 is used to be connected to the first node N1.

[0134] The first electrode of the twenty-second transistor T22 is connected to the first node N1, the second electrode of the twenty-second transistor T22 is connected to the third node N3N3, and the gate of the twenty-second transistor T22 is used to receive the third power signal VGL. The first electrode of the twenty-third transistor T23 is connected to the eighth node N8, the second electrode of the twenty-third transistor T23 is connected to the fourth node N4, and the gate of the twenty-third transistor T23 is used to receive the third power signal VGL. The first electrode of the twenty-fourth transistor T24 is connected to the third node N3, and the second electrode and the gate of the twenty-fourth transistor T24 are respectively connected to the eighth node N8.

[0135] The first end of the seventh capacitor C7 is connected to the eighth node N8, and the second end of the seventh capacitor C7 is connected to the ninth node N9. The first electrode of the twenty-fifth transistor T25 is used to receive the first power signal VGH1, the second electrode of the twenty-fifth transistor T25 is connected to the ninth node N9, and the gate of the twenty-fifth transistor T25 is connected to the fifth node N5. The first electrode of the twenty-sixth transistor T26 is connected to the ninth node N9, the second electrode of the twenty-sixth transistor T26 is used to receive the second clock signal XCK, and the gate of the twenty-sixth transistor T26 is connected to the eighth node N8. The first electrode of the twenty-seventh transistor T27 is connected to the first node N1, the second electrode of the twenty-seventh transistor T27 is used to receive the first power signal VGH1, and the gate of the twenty-seventh transistor T27 is used to receive the reset signal RST.

[0136] Please continue reading Fig.12 and Fig.13 In some embodiments, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26, and the twenty-seventh transistor T27 are all P-type transistors, for example, they can be PTFTs or PMOS; based on this, the transistors T16 to T27 are disconnected in response to a high level and turned on in response to a low level to achieve effective control of the second node signal output from the second node N2 and the third node signal of the third node N3.

[0137] Please continue reading Fig.13 In some embodiments, the seventeenth transistor T17 may be a dual-gate transistor, for example, including a third sub-transistor and a fourth sub-transistor, wherein the gate of the third sub-transistor and the gate of the fourth sub-transistor are respectively connected to the first node N1, the first electrode of the third sub-transistor is connected to the fifth node, the second electrode of the third sub-transistor is connected to the first electrode of the fourth sub-transistor, and the second electrode of the fourth sub-transistor is used to receive the first clock signal CK. In this way, leakage can be prevented, the leakage of the first clock signal CK to the fifth node is reduced, and the stability of the output of the initial scanning signal Next by the driving module 10 is improved.

[0138] Fig.14 A schematic diagram of the structure of a shift register provided in an embodiment of the present application is shown in FIG. Fig.15 A timing diagram of multiple signals in a scenario where a shift register outputs a first power signal VGH1 provided by an embodiment of the present application is shown in FIG. Fig.16 A timing diagram of multiple signals in a scenario where a shift register outputs a third power signal VGL provided by an embodiment of the present application.

[0139] Combination Figures 14 to 16 As shown, in some embodiments, a shift register is provided, and the shift register includes a driving module 10 and a control module 20. The driving module 10 can adopt the above-mentioned embodiments and Fig.13 The control module 20 can adopt the above-mentioned embodiment and Fig. 9 The 9T5C structure provided is a P-type transistor, wherein each transistor is a P-type transistor, "T" represents a transistor, and "C" represents a capacitor. The specific introduction of the driving module 10 and the control module 20 can be found in the relevant content above, which will not be repeated here.

[0140] In the application, the shift register is applied to the pixel circuit connected to the display panel, and the display area corresponding to the pixel circuit is taken as an example to explain as the high-frequency area.

[0141] like Fig.14 and Fig.15 As shown, in the refresh phase of the display panel, the first frequency control signal Ctrl1 is a valid pulse, that is, it maintains a low level state, and the third transistor T18 is normally open; in this case, the second frequency control signal Ctrl2 is an invalid pulse, that is, it is a high level state.

[0142] In the refresh phase T1, the drive module 10 writes the start signal STV, and the third node N3 writes a high level. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned off, the potential of the second node N2 is maintained at VGH1, the twelfth transistor T9 and the fourth transistor T20 are turned off, and the initial scan signal Next and the gate scan signal OUT both maintain the output low level VGL.

[0143] In the refresh phase T2, the second clock signal XCK is converted from a high level to a low level. At this time, the second node N2 and the seventh control node R7 are written with a low level VGL, the twelfth transistor T9 and the fourth transistor T20 are turned on, and the initial scan signal Next and the gate scan signal OUT both output a high level VGH1.

[0144] In the T3 stage of the refresh phase, the first clock signal CK is written to STV at a low level. At this time, the third node N3 is at a low level. VGH1 is written to the second node N2 and the seventh control node R7 through the twenty-first transistor T6. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned on, the twelfth transistor T9 and the fourth transistor T20 are turned off, and the initial scan signal Next and the gate scan signal OUT both output the third power supply signal VGL, which is a low level.

[0145] like Fig.14 and Fig.16As shown, in the maintenance phase of the display panel, the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both invalid pulses, that is, they maintain a high level state, and the third transistor T18 is in a closed state. In the T4 phase of the maintenance phase, since the third transistor T18 is closed, the low level of the second node N2 cannot be transmitted to the seventh control node R7, so at this time the gate scan signal OUT maintains the third power signal VGL, that is, a low level, and cannot output the target power signal, that is, a high level. In this case, the pixel circuit of the display panel is in a maintenance state.

[0146] Fig.17 A schematic diagram of the structure of a shift register provided in this application, Fig.18 A timing diagram of multiple signals in a scenario where a shift register outputs a first power signal VGH1 provided by an embodiment of the present application is shown in FIG. Fig.19 A timing diagram of multiple signals in a scenario where a shift register outputs a third power signal VGHL is provided in an embodiment of the present application.

[0147] Combination Figures 17 to 19 As shown, in some embodiments, a shift register is provided, and the shift register includes a driving module 10 and a control module 20. The driving module 10 adopts the above-mentioned embodiments and Fig.13 The 16T3C structure provided, each transistor is a P-type transistor; the control module 20 adopts the above-mentioned embodiment and Fig.10 The 13T3C structure provided, wherein the fifth transistor T5 and the sixth transistor T6 are N-type transistors, and the other transistors are P-type transistors. The specific introduction of the driving module 10 and the control module 20 can be found in the above related content, which will not be repeated here.

[0148] In the application, the shift register is applied to the pixel circuit connected to the display panel, and the display area corresponding to the pixel circuit is taken as an example to explain as the high-frequency area.

[0149] During the refresh phase of the display panel, the first frequency control signal Ctrl1 is a valid pulse, i.e., maintains a high level state. At this time, the ninth transistor T9 is normally off and the sixth transistor T6 is normally on. In this case, the second frequency control signal Ctrl2 is an invalid pulse, i.e., maintains a low level state.

[0150] like Fig.17 and Fig.18As shown, in the T5 stage of the refresh stage, the driving module 10 writes the start signal STV, and the third node N3 writes a high level. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned off, the second node N2 and the seventh control node R7 and the fifth control node R5 are maintained at a high level state, the twelfth transistor T9 and the tenth transistor T10 are turned off, and the initial scan signal Next and the gate scan signal OUT both maintain the output of the third power supply signal VGL.

[0151] In the T6 stage of the refresh phase, the second clock signal XCK is converted from a high level to a low level. At this time, the second node N2, the seventh control node R7 and the fifth control node R5 are written with a low level VGL, the twelfth transistor T9 and the tenth transistor T10 are turned on, the initial scan signal Next and the gate scan signal OUT both output a high level VGH1, i.e., a high level, and the eighth transistor T8 is turned off, and the ninth transistor T9 is turned on.

[0152] In the T7 stage of the refresh phase, the first clock signal CK is written at a low level. At this time, the third node N3 is at a low level. The high level is written into the second node N2, the seventh control node R7 and the fifth control node R5 through the transistor T6. At this time, the thirteenth transistor T10 and the eleventh transistor T11 are turned on, the twelfth transistor T9 and the tenth transistor T10 are turned off, Next outputs a low level, the fifth transistor T5 is turned off, the eighth transistor T8 is turned on, and the high level is written into the third control node R3 and the fifth control node R5.

[0153] like Fig.17 and Fig.19 As shown, in the maintenance phase of the display panel, the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both invalid pulses, that is, they maintain a low level state, the ninth transistor T9 is turned on, and the sixth transistor T6 is turned off. In the T8 stage of the maintenance phase, since the sixth transistor T6 is turned off, the low level cannot be transmitted to the seventh control node R7 and the fifth control node R5, so at this time, the first output node SOUT outputs the gate scanning signal OUT to maintain a low level and cannot output a high level, and the pixel circuit is in a maintenance state.

[0154] It should be noted that, in the application, the control logic of the shift register outputting the second power signal VGH2 is similar to the control logic of the first power signal VGH1 outputted above. Figures 14 to 19 And related content, and the control module 20 can select the 9T5C structure or the 13T3C structure according to actual needs, and set the level type of the effective pulse of each signal accordingly.

[0155] Based on the same application concept, an embodiment of the present application further provides a gate driving circuit, comprising a plurality of cascaded shift registers as in any of the previous embodiments.

[0156] Fig. 20 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application. Fig. 20 As shown, in the gate driving circuit 30, the driving module 10 in the first-stage shift register 301 is used to receive the start signal STV, the driving module 10 of the i-th stage shift register 301 is connected to the driving module 10 of the i-1-th stage shift register 301, and the driving module 10 of the i-th stage shift register 301 is used to receive the initial scanning signal Next output by the driving module 10 of the i-1-th stage shift register 301, and the initial scanning signal Next output by the driving module 10 of the i-th stage shift register 301 is used as the start signal STV of the driving module 10 of the i-1-th stage shift register 301. The driving module 10 in each stage shift register 301 can also receive the first clock signal CK, the second clock signal XCK, the first power signal VGH1 and the third power signal VGL respectively, so as to output the initial scanning signal Next in sequence. Among them, the specific structure of the shift register 301 can be referred to the above introduction, which will not be repeated here.

[0157] The gate drive circuit 30 provided in the embodiment of the present application includes a plurality of cascaded shift registers 301, which can provide a plurality of stage-by-stage gate drive signals; wherein the shift register 301 can select to output the first power supply signal VGH1 or the second power supply signal VGH2 as the gate scan signal OUT by controlling the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2, specifically, by controlling the initial scan signal Next and the first frequency control signal Ctrl1 to be valid and the second frequency control signal Ctrl2 to be invalid, so that the shift register 301 outputs the first power supply signal VGH1 as the gate scan signal OUT, and controls the first frequency control signal Ctrl1 to be invalid and the initial scan signal Next to be invalid. and the second frequency control signal Ctrl2 are both valid, so that the shift register 301 outputs the second power supply signal VGH2 as the gate scan signal OUT, so that the same shift register 301 can provide different power supply signals as the gate scan signal OUT for different refresh frequencies or different display modes, and different shift registers 301 can provide different power supply signals as the gate scan signal OUT, that is, through the gate scan signal OUT with different potentials, the characteristic drift difference of the transistor in the zoned frequency-departure display scenario is compensated, and then the display brightness difference between different display areas in the zoned frequency-departure scenario can be compensated, so that the display brightness of different display areas is balanced, thereby achieving the purpose of improving display uniformity.

[0158] Based on the same application concept, an embodiment of the present application provides a display panel, including at least a gate driving circuit and a pixel circuit as in any of the previous embodiments, and the gate driving circuit is connected to the pixel circuit.

[0159] In some embodiments, the display panel includes a first display area and a second display area, and the refresh frequency of the first display area is different from the refresh frequency of the second display area, wherein the shift register connected to the pixel circuit of the first display area outputs a first power signal VGH1 as a gate scan signal OUT, and the shift register connected to the pixel circuit of the second display area outputs a second power signal VGH2 as a gate scan signal OUT. For example, the refresh frequency of the first display area is greater than the refresh frequency of the second display area, and correspondingly, the first power signal VGH1 is greater than the second power signal VGH2. In this way, by providing gate scan signals OUT of different potentials to different display areas, the display brightness differences of different display areas are compensated to balance the overall display brightness of the display panel and improve display uniformity.

[0160] In some embodiments, the pixel circuits are arranged in an array, and each shift register in the gate drive circuit is connected to at least one row of pixel circuits. For example, each shift register in the gate drive circuit is connected to a row of pixel circuits, that is, a one-drive-one connection method is adopted. For another example, each shift register in the gate drive circuit is connected to two rows of pixel circuits, that is, a one-drive-two connection method is adopted. It should be noted that this is only an exemplary description, and the connection method between the shift register and the pixel circuit can be set according to the needs in actual applications without making too many restrictions.

[0161] In some embodiments, each shift register in the gate drive circuit is connected to the gate reset transistor M4 in the pixel circuit to provide the first scan signal S1N for the gate reset transistor M4. In other embodiments, each shift register in the gate drive circuit is connected to the threshold compensation transistor M5 in the pixel circuit to provide the second scan signal S2N for the threshold compensation transistor M5. In another embodiment, in the gate drive circuit, at least part of the shift registers are connected to the gate reset transistor M4 of the pixel circuit to provide the first scan signal S1N for the gate reset transistor M4; and at least part of the shift registers are connected to the threshold compensation transistor M5 of the pixel circuit to provide the second scan signal S2N for the threshold compensation transistor M5. It should be noted that in the application, the connection relationship between the shift register and the transistor in the pixel circuit can be set according to the needs, and it is not limited too much here.

[0162] Fig.21 A schematic diagram of a gate drive circuit provided in an embodiment of the present application is shown in FIG. Fig. 22 A schematic diagram of the structure of a pixel circuit 40 and a light emitting element D provided in an embodiment of the present application. Fig.21 and Fig. 22As shown, in some embodiments, the display panel includes a first gate driving circuit 31, a second gate driving circuit 32 and a pixel circuit 40, wherein the pixel circuit 40 is arranged in an array.

[0163] In the first gate driving circuit 31, the i-th stage shift register 311 is connected to the gate reset transistors M4 of the pixel circuits 40 in the 2i-1th row and the 2ith row, respectively, and the gate scanning signal OUT output by the shift register 311 in the first gate driving circuit 31 is used as the first scanning signal S1N of the gate reset transistor M4. i is a positive integer. The start signal received by the first stage shift register 311 is STV1.

[0164] In the second gate driving circuit 32, the j-th shift register 321 is respectively connected to the threshold compensation transistors M5 of the pixel circuits 40 in the 2j-1th row and the 2jth row, and the gate scanning signal OUT output by the shift register 321 in the second gate driving circuit 32 is used as the second scanning signal S2N of the gate reset transistor M4. j is a positive integer. Among them, the start signal received by the first-stage shift register 321 is STV2.

[0165] The first gate driving circuit 31 and the second gate driving circuit 32 can be the gate driving circuits in any of the aforementioned embodiments respectively, and the structure of each shift register in the first gate driving circuit 31 and the second gate driving circuit 32 is the shift register in any of the aforementioned embodiments. For details, please refer to the previous introduction and will not be repeated here.

[0166] It should be noted that the above is explained using the example of a shift register connecting two rows of pixel circuits 40, that is, a one-drive-two method. Other driving methods can also be used in the application. For example, a shift register is connected to a row of pixel circuits 40, that is, one-drive-one, one-drive-three, and other methods. No excessive limitations are made here.

[0167] like Fig. 22 As shown, in some embodiments, the pixel circuit 40 includes a driving transistor M0, a data writing transistor M1, a first light emission control transistor M2, a second light emission control transistor M3, a gate reset transistor M4, a threshold compensation transistor M5, an anode reset transistor M6 and a storage capacitor Cst.

[0168] The gate of the driving transistor M0 is respectively connected to the first end of the storage capacitor Cst, the second electrode of the gate reset transistor M4, and the first electrode of the threshold compensation transistor M5. The first electrode of the driving transistor M0 is respectively connected to the first electrode of the data write transistor M1 and the second electrode of the first light-emitting control transistor M2. The second electrode of the driving transistor M0 is respectively connected to the second electrode of the threshold compensation transistor M5 and the first electrode of the second light-emitting control transistor M3. The driving transistor M0 is used to control the driving current.

[0169] The gate of the data writing transistor M1 is used to receive the data writing control signal SP, the second electrode of the data writing transistor M1 is used to receive the data signal VData, and the data writing transistor M1 is used to write the data signal VData to the gate of the driving transistor M0 under the action of the data writing control signal SP.

[0170] The gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor M3 are respectively used to receive the light-emitting control signal Emit, the first electrode of the first light-emitting control transistor M2 is used to receive the fourth power supply signal PVDD, and the first light-emitting control transistor M2 is used to control the light-emitting element D to emit light. The second electrode of the second light-emitting control transistor M3 is respectively connected to the second electrode of the anode reset transistor M6 and the anode of the light-emitting element D, and the second light-emitting control transistor M3 is used to control the light-emitting element D to emit light.

[0171] The gate of the gate reset transistor M4 is used to receive the first scanning signal S1N, the first electrode of the gate reset transistor M4 is used to receive the first initialization signal Vref1, and the gate reset transistor M4 is used to reset the gate of the driving transistor M0. The gate of the threshold compensation transistor M5 is used to receive the second scanning signal S2N, and the threshold compensation transistor M5 is used to compensate the threshold voltage of the driving transistor M0. The gate of the anode reset transistor M6 is used to receive the anode reset control signal SP*, the first electrode of the anode reset transistor M6 is used to receive the second initialization signal Vref2, and the anode reset transistor M6 is used to reset the anode of the light emitting element D.

[0172] In some embodiments, the gate reset transistor M4 and the threshold compensation transistor M5 may be N-type transistors, for example, NTFT or NMOS; the driving transistor M0, the data writing transistor M1, the first light emission control transistor M2, the second light emission control transistor M3 and the anode reset transistor M6 may all be P-type transistors, for example, PTFT or PMOS. In other embodiments, each transistor M1 to M6 in the pixel circuit 40 may all be P-type transistors, for example, PTFT or PMOS.

[0173] It should be noted that the above description is made by taking the pixel circuit 40 including 7T1C as an example. In application, the pixel circuit 40 may also adopt any other suitable structure, for example, 7T2C, 8T1C, 8T2C, 9T1C, etc., which is not limited too much here.

[0174] Please continue reading Fig. 22In some embodiments, the pixel circuit 40 may further include a bias transistor M7, the gate of the bias transistor M7 is used to receive a bias control signal SP*, the first electrode of the bias transistor M7 is respectively connected to the first electrode of the driving transistor M0, the second electrode of the first light-emitting control transistor M2, and the first electrode of the data writing transistor M1, the second electrode of the bias transistor M7 is used to receive a bias signal DVH, and the bias transistor M7 is used to bias the driving transistor M0. The bias control signal SP* and the anode reset control signal SP* may be the same or different. That is, the pixel circuit 40 adopts an 8T1C structure, and the bias adjustment of the driving transistor M0 is implemented by the bias transistor M7, which helps to improve the display performance of the display panel. Exemplarily, the bias transistor M7 may be a P-type transistor, such as a PMOS or a PTFT.

[0175] In each embodiment of the present application, the N-type transistor may be an oxide transistor, for example, the oxide may be IGZO (Indium Gallium Zinc Oxide); the P-type transistor may be a low temperature polycrystalline silicon (Low Temperature Polycrystalline Silicon, LTPS) transistor.

[0176] Fig.23 A schematic diagram of a process flow of a display panel driving method provided in an embodiment of the present application is provided. Fig.24 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Fig.23 and Fig.24 As shown, based on the same application concept, the embodiment of the present application also provides a method for driving a display panel, which can be a display panel provided by any of the above embodiments. The display panel includes a gate drive circuit and a pixel circuit, and the specific introduction can be referred to the relevant content above, which will not be repeated here.

[0177] The method for driving the display panel includes the following steps S2302 and S2304.

[0178] S2302: drive the pixel circuit of the first display area by controlling part of the shift registers in the gate driving circuit to output the first power signal VGH1, so as to drive the first display area to display at a first frequency.

[0179] S2304: driving the pixel circuit of the second display area by controlling the remaining shift registers in the gate drive circuit to output the second power signal VGH2, so as to drive the second display area to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power signal VGH1 is different from the second power signal VGH2.

[0180] It can be understood that the display panel includes a first display area 51 and a second display area 52. The refresh frequencies of the first display area 51 and the second display area 52 can be different, that is, the scene is displayed in different areas and at different frequencies. The refresh frequencies of the first display area 51 and the second display area 52 can be the same, that is, the scene is displayed at the same frequency on the entire screen.

[0181] The pixel circuits of the first display area 51 are connected to a part of the shift registers in the gate driving circuit, and the pixel circuits of the second display area 52 are connected to the remaining part of the shift registers in the gate driving circuit.

[0182] In an application, the first display area 51 can be driven to display at a first frequency by controlling the shift register corresponding to the first display area 51 to output the first power signal VGH1, wherein the initial scan signal Next and the first frequency control signal Ctrl1 are controlled to be valid, and the second frequency control signal Ctrl2 is controlled to be invalid, thereby controlling the shift register to output the first power signal VGH1.

[0183] Furthermore, the second display area 52 can be driven to display at the second frequency by controlling the shift register corresponding to the second display area 52 to output the second power supply signal VGH2, thereby realizing zoned and frequency-controlled display; wherein, the first frequency control signal Ctrl1 is controlled to be invalid, and the initial scanning signal Next and the second frequency control signal Ctrl2 are valid, thereby controlling the shift register to output the second power supply signal VGH2.

[0184] In addition, the first display area 51 and the second display area 52 can be driven to display at the first frequency by controlling the shift registers corresponding to the first display area 51 and the second display area 52 to output the first power supply signal VGH1; the first display area 51 and the second display area 52 can be driven to display at the second frequency by controlling the shift registers corresponding to the first display area 51 and the second display area 52 to output the second power supply signal VGH2, thereby realizing the same-frequency display of the entire screen.

[0185] Fig.25 A timing diagram of multiple signals provided in an embodiment of the present application. Fig.25As shown, the display panel includes a refresh frame and a maintenance frame. Take the second display area 52 of the display panel, i.e., the low-frequency area, as an example, wherein the second display area 52 includes pixel circuits from the 1st row to the nth row, wherein n is a positive integer. In the refresh frame, by controlling the shift register of the second display area 52, the initial scan signal Next and the second frequency control signal Ctrl2 are both valid, and the first frequency control signal Ctrl1 is invalid, i.e., the initial scan signal Next and the first frequency control signal Ctrl1 are high level, and the second frequency control signal Ctrl2 is low level, so that the shift register of the second display area 52 outputs the second power signal VGH2; in the maintenance frame, by controlling the shift register of the second display area 52, the second frequency control signal Ctrl2 and the first frequency control signal Ctrl1 are both invalid, i.e., the first frequency control signal Ctrl1 and the second frequency control signal Ctrl2 are both high level, so that the shift register of the second display area 52 outputs the third power signal VGL.

[0186] It should be noted that the first display area 51 outputs the first power signal VGH1 in the refresh frame and outputs the third power signal VGL in the sustain frame, which is similar to the first display area 51 outputting the second power signal VGH2 and the third power signal VGL, and will not be repeated here.

[0187] The driving method of the display panel provided in the embodiment of the present application drives the pixel circuit of the first display area 51 by controlling part of the shift registers in the gate driving circuit to output the first power signal VGH1, so as to drive the first display area 51 to display at a first frequency; and drives the pixel circuit of the second display area 52 by controlling the remaining part of the shift registers in the gate driving circuit to output the second power signal VGH2, so as to drive the second display area 52 to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power signal VGH1 is different from the second power signal VGH2, so that different display areas are driven by different power signals, and the characteristic drift difference of the transistor in the partitioned frequency-frequency display scenario is compensated, and then the display brightness difference between different display areas in the partitioned frequency-frequency display scenario can be compensated, so that the display brightness of different display areas is balanced, and the display uniformity is improved.

[0188] In some embodiments, the first frequency is greater than the second frequency, and the first power signal VGH1 is greater than the second power signal VGH2. It can be understood that the display area that displays at a higher frequency such as the first frequency is more likely to have a characteristic drift in the transistors in the pixel circuit compared to the display area that displays at a lower frequency such as the second frequency, resulting in differences in display brightness in different display areas. In this regard, the embodiment of the present application provides a larger power signal for the display area that displays at a higher frequency to drive the pixel circuit to provide a larger driving current, thereby compensating for the brightness reduction caused by the transistor characteristic drift, thereby balancing the brightness difference between display areas of different frequencies and improving display uniformity.

[0189] In some embodiments, the first frequency is greater than the second frequency; accordingly, the first power signal VGH1 is less than the second power signal VGH2. In this way, a smaller power signal can be provided to the display area with a higher frequency to drive the pixel circuit to provide a smaller driving current, thereby compensating for the increase in brightness caused by the drift of transistor characteristics, thereby balancing the brightness difference between display areas with different frequencies and improving display uniformity.

[0190] It should be noted that the magnitude correspondence between the first frequency and the second frequency, and between the first power signal VGH1 and the second power signal VGH2 can be determined according to the display brightness difference of actual products.

[0191] In some embodiments, the method further includes: obtaining the cumulative duration of the first display area 51 displaying at the first frequency, and adjusting the first power signal VGH1 according to the cumulative duration. The cumulative duration refers to the cumulative duration of the first display area 51 displaying at the first frequency. In this way, the first power signal VGH1 can be dynamically adjusted according to the brightness difference between the first display area 51 and the second display area 52, thereby achieving dynamic compensation for the brightness difference between different display areas, which helps to further improve the display uniformity.

[0192] For example, Fig.26 As shown, the step of adjusting the first power signal VGH1 according to the accumulated time may include: a step of linearly increasing the first power signal VGH1 according to the accumulated time. The linear relationship between the voltage value of the first power signal VGH1 and the accumulated time can be set accordingly according to the brightness difference between the first display area 51 and the second display area 52, which can be obtained through experiments or simulations in applications and is not limited too much here.

[0193] Another exemplary example is Fig. 27As shown, the step of adjusting the first power signal VGH1 according to the accumulated time may include: increasing the first power signal VGH1 according to a preset step length according to the accumulated time length. The preset step length refers to the voltage difference before and after the adjustment of the first power signal VGH1. The preset step length is pre-set and can be obtained according to experiments or simulations, and is not limited too much here.

[0194] It should be noted that, in application, the first power signal VGH1 may be adjusted linearly or in a stepwise manner, or in other suitable manners, for example, adjusting the first power signal VGH1 according to the accumulated time and a preset mapping table.

[0195] In one embodiment, a method for driving a display panel is provided. Fig.24 Taking the display panel shown as an example, the method may include: driving the pixel circuit of the first display area by controlling part of the shift registers in the gate drive circuit to output the first power signal VGH1, so as to drive the first display area to display at a first frequency; driving the pixel circuit of the second display area by controlling the remaining part of the shift registers in the gate drive circuit to output the second power signal VGH2, so as to drive the second display area to display at a second frequency; obtaining the cumulative time duration of the first display area displaying at the first frequency, and linearly increasing the first power signal VGH1 according to the cumulative time duration.

[0196] For the low frequency area, i.e., the second display area, the shift register outputs the second power signal VGH2 to the pixel circuit corresponding to the second display area, thereby driving the second display area to display at the second frequency; for the high frequency area, i.e., the first display area, the shift register outputs the first power signal VGH1 to the pixel circuit corresponding to the first display area, thereby driving the first display area to display at the first frequency. For example, when the brightness of the high frequency area is low, the first power signal VGH1 can be adjusted so that the first power signal VGH1 is greater than the second power signal VGH2, i.e., VGH1>VGH2, thereby increasing the brightness of the high frequency area; conversely, if the brightness of the high frequency area is high, the first power signal VGH1 can be adjusted so that the first power signal VGH1 is less than the second power signal VGH2, i.e., VGH1>VGH2. <VGH2。

[0197] Based on the same application concept, an embodiment of the present application also provides a display device. Fig.28 A schematic diagram of the structure of a display device 70 provided in an embodiment of the present application is shown in FIG. Fig.28 As shown, the display device 70 includes the display panel 60 in any of the above embodiments. Fig.28As shown, the display device 70 includes a display panel 60. Therefore, the display device 70 also has the beneficial effects of the display panel 60 in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel 60, which will not be repeated below.

[0198] The display device 70 provided in the embodiment of the present application can be Fig.28 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0199] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0200] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A shift register, characterized in that: include: A driving module, used for outputting an initial scanning signal; a control module connected to the driving module, and configured to receive at least the initial scanning signal, the first power signal, the second power signal, the third power signal, the first frequency control signal, and the second frequency control signal; the first power signal, the second power signal, and the third power signal are different from each other; The control module is also used to output the first power supply signal as a gate scan signal when the initial scan signal and the first frequency control signal are both valid and the second frequency control signal is invalid; or to output the second power supply signal as a gate scan signal when the first frequency control signal is invalid and the initial scan signal and the second frequency control signal are both valid.

2. The shift register according to claim 1, characterized in that: The control module is further configured to output the third power supply signal as a gate scanning signal when both the first frequency control signal and the second frequency control signal are invalid.

3. The shift register according to claim 1 or 2, characterized in that: The control module includes a first control module, a second control module and an output module; The first control module is connected to the driving module and the output module respectively, and is used to receive at least the initial scanning signal, the first power signal, the third power signal and the first frequency control signal, and control the gate scanning signal output by the first output node of the output module; The second control module is connected to the driving module and the output module respectively, and is used to receive at least the second power supply signal, the third power supply signal and the second frequency control signal, and control the gate scanning signal output by the first output node; The output module is connected to the driving module, and is used to at least receive the third power supply signal and control the gate scanning signal output by the first output node.

4. The shift register according to claim 3, characterized in that: The first control module and the second control module both include a first control unit and a second control unit; wherein, The first control unit is connected to the target node of the driving module, and is used to receive the target node signal, the target frequency control signal and the third power supply signal of the target node, and control the output of the first control signal; The second control unit is respectively connected to the first control unit, the first output node, the first node of the driving module and the second node of the driving module, and the second control unit is used to receive the first control signal, the first node signal of the first node, the second node signal of the second node and the target power signal, and control the gate scanning signal output by the first output node; wherein, In the first control module, the target node is the second output node of the driving module, the target node signal is the initial scanning signal, the target frequency control signal is the first frequency control signal, and the target power signal is the first power signal; In the second control module, the target node is the first node, the target node signal is the first node signal, the target frequency control signal is the second frequency control signal, and the target power signal is the second power signal.

5. The shift register according to claim 4, characterized in that: The first control unit includes a first transistor and a first capacitor; the gate of the first transistor is connected to the target node; the first electrode of the first transistor is respectively connected to the second control unit and the first end of the first capacitor, and the first electrode of the first transistor is used to output the first control signal; the second electrode of the first transistor is used to receive the target frequency control signal; the second end of the first capacitor is used to receive the third power supply signal.

6. The shift register according to claim 5, characterized in that: The first transistor comprises a double-gate transistor; the first transistor is a P-type transistor.

7. The shift register according to claim 4, characterized in that: The second control unit includes a second transistor, a third transistor and a fourth transistor; the gate of the second transistor is connected to the first control unit, the first electrode of the second transistor is connected to the second node, the second electrode of the second transistor is respectively connected to the second electrode of the third transistor and the gate of the fourth transistor, the gate of the third transistor is connected to the first node, the first electrode of the third transistor and the first electrode of the fourth transistor are respectively used to receive the target power supply signal, and the second electrode of the fourth transistor is connected to the first output node.

8. The shift register according to claim 7, characterized in that: The second control unit also includes a second capacitor, and the second capacitor is connected to the first electrode and the gate of the fourth transistor respectively.

9. The shift register according to claim 8, characterized in that: The second transistor, the third transistor and the fourth transistor are P-type transistors respectively.

10. The shift register according to claim 3, characterized in that: The first control module and the second control module both include a third control unit and a fourth control unit; wherein, The third control unit is connected to the second output node and the first output node of the driving module respectively, and is used to receive the initial scanning signal, the target frequency control signal and the third power supply signal, and control the output of the second control signal and the third control signal; The fourth control unit is connected to the third control unit, the first output node and the second output node respectively, and the fourth control unit is used to receive the second control signal, the third control signal, the initial scan signal and the target power signal, and control the gate scan signal output by the first output node; wherein, In the first control module, the target frequency control signal is the first frequency control signal, and the target power signal is the first power signal; In the second control module, the target frequency control signal is the second frequency control signal, and the target power signal is the second power signal.

11. The shift register according to claim 10, characterized in that: The third control unit includes a fifth transistor, a sixth transistor and a seventh transistor; the gate of the fifth transistor is respectively connected to the second output node and the gate of the seventh transistor, the first electrode of the fifth transistor is respectively connected to the gate of the sixth transistor and the fourth control unit, the first electrode of the fifth transistor is used to output the third control signal, the second electrode of the fifth transistor is used to receive the target frequency control signal, the first electrode of the sixth transistor is connected to the first electrode of the seventh transistor, the second electrode of the sixth transistor is connected to the fourth control unit, the second electrode of the sixth transistor is used to output the second control signal, and the second electrode of the seventh transistor is used to receive the third power supply signal.

12. The shift register according to claim 11, characterized in that: The fifth transistor is a P-type transistor, and the sixth transistor and the seventh transistor are N-type transistors respectively.

13. The shift register according to claim 10, characterized in that: The fourth control unit includes an eighth transistor, a ninth transistor, a tenth transistor and a third capacitor; wherein the gate of the eighth transistor is connected to the second output node; the first electrode of the eighth transistor, the second electrode of the ninth transistor, the first electrode of the tenth transistor, and the first end of the third capacitor are connected, and the first electrode of the eighth transistor is used to receive the target power supply signal; the second electrodes of the eight transistors are respectively connected to the third control unit, the first electrode of the ninth transistor and the gate of the tenth transistor; the gate of the ninth transistor is respectively connected to the third control unit and the second end of the third capacitor; the second electrode of the tenth transistor is connected to the first output node.

14. The shift register according to claim 13, characterized in that: The eighth transistor, the ninth transistor, and the tenth transistor are P-type transistors respectively.

15. The shift register according to claim 3, characterized in that: The output module includes an eleventh transistor, a gate of the eleventh transistor is connected to the third node of the driving module, a first electrode of the eleventh transistor is connected to the first output node, and a second electrode of the eleventh transistor is used to receive the third power supply signal.

16. The shift register according to claim 15, characterized in that: The output module further includes a fourth capacitor, and the fourth capacitor is respectively connected to the first electrode and the gate of the eleventh transistor.

17. A gate drive circuit, characterized in that: A shift register comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 16.

18. A display panel, characterized in that: The method comprises at least one gate driving circuit and a pixel circuit as claimed in claim 17, wherein the gate driving circuit is connected to the pixel circuit.

19. A method for driving a display panel, characterized in that: Applied to the display panel as claimed in claim 18, the display panel comprises a first display area and a second display area, the method comprising: By controlling part of the shift registers in the gate driving circuit to output a first power supply signal, the pixel circuit of the first display area is driven to drive the first display area to display at a first frequency; The remaining shift registers in the gate drive circuit are controlled to output a second power supply signal to drive the pixel circuit of the second display area to drive the second display area to display at a second frequency; wherein the first frequency is different from the second frequency, and the first power supply signal is different from the second power supply signal.

20. The method according to claim 19, characterized in that The first frequency is greater than the second frequency, and the first power signal is greater than the second power signal.

21. The method according to claim 20, characterized in that The method further comprises: Obtaining a cumulative duration of displaying the first display area at the first frequency; The first power signal is adjusted according to the accumulated time.

22. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

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