Semiconductor memory device with stacked chip structure

Abstract

A semiconductor memory device may include: a first chip including a first array matrix and a second array matrix adjacent to each other and including memory cells; and a second chip under the first chip and including a sense amplifier configured to drive the memory cells, where the first cell bit lines are located in a first array matrix and the second cell bit lines are located in a second array matrix, where the first bit lines and the first complementary bit lines are located under the first array matrix and where the second bit lines and the second complementary bit lines are located under the second array matrix. The first bit line and the second complementary bit line are located below the first array matrix, and the second bit line and the second complementary bit line are located below the second array matrix, and wherein the first bit line and the second bit line are connected to the first cell bit line and the second cell bit line, respectively, and the first complementary bit line and the second complementary bit line are connected to the second cell bit line and the first cell bit line, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0145526 filed in the Korean Intellectual Property Office on October 27, 2023, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor memory device. More particularly, the present disclosure relates to a semiconductor memory device having a structure in which a memory cell array and a bit line sense amplifier (BLSA; hereinafter also referred to as a sense amplifier) ​​are located on different wafers and vertically overlapped. Background Art

[0004] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when the power is cut off, while non-volatile memory devices retain stored data even when the power is cut off. Volatile memory devices include DRAM, FRAM, etc.

[0005] In order to increase the integration degree of semiconductor memory devices, various cell structures are being developed, and a structure is being developed in which a memory cell array and a sense amplifier detecting data stored in the memory cell are formed on different chips and arranged to vertically overlap each other. Summary of the invention

[0006] Some example embodiments provide a semiconductor memory device having a stacked chip structure in which wirings are efficiently arranged.

[0007] Some example embodiments reduce coupling between a bit line and a complementary bit line in a semiconductor memory device having a stacked chip structure.

[0008] According to an example embodiment, a semiconductor memory device includes: a first chip including a first array matrix and a second array matrix adjacent to each other, the first array matrix and the second array matrix each including a plurality of memory cells; and a second chip located below the first chip, the second chip including a plurality of sense amplifiers configured to drive the memory cells of the first array matrix and the second array matrix. A plurality of first cell bit lines are located in the first array matrix, a plurality of second cell bit lines are located in the second array matrix, a plurality of first bit lines and a plurality of first complementary bit lines are located below the first array matrix, and a plurality of second bit lines and a plurality of second complementary bit lines are located below the second array matrix. Each of the first bit lines is connected to one of the first cell bit lines, each of the first complementary bit lines is connected to one of the second cell bit lines, each of the second bit lines is connected to one of the second cell bit lines, and each of the second complementary bit lines is connected to one of the first cell bit lines, and the sense amplifier includes a plurality of first sense amplifiers and a plurality of second sense amplifiers, at least a portion of the plurality of first sense amplifiers is located below the first array matrix, and at least a portion of the plurality of second sense amplifiers is located below the second array matrix. One of the paired first bit lines and a corresponding one of the first complementary bit lines are connected to a corresponding one of the first sense amplifiers, and one of the paired second bit lines and a corresponding one of the second complementary bit lines are connected to a corresponding one of the second sense amplifiers.

[0009] According to an example embodiment, a semiconductor memory device includes: a first chip including an array matrix including a plurality of memory cells; and a second chip including a plurality of sense amplifiers located below the first chip and configured to drive the memory cells of the array matrix. A plurality of cell bit lines are located in the array matrix, a plurality of bit lines and a plurality of complementary bit lines are located below the array matrix, one of the paired bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers, and at least one of a shield line, a second one of the bit lines, and a second one of the complementary bit lines is located between one of the paired bit lines and a corresponding one of the complementary bit lines commonly connected to a corresponding one of the sense amplifiers.

[0010] According to an example embodiment, a semiconductor memory device includes: a first chip including an array matrix including a plurality of memory cells; and a second chip including a plurality of sense amplifiers located below the first chip and configured to drive the memory cells of the array matrix. A plurality of cell bit lines are located in the array matrix, a plurality of bit lines and a plurality of complementary bit lines are located below the array matrix, and one of the paired bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers. The second chip includes a plurality of lower bonding pads connecting the bit lines and the complementary bit lines to the sense amplifiers, a plurality of first connection layers, and a plurality of second connection layers. One of the first connection layers is connected to a first input terminal of a corresponding one of the sense amplifiers, and a corresponding one of the second connection layers is connected to a second input terminal of the corresponding one of the sense amplifiers, each of the first connection layers is connected to a corresponding one of the lower bonding pads, and each of the second connection layers is connected to a corresponding one of the lower bonding pads.

[0011] According to example embodiments, by efficiently arranging wirings connecting memory cells and sense amplifiers, the length of the wirings may be reduced.

[0012] According to example embodiments, coupling between a bit line and a complementary bit line may be reduced by providing a wiring connecting other bit lines or complementary bit lines to a sense amplifier between wiring connecting the bit line and the complementary bit line to the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a layout diagram of a semiconductor memory device according to example embodiments.

[0014] Figure 2 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BLB1.

[0015] Figure 3 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BL1.

[0016] Figure 4 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BL3.

[0017] Figure 5 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BLB3.

[0018] Figure 6 yes Figure 1 An enlarged layout diagram of portion A1.

[0019] Figure 7 is along Figure 6 A cross-sectional view taken along line AA'.

[0020] Figure 8 It shows that Figure 6 Layout diagram of the connection of wiring centered on the bonding pad for different aspect ratios of section A2.

[0021] Fig. 9 is a schematic diagram illustrating connections between sense amplifiers and bonding pads on a peripheral circuit chip in a semiconductor memory device according to example embodiments.

[0022] Fig.10 is a schematic diagram illustrating connections between sense amplifiers and bonding pads on a peripheral circuit chip in a semiconductor memory device according to another example embodiment. DETAILED DESCRIPTION

[0023] The present disclosure will be described more fully below with reference to the accompanying drawings, in which some example embodiments of the present disclosure are shown. As will be appreciated by those skilled in the art, the described example embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0024] The drawings and descriptions described herein should be considered in a descriptive sense only and not for a limiting purpose.Throughout the specification, like reference numerals designate like constituent elements.

[0025] In the drawings, for better understanding and ease of description, the size and thickness of each component element may be arbitrarily shown, and the present disclosure is not necessarily limited to the contents shown in the drawings. In the drawings, for the sake of clarity, the thickness of layers, films, plates, panels, regions, areas, etc. may be exaggerated. In the drawings, for better understanding and ease of description, the thickness of some layers, regions and areas may be exaggerated.

[0026] As used herein, singular forms (eg, a, an, and the) are intended to include the plural forms as well (and vice versa), unless the context clearly indicates otherwise.

[0027] For the purpose of its meaning and interpretation, in the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B".

[0028] For the purpose of its meaning and interpretation, in the specification and claims, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0029] Terms such as first, second, etc. will only be used to describe various components and will not be interpreted as limiting these components. The terms are only used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form.

[0030] When an element such as a layer, film, region, area or substrate is described as being "over" another element, it can be directly over the other element or there can be intervening elements. Conversely, when a first element is described as being "directly over" a second element, there are no intervening elements. Throughout the specification, the term "over a target element" must be understood as being disposed above or below the target element, and does not necessarily mean "over" in the opposite direction relative to gravity.

[0031] For example, the spatially relative terms "below" or "above" may be used to facilitate description of the relationship of one element or component shown in the drawings to other components. Spatially relative terms are intended to include other directions of use or operation in addition to the directions shown in the drawings. For example, when the devices shown in the drawings are turned over, a device disposed below another device may be disposed "above" the other device. Thus, the example term "below" may include a lower position and an upper position. Devices may also be oriented in other directions, so spatially relative terms may be analyzed differently depending on the direction.

[0032] When it is described in the specification that an element (or region, area, layer, part, etc.) is “connected” or “combined” to another element, it may be directly disposed, connected or combined on the other element, or an element may be disposed between them.

[0033] The term "connected to" or "combined to" may include a physical connection or an electrical connection or combination.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined herein, terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with the meaning in the context of the relevant art, and will not be understood as an idealized or overly formal meaning.

[0035] Figure 1 is a layout diagram of a semiconductor memory device according to example embodiments. Figure 2 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BLB1. Figure 3is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BL1. Figure 4 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BL3. Figure 5 is shown with the sense amplifier Figure 1 A cross-sectional view of the connection between BLB3.

[0036] Reference Figure 1 , the semiconductor memory device may include a plurality of array matrices AM1, AM2, and AM3 each including a plurality of memory cells. Each of the plurality of array matrices AM1, AM2, and AM3 may include a plurality of cell bit lines GBL and a plurality of word lines, and the memory cells may be arranged in an area where the plurality of cell bit lines GBL and the plurality of word lines intersect. Here, the plurality of memory cells may be volatile memory cells such as DRAM, resistive memory cells such as phase change RAM (PRAM) and resistive RAM (RRAM), or may be nano floating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), or flash memory cells. Each memory cell may include a cell capacitor and a transistor that connects the cell capacitor to the cell bit line GBL or disconnects the cell capacitor from the cell bit line GBL, and the transistor includes a channel that is turned on and off according to a word line (WL) signal. Here, the channel may be formed perpendicular to the array matrices AM1, AM2, and AM3, and the cell bit line GBL below the channel may be connected to the cell capacitor above the channel.

[0037] Cell bit lines GBL included in two adjacent array matrices of the array matrices AM1 , AM2 , and AM3 are separated, and the cell bit lines GBL, word lines, and memory cells may not be disposed in a boundary region between the array matrices AM1 , AM2 , and AM3 .

[0038] Each of the cell bit lines GBL may be connected to bit lines BL0, BL1, BL2, and ... or complementary bit lines BLB0, BLB1, BLB2, and ... A bit of data may be read based on a difference between a signal on a specific bit line and a signal on a complementary bit line corresponding to the specific bit line, rather than based on the signal from the bit line or the complementary bit line itself. Figure 1, the topmost cell bit line GBL of the second array matrix AM2 may be connected to the complementary bit line BLB0, and the cell bit line GBL below it may be sequentially connected to the bit line BL1, the bit line BL2, the complementary bit line BLB3, the complementary bit line BLB4, the bit line BL5, the bit line BL6, the complementary bit line BLB7, the complementary bit line BLB8, and .... The connection of the cell bit line GBL to the bit lines BL0, BL1, BL2, and ... or the complementary bit lines BLB0, BLB1, BLB2, and ... may be made in the boundary region between the array matrices AM1, AM2, and AM3.

[0039] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , the bit lines BL0, BL1, BL2, and ... and the complementary bit lines BLB0, BLB1, BLB2, and ... may be located in a different layer from the memory cell, specifically, below the memory cell. The bit lines BL0, BL1, BL2, and ... and the complementary bit lines BLB0, BLB1, BLB2, and ... may be part of the wiring connecting the cell bit line GBL with the sense amplifier BLSA.

[0040] Reference Figure 2 , Figure 3 , Figure 4 and Figure 5 , a semiconductor memory device according to example embodiments may include a memory cell array chip 1 in which a plurality of memory cells are located and a peripheral circuit chip 2 in which a sense amplifier BLSA is located.

[0041] The memory cell array chip 1 may include a cell capacitor 11, a vertical channel transistor 12, a cell bit line GBL, a bit line shielding layer 14, upper wirings LM0, LM1, LM2, and LM3 forming at least a portion of the bit lines BL1 and BL3 and the complementary bit lines BLB1 and BLB3, and an upper via V1, an upper bonding pad P1, etc. The upper bonding pad P1 may include copper (Cu). The cell capacitor 11 may be connected to the cell bit line GBL through the vertical channel transistor 12, and the cell bit line GBL may be connected to the bit lines BL1 and BL3 or the complementary bit lines BLB1 and BLB3 including the upper via V1 and at least a portion of the upper wirings LM0, LM1, LM2, and LM3 in the boundary region between the array matrices AM1, AM2, and AM3. Between the cell capacitor 11, the vertical channel transistor 12, the cell bit line GBL, the bit line shielding layer 14, the upper wiring LM0, LM1, LM2 and LM3, the upper via V1, the upper bonding pad P1, etc., a single or multiple insulating layers may be provided to insulate them from each other. The bit line shielding layer 14 may be a layer for blocking or preventing the cell bit line GBL from being affected by the electrical signal of the circuit wiring flowing through it below. That is, the bit line shielding layer 14 may be used as a shielding member for the cell bit line GBL to resist the electromagnetic effect caused by the electrical signal of the circuit wiring flowing through it below. The peripheral circuit chip 2 may include various peripheral circuits for driving the memory cell, such as a sub-word line driver, a row decoder, a column decoder, and a sense amplifier BLSA. In addition, the peripheral circuit chip 2 may include a lower bonding pad P2, lower wirings M1, M2, M3, M4 and M5 connecting the sense amplifier BLSA to the lower bonding pad P2, a connection layer BP, a lower via V2, etc. The lower bonding pad P2 may include copper. The sense amplifier BLSA may be located below the array matrix AM1, AM2, and AM3, and may vertically overlap the cell bit line GBL and the bit lines BL1 and BL3 and the complementary bit lines BLB1 and BLB3. The connection layer BP may include polysilicon. The memory cell array chip 1 and the peripheral circuit chip 2 may be bonded so that the upper bonding pad P1 and the lower bonding pad P2 are aligned to contact each other. Through this bonding, the cell bit line GBL may be connected to the sense amplifier BLSA.

[0042] Reference Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5, the bit line BL1 and the complementary bit line BLB1 may extend under the array matrix AM2 on the left side of the boundary region between the array matrix AM2 and the array matrix AM3 (hereinafter referred to as the "left side of the boundary region"), and the bit line BL3 and the complementary bit line BLB3 may extend under the array matrix AM3 on the right side of the boundary region between the array matrix AM2 and the array matrix AM3 (hereinafter referred to as the "right side of the boundary region"). Subsequently, the bit line BL5 and the complementary bit line BLB5 may extend under the array matrix AM2 on the left side of the boundary region, and the bit line BL7 and the complementary bit line BLB7 may extend under the array matrix AM3 on the right side of the boundary region. In this way, in the boundary region between the array matrix AM2 and the array matrix AM3, the odd-numbered bit lines BL1, BL3, BL5, and ... and the odd-numbered complementary bit lines BLB1, BLB3, BLB5, and ... may be connected to the cell bit line GBL, and the bit lines BL1, BL3, BL5, and ... and the complementary bit lines BLB1, BLB3, BLB5, and ... corresponding thereto may extend in the same direction. In addition, the bit lines BL1, BL3, BL5, and . . . and the complementary bit lines BLB1, BLB3, BLB5, and . . . corresponding thereto may extend alternately to the left and to the right sequentially from the top.

[0043] In this way, when the bit lines BL1, BL3, BL5, and ... and their corresponding complementary bit lines BLB1, BLB3, BLB5, and ... extend in the same direction and extend alternately to the left and right, the wiring can be effectively set so that their length can be reduced.

[0044] Figure 6 yes Figure 1 An enlarged layout diagram of portion A1. Figure 7 is along Figure 6 A cross-sectional view taken along line AA'. Figure 8 It shows that Figure 6 Layout diagram of the connection of wiring centered on the bonding pad with different aspect ratios in part A2.

[0045] Reference Figure 6 Shielding lines BLS may be respectively provided between two adjacent sense amplifiers BLSA and between bit lines BL0, BL8, ... and complementary bit lines BLB4, BLB12, ... The shielding lines BLS may reduce signal interference between adjacent bit lines and complementary bit lines.

[0046] Reference Figure 6 and Figure 7, the shielding line BLS, some bit lines BL4, BL12, BL20, BL28, and ... and some complementary bit lines BLB0, BLB8, BLB16, BLB24, and ... may extend in a straight line, and the remainder (e.g., the bit lines BL0, BL8, BL16, BL24, and ... and the complementary bit lines BLB4, BLB12, BLB20, BLB28, and ...) may be a folded line with a plurality of bending points. According to example embodiments, the bit lines BL0, BL8, BL16, BL24, and ... and the complementary bit lines BLB4, BLB12, BLB20, BLB28, and ... may be straight lines, and the bit lines BL4, BL12, BL20, BL28, and ... and the complementary bit lines BLB0, BLB8, BLB16, BLB24, and ... may be folded lines. The straight lines and the folded lines may be selected in various ways. The shielding line BLS, some bit lines extending in a straight line among the bit lines (e.g., BL4, BL12, BL20, BL28, and ...) and some complementary bit lines extending in a straight line among the complementary bit lines (e.g., BLB0, BLB8, BLB16, BLB24, and ...) may include a third upper wiring LM2, and some bit lines as folded lines among the bit lines (e.g., BL0, BL8, BL16, BL24, and ...) and some complementary bit lines as folded lines among the complementary bit lines (e.g., BLB4, BLB12, BLB20, BLB28, and ...) may include a third upper wiring LM2, a fourth upper wiring LM3, and an upper via V1 connecting the third upper wiring LM2 and the fourth upper wiring LM3 to each other. The bit lines BL0, BL8, BL16, BL24, and ... as broken lines and the complementary bit lines BLB4, BLB12, BLB20, BLB28, and ... may respectively include two portions located at both sides of the shielding line BLS and / or the bit lines BL0, BL8, BL16, BL24, and ..., and the two portions may be connected to each other by crossing the shielding line BLS and / or the bit lines BL0, BL8, BL16, BL24, and ... arranged therebetween in an insulated state. At this time, the two portions located at both sides of the shielding line BLS and / or the bit lines BL0, BL8, BL16, BL24, and ... may be the third upper wiring LM2, and the portion connecting the two portions may be the fourth upper wiring LM3 and the upper via V1. For example, referring to Figure 7 , the two parts BLB12 (LM2) of the complementary bit line BLB12 can be located at both sides of the shielding line BLS (LM2) and the bit line BL8 (LM2), the connecting part BLB12 (LM3) connecting the two parts BLB12 (LM2) can be located in a different layer therebelow, and the connecting part BLB12 (LM3) can be connected to the two parts BLB12 (LM2) of the complementary bit line BLB12 through the upper via V1.

[0047] By way of example arrangement, a bit line and a corresponding complementary bit line may be blocked or prevented from being adjacent to each other. That is, by way of the above example embodiments, a first bit line and a second bit line complementary to the first bit line may be arranged in such a way that they are not directly adjacent to each other. For example, at least one of another bit line, another complementary bit line, and a shielding line may be located between a bit line and a corresponding complementary bit line. For example, referring to Figure 6 , a portion of the complementary bit line BLB4 and the bit line BL4 may be located between the complementary bit line BLB0 and the bit line BL0. The bit line BL0 and the shielding line BLS may be located between the bit line BL4 and the complementary bit line BLB4. Through these exemplary arrangements, signal interference between a bit line and its corresponding complementary bit line may be mitigated.

[0048] Reference Figure 6 and Figure 8 , the bit lines BL0, BL4, BL8, BL12, BL16, BL20, BL24, BL28, and ... and the complementary bit lines BLB0, BLB4, BLB8, BLB12, BLB16, BLB20, BLB24, BLB28, and ... may be connected to one of the fourth upper wirings LM3 extending vertically. Figure 8 , the complementary bit line BLB0 may be connected to the fourth upper wiring LM31 through the upper via member V1, and the bit line BL0 may be connected to the fourth upper wiring LM35 through the upper via member V1. Subsequently, the complementary bit line BLB8 may be connected to the fourth upper wiring LM32 through the upper via member V1, and the bit line BL8 may be connected to the fourth upper wiring LM36 through the upper via member V1. The complementary bit line BLB16 may be connected to the fourth upper wiring LM33 through the upper via member V1, and the bit line BL16 may be connected to the fourth upper wiring LM37 through the upper via member V1. The complementary bit line BLB24 may be connected to the fourth upper wiring LM34 through the upper via member V1, and the bit line BL24 may be connected to the fourth upper wiring LM38 through the upper via member V1.

[0049] Reference Figure 2 and Figure 8 , the fourth upper wiring LM3 (LM31, LM32, LM33, LM34, LM35, LM36, LM37, LM38) extending vertically may be connected to the upper bonding pad P1 through the contact hole member C1. The upper bonding pad P1 may be bonded to the lower bonding pad P2, and thus may be connected to the sense amplifiers BLSA (BLSA0, BLSA8, BLSA16, BLSA24) through the lower wirings M1, M2, M3, M4, and M5, the connection layer BP, the lower via member V2, etc., respectively.

[0050] Figure 8 The upper bonding pad P1 is shown to be oval in shape, but may be circular, polygonal, etc. according to example embodiments. Figure 8The upper bonding pads P1 are shown to be located in line above the two center sense amplifiers BLSA8 and BLSA16 , but according to example embodiments, they may be located above the other sense amplifiers BLSA1 and BLSA24 , or their positions may be changed vertically.

[0051] Fig. 9 is a schematic diagram illustrating connections between sense amplifiers and bonding pads on a peripheral circuit chip in a semiconductor memory device according to example embodiments.

[0052] Reference Fig. 9 , the sense amplifier BLSA may include a plurality of NMOS sense amplifier drivers (NSA), a plurality of PMOS sense amplifier drivers (PSA), a bit line lead-in line BL input or connected to one of the NSAs, and a complementary bit line lead-in line BLB input or connected to one of the PSAs. Above the sense amplifier BLSA, a first connection layer BP1 and a second connection layer BP2 may be placed, the first connection layer BP1 may be connected to the bit line lead-in line BL, and the second connection layer BP2 may be connected to the complementary bit line lead-in line BLB. The first connection layer BP1 may be placed to correspond to the lower bonding pads P21, P22, P23, and P24 on the left half side among the plurality of lower bonding pads P21, P22, P23, P24, P25, P26, P27, and P28, and the second connection layer BP2 may be placed to correspond to the lower bonding pads P25, P26, P27, and P28 on the right half side among the plurality of lower bonding pads P21, P22, P23, P24, P25, P26, P27, and P28. The first connection layer BP1 and the second connection layer BP2 may include polysilicon. The first connection layer BP1 may be connected to one of the lower bonding pads P21, P22, P23, and P24 on the left side (e.g., P21), and the second connection layer BP2 may be connected to one of the lower bonding pads P25, P26, P27, and P28 on the right side (e.g., P25). When the first connection layer BP1 and the second connection layer BP2 are thus arranged, wiring for connecting the lower bonding pads P21, P22, P23, P24, P25, P26, P27 and P28 with the readout amplifier BLSA can be effectively arranged, and thus the length of the wire can be reduced.

[0053] Fig.10 is a schematic diagram illustrating connections between sense amplifiers and bonding pads on a peripheral circuit chip in a semiconductor memory device according to another example embodiment.

[0054] Reference Fig.10, the sense amplifier BLSA may include a plurality of NMOS sense amplifier drivers (NSA), a plurality of PMOS sense amplifier drivers (PSA), and a bit line lead-in line (or bit line) BL input or connected to one of the NSA and a complementary bit line lead-in line (or complementary bit line) BLB input or connected to one of the PSA. Above the sense amplifier BLSA, a first connection layer BP3 and a second connection layer BP4 may be placed, and the first connection layer BP3 may be connected to the bit line lead-in line BL, and the second connection layer BP4 may be connected to the complementary bit line lead-in line BLB. All of the first connection layer BP3 and the second connection layer BP4 may be placed to correspond to all of the plurality of lower bonding pads P21, P22, P23, P24, P25, P26, P27, and P28. The first connection layer BP3 and the second connection layer BP4 may include polysilicon. The first connection layer BP3 and the second connection layer BP4 may be located in different layers, or may be located on the same layer but at different positions on the same plane. The first connection layer BP3 may be connected to one of the lower bonding pads P21, P22, P23, and P24 located on the left side (e.g., P21), and the second connection layer BP4 may be connected to one of the lower bonding pads P25, P26, P27, and P28 located on the right side (e.g., P25). When the first connection layer BP3 and the second connection layer BP4 are so arranged, wiring for connecting the lower bonding pads P21, P22, P23, P24, P25, P26, P27, and P28 with the sense amplifier BLSA may be effectively arranged, and thus the length of the wiring may be reduced.

[0055] Refer again Fig.10 , a group of multiple lower bonding pads (e.g., P21, P22, P23, P24, P25, P26, P27, and P28) corresponds to or vertically overlaps the first connection layer BP3 and the second connection layer BP4 corresponding to the first connection layer BP3. In addition, half of the group of lower bonding pads (e.g., P21, P22, P23, and P24) are connected to the bit line BL, and the remaining half (e.g., P25, P26, P27, and P28) are connected to the complementary bit line BLB. The first connection layer BP3 is connected to one input terminal of the corresponding sense amplifier BLSA, and the second connection layer BP4 corresponding to the first connection layer BP3 is connected to the other input terminal of the corresponding sense amplifier BLSA.

[0056] Although some example embodiments of the present disclosure are described with reference to the accompanying drawings, it will be understood by those skilled in the art to which the present disclosure belongs that the present disclosure may be implemented in other specific forms without changing the technical ideas or essential features. Therefore, it should be understood that the above example embodiments are only for illustrative purposes, and the scope of the present disclosure is not limited thereto.

Claims

1. A semiconductor memory device, comprising: A first chip including a first array matrix and a second array matrix adjacent to each other, the first array matrix and the second array matrix each including a plurality of memory cells; as well as a second chip located below the first chip, the second chip comprising a plurality of sense amplifiers configured to drive memory cells of the first array matrix and the second array matrix, wherein a plurality of first unit bit lines are located in the first array matrix, and a plurality of second unit bit lines are located in the second array matrix, wherein a plurality of first bit lines and a plurality of first complementary bit lines are located below the first array matrix, and a plurality of second bit lines and a plurality of second complementary bit lines are located below the second array matrix, wherein each of the first bit lines is connected to one of the first unit bit lines, each of the first complementary bit lines is connected to one of the second unit bit lines, each of the second bit lines is connected to one of the second unit bit lines, and each of the second complementary bit lines is connected to one of the first unit bit lines, The sense amplifier includes a plurality of first sense amplifiers and a plurality of second sense amplifiers, at least a portion of the plurality of first sense amplifiers are located below the first array matrix, and at least a portion of the plurality of second sense amplifiers are located below the second array matrix. wherein one of the first bit lines and a corresponding one of the first complementary bit lines in a pair are connected to a corresponding one of the first sense amplifiers, and One of the second bit lines and a corresponding one of the second complementary bit lines in a pair are connected to a corresponding one of the second sense amplifiers.

2. The semiconductor memory device according to claim 1, wherein: The first cell bit lines respectively connected to the first bit lines and the first cell bit lines respectively connected to the second complementary bit lines alternate with each other; and The second cell bit lines respectively connected to the first complementary bit lines and the second cell bit lines respectively connected to the second bit lines alternate with each other.

3. The semiconductor memory device according to claim 2, wherein: The connection between the first bit line and the first unit bit line, the connection between the second complementary bit line and the first unit bit line, the connection between the first complementary bit line and the second unit bit line, and the connection between the second bit line and the second unit bit line are located in a boundary area between the first array matrix and the second array matrix.

4. The semiconductor memory device according to claim 3, wherein: Each of the first bit line, the first complementary bit line, the second bit line, and the second complementary bit line is located in the first chip and includes a plurality of upper wirings and a plurality of upper vias.

5. The semiconductor memory device according to claim 4, wherein: The second chip includes a plurality of lower wirings and a plurality of lower vias connecting the first bit line, the first complementary bit line, the second bit line, and the second complementary bit line to the sense amplifier.

6. The semiconductor memory device according to claim 5, wherein: The first chip includes an upper bonding pad connected to the upper wiring or the upper via; The second chip includes a lower bonding pad connected to the lower wiring or the lower via; and The upper bonding pad is bonded to the lower bonding pad.

7. The semiconductor memory device according to claim 1, wherein: At least one of a shield line, another one of the first bit lines, and another one of the first complementary bit lines is placed between one of the first bit lines and a corresponding one of the first complementary bit lines commonly connected to a corresponding one of the first sense amplifiers.

8. The semiconductor memory device according to claim 7, wherein: Of one of the first bit lines and a corresponding one of the first complementary bit lines commonly connected to a corresponding one of the first sense amplifiers, one is a straight line and the other is a broken line.

9. The semiconductor memory device according to claim 8, wherein: The fold line crosses the shield line and is insulated from the shield line.

10. The semiconductor memory device according to claim 9, wherein: The fold line includes a first portion and a second portion located at both sides of the shielding line, a connecting portion crossing and insulated from the shielding line, a first via connected between the first portion and the connecting portion, and a second via connected between the second portion and the connecting portion.

11. The semiconductor memory device according to claim 10, wherein: The fold line crosses and is insulated from at least one of the first bit line and the first complementary bit line.

12. The semiconductor memory device according to claim 1, wherein: The second chip includes a plurality of lower bonding pads connecting the first bit line and the first complementary bit line to the sense amplifier, a plurality of first connection layers, and a plurality of second connection layers; and One of the first connection layers is connected to a first input terminal of a corresponding one of the sense amplifiers, and one of the second connection layers corresponding to the one of the first connection layers is connected to a second input terminal of the corresponding one of the sense amplifiers; and Each of the first connection layers is connected to one of the lower bonding pads; and Each of the second connection layers is connected to another one of the lower bonding pads.

13. The semiconductor memory device according to claim 12, wherein: The one of the lower bonding pads is connected to the first bit line, and the other of the lower bonding pads is connected to the first complementary bit line.

14. The semiconductor memory device according to claim 12, wherein: The group of the plurality of lower bonding pads corresponds to both one of the first connection layers and a corresponding one of the second connection layers.

15. The semiconductor memory device according to claim 14, wherein: Half of the set of lower bonding pads are connected to the first bit line and the remaining half of the set of lower bonding pads are connected to the first complementary bit line.

16. A semiconductor memory device comprising: A first chip comprising an array matrix, wherein the array matrix comprises a plurality of memory cells; as well as a second chip comprising a plurality of sense amplifiers located below the first chip and configured to drive memory cells of the array matrix, Wherein, a plurality of unit bit lines are located in the array matrix, Wherein, a plurality of bit lines and a plurality of complementary bit lines are located below the array matrix, wherein one of the pair of bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers, and wherein at least one of the shielding line, the second one of the bit lines, and the second one of the complementary bit lines is located between one of the bit lines and a corresponding one of the complementary bit lines in a pair commonly connected to a corresponding one of the sense amplifiers.

17. The semiconductor memory device according to claim 16, wherein: Of one of the bit lines and a corresponding one of the complementary bit lines commonly connected to a corresponding one of the sense amplifiers, one is a straight line and the other is a broken line.

18. The semiconductor memory device according to claim 17, wherein: The fold line crosses the shield line and is insulated from the shield line.

19. A semiconductor memory device comprising: A first chip comprising an array matrix, wherein the array matrix comprises a plurality of memory cells; as well as a second chip comprising a plurality of sense amplifiers located below the first chip and configured to drive memory cells of the array matrix, Wherein, a plurality of unit bit lines are located in the array matrix, Wherein, a plurality of bit lines and a plurality of complementary bit lines are located below the array matrix, wherein one of the pair of bit lines and a corresponding one of the complementary bit lines are connected to a corresponding one of the sense amplifiers, wherein the second chip comprises a plurality of lower bonding pads connecting the bit lines and the complementary bit lines to the sense amplifier, a plurality of first connection layers, and a plurality of second connection layers, wherein one of the first connection layers is connected to a first input terminal of a corresponding one of the sense amplifiers, and a corresponding one of the second connection layers is connected to a second input terminal of the corresponding one of the sense amplifiers, wherein each of the first connection layers is connected to a corresponding one of the lower bonding pads, and Wherein, each of the second connection layers is connected to a corresponding one of the lower bonding pads.

20. The semiconductor memory device according to claim 19, wherein The group of lower bonding pads corresponds to both one of the first connection layers and a corresponding one of the second connection layers.

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