Inverter and driving device thereof

Abstract

The invention provides an inverter and a driving device thereof, and the driving device comprises a driving signal generation module which is configured to generate a first driving signal; the isolation sampling module is configured to sample the first driving signal to obtain an ideal driving signal; the driving current amplification circuit module and the isolation sampling module share the same reference ground, and the driving current amplification circuit module is configured to receive the first driving signal and generate a driving reference signal based on the first driving signal; and the comparison isolation compensation circuit module is configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal. According to the driving device provided by the invention, the problem that a narrow pulse wave sending signal near a PWM zero-crossing sequence point is easy to generate distortion can be relieved.

Description

Technical Field

[0001] The present application relates to the field of inverter control technology, and in particular to an inverter and a driving device thereof. Background Art

[0002] In the NPC three-level inverter, the driving signal generated by DSP (Digital Signal Processing) and CPLD (Complex Programmable Logic Device) is transmitted to the three-phase IGBT driver board. The three-phase driver board drives the IGBT module after level processing and power amplification of the CPLD driving signal. In the three-phase driver board, due to the delay characteristics of electronic devices such as resistors and capacitors and the existence of stray inductance characteristics in the circuit, the narrow pulse wave signal near the PWM zero-crossing point often produces distortion. After the distorted PWM signal is used as the Vge voltage signal to drive the IGBT gate, the IGBT collector turns off the Vce voltage and generates a pulse spike instantaneously, causing damage to the IGBT driver tube. At the same time, it will also cause uneven voltage stress and switching loss of different driver tubes in the IGBT module. However, in the prior art, most of them correct the CPLD wave PWM signal by correcting the triangular carrier signal, ignoring the influence of the circuit of the driver circuit board on the PWM signal. Because the PWM signal sent from the CPLD can only be used as the IGBT gate drive Vge voltage signal after passing through the current amplifier circuit in the driver circuit board. Therefore, after the triangular carrier signal is corrected in the prior art, the IGBT gate drive Vge voltage signal in the actual hardware circuit may still be distorted. In addition, such correction methods have complex calculation time and long cycle, and the hardware response speed is slow.

[0003] In addition, the method described in the CN116885931A patent: the modulation wave range that avoids narrow pulses is calculated, and the modulation wave is obtained by adding the zero-sequence voltage after judging the difference between the upper capacitor voltage and the lower capacitor voltage. However, there is a difference between the range of the modulation wave that avoids narrow pulses in the calculation and the range of the modulation wave that actually generates narrow pulses in the circuit, so there is a deviation between the numerical range obtained by calculation and the numerical range generated by the actual circuit. Secondly, judging the difference between the upper capacitor voltage and the lower capacitor voltage as the modulation wave obtained by adding the zero-sequence voltage later will have a certain deviation. In this way, it cannot be guaranteed that the first narrow pulse generated in the actual circuit will not be distorted, and then it cannot be guaranteed that the gate drive square wave Vge of the IGBT generated by the first narrow pulse will not be distorted, so it cannot be guaranteed that the first Vce voltage stress generated by the IGBT drive is within the rated range of the IGBT tube.

[0004] The method described in the CN105450068A patent: by sampling the output voltage peak point, selecting the corresponding strategy to suppress the PWM narrow pulse, the output voltage is already at the peak point, and the IGBT gate drive may have been affected by the first narrow pulse. This method cannot guarantee that the circuit does not generate narrow pulses, but can only reduce the number of narrow pulses generated. When the output crosses the zero point, the three-level modulation is switched to the two-level modulation. Such a modulation strategy has lost the characteristic of low harmonic content of the three-level modulation, and brings back the problem of high harmonic content of the two-level modulation. Summary of the invention

[0005] The purpose of the present application is to provide a technical solution to alleviate the problem in the related art that a narrow pulse wave signal near a PWM zero-crossing point generates distortion, which causes a hidden danger of damage to a driving tube.

[0006] Based on the above objectives, the present application provides a driving device of an inverter, which is applied to a three-level inverter, and the driving device includes: A driving signal generating module, configured to generate a first driving signal; An isolation sampling module is configured to sample the first driving signal to obtain an ideal driving signal; A driving current amplifying circuit module, the driving current amplifying circuit module and the isolation sampling module are configured with a common reference ground, the driving current amplifying circuit module is configured to receive a first driving signal and generate a driving reference signal based on the first driving signal; The comparison isolation compensation circuit module is configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal.

[0007] According to the above description, the driving device provided by the present application is provided with a sampling circuit module and a driving current amplifying circuit module configured with a common reference ground, and a comparison isolation compensation circuit module is provided to compare and compensate between the driving reference signal and the ideal driving signal, so that the driving waveform can be corrected to obtain the second driving signal, thereby alleviating the problem that the narrow pulse transmission signal near the PWM zero-crossing point is prone to distortion.

[0008] Furthermore, the voltage divider circuit, the first optical coupler and the MOS tube circuit, wherein: The voltage divider circuit receives a first drive signal, and the output end of the voltage divider circuit is connected to the primary side of the first optocoupler, the first optocoupler is configured as a logic gate circuit output type first optocoupler, the secondary side of the first optocoupler outputs an intermediate signal that is opposite to the first drive signal, and the intermediate signal is inverted through the MOS tube circuit to obtain an ideal drive signal.

[0009] Furthermore, the driving current amplifying circuit module includes a second optical coupler and an amplifying circuit, wherein: The primary input end of the second optocoupler receives the first drive signal, the secondary side of the second optocoupler is connected to the amplifier circuit, the drive reference signal is output through the amplifier circuit, and the secondary side of the second optocoupler and the secondary side of the first optocoupler are configured with a common reference ground.

[0010] Furthermore, the driving signal generating module includes: A PWM drive signal generating circuit is configured to generate a PWM drive signal; A level conversion circuit is configured to convert the PWM drive signal into a drive voltage adapted to a drive tube of the inverter; The logic gate circuit is configured to invert the output timing of the level conversion circuit to obtain a first driving signal.

[0011] Furthermore, the comparison isolation compensation circuit module includes: A square wave signal memory is configured to latch an ideal driving signal and a driving reference signal; A square wave signal sampling extractor is configured to sample and extract the maximum amplitude, the maximum amplitude starting time and the maximum amplitude ending time of the ideal driving signal and / or the driving reference signal; A maximum amplitude starting time predictor is configured to predict according to the sampling value of the maximum amplitude starting time of the ideal driving signal to obtain a repair prediction value of the starting time of the rising edge, and the repair prediction value of the starting time of the rising edge is used to repair the rising edge of the driving reference signal; A maximum amplitude end time predictor is configured to predict according to the sampling value of the maximum amplitude end time of the ideal driving signal to obtain a repair prediction value of the start time of the falling edge, and the repair prediction value of the start time of the falling edge is used to repair the falling edge of the driving reference signal; an amplitude comparator configured to compare the amplitude of the driving reference signal with the amplitude of the ideal driving signal; an amplitude repairer configured to perform amplitude repair on the edge-repaired driving reference signal based on the comparison result of the amplitude comparator, so that the amplitude of the repaired output signal is consistent with the amplitude of the ideal driving signal; The comparison isolation compensation circuit module outputs a second driving signal, and the second driving signal is a square wave signal with the rising edge and the falling edge starting time repaired and the amplitude repaired.

[0012] Further, the amplitude comparator includes a first operational amplifier and a second operational amplifier, wherein the non-inverting input terminal of the first operational amplifier receives the ideal driving signal, the inverting input terminal receives the driving reference signal, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit; The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs a feedback signal through a resistor; The amplitude repairer performs amplitude repair on the edge-repaired driving reference signal based on the feedback signal.

[0013] Furthermore, the driving device also includes an on-resistance and an off-resistance; The second driving signal generates a driving tube driving signal through the turn-on resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn on; The second driving signal generates a driving tube driving signal through a turn-off resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn off; The comparison isolation compensation circuit module also includes: The discharge time detection and repair device is configured to receive a drive tube driving signal and adjust the discharge time of the corresponding drive tube in the inverter.

[0014] Furthermore, the discharge time detection repairer includes: The discharge time detection circuit includes: a voltage-stabilizing diode, a diode and an RC circuit, wherein the driving signal of the driving tube passes through the voltage-stabilizing diode, the diode and the RC circuit in sequence, and then outputs a discharge time feedback signal at the high potential end of the RC circuit.

[0015] Furthermore, the discharge time detection repairer also includes: The discharge time adjustment circuit comprises: A triode, the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and a capacitor is connected in parallel at both ends of the grounding resistor; A first input terminal, the first input terminal receives a driving signal of the driving tube, and the first input terminal is electrically connected to the base of the transistor through a resistor; The second input terminal receives a discharge control signal, and the second input terminal is electrically connected to the base of the transistor through a resistor and a diode, wherein the discharge control signal is generated based on a discharge duration feedback signal.

[0016] In a second aspect, the present application further provides an inverter, comprising an inverter unit and a driving device as described in any one of the above items, wherein the driving device is used to drive a driving tube in the inverter unit.

[0017] In this technical solution, since the inverter adopts the inverter driving device of any one of the above technical solutions, it has all the beneficial effects of the inverter driving device, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1It is a schematic diagram of the current topology structure of an NPC three-phase inverter in the related art; Figure 2 A schematic diagram of a driving device provided in one embodiment of the present application; Figure 3 A schematic diagram of a PWM drive signal generating circuit provided in an embodiment of the present application; Figure 4 A schematic diagram of a level conversion circuit provided in an embodiment of the present application; Figure 5 A schematic diagram of a logic gate circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of a driving device provided in another embodiment of the present application; Figure 7 A schematic diagram of a narrow pulse distortion waveform provided in an embodiment of the present application; Figure 8 A schematic diagram of an isolated sampling module provided in an embodiment of the present application; Fig. 9 A schematic diagram of a comparison isolation compensation circuit module provided in an embodiment of the present application; Fig.10 A schematic diagram of using a DSP chip circuit and a CPLD chip circuit to implement the function of a comparison isolation compensation circuit module provided in an embodiment of the present application; Fig.11 A schematic diagram of an amplitude comparator provided in an embodiment of the present application; Fig.12 A schematic diagram of a discharge time detection circuit provided in an embodiment of the present application; Fig.13 A schematic diagram of a discharge time adjustment circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The present application will be described in detail below in conjunction with the specific implementation modes shown in the accompanying drawings, but these implementation modes do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in the field based on these implementation modes are included in the protection scope of the present application.

[0020] The purpose of the present application is to alleviate or solve the problem that the narrow pulse wave signal near the PWM zero-crossing point of the three-level inverter often produces distortion. After the distorted PWM signal is used as the driving signal of the driving tube, there is a hidden danger of damaging the driving tube. In practical applications, there are many forms of inverter driving tubes. The driving tube can be an IGBT, a switching device such as SiC, or a switching module, which includes several switching devices. Regardless of the form of the driving tube, the inverter is driven based on the PWM control principle. Taking IGBT as an example, after the distorted PWM signal is used as the Vge voltage signal to drive the IGBT gate, the IGBT collector turns off the Vce voltage and generates a pulse spike instantaneously, which causes damage to the IGBT driving tube. At the same time, it will also cause uneven voltage stress and switching loss of different driving tubes in the IGBT module. For the sake of convenience, the driving tube is an IGBT as an example in the embodiment of the present application.

[0021] Based on the above purpose, the present application provides an inverter driving device, which is applied to a three-level inverter. For example, the present application embodiment takes the application of the NPC three-phase inverter current topology structure as an example to illustrate the driving device. Figure 1 As shown, the NPC three-phase inverter circuit topology includes three-phase circuits of phase A, phase B and phase C, each phase circuit includes an IGBT module, each IGBT module includes 4 drive tubes (i.e., IGBT), and the drive device provided in the present application is used to drive the switch state change of each phase drive tube, wherein the drive strategy of the drive device for each phase drive tube is similar. For the convenience of explanation, the drive strategy of each drive tube of phase A is selected as an example in the embodiment of the present application. The respective drive tubes in the bridge arm of phase A are respectively referred to as the first to fourth drive tubes, wherein the first drive tube TA1 and the fourth drive tube TA4 are outer tubes, and the second drive tube TA2 and the third drive tube TA3 are inner tubes.

[0022] like Figure 2 As shown, as an optional implementation, the driving device includes a driving signal generating module, an isolation sampling module, a driving current amplifying circuit module and a comparison isolation compensation circuit module.

[0023] The drive signal generation module is configured to generate a first drive signal, which is used as the basis for the subsequent control of each drive tube. Exemplarily, the drive signal generation module may include a PWM drive signal generation circuit and a level conversion circuit, wherein the PWM drive signal generation circuit is configured to generate a PWM drive signal, and the level conversion circuit converts the PWM drive signal into a drive voltage adapted to the drive tube of the inverter.

[0024] like Figure 3As shown in FIG. 1 , a method for implementing a drive signal generation module is shown. The PWM drive signal generation circuit includes an isolation sampling circuit, a DSP (Digital Signal Processing, digital signal processor) and a CPLD (Complex Programmable Logic Device, complex programmable logic device). Figure 3 As shown, the isolated sampling circuit is configured to collect the following electrical parameter information, which includes: DC side voltage Vdc, DC side current Idc, internal inductor currents Ia1, Ia2, Ia3, internal capacitor voltages Ua1, Ua2, Ua3, AC measured external inductor currents Iao1, Iao2, Iao3, AC side voltages Uao1, Uao2, Uao3. At least part of the above electrical parameter information enters the DSP for FOC calculation, and is compared with the carrier wave to form a PWM wave after the calculation and send it to the CPLD. The CPLD determines the opening and closing timing of the internal and external tubes and then sends a PWM drive signal. The PWM drive signal of each drive tube of phase A is recorded as DR_An_3.3V, n=1, 2, 3, 4.

[0025] As an optional implementation, Figure 4 As shown, the level conversion circuit can be implemented using transistor Q1 to convert Figure 3 The DR_An_3.3V level signal generated by the CPLD is converted into a 15V voltage signal that matches the driver tube, such as Figure 4 As shown, after the level conversion, the signal corresponding to each driving tube is recorded as DR_An_15V, n=1, 2, 3, 4.

[0026] As an optional implementation, the structures of the level conversion circuits corresponding to the various drive tubes are consistent, and only the level conversion circuit corresponding to the first drive tube in phase A is used as an example for description. Figure 4 As shown, the level conversion circuit includes a transistor Q1, the collector of the transistor Q1 is connected to the 15V voltage source through the resistor R2 and the resistor R1 in sequence, the base of the transistor Q1 receives the PWM drive signal DR_A1_3.3V through the resistor R3, the emitter of the transistor Q1 is grounded, and the emitter of the transistor Q1 is connected to the base through the resistor R4.

[0027] like Figure 5As shown, further, the drive signal generation module also includes a logic gate circuit, which is configured to flip the output timing of the level conversion circuit to obtain a first drive signal. Specifically, in the embodiment of the present application, a level conversion circuit is used to convert the level signal from 3.3V to 15V. Based on the structural characteristics of the level conversion circuit, the DR_A1_15V signal output by the level conversion circuit is inverted from the DR_A1_3.3V signal. The DR_A1_15V signal timing can be flipped by setting a Schmidt NAND gate logic circuit, so that the first drive signal finally output is in phase with the DR_A1_3.3V signal. For ease of explanation, in the embodiment of the present application, the first drive signal corresponding to each drive tube of phase A is recorded as PWMAn_15V, n=1, 2, 3, 4.

[0028] Through the above settings, the driving device provided in the embodiment of the present application obtains a first driving signal. However, in actual applications, the driving signal can only be used as the IGBT gate driving Vge voltage signal after passing through the current amplification circuit in the driving circuit board. Considering the delay characteristics of electronic devices such as resistors and capacitors in the three-phase driving board and the existence of stray inductance characteristics of the circuit, the narrow pulse wave signal near the PWM zero-sequence point will often be distorted. After the distorted PWM signal is used as the Vge voltage signal to drive the IGBT gate, the IGBT collector turns off the Vce voltage to generate a pulse spike instantaneously, causing damage to the IGBT driver tube. In order to solve the above problems, the present application further designs the driving device as follows. The driving device also includes: An isolation sampling module is configured to sample the first driving signal to obtain an ideal driving signal; A driving current amplifying circuit module, the driving current amplifying circuit module and the isolation sampling module are configured with a common reference ground, the driving current amplifying circuit module is configured to receive a first driving signal and generate a driving reference signal based on the first driving signal; The comparison isolation compensation circuit module is configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal.

[0029] like Figure 6 As shown, the drive signal generation module is used to generate a first drive signal, and the first drive signal includes four groups of PWM signal waves for driving the four drive tubes of phase A. For the convenience of explanation, the signal waves corresponding to the drive tubes of phase A in the first drive signal in the embodiment of the present application are recorded as PWMAn_15V, n=1, 2, 3, 4. Of course, the drive signal generation module also includes PWM signal waves for driving phases B and C. The driving principles of phases B and C are similar to those of phase A, and reference is made to phase A.

[0030] For phase A, the first to fourth isolation sampling modules are set to respectively collect the first drive signal of the corresponding drive tube to generate the ideal drive signal of the first to fourth drive tube. For the convenience of explanation, the ideal drive signal of the first to fourth drive tube corresponding to phase A is recorded as PWMAn_n_15V, n=1, 2, 3, 4.

[0031] For phase A, the first to fourth drive current amplifying circuit modules are set to respectively collect the first drive signals of the corresponding drive tubes to generate drive reference signals corresponding to the first to fourth drive tubes. For ease of explanation, the drive reference signals corresponding to the first to fourth drive tubes of phase A are recorded as GAn_15V, n=1, 2, 3, 4.

[0032] It should be noted that, in the embodiment of the present application, the driving current amplifying circuit module and the isolation sampling module are configured with a common reference ground. Specifically, for the Nth driving tube of phase A, the Nth isolation sampling module and the Nth driving current amplifying circuit module are set with a common reference ground, N=1, 2, 3, 4. Through this setting, the subsequent comparison isolation compensation circuit module can compare and compensate the driving reference signal and the ideal driving signal for any driving tube.

[0033] Since the ideal drive signal output by the isolation sampling module is equivalent to the PWM wave directly output by the chip, it can be regarded as an ideal waveform, while the drive reference signal output by the drive current amplifier circuit module may be distorted after passing through the drive current amplifier circuit module. Therefore, the ideal drive signal output by the isolation sampling module is more ideal than the PWM waveform output by the drive current amplifier circuit module. Therefore, it is called an ideal drive signal, which does not mean it is absolutely ideal. For example, Figure 7 As shown, compared with the ideal driving signal PWMA1_15V as the reference square wave, the narrow pulse distorted waveform can be divided into four categories: 1. The rising and falling edges slow down, and both have pulse spikes; 2. The rising edge slows down and the waveform is missing, the falling edge slows down and there are pulse spikes; 3. The rising edge slows down and there are pulse spikes, the falling edge slows down and the waveform is missing; 4. The rising and falling edges slow down, and both are missing. The present application makes the driving reference signal and the ideal driving signal have a common reference ground, so that the driving reference signal and the ideal driving signal can be compared and compensated, so that the driving waveform can be corrected to obtain the second driving signal, and the problem that the narrow pulse wave signal near the PWM zero-crossing point is easily distorted is alleviated.

[0034] For example, Figure 8 As shown, an implementation method of an isolated sampling module is provided. The isolated sampling module includes: a voltage divider circuit, a first optical coupler and a MOS tube circuit. Figure 8As shown, the voltage divider circuit includes resistors R26, R28, R29 and transistor Q5, the base of transistor Q5 receives the first drive signal PWMA1_15V through resistor R26, the collector of transistor Q5 is connected to 15V voltage, and the emitter of transistor Q5 is grounded through resistors R28 and R29, wherein the connection node between resistors R28 and R29 is connected to pin No. 2 of the first optocoupler. The base of transistor Q5 is connected to pin No. 3 of the first optocoupler through resistor R27. For the secondary side of the first optocoupler, pins No. 7 and No. 8 are connected to 5V voltage, and pin No. 8 is grounded through resistors R30 and R31, one end of resistor R31 is connected to pin No. 5 of the first optocoupler, and the other end of resistor R31 is also connected to pin No. 6 of the first optocoupler, and a capacitor is also arranged between pins No. 5 and No. 6 of the first optocoupler. The gate of the MOS tube is connected to the sixth pin of the first optocoupler, the drain of the MOS tube is connected to the fifth pin of the first optocoupler through a resistor R33, and the source of the MOS tube is connected to a 15V potential through a resistor R32.

[0035] Based on the above-mentioned isolation sampling module, the first drive signal PWMA1_15V enters the first optocoupler through the voltage divider circuit and is output from the sixth pin of the first optocoupler. At this time, the signal voltage of the sixth pin and the PWMA1_15V signal are reversed, and the MOS tube circuit is set to be reversed again to obtain the ideal drive signal PWMA1_1_15V.

[0036] As an optional implementation, the driving current amplifying circuit module can also be configured as a driving current amplifying circuit module with optical coupling isolation. Exemplarily, the driving current amplifying circuit module includes a second optical coupler and an amplifying circuit, wherein: The primary input end of the second optocoupler receives the first driving signal, the secondary side of the second optocoupler is connected to the amplifier circuit, and the driving reference signal is output through the amplifier circuit. The secondary side of the second optocoupler and the secondary side of the first optocoupler are configured with a common reference ground. Specifically, the secondary side reference ground of the second optocoupler and the secondary side reference ground of the first optocoupler can be set to a common ground. By configuring the secondary side of the second optocoupler and the secondary side of the first optocoupler with a common reference ground, the common reference ground configuration of the driving current amplification circuit module and the isolation sampling module is achieved, so that the comparison isolation compensation circuit module of the subsequent stage can compare and compensate the driving reference signal and the ideal driving signal for any driving tube.

[0037] like Fig. 9 As shown, as an optional implementation, the comparison isolation compensation circuit module includes: A square wave signal memory is configured to latch an ideal driving signal and a driving reference signal; A square wave signal sampling extractor is configured to obtain a maximum amplitude, a maximum amplitude start time, and a maximum amplitude end time of an ideal driving signal and / or a driving reference signal; A maximum amplitude starting time predictor is configured to predict according to the sampling value of the maximum amplitude starting time to obtain a repair prediction value of the starting time of the rising edge, and the repair prediction value of the starting time of the rising edge is used to repair the rising edge of the driving reference signal; A maximum amplitude end time predictor is configured to predict according to the sampled value of the maximum amplitude end time to obtain a repair prediction value of the start time of the falling edge, and the repair prediction value of the start time of the falling edge is used to repair the falling edge of the driving reference signal; an amplitude comparator configured to compare the amplitude of the repaired driving reference signal with the amplitude of the ideal driving signal; an amplitude repairer configured to perform amplitude repair on the repaired driving reference signal based on the comparison result of the amplitude comparator, so that the amplitude of the repaired output signal is consistent with the amplitude of the ideal driving signal; The comparison isolation compensation circuit module outputs a second driving signal, and the second driving signal is a square wave signal with the rising edge and the falling edge starting time repaired and the amplitude repaired.

[0038] Schematically, the comparison isolation compensation circuit module for the first driving tube is taken as an example for description, and the working methods of other comparison isolation compensation circuit modules are similar and will not be described in detail. The details are as follows: The square wave signal memory latches the input signal (including the ideal drive signal PWMA1-1-15V and the drive reference signal GA1_15V) after assigning different address bit information. The square wave signal sampling extractor extracts the maximum amplitude starting time, maximum amplitude ending time, and maximum amplitude sampling of the ideal drive signal PWMA1-1-15V and the drive reference signal GA1_15V stored in the square wave signal memory.

[0039] The maximum amplitude starting time predictor predicts based on the sampling value of the maximum amplitude starting time to obtain a repair prediction value of the starting time of the rising edge, and stores the repair prediction value of the starting time of the rising edge to the corresponding address bit in the square wave signal memory to repair the rising edge of the driving reference signal.

[0040] The maximum amplitude end time predictor predicts based on the sampling value of the maximum amplitude end time to obtain the repair prediction value of the starting time of the falling edge, and stores the repair prediction value of the starting time of the falling edge to the corresponding address bit in the square wave signal memory to repair the falling edge of the driving reference signal.

[0041] The amplitude comparator is used to compare the amplitudes of the ideal driving signal PWMA1-1-15V and the driving reference signal GA1_15V, and the waveforms that are higher or lower than the maximum amplitude of the ideal driving signal PWMA1-1-15V are repaired.

[0042] After the above-mentioned rising edge and falling edge starting time repair and amplitude repair, the comparison isolation compensation circuit module can output a second drive signal, wherein the second drive signal corresponding to the first drive tube of phase A is recorded as GATE_A1 signal.

[0043] As an optional implementation, the driving device further includes an on-resistance R18. The second driving signal GATE_A1 is converted into a driving tube driving signal GA1_1_15V corresponding to the first driving tube through the on-resistance R18, and the driving tube driving signal GA1_1_15V is used to drive the first driving tube to be turned on.

[0044] As an optional implementation, the driving device further includes: a turn-off resistor R19 and a discharge time detection repairer, wherein the second driving signal generates a drive tube driving signal through the turn-off resistor, and the drive tube driving signal is used to drive the inverter drive tube to turn off; the discharge time detection repairer is configured to receive the drive tube driving signal and adjust the discharge time of the corresponding drive tube in the inverter. In this way, the discharge time design can be optimized, which is convenient for efficiently matching the turn-on and turn-off resistances of the IGBT drive tube in the double pulse experiment.

[0045] In order to further illustrate the driving device provided in the embodiment of the present application, the internal functions in the comparison isolation compensation circuit module are described in detail below.

[0046] like Fig.10 As shown, the DSP chip circuit and the CPLD chip circuit are used to realize the function of the comparison isolation compensation circuit module. The square wave signal sampling and extraction is composed of the W11 pin of the DSP chip and the internal circuit of the chip. The PWM square wave latch is composed of the K19 pin of the DSP chip and the internal circuit of the chip. The B16 pin, B17 pin, A17 pin, and B18 pin of the DSP chip are respectively connected to the G13, H13, G12, and F12 pins of the CPLD as signal transmission control connections. The D15 pin of the DSP and the internal circuit of the chip predict the maximum amplitude start time, the A14 pin and the internal circuit of the chip predict the maximum amplitude end time, the C15 and the internal circuit of the chip perform the rising edge start time repair function, and the B14 pin and the internal circuit of the chip perform the falling edge start time repair function.

[0047] The A9 pin of the CPLD and the internal circuit of the chip are used as the feedback signal function of the amplitude comparison circuit. The A10 pin of the CPLD and the internal circuit of the chip are used as the sampling function of the discharge time detection and repair circuit. The A7 pin of the CPLD is used as the second drive signal GATE_A1 output.

[0048] Specifically, Fig.10In the example, the driving reference signal GA1_15V and the ideal driving signal PWMA1-1-15V are respectively transmitted to the D15 and A14 pins of the DSP chip after being sampled and extracted by the square wave signal. The D15 pin of the DSP and the internal circuit of the chip predict the maximum amplitude start time, and the A14 pin of the DSP and the internal circuit of the chip predict the maximum amplitude end time. After the prediction, the C15 pin circuit of the DSP chip repairs the rising edge start time, and the B14 pin circuit of the DSP chip repairs the falling edge start time. The repaired waveform is locked in the K19 pin circuit of the DSP.

[0049] At the same time, the driving reference signal GA1_15V and the ideal driving signal PWMA1-1-15V are compared in amplitude by the amplitude comparison circuit, and then the feedback signal AD_AMP_CPLD is output to the A9 pin circuit of the CPLD chip. The A7 pin of the CPLD and its internal circuit perform square wave signal repair based on the amplitude comparison AD_AMP_CPLD feedback signal of the A9 pin of the CPLD chip and the latch signal in the K19 pin circuit of the DSP, thereby outputting the second driving signal GATE_A1.

[0050] Further, such as Fig.11 As shown, it exemplarily shows an implementation method of an amplitude comparator. The amplitude comparator includes a first operational amplifier and a second operational amplifier. Among them, the positive and negative power supply terminals of the first operational amplifier are respectively connected to ±15V voltages, the in-phase input terminal of the first operational amplifier receives the ideal drive signal PWMA1-1-15V, the inverting input terminal receives the drive reference signal GA1_15V, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit. The output terminal of the first operational amplifier is also connected to the in-phase input terminal of the second operational amplifier through a resistor R37, the output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs the AD_AMP_CPLD signal through a resistor R39. Among them, the connection node between the resistor R37 and the in-phase input terminal of the second operational amplifier is grounded through an RC parallel circuit, and the resistor R39 is grounded through a capacitor C4.

[0051] The present invention can not only reduce the generation of distorted narrow pulse signals and reduce the risk of Vce overvoltage pulses caused by distorted voltage signals damaging the IGBT, but also make the Vce pulse voltages and voltage stresses of different IGBTs uniform, making it easier for design engineers to efficiently match the on-resistance and off-resistance of the IGBT driver tube in double pulse experiments.

[0052] As an optional implementation, the discharge time detection repairer includes: a discharge time detection circuit. Fig.12As shown, the discharge time detection circuit includes: a voltage regulator diode, a diode and an RC circuit. Among them, one end of the resistor R40 receives the driving tube drive signal GA1_1_15V, the other end of the resistor R40 is connected to the cathode of the voltage regulator diode ZD1, the anode of the voltage regulator diode ZD1 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to one end of the resistor R41, the other end of the resistor R41 is grounded through the RC parallel circuit, and the connection node between the resistor R41 and the RC parallel circuit is used as the output port of the discharge time detection circuit, which is used to output the discharge time feedback signal AD_DT_CPLD. The discharge time (that is, the turn-off time of the IGBT) can be detected by the discharge time detection circuit, which is conducive to further determining the resistance value of the turn-off resistor adapted by the IGBT. In this embodiment, from another perspective, by setting the voltage regulator tube ZD1, the current size of the discharge time detection circuit is changed by the selection of ZD1, so that the discharge time can be slowed down or accelerated, which is conducive to determining the resistance value of the turn-off resistor adapted by the IGBT. By setting up an RC circuit and designing the parameters of the RC circuit, the current size of the discharge time detection circuit can also be changed, thereby slowing down or accelerating the discharge time to achieve the same effect.

[0053] As an optional implementation, Fig.13 As shown, the discharge time detection repairer also includes a discharge time adjustment circuit, and the discharge time adjustment circuit includes: A triode, the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and a capacitor is connected in parallel at both ends of the grounding resistor; A first input terminal, the first input terminal receives a driving signal GA1_1_15V of the driving transistor, and the first input terminal is electrically connected to the base of the transistor through a resistor R43; The second input terminal receives the discharge control signal DT_C_CPLD, and the second input terminal is electrically connected to the base of the transistor through a resistor R44 and a diode D2, wherein the discharge control signal DT_C_CPLD is generated based on the discharge time feedback signal AD_DT_CPLD. Specifically, the CPLD controls the output DT_C_CPLD signal to be high or low level according to the discharge time feedback signal AD_DT_CPLD, thereby achieving the function of controlling whether the transistor Q5 is turned on or off, and by controlling the on / off of the transistor Q5, it plays the role of accelerating / slowing down the discharge time of the drive tube drive signal GA1_1_15V. In this embodiment, the IGBT turn-off signal enters the discharge time adjustment circuit to optimize the discharge time design, which further facilitates the design engineer to efficiently match the resistance value of the turn-off resistor of the IGBT drive tube in the double pulse experiment.

[0054] The present application also provides an inverter, comprising an inverter unit and the driving device as described above, wherein the driving device is used to drive a driving tube in the inverter unit.

[0055] In this technical solution, since the inverter adopts the inverter driving device of any one of the above technical solutions, it has all the beneficial effects of the inverter driving device, which will not be described in detail here.

[0056] The above disclosure is only the preferred embodiment of the present application, but it is not intended to limit the scope of rights of the present application. A person of ordinary skill in the art can understand that without departing from the spirit and scope of the present application and the appended claims, changes, modifications, substitutions, combinations, and simplifications should all be equivalent replacement methods and still fall within the scope of the invention.

Claims

1. An inverter driving device, applied to a three-level inverter, characterized in that: The driving device comprises: A driving signal generating module, configured to generate a first driving signal; an isolation sampling module, configured to sample the first driving signal to obtain an ideal driving signal; a driving current amplifying circuit module, wherein the driving current amplifying circuit module and the isolation sampling module are configured with a common reference ground, and the driving current amplifying circuit module is configured to receive the first driving signal and generate a driving reference signal based on the first driving signal; The comparison isolation compensation circuit module is configured to compare and compensate the ideal driving signal and the driving reference signal to obtain a second driving signal, and the inverter is driven based on the second driving signal.

2. The inverter driving device according to claim 1, characterized in that: The isolation sampling module comprises: A voltage divider circuit, a first optical coupler and a MOS tube circuit, wherein: The voltage divider circuit receives the first drive signal, and the output end of the voltage divider circuit is connected to the primary side of the first optocoupler, the first optocoupler is configured as a logic gate circuit output type first optocoupler, the secondary side of the first optocoupler outputs an intermediate signal that is opposite to the first drive signal, and the intermediate signal is inverted by the MOS tube circuit to obtain the ideal drive signal.

3. The inverter driving device according to claim 1, characterized in that: The driving current amplifying circuit module includes a second optical coupler and an amplifying circuit, wherein: The primary input end of the second optocoupler receives the first drive signal, the secondary side of the second optocoupler is connected to the amplifier circuit, the drive reference signal is output through the amplifier circuit, and the secondary side of the second optocoupler is configured with a common reference ground as the secondary side of the first optocoupler.

4. The inverter driving device according to claim 1, characterized in that: The driving signal generating module comprises: A PWM drive signal generating circuit is configured to generate a PWM drive signal; A level conversion circuit is configured to convert the PWM drive signal into a drive voltage adapted to a drive tube of an inverter; The logic gate circuit is configured to invert the output timing of the level conversion circuit to obtain the first driving signal.

5. The inverter driving device according to any one of claims 1 to 4, characterized in that: The comparison isolation compensation circuit module comprises: A square wave signal memory configured to latch the ideal driving signal and the driving reference signal; A square wave signal sampling extractor is configured to sample and extract the maximum amplitude, the maximum amplitude starting time and the maximum amplitude ending time of the ideal driving signal and / or the driving reference signal; a maximum amplitude starting time predictor, configured to predict according to the sampling value of the maximum amplitude starting time of the ideal driving signal to obtain a repair prediction value of the starting time of the rising edge, wherein the repair prediction value of the starting time of the rising edge is used to repair the rising edge of the driving reference signal; a maximum amplitude end time predictor, configured to predict according to the sampled value of the maximum amplitude end time of the ideal drive signal to obtain a repair prediction value of the start time of the falling edge, wherein the repair prediction value of the start time of the falling edge is used to repair the falling edge of the drive reference signal; an amplitude comparator configured to compare the amplitude of the driving reference signal with the amplitude of the ideal driving signal; an amplitude repairer configured to perform amplitude repair on the edge-repaired driving reference signal based on the comparison result of the amplitude comparator, so that the amplitude of the repaired output signal is consistent with the amplitude of the ideal driving signal; The comparison isolation compensation circuit module outputs the second drive signal, which is a square wave signal with the rising edge and the falling edge starting time repaired and the amplitude repaired.

6. The inverter driving device according to claim 5, characterized in that: The amplitude comparator comprises a first operational amplifier and a second operational amplifier, wherein the non-inverting input terminal of the first operational amplifier receives the ideal driving signal, the inverting input terminal receives the driving reference signal, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the first operational amplifier through an RC parallel circuit; The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the output terminal of the second operational amplifier is connected to the inverting input terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs a feedback signal through a resistor; The amplitude repairer performs amplitude repair on the edge-repaired driving reference signal based on the feedback signal.

7. The inverter driving device according to claim 5, characterized in that: The driving device also includes an on-resistance and an off-resistance; The second driving signal generates a driving tube driving signal through the turn-on resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn on; The second driving signal generates a driving tube driving signal through the turn-off resistor, and the driving tube driving signal is used to drive the inverter driving tube to turn off; The comparison isolation compensation circuit module also includes: The discharge time detection and repair device is configured to receive the drive tube driving signal and adjust the discharge time of the corresponding drive tube in the inverter.

8. The inverter driving device according to claim 7, characterized in that: The discharge time detection repair device comprises: A discharge time detection circuit, the discharge time detection circuit comprises: a voltage stabilizing diode, a diode and an RC circuit, wherein the drive tube driving signal passes through the voltage stabilizing diode, the diode and the RC circuit in sequence, and then outputs a discharge time feedback signal at the high potential end of the RC circuit.

9. The inverter driving device according to claim 8, characterized in that: The discharge time detection repairer also includes: The discharge time adjustment circuit comprises: A triode, wherein the emitter of the triode is grounded, the base of the triode is grounded through a resistor, and a capacitor is connected in parallel to both ends of the grounding resistor; A first input terminal, the first input terminal receives the driving signal of the driving tube, and the first input terminal is electrically connected to the base of the transistor through a resistor; A second input terminal, the second input terminal receives a discharge control signal, and the second input terminal is electrically connected to the base of the transistor through a resistor and a diode, wherein the discharge control signal is generated based on the discharge duration feedback signal.

10. An inverter, characterized in that: It comprises an inverter unit and a driving device as claimed in any one of claims 1 to 9, wherein the driving device is used to drive a driving tube in the inverter unit.

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