Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a first bit line extending in a first direction; a first transistor configured to include a first gate and a first active region, the first gate extending in a second direction perpendicular to the first direction; a second bit line extending in the first direction; and a second transistor configured to include a second active region connected to the second bit line and a second gate overlapping the second active region. The first active region includes: a horizontal portion configured to contact the first bit line; and a vertical portion contacting the horizontal portion and extending in a third direction perpendicular to each of the first direction and the second direction. The second gate contacts the vertical portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0146105, filed on October 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Techniques and embodiments disclosed in the present disclosure relate generally to semiconductor devices, and more particularly to semiconductor devices including memory cells. Background Art

[0004] As miniaturization and higher integration of semiconductor devices have become major issues, memory cells included in semiconductor devices may be formed to have a three-dimensional (3D) pattern. Miniaturized memory cells having a three-dimensional (3D) pattern may be provided with a configuration that improves operating characteristics of the memory cells. Summary of the invention

[0005] Various embodiments of the present disclosure are directed to a semiconductor memory device including two transistors and having a higher degree of integration.

[0006] Various embodiments of the present disclosure are directed to a semiconductor memory device that prevents signal interference between word lines.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a first bit line extending in a first direction; a first transistor configured to include a first gate and a first active region, the first gate extending in a second direction perpendicular to the first direction; a second bit line extending in the first direction; and a second transistor configured to include a second active region connected to the second bit line and a second gate overlapping the second active region. The first active region may include: a horizontal portion configured to contact the first bit line; and a vertical portion contacting the horizontal portion and extending in a third direction perpendicular to each of the first direction and the second direction. The second gate may contact the vertical portion.

[0008] In some embodiments, the first gate may be connected to a first word line.

[0009] In some embodiments, the semiconductor device may further include a second word line extending along the second direction, wherein the second word line is connected to the second active region.

[0010] In some embodiments, the second transistor may be configured to share the second active region with another adjacent second transistor.

[0011] In some embodiments, second gates of the shared second active region included in the second transistors may contact vertical portions of different first transistors, respectively.

[0012] In some embodiments, a source region and / or a drain region of the first transistor may be included in the first active region, and a source region and / or a drain region of the second transistor may be included in the second active region.

[0013] In some embodiments, the source region and / or drain region of the first transistor may be connected to the second gate or the first bit line, and the source region and / or drain region of the second transistor may be connected to the second bit line or the second word line extending along the second direction.

[0014] In some embodiments, the semiconductor device may further include a plurality of memory cells, each memory cell including two first transistors and two second transistors.

[0015] In some embodiments, the two first transistors may be connected to each other in parallel; and the two second transistors may be connected to each other in series.

[0016] In some embodiments, each of the first active region and the second active region may include indium gallium zinc oxide (IGZO).

[0017] In some embodiments, the semiconductor device may further include a third gate disposed between vertical portions respectively included in adjacent first active regions and extending along the second direction.

[0018] In some embodiments, the third gate may be configured to receive a ground voltage as an input.

[0019] In some embodiments, the first gate may include a first sub-gate and a second sub-gate extending along the second direction; and the vertical portion may be disposed between the first sub-gate and the second sub-gate.

[0020] In some embodiments, the same activation voltage may be provided to the first sub-gate and the second sub-gate.

[0021] In some embodiments, the semiconductor device may further include: a first gate insulating layer disposed between the first gate and the first active region; and a second gate insulating layer disposed between the second gate and the second active region.

[0022] In some embodiments, the second active region may be connected to the second bit line via a via contact.

[0023] According to another embodiment of the present disclosure, a semiconductor device may include: a first bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a first active region configured to include a vertical portion extending along a third direction perpendicular to each of the first direction and the second direction, and a horizontal portion extending along the first direction and contacting the first bit line; a first gate insulating layer disposed between the first gate and the first active region; a second gate configured to contact the vertical portion; a second gate insulating layer disposed on the second gate; a second active region disposed on the second gate insulating layer; a second bit line extending along the first direction and connected to the second active region; and a second word line extending along the second direction and connected to the second active region.

[0024] In some other embodiments, the semiconductor device may further include: another first active region, which is configured to contact the first bit line and has the same shape as the first active region; and another second gate, which is configured to contact the other first active region, wherein a second gate insulation layer is disposed between the second active region and the other second gate.

[0025] In some other embodiments, the semiconductor device may further include: another first gate extending along the second direction; and another first gate insulating layer disposed between the another first gate and the another first active region.

[0026] In some other embodiments, the semiconductor device may further include a third gate, which is disposed between the first active region and another first active region and extends along the second direction.

[0027] In some other embodiments, the semiconductor device may further include another second word line extending along the second direction and connected to the second active region.

[0028] It is to be understood that both the foregoing general description of the disclosed embodiments and the following detailed description are illustrative and descriptive and are intended to provide further description of the embodiments of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features and advantageous aspects of the embodiments of the present disclosure will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0030] Figure 1A is a schematic perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 1B is a schematic perspective view showing a semiconductor device according to another embodiment of the present disclosure.

[0032] Figure 2Ais a diagram showing an embodiment of the present disclosure Figure 1A A cross-sectional view of the semiconductor device taken along a first cutting line is shown.

[0033] Figure 2B is a diagram showing another embodiment of the present disclosure. Figure 1B A cross-sectional view of the semiconductor device taken along a second cutting line is shown.

[0034] Figure 3 An equivalent circuit diagram of a memory cell included in a semiconductor device according to an embodiment of the present disclosure is shown.

[0035] FIG. 4A to FIG. 4Q is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0036] FIG. 5A to FIG. 5M is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The present disclosure provides embodiments and examples of semiconductor devices including memory cells, which can be used in configurations to substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other semiconductor devices. Some embodiments of the present disclosure relate to a semiconductor memory device including two transistors and having a higher degree of integration. Some embodiments of the present disclosure relate to a semiconductor memory device that prevents signal interference between word lines. Recognizing the above problems, embodiments of the present disclosure can provide a semiconductor device having a three-dimensional (3D) channel to improve integration. In addition, embodiments of the present disclosure can provide a semiconductor device having at least one transistor that operates as a storage element, resulting in a simplified manufacturing process.

[0038] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used throughout the drawings to represent the same or similar components. Although the present disclosure is capable of various modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0039] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to specific embodiments, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized.

[0040] In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted to avoid obscuring the present subject matter.

[0041] The terms used herein are only used for the purpose of describing specific embodiments, and are not intended to limit the scope of the present disclosure. As used herein, the singular form is also intended to include the plural form, unless the context clearly states otherwise. It will also be understood that the terms "include", "comprise", "comprises" and / or "comprises" when used in this specification specify the existence of the stated constituent elements, steps, operations and / or parts, but do not exclude the existence or addition of one or more other constituent elements, steps, operations and / or their parts. The term "and / or" can include a combination of multiple items or any one of multiple items.

[0042] Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0043] Figure 1A is a schematic perspective view showing a semiconductor device 100 a according to an embodiment of the present disclosure.

[0044] Figure 1B is a schematic perspective view showing a semiconductor device 100 b according to another embodiment of the present disclosure.

[0045] The structures of the semiconductor devices 100a and 100b will be referred to below. Figure 1A and Figure 1B A description will be given, but its redundant description will be omitted here.

[0046] Each of the semiconductor devices 100a, 100b may include a substrate LS and a plurality of memory cells formed on the substrate LS and repeatedly arranged on the substrate LS. Each of the memory cells may have a three-dimensional (3D) structure.

[0047] More specifically, each memory cell included in the semiconductor devices 100 a , 100 b may include a first transistor TR1 and a second transistor TR2 .

[0048] The substrate LS may be a material suitable for semiconductor processing. The substrate LS may include at least one of a conductive material, an insulating material (also referred to as a dielectric material), and a semiconductor material (also referred to as a semiconductive material). In some embodiments, a plurality of material layers may be formed on the substrate LS.

[0049] The substrate LS may include a semiconductor material. For example, the substrate LS may be formed of a semiconductor material containing silicon. The substrate LS may include silicon, single crystal silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate LS may also include other semiconductor materials, such as germanium. The substrate LS may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs.

[0050] The substrate LS may include a silicon-on-insulator (SOI) substrate. In another embodiment, the substrate LS may include a peripheral circuit region (not shown) located at a lower portion thereof. The peripheral circuit region may include a plurality of control circuits for controlling the memory cells. At least one control circuit in the peripheral circuit region may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit region may include an address decoder circuit, a read circuit, a write circuit, etc.

[0051] At least one control circuit included in the peripheral circuit region may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), and the like.

[0052] At least one control circuit included in the peripheral circuit region may be electrically connected to the bit lines BL1, BL2, the first gate G1, or the second word line WL2. The peripheral circuit region may include a sense-amp, which may be electrically connected to the bit lines BL1, BL2. Although not shown, a multi-level metal interconnection may be provided between the substrate LS and the memory cell. The peripheral circuit region, the bit lines BL1, BL2, the first gate G1, or the second word line WL2 may be connected to each other through a multi-layer metal interconnection (MLM).

[0053] refer to Figure 1A According to an embodiment, the first transistor TR1 may include a first gate G1, a first active region ACT1, and a third gate G3. The second transistor TR2 may include a second gate G2 and a second active region ACT2.

[0054] The first active region ACT1 included in the first transistor TR1 may be connected to a first bit line BL1 extending in the first direction D1 and may be connected to a second gate G2 included in the second transistor TR2 .

[0055] The first gate G1 may extend in a second direction D2 perpendicular to the first direction D1. The first gate G1 may be connected to a first word line (not shown).

[0056] The third gate G3 may extend in the second direction D2 and may be disposed between vertical portions respectively included in two adjacent first active regions ACT1 .

[0057] Each of the first gates G1 may be connected to a first word line (not shown), and may receive an activation voltage corresponding to a word line activation signal from the first word line.

[0058] The third gate G3 can work as a back gate to block interference between adjacent first gates G1.

[0059] For example, the third gate G3 may include metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof.

[0060] The first active region ACT1 may include a horizontal portion connected to the first bit line BL1 and a vertical portion extending in a third direction D3 perpendicular to the second direction D2. The vertical portion may contact the horizontal portion on one side thereof and may contact the second gate G2 on the other side thereof. For example, the first active region ACT1 may include one horizontal portion and two vertical portions.

[0061] The second gate G2 may be in contact with one vertical portion. In addition, the second gate G2 may be arranged in a matrix structure on one surface of the substrate LS, and may be arranged at a position corresponding to each vertical portion.

[0062] The second active region ACT2 included in the second transistor TR2 may be located above the second gate G2 and may be electrically isolated from the second gate G2.

[0063] The second active region ACT2 may be connected to a second bit line BL2 extending in the first direction D1 and may be connected to a second word line WL2 extending in the second direction D2.

[0064] The second active region ACT2 and the second bit line BL2 may be connected via at least one via contact C.

[0065] The active regions ACT1, ACT2 and the gates G1, G2, G3 may be electrically isolated from each other by an insulating layer (not shown). In addition, the gates G1, G2, G3, the bit lines BL1, BL2 and the second word line WL2 may be electrically isolated from each other by an insulating layer (not shown).

[0066] The insulating layer may include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. In some other embodiments, the insulating layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, etc., or may include SiCO, etc.

[0067] The composition of the insulating layers may be different depending on the location of the insulating layers. For example, the insulating layer disposed between the first gates G1 may include silicon oxide, and the insulating layer disposed between the first gates G1 and the first active area ACT1 may include a high-k material.

[0068] Each of the first and second bit lines BL1 and BL2 may include a conductive material.

[0069] Each bit line BL1, BL2 may include a silicon-based material, a metal-based material, or a combination thereof. Each bit line BL1, BL2 may include polysilicon, metal, metal nitride, metal silicide, or a combination thereof.

[0070] Each of the bit lines BL1 and BL2 may include polysilicon, titanium nitride, tungsten (W), or a combination thereof. For example, the bit lines BL1 and BL2 may include titanium nitride (TiN) or polysilicon doped with N-type impurities.

[0071] Each of the bit lines BL1 , BL2 may include a stack structure (TiN / W) of titanium nitride (TiN) and tungsten (W). Each of the bit lines BL1 , BL2 may further include an ohmic contact layer formed of, for example, metal silicide.

[0072] The first and second bit lines BL1 and BL2 may be located over the substrate LS and may be horizontally oriented in a first direction D1 .

[0073] Each of the first and second bit lines BL1 and BL2 may be referred to as a laterally oriented bit line or a laterally extending bit line.

[0074] A plurality of first transistors TR1 arranged in the first direction D1 may share one first bit line BL1. Also, a plurality of second transistors TR2 arranged in the first direction D1 may share one second bit line BL2.

[0075] The plurality of first transistors TR1 arranged in the second direction D2 may share a first gate G1 extending in the second direction D2. In addition, the plurality of second transistors TR2 arranged in the second direction D2 may share one second word line WL2.

[0076] Each of the first gate G1 and the second word line WL2 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof.

[0077] The first gate G1 may extend in a direction perpendicular to the bit line BL1 , and the second word line WL2 may extend in a direction perpendicular to the bit line BL2 .

[0078] Each of the first active region ACT1 and the second active region ACT2 may include a semiconductor material or an oxide semiconductor material. Each of the active regions ACT1, ACT2 may include a plurality of impurity regions. Each impurity region may include a source region and / or a drain region of each transistor TR1, TR2.

[0079] Each of the active regions ACT1, ACT2 may include doped polysilicon, undoped polysilicon, amorphous silicon, IGZO (amorphous indium gallium zinc oxide semiconductor), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO3), and the like.

[0080] refer to Figure 1B According to another embodiment, the first transistor TR1 may include a first sub-gate SG1 and a first active region ACT1. The second transistor TR2 may include a second gate G2 and a second active region ACT2.

[0081] The first active region ACT1 included in the first transistor TR1 may be connected to a first bit line BL1 extending in the first direction D1 and may be connected to a second gate G2 included in the second transistor TR2 .

[0082] and Figure 1A The embodiments shown are different. Figure 1B The first transistor TR1 shown may include a first sub-gate SG1 and a second sub-gate SG2 extending in a second direction D2 perpendicular to the first direction D1. Figure 1B In the embodiment of the present invention, the paired first sub-gate SG1 and the second sub-gate SG2 may correspond to Figure 1A The first gate G1 is shown in FIG. Figure 1B The pair of first sub-gate SG1 and second sub-gate SG2 shown in FIG. Figure 1A The first gate G1 shown in FIG.

[0083] exist Figure 1B In the embodiment of the present invention, the pair of first sub-gate SG1 and second sub-gate SG2 may be connected to a first word line (not shown). The pair of first sub-gate SG1 and second sub-gate SG2 may receive an activation voltage corresponding to a word line activation signal from the first word line.

[0084] The first transistor TR1 including the two sub-gates SG1 , SG2 may be referred to as a double-gate transistor.

[0085] Since the first transistor TR1 includes two sub-gates SG1 and SG2, the first word line WL1 can be provided as a double gate structure. Since the first word line WL1 has a double gate structure, a channel region can be formed on both sides of the vertical portion included in the first active region ACT1. Since two channel regions are formed, the electron mobility in the channel region can be increased, and the semiconductor device can be controlled to have increased electron mobility at a low activation voltage.

[0086] The shape of the first active region ACT1 and the shape of the second transistor TR2 are similar to the reference Figure 1AThe shapes in the embodiments are the same, so for the sake of brevity, redundant descriptions thereof will be omitted here.

[0087] Similarly, the connection relationship between transistors TR1, TR2 and bit lines BL1, BL2 is the same as that of reference 1. Figure 1A The connection relationship in the embodiments is the same, so for the sake of brevity, the redundant description thereof will be omitted here.

[0088] Figure 2A is a diagram showing the Figure 1A FIG. 2 is a cross-sectional view 200 a of a semiconductor device taken along a first cutting line AA′ shown in FIG.

[0089] Reference Figure 2A , the semiconductor device may include a substrate layer 210 , a first interlayer insulating layer 220 formed over the substrate layer 210 , and a second interlayer insulating layer 230 formed over the first interlayer insulating layer 220 .

[0090] The substrate layer 210 may include a silicon semiconductor material, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, etc.

[0091] The substrate layer 210 may include a plurality of control circuits configured to control the operation of the semiconductor device. The region of the substrate layer 210 where the control circuits are disposed may be referred to as a peripheral circuit region.

[0092] The first interlayer insulating layer 220 formed over the substrate layer 210 may include a metal silicide material such as cobalt silicide (CoSi). The first interlayer insulating layer 220 is provided in the semiconductor device so that the operating resistance of the semiconductor device can be reduced.

[0093] The first interlayer insulating layer 220 may protect the substrate layer 210. The first interlayer insulating layer 220 may prevent damage to the substrate layer 210 during a semiconductor manufacturing process.

[0094] The second interlayer insulating layer 230 may include a layer including silicon nitride. Since the second interlayer insulating layer 230 includes silicon nitride, damage to the substrate layer 210 may be prevented during a high-temperature semiconductor manufacturing process.

[0095] The third interlayer insulating layer 240 may be disposed on the second interlayer insulating layer 230. The third interlayer insulating layer 240 may include silicon oxide, etc., may function as an insulating layer together with the second interlayer insulating layer 230, and may electrically isolate the control circuit included in the substrate layer 210 from the first bit line 250.

[0096] The first bit line 250 disposed on the third interlayer insulating layer 240 may include a plurality of layers. For example, the first bit line 250 may include a first sub bit line layer 252 including titanium nitride (TiN), a second sub bit line layer 254 including tungsten (W), and a third sub bit line layer 256 including titanium nitride (TiN).

[0097] Since the first bit line 250 includes a plurality of layers, the operating resistance of the semiconductor device may be adjusted.

[0098] After depositing a plurality of layers, the first bit line 250 may be formed through an etching process using a mask.

[0099] Adjacent first bit lines 250 may be electrically isolated from each other by a first bit line isolation layer (not shown). The first bit line isolation layer may include a plurality of layers including silicon nitride or silicon oxide.

[0100] A fourth interlayer insulating layer 260 and a fifth interlayer insulating layer 270 may be disposed over the first bit line 250 .

[0101] Each of the fourth interlayer insulating layer 260 and the fifth interlayer insulating layer 270 may include a layer including at least one of silicon oxide, carbon-containing silicon oxide, and silicon nitride.

[0102] Since the fourth interlayer insulating layer 260 and the fifth interlayer insulating layer 270 are provided in the semiconductor device, the third gate 280 and the first bit line 250 may be electrically isolated from each other.

[0103] The third gate 280 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the third gate 280 may include titanium nitride. Figure 1A The second direction D2 shown in FIG.

[0104] The sixth interlayer insulating layer 290 may be disposed on the third gate 280. The sixth interlayer insulating layer 290 may be used as a mask (hereinafter referred to as an etching mask) for an etching process required to form the third gate 280. The sixth interlayer insulating layer 290 may include, for example, silicon nitride.

[0105] The third gate insulating layer 300 may be disposed at a sidewall of the vertical portion included in the first active region 310 , and may electrically isolate the third gate 280 from the vertical portion.

[0106] The third gate insulating layer 300 may include, for example, silicon oxide.

[0107] The third gate insulating layer 300 may be formed along the sidewall of the third gate 280 and may be formed at Figure 1A Extends in the second direction D2 shown in .

[0108] At least a portion of the first active region 310 may be disposed to contact the first bit line 250. A horizontal portion included in the first active region 310 may contact the first bit line 250.

[0109] The first active region 310 may include two vertical portions and one horizontal portion. The vertical portion may be formed along Figure 1A The third party shown in FIG. 1 extends in the direction D3.

[0110] The first active region 310 including two vertical portions and one horizontal portion may be Figure 1A The arrangement is repeated in a matrix structure in the first direction D1 and the second direction D2 as shown in FIG.

[0111] For example, the first active region 310 may include an oxide semiconductor material. The oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0112] According to another embodiment, the first active region 310 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0113] Since IGZO has a low leakage current characteristic and the first active region 310 is formed of IGZO, a semiconductor device with low standby power can be realized. In addition, using IGZO for the first active region 310 reduces the difficulty of the manufacturing process, and the first active region 310 having a three-dimensional (3D) structure including a vertical portion and a horizontal portion can be easily formed.

[0114] The source region and the drain region of the first transistor TR1 may be disposed in the first active region 310. When an activation voltage is supplied to the first gate 330 of the first transistor TR1, a channel region may be formed in the first active region 310 so that electron movement may occur between the source region and the drain region.

[0115] The first gate insulating layer 320 may be disposed between the first active region 310 and the first gate 330. For example, the first gate insulating layer 320 may include silicon oxide. The first gate 330 and the first active region 310 may be electrically isolated from each other by the first gate insulating layer 320.

[0116] The first gate 330 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 330 and the third gate 280 may include titanium nitride. Figure 1A The second direction D2 shown in FIG.

[0117] When the activation voltage is supplied to the first gate 330, the ground voltage may be supplied to the third gate 280. For example, the activation voltage may be a first word line activation voltage. The first gate 330 may function as a first word line.

[0118] When a ground voltage is supplied to the third gate 280 , the third gate 280 may supply a reverse bias voltage to the semiconductor device.

[0119] The third gate 280 may be disposed between two adjacent first gates 330 and the first active region 310 corresponding to the first gates 330 .

[0120] When the local voltage is supplied to the third gate 280 , adjacent first gates 330 may be electrically isolated from each other.

[0121] Such electrical isolation between adjacent first gates 330 may mean that electrical interference between adjacent first gates 330 is blocked.

[0122] As the size of the semiconductor device is reduced, the distance between the first gates 330 becomes shorter. When the distance between the first gates 330 becomes shorter, a coupling phenomenon may occur between adjacent first gates 330 due to the first word line activation voltage supplied to each first gate 330. Due to the coupling phenomenon, unexpected errors may occur during data read / write operations of the semiconductor device.

[0123] In some embodiments, the third gate 280 is disposed between the first gates 330 and a ground voltage is supplied to the third gate 280 , so that a coupling phenomenon between the first gates 330 is prevented, thereby improving operation characteristics of the semiconductor device.

[0124] In addition, the third gate 280 supplied with the ground voltage may provide a reverse bias voltage to the semiconductor device, thereby effectively suppressing leakage current (eg, gate induced drain leakage (GIDL), etc.) and improving electrical characteristics of the semiconductor device.

[0125] The seventh interlayer insulating layer 340 may include an insulating layer disposed between two adjacent first gate electrodes 330. The adjacent first gate electrodes 330 may be electrically isolated from each other by the seventh interlayer insulating layer 340. For example, the seventh interlayer insulating layer 340 may include silicon oxide, silicon nitride, or the like.

[0126] The second gate 350 may be disposed to contact one side of a vertical portion included in the first active region 310. The second gate 350 may include a plurality of layers.

[0127] For example, the second gate 350 may include a lower gate layer 352 and an upper gate layer 354 .

[0128] The lower gate layer 352 may include the same material as the first active region 310. For example, the lower gate layer 352 may include an oxide semiconductor such as IGZO.

[0129] Since the lower gate layer 352 includes the same material as the first active region 310 , an interface resistance between the second gate 350 and the first active region 310 may be reduced.

[0130] The upper gate layer 354 formed on the lower gate layer 352 may include a conductive material such as a metal nitride material or a metal material. Operation characteristics (eg, active voltage, etc.) of the second transistor TR2 may be controlled by adjusting characteristics of constituent materials included in the upper gate layer 354 .

[0131] The eighth interlayer insulating layer 360 may electrically isolate adjacent second gate electrodes 350 from each other. The eighth interlayer insulating layer 360 may be formed to surround each second gate electrode 350 , and may be disposed between the second gate electrodes 350 .

[0132] The eighth interlayer insulating layer 360 may include, for example, silicon nitride or silicon oxide.

[0133] The second gate insulating layer 370 may include an insulating layer formed on the second gate 350. The second gate insulating layer 370 may be arranged to overlap the second gate 350 and may include silicon oxide. The second gate 350 and the second active region 380 may be electrically isolated from each other by the second gate insulating layer 370.

[0134] Each second active region 380 may be shared by two adjacent second transistors TR2. Figure 2A As can be seen in FIG. 1 , one second active region 380 may overlap with two second gates 350 , and activation voltages may be provided to the second gates 350 at different time points.

[0135] The source and drain regions of the second transistor TR2 may be disposed in each second active region 380. When an activation voltage is supplied to the second gate 350 of the second transistor TR2, a channel region may be formed in each second active region 380 so that electron movement may occur between the source and drain regions of the second active region 380.

[0136] In some embodiments, since each second transistor TR2 is formed in a vertical shape, the second transistor TR2 can be easily stacked in a small area. In addition, since the second transistor TR2 is used instead of a capacitor as a data storage element, the process of forming the data storage element can be simplified and the degree of freedom of the layout structure of the semiconductor device can be improved.

[0137] The ninth interlayer insulating layer 390 may electrically isolate the adjacent second active regions 380 from each other. The ninth interlayer insulating layer 390 may include, for example, silicon nitride or silicon oxide.

[0138] At least one second word line 400 and at least one first via contact 410 may be formed by etching the ninth interlayer insulating layer 390. Each second word line 400 and each first via contact 410 may include a conductive material such as a metal or a metal nitride. The first via contact 410 may penetrate the ninth interlayer insulating layer 390 in the vertical direction D3.

[0139] The second word line 400 may be Figure 1A The first through-hole contacts 410 may be repeatedly arranged in the first direction D1 and the second direction D2, and each of the second active regions 380 may be connected to the first through-hole contact 410 corresponding thereto.

[0140] The tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430 may be located over the ninth interlayer insulating layer 390. The tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430 may electrically isolate the second bit line 450 from the second word line 400.

[0141] Providing the tenth and eleventh interlayer insulating layers 420 and 430 in the semiconductor device may prevent damage to the semiconductor device during formation of the second bit line 450. Each of the tenth and eleventh interlayer insulating layers 420 and 430 may include a layer containing silicon oxide or silicon nitride.

[0142] Each second via contact 440 may penetrate the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430 in the vertical direction D3. Each second via contact 440 may include a conductive material such as metal or metal nitride and may electrically connect the second bit line 450 to the second active region 380.

[0143] The second bit line 450 may include Figure 2A The single layer shown may include multiple layers including a conductive material. The conductive material may include any suitable conductive material, such as, for example, metal nitrides, metals, and the like.

[0144] Figure 2B is a diagram showing another embodiment according to the present disclosure Figure 1B The cross-sectional view 200 b of the example semiconductor device is taken along the second cutting line BB′.

[0145] refer to Figure 2B, the semiconductor device may include a substrate layer 510 , a first interlayer insulating layer 520 formed on the substrate layer 510 , and a second interlayer insulating layer 530 formed on the first interlayer insulating layer 520 .

[0146] The substrate layer 510 may include a silicon semiconductor material, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, etc.

[0147] The substrate layer 510 may include a plurality of control circuits configured to control one or more operations of the semiconductor device. The region in the substrate layer 510 where the control circuits are disposed may be referred to as a peripheral circuit region.

[0148] The first interlayer insulating layer 520 may include a metal silicide material such as cobalt silicide (CoSi). The first interlayer insulating layer 220 may reduce the operating resistance of the semiconductor device.

[0149] The first interlayer insulating layer 520 may protect the substrate layer 210. The first interlayer insulating layer 520 may prevent damage to the substrate layer 210 during a semiconductor manufacturing process.

[0150] The second interlayer insulating layer 530 may include a layer including silicon nitride. By including silicon nitride, the second interlayer insulating layer 530 may prevent damage to the substrate layer 510 during a high-temperature semiconductor manufacturing process.

[0151] The third interlayer insulating layer 540 may be disposed on the second interlayer insulating layer 530. The third interlayer insulating layer 540 may include a layer including silicon oxide or the like, may function as an insulating layer together with the second interlayer insulating layer 530, and may electrically isolate the control circuit included in the substrate layer 210 from the first bit line 250.

[0152] The first bit line 550 may be disposed on the third interlayer insulating layer 540. The first bit line 550 may include a plurality of layers. For example, the first bit line 550 may include a first sub bit line layer 552 including titanium nitride (TiN), a second sub bit line layer 554 including tungsten (W), and a third sub bit line layer 556 including titanium nitride (TiN).

[0153] Forming the first bit line 550 including a plurality of layers allows the operating resistance of the semiconductor device to be adjusted to a desired value more easily and efficiently.

[0154] After depositing a plurality of layers, the first bit line 550 may be formed through an etching process using a mask.

[0155] Adjacent first bit lines 550 may be electrically isolated from each other by a first bit line isolation layer (not shown). The first bit line isolation layer may include a plurality of layers including silicon nitride or silicon oxide.

[0156] A fourth interlayer insulating layer 560 and a fifth interlayer insulating layer 570 may be disposed over the first bit line 550 .

[0157] Each of the fourth interlayer insulating layer 560 and the fifth interlayer insulating layer 570 may include a layer including at least one of silicon oxide, carbon-containing silicon oxide, and silicon nitride.

[0158] Since the fourth interlayer insulating layer 560 and the fifth interlayer insulating layer 570 are provided in the semiconductor device, the second sub-gate 580 and the first bit line 550 may be electrically isolated from each other.

[0159] The second sub-gate 580 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second sub-gate 580 may include titanium nitride. Figure 1B The second direction D2 is shown.

[0160] The sixth interlayer insulating layer 590 may be disposed between two adjacent second sub-gates 580. The sixth interlayer insulating layer 590 may be a layer used as a spacer to form the second sub-gates 580 spaced apart from each other. The sixth interlayer insulating layer 590 may include, for example, silicon oxide. The sixth interlayer insulating layer 590 may extend along the second direction D2 to electrically isolate the two adjacent second sub-gates 580 from each other.

[0161] The second sub-gate insulating layer 600 may overlap with the sidewall of the vertical portion included in the first active region 610 , may overlap with the upper portion of the second sub-gate 580 , may overlap with the upper portion of the sixth interlayer insulating layer 590 , and may electrically isolate the second sub-gate 580 from the vertical portion of the first active region 610 .

[0162] The second sub-gate insulating layer 600 may include, for example, silicon oxide.

[0163] The second sub-gate insulating layer 600 may be formed along the sidewalls of the second sub-gate 580 and the top surface of the second sub-gate 580, and may be formed along the Figure 1B The second direction D2 is shown extending.

[0164] At least a portion of the first active region 610 may be arranged to contact the first bit line 550. A horizontal portion included in the first active region 610 may contact the first bit line 550.

[0165] The first active region 610 may include two vertical portions and one horizontal portion, and the vertical portions may be formed along Figure 1B The third direction shown extends in the direction D3.

[0166] The first active region 610 including two vertical portions and one horizontal portion may be Figure 1B As shown, the first direction D1 and the second direction D2 are repeatedly arranged in a matrix structure.

[0167] The first active region 610 may include, for example, an oxide semiconductor material, and the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0168] In some other embodiments, the first active region 610 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), and the like.

[0169] Since IGZO has a low leakage current characteristic and the first active region 610 is formed of IGZO, a semiconductor device with low standby power can be realized. In addition, since the first active region 610 includes IGZO, the difficulty of the manufacturing process can be reduced, and the first active region 610 having a three-dimensional (3D) structure including a vertical portion and a horizontal portion can be easily formed.

[0170] The source region and the drain region of the first transistor TR1 may be disposed in the first active region 610. When an activation voltage is supplied to the first subgate 630 of the first transistor TR1, a channel region is formed in the first active region 610 so that electron movement may occur between the source region and the drain region.

[0171] The first sub-gate insulating layer 620 may be disposed between the first active region 610 and the first sub-gate 630. For example, the first sub-gate insulating layer 620 may include silicon oxide. The first sub-gate 630 and the first active region 610 may be electrically isolated from each other by the first sub-gate insulating layer 620.

[0172] The first sub-gate 630 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first sub-gate 630 and the second sub-gate 580 may include titanium nitride. Figure 1B The second direction D2 is shown extending.

[0173] When the activation voltage is provided to the first sub-gate 630, the second sub-gate 580 may be provided with the same activation voltage as the first sub-gate 630. The activation voltage may be, for example, a first word line activation voltage. In addition, the first word line activation voltage may be provided to the first word line at a data read / write time point.

[0174] The paired first sub-gate 630 and second sub-gate 580 may operate as one first word line. A vertical portion of the first active region 610 may be disposed between the first sub-gate 630 and second sub-gate 580 that are paired with each other.

[0175] When an activation voltage corresponding to a first word line activation voltage is supplied to the first sub-gate 630 and the second sub-gate 580 adjacent to each other, two channel regions may be formed at both sidewalls of a vertical portion included in the first active region 610 .

[0176] Since two channel regions are formed, electron mobility can be improved and the semiconductor device can be easily controlled with a low activation voltage.

[0177] A semiconductor device according to another embodiment may include the first sub-gate 630 and the second sub-gate 580 , thereby realizing an evolved semiconductor device having improved operating current characteristics and higher electron mobility.

[0178] The seventh interlayer insulating layer 640 may be disposed between two adjacent first sub-gates 630 to electrically isolate the two adjacent first sub-gates 630 from each other. The seventh interlayer insulating layer 640 may include, for example, silicon oxide or silicon nitride.

[0179] The second gate 650 may be disposed to contact one side of a vertical portion included in the first active region 610. The second gate 650 may include a plurality of layers.

[0180] For example, the second gate 650 may include a lower gate layer 652 and an upper gate layer 654 .

[0181] The lower gate layer 652 may include the same material as the first active region 610. For example, the lower gate layer 652 may include an oxide semiconductor such as IGZO.

[0182] Since the lower gate layer 652 includes the same material as the first active region 610 , an interface resistance between the second gate 650 and the first active region 610 may be reduced.

[0183] The upper gate layer 654 formed on the lower gate layer 652 may include a conductive material such as metal nitride or a metal material. Since the characteristics of the material included in the upper gate layer 654 are adjusted, the operating characteristics (eg, activation voltage, etc.) of the second transistor TR2 may be controlled.

[0184] The eighth interlayer insulating layer 660 may be disposed between the second gate electrodes 650. The eighth interlayer insulating layer 660 may surround a sidewall of each second gate electrode 650. The eighth interlayer insulating layer 660 may electrically isolate adjacent second gate electrodes 650 from each other.

[0185] The eighth interlayer insulating layer 660 may include, for example, silicon nitride or silicon oxide.

[0186] The second gate insulating layer 670 may include an insulating layer formed on the second gate 650. The second gate insulating layer 670 may be disposed to overlap the second gate 650 and may include silicon oxide. The second gate 650 and the second active region 680 may be electrically isolated from each other by the second gate insulating layer 670.

[0187] Each second active region 680 may be shared by two adjacent second transistors TR2. Figure 2B It can be seen that one second active region 680 may overlap with two second gates 650 , and activation voltages may be provided to the second gates 650 at different time points.

[0188] A source region and a drain region of the second transistor TR2 may be provided in each second active region 680. When an activation voltage is provided to the second gate 650 of the second transistor TR2, a channel region may be formed in each second active region 680 so that electron movement may occur between the source region and the drain region of the second active region 680.

[0189] In some embodiments, since each second transistor TR2 is formed in a vertical shape, the second transistor TR2 can be easily stacked in a small size area. In addition, since the second transistor TR2 is used instead of the capacitor as the data storage element, the process of forming the data storage element can be simplified, and the degree of freedom of the layout structure of the semiconductor device can be improved.

[0190] The ninth interlayer insulating layer 690 may electrically isolate the adjacent second active regions 680 from each other. The ninth interlayer insulating layer 690 may include, for example, silicon nitride or silicon oxide.

[0191] At least one second word line 700 and at least one first via contact 710 may be formed by etching the ninth interlayer insulating layer 690. Each second word line 700 and each first via contact 710 may include a conductive material such as a metal or a metal nitride. The first via contact 710 may penetrate the ninth interlayer insulating layer 690 in the vertical direction D3.

[0192] The second word line 700 may be along Figure 1B The first through-hole contacts 710 may be repeatedly arranged along the first direction D1 and the second direction D2, and each second active region 680 may be connected to the first through-hole contact 710 corresponding thereto.

[0193] The tenth interlayer insulating layer 720 and the eleventh interlayer insulating layer 730 may be located over the ninth interlayer insulating layer 690. The tenth interlayer insulating layer 720 and the eleventh interlayer insulating layer 730 may electrically isolate the second bit line 750 from the second word line 700.

[0194] Since the tenth and eleventh interlayer insulating layers 720 and 730 are provided in the semiconductor device, damage to the semiconductor device can be prevented during a process of forming the second bit line 750. Each of the tenth and eleventh interlayer insulating layers 720 and 730 may include a layer including silicon oxide or silicon nitride.

[0195] Each of the second via contacts 740 may penetrate the tenth interlayer insulating layer 720 and the eleventh interlayer insulating layer 730 in the vertical direction D3. Each of the second via contacts 740 may include a conductive material such as a metal or a metal nitride. Each of the second via contacts 740 may electrically connect the second bit line 750 to the second active region 680.

[0196] The second bit line 750 may include a single layer including a conductive material, such as Figure 2B However, in other embodiments, the second bit line 750 may include a plurality of layers including a conductive material. The conductive material may include, for example, a metal nitride and a metal.

[0197] Figure 3 is an equivalent circuit diagram showing a memory cell included in a semiconductor device according to an embodiment of the present disclosure.

[0198] refer to Figure 3 , the memory cell according to the embodiment may include two first transistors TR1a, TR1b and two second transistors TR2a, TR2b. Since the memory cell includes a plurality of first transistors TR1a, TR1b and a plurality of second transistors TR2a, TR2b, damage to the data stored in the memory cell can be prevented. In addition, the memory cell can perform high-speed read / write operations.

[0199] According to another embodiment, a memory cell may be configured to have one first transistor and one second transistor.

[0200] Figure 3 The first transistors TR1a, TR1b shown in FIG. Figure 1A , 1B , the first transistor TR1 described in 2A and 2B, and Figure 3 The second transistors TR2a, TR2b shown in FIG. 2 may correspond to the reference Figure 1A , 1B , 2A and 2B describe the second transistor TR2.

[0201] refer to Figure 1A and 2A The third gate electrode ( Figure 1AG3 of or 2A may be used as a component for electrically isolating adjacent first word lines WL1a, WL1b from each other, and therefore, it will be omitted from the equivalent circuit diagram herein for ease of description.

[0202] also, Figure 1A and Figure 1B The first gate G1 shown in FIG. 1 may be connected to Figure 3 Each first word line (WL1a, WL1b) is shown.

[0203] according to Figure 3 As shown in the equivalent circuit diagram of the memory cell, two adjacent first transistors TR1a and TR1b may be connected in parallel to each other, and two adjacent second transistors TR2a and TR2b may be connected in series to each other.

[0204] According to an embodiment, the storage unit may include a plurality of independent write paths and a plurality of independent read paths.

[0205] For example, the first word lines WL1a and WL1b may be write word lines, and the first bit line BL1 may be a write bit line. In addition, the second word lines WL2a and WL2b may be read word lines, and the second bit line BL2 may be a read bit line.

[0206] The same signal may be provided to each of the first word lines WL1 a , WL1 b included in one memory cell.

[0207] When a signal corresponding to an activation voltage is provided to the first word lines WL1a and WL1b, the first transistors TR1a and TR1b may be turned on. When the first transistors TR1a and TR1b are turned on, a voltage change may occur in the second gates G2a and G2b due to the voltage provided to the first bit line BL1. At this time, the type of data (e.g., 0 or 1) stored in the second gates G2a and G2b may be determined according to the voltage provided to the first bit line BL1. The above operation may be referred to as a write operation.

[0208] When a signal other than the activation voltage is provided to the first word line WL1a, WL1b, the first transistor TR1a, TR1b may be turned off. When the first transistor TR1a, TR1b is turned off, the on / off action of the second transistor TR2a, TR2b may be determined according to the voltage change that occurs in the second gate G2a, G2b during the write operation. During the read operation, the activation voltage may be provided to the second word line WL2a, WL2b. Therefore, when the second transistor TR2a, TR2b is turned on, a signal corresponding to the activation voltage may be output through the second bit line BL2, and when the second transistor TR2a, TR2b is turned off, a signal corresponding to the deactivation voltage may be output through the second bit line BL2. The operation of outputting the above-mentioned signal corresponding to the voltage change that has occurred in the second gate G2a, G2b during the write operation may be referred to as a read operation hereinafter.

[0209] FIG. 4A to FIG. 4Q is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0210] The following will refer to Figure 4A A process for forming the fourth interlayer insulating layer 260 , the fifth interlayer insulating layer 270 , the third gate electrode 280 , and the sixth interlayer insulating layer 290 on the first bit line 250 is described.

[0211] A plurality of insulating layers, conductive material layers, and mask layers are disposed on the first bit line 250 and then partially etched so that a fourth interlayer insulating layer 260 , a fifth interlayer insulating layer 270 , a third gate electrode 280 , and a sixth interlayer insulating layer 290 may be formed.

[0212] Each of the fourth and fifth interlayer insulating layers 260 and 270 may be a layer including at least one of silicon oxide, carbon-containing silicon oxide, and silicon nitride, and may electrically isolate the first bit line 250 and the third gate 280 from each other.

[0213] The sixth interlayer insulating layer 290 formed on the third gate 280 may be a mask for selectively etching the third gate 280. The sixth interlayer insulating layer 290 may include silicon nitride. The third gate 280 may extend in a direction perpendicular to the first bit line 250. The fourth interlayer insulating layer 260, the fifth interlayer insulating layer 270, and the sixth interlayer insulating layer 290 may also extend in a direction perpendicular to the first bit line 250.

[0214] The following will refer to Figure 4B A process for forming the third preliminary gate insulating layer 302 overlapping the sixth interlayer insulating layer 290 and the first bit line 250 is described.

[0215] The third preliminary gate insulating layer 302 may contact a sidewall of the third gate 280. The third preliminary gate insulating layer 302 may also be disposed to overlap a top portion of the first bit line 250 and the sixth interlayer insulating layer 290. The third preliminary gate insulating layer 302 may include silicon oxide.

[0216] Figure 4C An operation of forming the third gate insulating layer 300 by selectively etching the third preliminary gate insulating layer 302 is shown.

[0217] refer to Figure 4C By selectively etching the third preliminary gate insulating layer 302 , a third gate insulating layer 300 may be formed to electrically isolate the third gate 280 from the adjacent first active region 310 .

[0218] Furthermore, the third preliminary gate insulating layer 302 overlapping at least a portion of the first bit line 250 may be removed to allow the first active region 310 to be electrically connected to the first bit line 250 .

[0219] Figure 4D An operation of forming the first preliminary active region 312 by forming an oxide semiconductor layer and selectively etching the oxide semiconductor layer using a first mask MASK1 is shown.

[0220] refer to Figure 4D , the oxide semiconductor layer may overlap the first bit line 250, the sixth interlayer insulating layer 290, and the third gate insulating layer 300. The oxide semiconductor layer may include an oxide semiconductor material such as IGZO.

[0221] By selectively etching the oxide semiconductor layer using the first mask MASK1, the first preliminary active region 312 may be formed in the second direction (eg, Figure 1A The first mask MASK1 may include a spin-on carbon (SOC) and a SiON layer.

[0222] The thickness and physical characteristics of the first active region 310 may be adjusted by forming an oxide semiconductor layer through an atomic layer deposition (ALD) process.

[0223] Figure 4E An operation for forming a first preliminary gate insulating layer 322 on the first preliminary active region 312 is shown.

[0224] refer to Figure 4E , a first preliminary gate insulating layer 322 may be formed on the first preliminary active region 312 so that the first active region 310 and the first gate 330 may be electrically isolated from each other. The first preliminary gate insulating layer 322 may include, for example, silicon oxide.

[0225] Figure 4FAn operation for forming a first preliminary gate 332 on the first preliminary gate insulating layer 322 is shown.

[0226] The first preliminary gate 332 may include a conductive material such as a metal nitride. For example, the first preliminary gate 332 may include titanium nitride.

[0227] Figure 4G An operation for forming the first gate 330 by selectively etching the first preliminary gate 332 is shown.

[0228] refer to Figure 4G , the first gate 330 may be isolated from the first preliminary active region 312 by the first preliminary gate insulating layer 322 .

[0229] Figure 4H 2 shows an operation for forming a seventh preliminary interlayer insulating layer 342. The seventh preliminary interlayer insulating layer 342 may be formed to cover Figure 4G A seventh preliminary interlayer insulating layer 342 may be formed on the first gate electrode 330 .

[0230] The seventh preliminary interlayer insulating layer 342 may include an insulating material such as silicon nitride or silicon oxide. The seventh preliminary interlayer insulating layer 342 may electrically isolate adjacent first gate electrodes 330 from each other.

[0231] Fig. 4I Operations for forming a first active region 310 and then forming a preliminary lower gate layer 356 and a preliminary upper gate layer 358 on the first active region 310 are shown.

[0232] refer to Fig. 4I , a first active region 310 is formed, and a preliminary lower gate layer 356 and a preliminary upper gate layer 358 are formed on the first active region 310 .

[0233] By etching, portions of the seventh preliminary interlayer insulating layer 342 , the first preliminary gate insulating layer 322 , and the first preliminary active region 312 may be removed to form the first active region 310 , the first gate insulating layer 320 , and the seventh interlayer insulating layer 340 .

[0234] By etching the first preliminary active region 312, a first direction (eg, Figure 1A The first active regions 310 adjacent to each other on the D1 in the figure may be isolated from each other.

[0235] The preliminary lower gate layer 356 formed over the first active region 310 may include the same material as the first active region 310. For example, the preliminary lower gate layer 356 may include an oxide semiconductor such as IGZO.

[0236] Since the preliminary lower gate layer 356 is formed of the same material as the first active region 310 , the contact resistance between the second gate 350 and the first active region 310 may be reduced.

[0237] The preliminary upper gate layer 358 formed on the preliminary lower gate layer 356 may include a conductive material such as metal nitride. By adjusting the type of constituent material of the preliminary upper gate layer 358, the work function of the second gate 350 can be controlled and the electrical properties of the second transistor TR2 can be adjusted.

[0238] Figure 4J An operation for forming the second gate 350 is shown.

[0239] refer to Figure 4J The second gate 350 may be formed by removing the preliminary lower gate layer 356 and the preliminary upper gate layer 358 except for a region where the second gate 350 is to be formed through an etching process and then depositing an eighth interlayer insulating layer 360 .

[0240] Adjacent second gates 350 may be isolated from each other by the eighth interlayer insulating layer 360. Sidewalls of the second gates 350 may be surrounded by the eighth interlayer insulating layer 360, and a region where the second gates 350 are disposed may be defined by the eighth interlayer insulating layer 360.

[0241] The eighth interlayer insulating layer 360 may include, for example, silicon nitride or silicon oxide.

[0242] Figure 4K An operation for forming a second gate insulating layer 370 on the second gate 350 is illustrated.

[0243] refer to Figure 4K , a second gate insulating layer 370 is disposed on the second gate 350. The second gate insulating layer 370 may include an insulating material such as silicon oxide or silicon nitride.

[0244] According to another embodiment, the second gate insulating layer 370 may include a high-k material. By adjusting the dielectric constant of the second gate insulating layer 370, electrical properties of the second transistor TR2, such as leakage current and threshold voltage, may be adjusted.

[0245] Figure 4L An operation for forming a second preliminary active region 382 on the second gate insulating layer 370 is illustrated.

[0246] refer to Figure 4L, the second preliminary active region 382 may include the same oxide semiconductor material as the first active region 310. The second preliminary active region 382 may be formed by an atomic layer deposition (ALD) process. Since the second preliminary active region 382 is formed by the ALD process, the thickness of the second active region 380 may be easily adjusted.

[0247] Figure 4M An operation for forming the second active region 380 using the second preliminary active region 382 and forming a ninth interlayer insulating layer 390 on the second active region 380 is illustrated.

[0248] See also Figure 4M The second active region 380 may be selectively formed in a predetermined region by an etching process. For example, each second active region 380 may be formed to overlap with upper portions of two adjacent second gates 350 .

[0249] According to another embodiment, each second active region 380 may be formed to overlap with one second gate 350, or may be formed to overlap with four adjacent second gates 350. The connection relationship and number of second transistors included in one memory cell may vary according to the position where the second active region 380 is formed. The second transistors sharing the second active region 380 may be the second transistors included in one memory cell.

[0250] The ninth interlayer insulating layer 390 may electrically isolate the second active regions 380 from each other. The ninth interlayer insulating layer 390 may include an insulating layer such as silicon oxide or silicon nitride.

[0251] Figure 4N An operation for forming a second word line 400 and a first via contact 410 connected to the second active region 380 is illustrated.

[0252] See also Figure 4N , the second word lines 400 and the first through-hole contacts 410 may be formed by selectively etching the ninth interlayer insulating layer 390 using a mask. Each second word line 400 may have a second direction (eg, Figure 1A Each first through-hole contact 410 may overlap with the second active region 380 and may have a shape extending in a vertical direction (eg, Figure 1A D3) in the extended shape.

[0253] The second word lines 400 may be commonly connected to the second word lines along the second direction (eg, Figure 1A On the other hand, the first through-hole contact 410 may be connected to only one second active region 380.

[0254] The first via contact 410 and the second word line 400 may include a conductive material such as a metal or a metal nitride, and the conductive material may have a stack structure according to embodiments.

[0255] Fig.4O An operation for forming a tenth interlayer insulating layer 420 and an eleventh interlayer insulating layer 430 on the ninth interlayer insulating layer 390 is illustrated.

[0256] refer to Fig.4O Each of the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430 may include silicon oxide or silicon nitride. By forming the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430, damage to the semiconductor device during the process for forming the second bit line 450 may be prevented.

[0257] Figure 4P An operation for forming the second via contact 440 on the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430 is illustrated.

[0258] refer to Figure 4P , the second via contact 440 may be formed by selectively etching the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430. The second via contact 440 may overlap the first via contact 410. Each second via contact 440 may be disposed to be connected to only one second active region 380 in the same manner as the first via contact 410.

[0259] The second via contact 440 may include a conductive material such as a metal or a metal nitride.

[0260] Figure 4Q An operation for forming a second bit line 450 on the second via contact 440 and the eleventh interlayer insulating layer 430 is illustrated.

[0261] refer to Figure 4Q , each second bit line 450 may have a width along a first direction (eg, Figure 1A In addition, the adjacent second bit line 450 may be arranged in a second direction (eg, Figure 1A ) are arranged spaced apart from each other on D2).

[0262] The second bit line 450 may be formed by selectively etching the conductive material layer. Through the tenth interlayer insulating layer 420 and the eleventh interlayer insulating layer 430, damage to the semiconductor device during the etching process for forming the second bit line 450 may be prevented.

[0263] FIG. 5A to FIG. 5M is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0264] Figure 5A An operation for forming a fourth preliminary interlayer insulating layer 562 and a fifth preliminary interlayer insulating layer 572 on the first bit line 550 is illustrated.

[0265] refer to Figure 5A The fourth preliminary interlayer insulating layer 562 and the fifth preliminary interlayer insulating layer 572 may prevent damage to the first bit line 550 during a process of manufacturing a semiconductor device.

[0266] The fourth preliminary interlayer insulating layer 562 and the fifth preliminary interlayer insulating layer 572 may include at least one of silicon oxide, carbon-containing silicon oxide, and silicon nitride.

[0267] Figure 5B An operation for forming a sixth interlayer insulating layer 590 on the fifth preliminary interlayer insulating layer 572 is illustrated.

[0268] refer to Figure 5B The sixth interlayer insulating layer 590 may be configured to electrically isolate adjacent second sub-gates 580 from each other and may be arranged along the second direction (eg, Figure 1B D2) in extension.

[0269] The sixth interlayer insulating layer 590 may include, for example, silicon oxide, and may be formed by etching the silicon oxide layer formed on the fifth preliminary interlayer insulating layer 572 .

[0270] Figure 5C An operation for forming a second preliminary sub-gate 582 on the sixth interlayer insulating layer 590 is shown.

[0271] See also Figure 5C The second preliminary sub-gate 582 may include a conductive material (such as a metal or a metal nitride), and may be a region used as the second sub-gate 580 through a subsequent etching process.

[0272] Figure 5D An operation for forming the second sub-gate 580 from the second preliminary sub-gate 582 is shown.

[0273] refer to Figure 5D , the second sub-gate 580 may be arranged along a second direction (eg, Figure 1B D2) in the figure and may be arranged along both side walls of the sixth interlayer insulating layer 590.

[0274] Figure 5E An operation for forming a second preliminary sub-gate insulating layer 602 over the second sub-gate 580 and the sixth interlayer insulating layer 590 is illustrated.

[0275] refer to Figure 5EThe second preliminary sub-gate insulating layer 602 may include an insulating material such as silicon oxide or silicon nitride. The second preliminary sub-gate insulating layer 602 may electrically isolate the second sub-gate 580 from other adjacent layers.

[0276] Fig. 5F An operation for etching the second preliminary sub-gate insulating layer 602 , the fourth preliminary interlayer insulating layer 562 , and the fifth preliminary interlayer insulating layer 572 is shown.

[0277] refer to Fig. 5F By etching the second preliminary sub-gate insulating layer 602 , the fourth preliminary interlayer insulating layer 562 , and the fifth preliminary interlayer insulating layer 572 , a portion of the first bit line 550 may be exposed to the outside, and the first active region 610 formed on the bit line 550 may be connected to the first bit line 550 .

[0278] By etching the second preliminary sub-gate insulating layer 602 , the fourth preliminary interlayer insulating layer 562 , and the fifth preliminary interlayer insulating layer 572 , the second sub-gate insulating layer 600 , the fourth interlayer insulating layer 560 , and the fifth interlayer insulating layer 570 may be formed.

[0279] Figure 5G An operation of forming an oxide semiconductor layer and selectively etching the oxide semiconductor layer using a second mask MASK2 to form a first preliminary active region 612 is illustrated.

[0280] refer to Figure 5G The oxide semiconductor layer may entirely overlap the first bit line 550 and the second sub-gate insulating layer 600 , and may include an oxide semiconductor material such as IGZO.

[0281] By selectively etching the oxide semiconductor layer using the second mask MASK2, the first preliminary active region 612 may be formed in the second direction (eg, Figure 1B The second mask MASK2 may include a spin-on carbon (SOC) and a SiON layer.

[0282] The thickness and physical characteristics of the first active region 610 may be adjusted by forming an oxide semiconductor layer through an atomic layer deposition (ALD) process.

[0283] Figure 5H It is shown that a first preliminary sub-gate insulating layer 622 is formed on the first preliminary active region 612 .

[0284] refer to Figure 5H Since the first preliminary sub-gate insulating layer 622 is formed on the first preliminary active region 612, the first active region 610 and the first sub-gate 630 may be electrically isolated from each other. The first preliminary sub-gate insulating layer 622 may include, for example, silicon oxide.

[0285] Fig.5I An operation for forming a first preliminary sub-gate 632 on the first preliminary sub-gate insulating layer 622 is shown.

[0286] The first preliminary sub-gate 632 may include a conductive material such as a metal nitride. For example, the first preliminary sub-gate 632 may include titanium nitride.

[0287] Figure 5J It is shown that the first sub-gate 630 is formed by selectively etching the first preliminary sub-gate 632 .

[0288] refer to Figure 5J , the first sub-gate 630 may be isolated from the first preliminary active region 612 by the first preliminary sub-gate insulating layer 622 .

[0289] Figure 5K It is shown that a seventh preliminary interlayer insulating layer 642 is formed on the first sub-gate 630 .

[0290] refer to Figure 5K The seventh preliminary interlayer insulating layer 642 may include an insulating material such as silicon nitride or silicon oxide, and may electrically isolate adjacent first sub-gates 630 from each other.

[0291] Figure 5L Operations for forming a first active region 610 and then forming a preliminary lower gate layer 656 and a preliminary upper gate layer 658 over the first active region 610 are shown.

[0292] refer to Figure 5L Through an etching process, portions of the seventh preliminary interlayer insulating layer 642, portions of the first preliminary sub-gate insulating layer 622, and portions of the first preliminary active area 612 are removed to form a first active area 610, a first sub-gate insulating layer 620, and a seventh interlayer insulating layer 640.

[0293] By etching the first preliminary active region 612, a first direction (eg, Figure 1B Adjacent first active regions 610 adjacent to each other on D1 in FIG. 5 may be isolated from each other.

[0294] The preliminary lower gate layer 656 formed over the first active region 610 may include the same material as the first active region 610. For example, the preliminary lower gate layer 656 may include an oxide semiconductor such as IGZO.

[0295] Since the preliminary lower gate layer 656 is formed of the same material as the first active region 610 , the contact resistance between the second gate 650 and the first active region 610 may be reduced.

[0296] The preliminary upper gate layer 658 formed on the preliminary lower gate layer 656 may include a conductive material such as metal nitride. By adjusting the type of constituent material of the preliminary upper gate layer 658, the work function of the second gate 650 may be controlled, and the electrical performance of the second transistor TR2 may be adjusted.

[0297] Figure 5M An operation for forming the second gate 650 is shown.

[0298] refer to Figure 5M The second gate 650 may be formed by removing the preliminary lower gate layer 656 and the preliminary upper gate layer 658 except for the region where the second gate 650 is to be formed through an etching process and then depositing an eighth interlayer insulating layer 660 .

[0299] Adjacent second gate electrodes 650 may be isolated from each other by the eighth interlayer insulating layer 660. Sidewalls of the second gate electrodes 350 may be surrounded by the eighth interlayer insulating layer 660, and a region where the second gate electrodes 650 are disposed may be defined by the eighth interlayer insulating layer 660.

[0300] The eighth interlayer insulating layer 360 may include, for example, silicon nitride or silicon oxide.

[0301] The process of forming the second active region on the second gate 650 and then forming the second word line and the second bit line can be the same as that of the reference Figure 4K to Figure 4Q The processes described are basically the same, so for the sake of brevity, their redundant descriptions will be omitted herein.

[0302] As apparent from the above description, semiconductor devices according to some embodiments of the present disclosure include a three-dimensional (3D) channel to improve integration.

[0303] Furthermore, the semiconductor device according to some embodiments of the present disclosure includes at least one transistor used as a memory element, resulting in a simplified manufacturing process.

[0304] The embodiments of the present disclosure may provide various effects that can be recognized directly or indirectly.

[0305] Those skilled in the art will appreciate that the embodiments of the present disclosure may be implemented in other specific ways than those set forth herein. In addition, claims that are not explicitly presented in the appended claims may be presented in combination as embodiments, or may be included as new claims through subsequent amendments after the application is submitted.

[0306] Although a number of illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be designed based on what is described and / or illustrated in this disclosure. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: a first bit line extending in a first direction; a first transistor including a first gate and a first active region, wherein the first gate extends in a second direction perpendicular to the first direction; a second bit line extending in the first direction; as well as a second transistor including a second active region connected to the second bit line and a second gate overlapping the second active region, in The first active region comprises: a horizontal portion in contact with the first bit line; as well as a vertical portion that contacts the horizontal portion and extends in a third direction that is perpendicular to each of the first direction and the second direction, and The second gate contacts the vertical portion.

2. The semiconductor device according to claim 1, wherein The first gate is connected to a first word line.

3. The semiconductor device according to claim 2, further comprising: a second word line extending along the second direction, in, The second word line is connected to the second active region.

4. The semiconductor device according to claim 1, wherein The second transistor shares the second active region with another adjacent second transistor.

5. The semiconductor device according to claim 4, wherein The second gates included in the second transistors and sharing the second active region are in contact with vertical portions of different first transistors, respectively.

6. The semiconductor device according to claim 1, wherein: A source region and / or a drain region of the first transistor is included in the first active region; and A source region and / or a drain region of the second transistor is included in the second active region.

7. The semiconductor device according to claim 6, wherein: A source region and / or a drain region of the first transistor is connected to the second gate or the first bit line; and A source region and / or a drain region of the second transistor is connected to the second bit line or a second word line extending along the second direction.

8. The semiconductor device according to claim 1, further comprising: A plurality of memory cells, each memory cell comprising two first transistors and two second transistors.

9. The semiconductor device according to claim 8, wherein: The two first transistors are connected in parallel to each other; and The two second transistors are connected to each other in series.

10. The semiconductor device according to claim 1, wherein Each of the first active region and the second active region includes indium gallium zinc oxide (IGZO).

11. The semiconductor device according to claim 1, further comprising: The third gate is disposed between the vertical portions respectively included in the adjacent first active regions and extends along the second direction.

12. The semiconductor device according to claim 11, wherein The third gate receives a ground voltage as an input.

13. The semiconductor device according to claim 1, wherein: The first gate includes a first sub-gate and a second sub-gate extending along the second direction; and The vertical portion is disposed between the first sub-gate and the second sub-gate.

14. The semiconductor device according to claim 13, wherein The same activation voltage is supplied to the first sub-gate and the second sub-gate.

15. The semiconductor device according to claim 1, further comprising: a first gate insulating layer disposed between the first gate and the first active region; as well as A second gate insulating layer is disposed between the second gate and the second active region.

16. The semiconductor device according to claim 1, wherein The second active region is connected to the second bit line via a via contact.

17. A semiconductor device comprising: a first bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a first active region including a vertical portion extending in a third direction perpendicular to each of the first direction and the second direction, and a horizontal portion extending in the first direction and contacting the first bit line; a first gate insulating layer disposed between the first gate and the first active region; a second gate in contact with the vertical portion; a second gate insulating layer, disposed on the second gate; a second active region disposed on the second gate insulating layer; a second bit line extending along the first direction and connected to the second active region; as well as A second word line extends along the second direction and is connected to the second active region.

18. The semiconductor device according to claim 17, further comprising: another first active region, which contacts the first bit line and has the same shape as the first active region; as well as another second gate, which is in contact with the another first active region, in, The second gate insulating layer is disposed between the second active region and the another second gate.

19. The semiconductor device according to claim 18, further comprising: another first gate extending along the second direction; as well as Another first gate insulating layer is disposed between the another first gate and the another first active region.

20. The semiconductor device according to claim 19, further comprising: The third gate is disposed between the first active region and the another first active region and extends along the second direction.

21. The semiconductor device according to claim 17, further comprising: Another second word line extends along the second direction and is connected to the second active region.

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