Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a bit line extending in a first direction; a first gate extending in a second direction perpendicular to the first direction; an active region including a horizontal portion and a vertical portion, the horizontal portion contacting the bit line, the vertical portion contacting the horizontal portion and extending in a third direction, the third direction being perpendicular to each of the first direction and the second direction; and a second gate overlapping at least a portion of the horizontal portion and extending in the second direction, in which the vertical portion of the active region is disposed between the first gate and the second gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0146104, filed on October 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Techniques and embodiments disclosed in the present disclosure relate generally to semiconductor devices, and more particularly, to semiconductor devices including memory cells. Background Art

[0004] As miniaturization and higher integration of semiconductor devices become major issues, memory cells included in semiconductor devices may be formed to have a three-dimensional (3D) pattern. Miniaturized memory cells having a three-dimensional (3D) pattern may be provided with a configuration that improves memory cell operating characteristics. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a semiconductor memory device with higher integration.

[0006] Various embodiments of the present disclosure relate to a semiconductor memory device that prevents signal interference between word lines.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; an active region including a horizontal portion and a vertical portion, the horizontal portion contacting the bit line, the vertical portion contacting the horizontal portion and extending along a third direction, the third direction being perpendicular to each of the first direction and the second direction; and a second gate overlapping with at least a portion of the horizontal portion and extending along the second direction, wherein the vertical portion of the active region is disposed between the first gate and the second gate.

[0008] In some embodiments, the first gate may not overlap the horizontal portion.

[0009] In some embodiments, the semiconductor device may further include a contact pad contacting the vertical portion of the active region and spaced apart from the horizontal portion in the third direction.

[0010] In some embodiments, a contact pad may connect the capacitive element and the vertical portion of the active region to each other.

[0011] In some embodiments, the width of the contact pad may be greater than the vertical portion of the active region.

[0012] In some embodiments, the capacitive element may be a capacitor.

[0013] In some embodiments, the contact pad may include a plurality of layers, wherein a layer of the plurality of layers in contact with the vertical portion includes an oxide semiconductor material.

[0014] In some embodiments, the contact pad may include a plurality of layers, wherein a layer of the plurality of layers that contacts the capacitive element includes a metal or a metal nitride.

[0015] In some embodiments, the active region may include an oxide semiconductor material.

[0016] In some embodiments, the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0017] In some embodiments, the first gate may be configured to receive a control signal that is different from a control signal received by the second gate.

[0018] In some embodiments, a first gate may be disposed between the active region and another active region adjacent to the active region.

[0019] In some embodiments, the first gate may be configured to receive the same control signal as the second gate.

[0020] In some embodiments, a pair of first gates may be disposed between an active region and another active region adjacent to the active region.

[0021] In some embodiments, the second gate may include at least one contact portion connected to a conductive line.

[0022] In some embodiments, the contact portions may be arranged in a zigzag pattern with respect to the first direction, and may be spaced apart from each other by a predetermined distance.

[0023] According to another embodiment of the present disclosure, a semiconductor device may include: a bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a second gate extending along the second direction and facing the first gate or opposite to the first gate; and an active region including a vertical portion and a horizontal portion, the vertical portion being arranged between the first gate and the second gate and extending along a third direction, the third direction being perpendicular to each of the first direction and the second direction, and the horizontal portion contacting the bit line and extending along the first direction, wherein the first gate is arranged between the vertical portions respectively included in different active regions adjacent to each other.

[0024] In some other embodiments, the first gate may not overlap with the horizontal portion; and the second gate may overlap with the horizontal portion.

[0025] In some other embodiments, the semiconductor device may further include a contact pad that contacts the vertical portion of the active region and is spaced apart from the horizontal portion in the third direction.

[0026] In some other embodiments, a contact pad may connect the capacitive element and the vertical portion of the active region to each other.

[0027] In some other embodiments, the contact pad may include a plurality of layers, wherein a layer of the plurality of layers in contact with the vertical portion includes an oxide semiconductor material; and a layer of the plurality of layers in contact with the capacitive element includes a metal or a metal nitride.

[0028] It is to be understood that both the foregoing general description and the following detailed description of the embodiments of the present disclosure are illustrative and descriptive and are intended to provide further description of the embodiments of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features and advantageous aspects of the present disclosure will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0030] Figure 1A is a schematic perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 1B is a schematic perspective view showing a semiconductor device according to another embodiment of the present disclosure.

[0032] Figure 2A is a schematic diagram showing a layout structure of a semiconductor device according to an embodiment of the present disclosure.

[0033] Figure 2B is shown along Figure 2A 0 is a cross-sectional view of the semiconductor device taken along line A1 - A1 ′ shown in FIG. Figure 2C is shown along Figure 2A 0 is a cross-sectional view of the semiconductor device taken along line A2 - A2 ′ shown in FIG. Figure 2D is shown along Figure 2A 0 is a cross-sectional view of the semiconductor device taken along line A3 - A3 ′ shown in FIG.

[0034] Figure 2E is a schematic diagram showing a layout structure of a semiconductor device according to another embodiment of the present disclosure.

[0035] Figure 3A is a schematic diagram illustrating a semiconductor device according to another embodiment of the present disclosure.

[0036] Figure 3B is shown along Figure 3A 0 is a cross-sectional view of the semiconductor device taken along line B1 - B1 ′ shown in FIG. Figure 3C is shown along Figure 3A 0 is a cross-sectional view of the semiconductor device taken along line B2 - B2 ′ shown in FIG. Figure 3Dis shown along Figure 3A 0 is a cross-sectional view of the semiconductor device taken along line B3 - B3 ′ shown in FIG.

[0037] Figure 3E is a schematic diagram showing a layout structure of a semiconductor device according to another embodiment of the present disclosure.

[0038] Figure 4A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a bit line is formed over a first oxide layer.

[0039] Figure 4B is shown along Figure 4A A cross-sectional view of the semiconductor device taken along line C1-C1' shown in FIG. Figure 4C is shown along Figure 4A 0 is a cross-sectional view of the semiconductor device taken along line C2 - C2 ′ shown in FIG.

[0040] Figure 5A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a first gate is formed over a first bit line isolation layer, a second bit line isolation layer, and a third bit line isolation layer.

[0041] Figure 5B is shown along Figure 5A A cross-sectional view of the semiconductor device taken along line D1-D1' shown in FIG. Figure 5C is shown along Figure 5A 0 is a cross-sectional view of the semiconductor device taken along line D2 - D2 ′ shown in FIG.

[0042] Fig. 6A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a first gate oxide layer and a protective silicon layer are formed over a first gate.

[0043] Figure 6B is shown along Fig. 6A A cross-sectional view of the semiconductor device taken along line E1-E1' shown in FIG. Figure 6C is shown along Fig. 6A 0 is a cross-sectional view of the semiconductor device taken along line E2 - E2 ′ shown in FIG.

[0044] Fig. 7A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which at least a portion of a protective silicon layer, at least a portion of a first gate oxide layer, and at least a portion of a first bit line isolation layer are etched.

[0045] Figure 7B is shown along Fig. 7A A cross-sectional view of the semiconductor device taken along line F1-F1' shown in FIG. Figure 7Cis shown along Fig. 7A 0 is a cross-sectional view of the semiconductor device taken along line F2 - F2 ′ shown in FIG.

[0046] Fig. 8A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a pre-active region layer is formed over a first gate and a bit line.

[0047] Figure 8B is shown along Fig. 8A A cross-sectional view of the semiconductor device taken along line G1-G1' shown in FIG. Figure 8C is shown along Fig. 8A 0 is a cross-sectional view of the semiconductor device taken along line G2 - G2 ′ shown in FIG.

[0048] Fig. 9A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which an active region is selectively formed over a first gate and a bit line.

[0049] Fig. 9B is shown along Fig. 9A A cross-sectional view of the semiconductor device taken along line H1-H1' shown in FIG. Fig. 9C is shown along Fig. 9A 0 is a cross-sectional view of the semiconductor device taken along line H2 - H2 ′ shown in FIG.

[0050] Fig. 10A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a second gate oxide layer, a pre-second gate layer, and a contact mask are formed.

[0051] Fig. 10B is shown along Fig. 10A A cross-sectional view of the semiconductor device taken along line I1-I1' shown in FIG. Fig. 10C is shown along Fig. 10A A cross-sectional view of the semiconductor device taken along line I2-I2' shown in FIG. Fig. 10D is shown along Fig. 10A 1 is a cross-sectional view of the semiconductor device taken along line I3 - I3 ′ shown in FIG.

[0052] Fig.11A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a second gate layer and a contact portion are formed.

[0053] Fig. 11B is shown along Fig.11A A cross-sectional view of the semiconductor device taken along the line J1-J1' shown in FIG. Fig. 11C is shown along Fig.11A A cross-sectional view of the semiconductor device taken along line J2-J2' shown in FIG. Fig.11Dis shown along Fig.11A 0 is a cross-sectional view of the semiconductor device taken along line J3 - J3 ′ shown in FIG.

[0054] Fig. 12A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a third nitride layer and a second oxide layer are formed.

[0055] Fig. 12B is shown along Fig. 12A A cross-sectional view of the semiconductor device taken along line K1-K1' shown in FIG. Fig. 12C is shown along Fig. 12A A cross-sectional view of the semiconductor device taken along line K2-K2' shown in FIG. Fig.12D is shown along Fig. 12A 0 is a cross-sectional view of the semiconductor device taken along line K3 - K3 ′ shown in FIG.

[0056] Fig.13 is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a portion of the second oxide layer is etched.

[0057] Fig.14 is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a mask is formed over the etched second oxide layer.

[0058] Fig.15 is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a mask is removed after both ends of a second gate are selectively etched.

[0059] Fig.16A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein adjacent active regions are isolated from each other in a first direction ( D1 ).

[0060] Fig. 16B is shown along Fig.16A A cross-sectional view of the semiconductor device taken along line L1-L1' shown in FIG. Fig. 16C is shown along Fig.16A A cross-sectional view of the semiconductor device taken along line L2-L2' shown in FIG. Fig.16D is shown along Fig.16A 0 is a cross-sectional view of the semiconductor device taken along line L3 - L3 ′ shown in FIG.

[0061] Fig.17A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a contact pad contacting one end of a vertical portion included in an active region is formed.

[0062] Fig. 17B is shown along Fig.17A A cross-sectional view of the semiconductor device taken along the line M1-M1' shown in FIG. Fig. 17C is shown along Fig.17A 0 is a cross-sectional view of the semiconductor device taken along line M2 - M2 ′ shown in .

[0063] Fig.17D is shown after etching the second hard mask layer along Fig.17A A cross-sectional view of a semiconductor taken along the line M1-M1' shown in FIG. Fig.17E is shown after etching the second hard mask layer along Fig.17A 0 is a cross-sectional view of the semiconductor device taken along line M2 - M2 ′ shown in .

[0064] Fig.18A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a contact pad contacting one end of a vertical portion included in an active region is formed.

[0065] Fig.18B is shown along Fig.18A A cross-sectional view of the semiconductor device taken along line N1-N1' shown in FIG. Fig. 18C is shown along Fig.18A 0 is a cross-sectional view of the semiconductor device taken along line N2 - N2 ′ shown in FIG.

[0066] Fig.19A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which a contact pad contacting one end of a vertical portion included in an active region is formed.

[0067] Fig.19B is shown along Fig.19A A cross-sectional view of the semiconductor device taken along line O1-O1' shown in FIG. Fig.19C is shown along Fig.19A 02 - 02 ′ is a cross-sectional view of the semiconductor device taken along line O2 - O2 ′ shown in FIG.

[0068] Fig. 20A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein an isolation oxide layer is formed over a first bit line isolation layer, a second bit line isolation layer, and a third bit line isolation layer.

[0069] Fig. 20B is shown along Fig. 20A A cross-sectional view of the semiconductor device taken along line P1-P1' shown in FIG. Fig. 20C is shown along Fig. 20A 0 is a cross-sectional view of the semiconductor device taken along line P2 - P2 ′ shown in FIG.

[0070] Fig.21Ais a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a pre-first gate layer is formed on an isolation oxide layer.

[0071] Fig.21B is shown along Fig.21A A cross-sectional view of the semiconductor device taken along line Q1-Q1' shown in FIG. Fig. 21C is shown along Fig.21A 0 is a cross-sectional view of the semiconductor device taken along line Q2 - Q2 ′ shown in FIG.

[0072] Fig.22A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a first gate is formed by etching a pre-first gate layer, and a first gate oxide layer is formed on the first gate.

[0073] Fig. 22B is shown along Fig.22A A cross-sectional view of the semiconductor device taken along line R1-R1' shown in FIG. Fig. 22C is shown along Fig.22A 0 is a cross-sectional view of the semiconductor device taken along line R2 - R2 ′ shown in FIG.

[0074] Fig.23A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a protective silicon layer is formed over a first gate oxide layer.

[0075] Fig. 23B is shown along Fig.23A A cross-sectional view of the semiconductor device taken along the line S1-S1' shown in FIG. Fig.23C is shown along Fig.23A 0 is a cross-sectional view of the semiconductor device taken along line S2 - S2 ′ shown in FIG.

[0076] Fig.24A is a perspective view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, in which at least a portion of a protective silicon layer, at least a portion of a first gate oxide layer, and at least a portion of a first bit line isolation layer are etched.

[0077] Fig. 24B is shown along Fig.24A A cross-sectional view of the semiconductor device taken along line T1-T1' shown in FIG. Fig.24C is shown along Fig.24A 0 is a cross-sectional view of the semiconductor device taken along line T2 - T2 ′ shown in FIG.

[0078] Fig.25A is a perspective view showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, wherein a pre-active region layer is formed over a first gate oxide layer and a bit line.

[0079] Fig.25B is shown along Fig.25A A cross-sectional view of the semiconductor device taken along the line U1-U1' shown in FIG. Fig.25C is shown along Fig.25A 2 is a cross-sectional view of the semiconductor device taken along line U2 - U2 ′ in FIG. DETAILED DESCRIPTION

[0080] The present disclosure provides embodiments and examples of semiconductor devices including memory cells, which can be used in configurations that substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other semiconductor devices. Some embodiments of the present disclosure relate to semiconductor memory devices with higher integration. Some embodiments of the present disclosure relate to semiconductor memory devices that prevent signal interference between word lines. Recognizing the above problems, embodiments of the present disclosure can provide semiconductor devices with three-dimensional (3D) channels to improve integration. Embodiments of the present disclosure can provide semiconductor devices including multiple gates, so that integration can be improved and interference between adjacent gates can be minimized.

[0081] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the embodiments of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated in the accompanying drawings by way of example. However, the present disclosure should not be construed as being limited to the embodiments described herein.

[0082] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the embodiments are not limited to specific embodiments, but include various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various advantageous effects that can be directly or indirectly identified.

[0083] In the following description, a detailed description of related known configurations or functions included herein will be omitted to avoid obscuring the subject matter.

[0084] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It should also be understood that the terms "include", "comprise", "include" and / or "comprise" when used in this specification specify the presence of the constituent elements, steps, operations and / or components, but do not exclude the presence or addition of one or more other constituent elements, steps, operations and / or their components. The term "and / or" can include a combination of multiple items or one of multiple items.

[0085] Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0086] Figure 1A is a schematic perspective view showing a semiconductor device 100 a according to an embodiment of the present disclosure.

[0087] Figure 1B is a schematic perspective view showing a semiconductor device 100 b according to another embodiment of the present disclosure.

[0088] Reference Figure 1A and 1B Each of the semiconductor devices (100a, 100b) may include a substrate (LS) and a memory cell array (MCA) formed on the substrate (LS). The memory cell array (MCA) may include a plurality of memory cells (MC) repeatedly arranged on the substrate (LS).

[0089] In some embodiments, each memory cell may have a three-dimensional (3D) structure.

[0090] More specifically, each memory cell (MC) included in the memory cell array (MCA) may include a bit line (BL), a transistor (TR), a contact pad (PAD), and a capacitor (CAP).

[0091] The bit lines (BL) may be disposed on the substrate (LS) and may extend in a first direction (D1) parallel to one surface of the substrate (LS). Adjacent bit lines (BL) may be isolated from each other by an insulating layer (not shown).

[0092] The insulating layer may include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. In some other embodiments, the insulating layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiNO, etc. In some other embodiments, the insulating layer may include SiCO, etc.

[0093] In some embodiments, the capacitors (CAP) may be spaced apart from the bit lines (BL) in the third direction (D3) and may be arranged in a matrix structure.

[0094] In some other embodiments, the capacitor (CAP) may be arranged obliquely relative to the region where the gate (G1, G2) and the bit line (BL) overlap each other. More specifically, the capacitor (CAP) may be arranged to deviate from the center of the contact pad (PAD) on one side of the contact active area (ACT), and may be arranged in a zigzag or honeycomb shape relative to the contact pad (PAD) arranged in a matrix structure.

[0095] The transistor (TR) may be disposed between the bit line (BL) and the capacitor (CAP) in the third direction (D3).

[0096] The transistor (TR) may include at least a portion of an active region (ACT) connected to a bit line (BL), a first gate (G1), and a second gate (G2).

[0097] according to Figure 1A In an embodiment of the present invention, a word line driving voltage may be provided to a second gate (G2) extending along the second direction (D2). The second gate (G2) may operate as a word line of the transistor (TR).

[0098] At this time, a voltage different from the voltage of the second gate (G2) may be provided to the first gate (G1) extending opposite to the second gate (G2) to prevent interference between the second gates (G2) of adjacent transistors (TR). For example, a ground voltage may be provided to the first gate (G1). The first gate (G1) may operate as a back gate.

[0099] according to Figure 1B In an embodiment, the same word line driving voltage may be provided to the first gate (G1) and the second gate (G2) adjacent to each other based on the active region (ACT) between the first gate (G1) and the second gate (G2) adjacent to each other. The first gate (G1) and the second gate (G2) may operate as word lines of the transistor (TR). The transistor (TR) in which the first gate (G1) and the second gate (G2) operate as word lines may be referred to as a dual-gate transistor hereinafter.

[0100] The first direction (D1) may be perpendicular to the second direction (D2), and the third direction may be perpendicular to each of the first direction (D1) and the second direction (D2).

[0101] Each memory cell (MC) may include a contact pad (PAD) electrically connecting the capacitor (CAP) and the bit line (BL) to each other. The contact pad (PAD) may contact one side of the vertical portion of the active region (ACT).

[0102] The active region (ACT) may include a channel region and a source / drain region of the transistor (TR). For example, depending on a voltage applied to a gate (e.g., the first gate G1 or the second gate G2) of the transistor (TR), a channel region may be formed in the active region (ACT), and electrons may move between the source / drain regions through the channel region.

[0103] The active region (ACT) may include a horizontal portion extending in the first direction (D1) and a vertical portion extending in the third direction (D3).

[0104] Each memory cell (MC) may include a single transistor (TR).

[0105] Two adjacent vertical portions included in the active region (ACT) may be connected to each other through a horizontal portion. The horizontal portion of the active region (ACT) may be connected to the bit line (BL). The horizontal portion of the active region (ACT) may be a layer formed on the bit line (BL). In addition, the active region (ACT) may be electrically isolated from the gate (G1, G2) by an insulating layer (not shown).

[0106] The memory cell array (MCA) may include a DRAM cell array. In some other embodiments, the memory cell array (MCA) may include a phase change random access memory (PCRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc. The capacitor (CAP) may be replaced with another storage element as needed.

[0107] The substrate (LS) may be a material suitable for semiconductor processing. The substrate (LS) may include at least one of a conductive material, an insulating material (also referred to as a dielectric material), and a semiconductor material (also referred to as a semiconductive material). In some embodiments, a plurality of material layers may be formed on the substrate (LS).

[0108] The substrate (LS) may include a semiconductor substrate. For example, the substrate (LS) may be formed of a semiconductor material including silicon. The substrate (LS) may include silicon, single crystal silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate (LS) may also include other semiconductor materials such as germanium. The substrate (LS) may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide ("GaAs").

[0109] The substrate (LS) may include a silicon-on-insulator (SOI) substrate. In another embodiment, the substrate (LS) may include a peripheral circuit region (not shown) located at a lower portion thereof. The peripheral circuit region may include a plurality of control circuits for controlling a memory cell array (MCA). At least one control circuit in the peripheral circuit region may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit in the peripheral circuit region may include an address decoder circuit, a read circuit, a write circuit, etc.

[0110] At least one control circuit included in the peripheral circuit region may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), or the like.

[0111] At least one control circuit included in the peripheral circuit region may be electrically connected to the bit line (BL). The peripheral circuit region may include a sense amplifier (sense-amp), and the sense amplifier (sense-amp) may be electrically connected to the bit line (BL). Although not shown, a multi-level metal interconnection may be provided between the substrate (LS) and the memory cell array (MCA). The peripheral circuit region and the bit line (BL) may be connected to each other through a multi-level metal interconnection.

[0112] The bit lines (BL) may be disposed over the substrate (LS), an insulating layer may be disposed between the bit lines (BL), and the bit lines (BL) may be laterally (or horizontally) oriented in a first direction (D1).

[0113] The bit lines (BL) may be referred to as laterally oriented bit lines or laterally extending bit lines.

[0114] The bit line (BL) may include a conductive material. Each bit line (BL) may include a silicon-based material, a metal-based material, or a combination thereof. Each bit line (BL) may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof.

[0115] The bit line (BL) may include polysilicon, titanium nitride, tungsten (W), or a combination thereof. For example, the bit line (BL) may include polysilicon doped with N-type impurities, or titanium nitride (TiN).

[0116] The bit line (BL) may include a stack structure (TiN / W) of titanium nitride (TiN) and tungsten (W). The bit line (BL) may further include an ohmic contact layer formed of, for example, metal silicide.

[0117] Memory cells (MC) arranged horizontally in a first direction (D1) may share one bit line (BL). An insulating layer extending along the first direction (D1) may be disposed between adjacent bit lines (BL). The insulating layer may include a plurality of layers and may be used as a spacer to isolate adjacent bit lines (BL) from each other.

[0118] The transistors (TR) may be arranged in a matrix structure in the first direction (D1) and the second direction (D2).

[0119] Each transistor (TR) may be disposed between a corresponding one of the bit lines (BL) and a corresponding one of the capacitors (CAP).

[0120] Each transistor (TR) may include an active region (ACT), an insulating layer (not shown), and a gate (G1, G2).

[0121] The gates (G1, G2) may extend along the second direction (D2), and the active region (ACT) may include a horizontal portion extending along the first direction (D1) and a vertical portion extending along the third direction (D3).

[0122] An insulating layer may be provided to isolate adjacent active regions (ACT) and gates (G1, G2) from each other.

[0123] Each of the gates ( G1 , G2 ) may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof.

[0124] For example, the gate ( G1 , G2 ) may include a stack structure (TiN / W) in which titanium nitride and tungsten are sequentially stacked.

[0125] The gates (G1, G2) may extend in one direction, and the bit lines (BL) may extend in another direction perpendicular to the one direction. The active region (ACT) may include a semiconductor material or an oxide semiconductor material.

[0126] The bit line (BL) may be electrically isolated from the gate (G1, G2) by an insulating layer. The insulating layer may be disposed between the bit line (BL) and the gate (G1, G2).

[0127] The active region (ACT) may include a plurality of impurity regions. The impurity regions may include source / drain regions of the transistor (TR).

[0128] The active region (ACT) may include doped polysilicon, undoped polysilicon, amorphous silicon, IGZO (amorphous indium gallium zinc oxide semiconductor), indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0129] The horizontal portion included in the active area (ACT) may be electrically connected to the bit line (BL). In addition, a contact pad (PAD) may contact the vertical portion included in the active area (ACT), and the capacitor (CAP) and the active area (ACT) may be electrically connected to each other through the contact pad (PAD).

[0130] The active region (ACT) may be electrically isolated from the gate (G1, G2) by an insulating layer. The insulating layer may be disposed between the active region (ACT) and the gate (G1, G2) to prevent the active region (ACT) and the gate (G1, G2) from being electrically interconnected.

[0131] Furthermore, an insulating layer may be provided between the gates ( G1 , G2 ), and the gates ( G1 , G2 ) may be electrically isolated from each other by the insulating layer.

[0132] The insulating layer may include, for example, silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, etc. There may be differences in composition between the insulating layers depending on the location of the insulating layers. For example, the insulating layer disposed between the gates (G1, G2) may include silicon oxide, while the insulating layer disposed between the active region (ACT) and the gates (G1, G2) may include a high-k material.

[0133] The capacitor (CAP) may have a shape vertically extending from one surface of the substrate (LS) and may be arranged to contact a vertical portion included in the active region (ACT). The capacitor (CAP) may include a metal-insulator-metal (MIM) structure.

[0134] The capacitor (CAP) may include two electrodes and a dielectric layer disposed between the two electrodes. The dielectric layer may include silicon oxide, silicon nitride, a high-k material (eg, hafnium oxide or aluminum oxide), or a combination thereof.

[0135] The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer may include a high-k material having a dielectric constant of 4 or greater. For example, the high-k material may have a dielectric constant of about 20 or greater.

[0136] The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanium oxide (SrTiO3), etc. In another embodiment, the dielectric layer may include a composite layer of two or more layers formed of the above high-k materials.

[0137] The dielectric layer may include a stacked structure of a high-k material and a high-bandgap material, and the bandgap of the high-bandgap material is larger than that of the high-k material. For example, in addition to aluminum oxide (Al2O3), the dielectric layer may also include silicon oxide (SiO2) as another high-bandgap material. Leakage current may be suppressed by including a high-bandgap material in the dielectric layer.

[0138] The dielectric layer may include a laminate structure in which a high-k material and a high bandgap material are alternately stacked. For example, the laminate structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2).

[0139] The anode included in the capacitor (CAP) may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the anode included in the capacitor (CAP) may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, and tungsten nitride / tungsten (WN / W) stack.

[0140] In another embodiment, the electrode of the capacitor (CAP) may include a combination of a metal-based material and a silicon-based material. For example, the combination of the metal-based material and the silicon-based material may be a stacked structure of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN).

[0141] The capacitor (CAP) may have a three-dimensional (3D) structure, and the three-dimensional capacitor (CAP) may be repeatedly arranged in a matrix shape on one surface of the substrate (LS). The three-dimensional (3D) structure may be, for example, a barrel, a column, or a cylindrical barrel. Here, the cylindrical barrel may refer to a structure in which a column and a barrel are combined.

[0142] In another embodiment, the capacitor (CAP) may have a structure arranged obliquely relative to the contact pad (PAD), which is located in a region where the bit line (BL) and the gate (G1, G2) are arranged to overlap each other, so that a maximum number of capacitors (CAP) can be arranged in the same region.

[0143] The memory cell (MC) may share the first gate (G1) and the second gate (G2). The first gate (G1) and the second gate (G2) may include the same conductive material.

[0144] Figure 2A is a schematic diagram showing a layout structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2B is shown along Figure 2A A cross-sectional view of the semiconductor device taken along line A1-A1' shown in FIG. Figure 2C is shown along Figure 2A A cross-sectional view of the semiconductor device taken along line A2-A2' shown in FIG. Figure 2D is shown along Figure 2A 0 is a cross-sectional view of the semiconductor device taken along line A3 - A3 ′ shown in FIG.

[0145] The layout structure of the semiconductor device observed from the third direction (D3) is Figure 2A is shown in .

[0146] A semiconductor device may include a plurality of regions within a substrate (LS).

[0147] For example, the semiconductor device may include a first region (R1) and a second region (R2). The first region (R1) may be a region in which a plurality of contact pads (PAD) and a plurality of capacitors (CAP) overlapping the contact pads (PAD) are provided. The second region (R2) may be a region adjacent to the first region (R1). The second region may include gates (G1, G2).

[0148] The plurality of capacitors (CAP) disposed in the first region (R1) may overlap the contact pads (PAD) disposed in a matrix structure. The physical footprint of the capacitors (CAP) may intersect or cover the contact pads (PAD). Figure 1A As shown, each capacitor (CAP) may be located on a corresponding contact pad (PAD). The occupied area of ​​each capacitor (CAP) may be the same as the occupied area of ​​the corresponding contact pad (PAD). However, the embodiments of the present disclosure are not limited in this manner. For example, typically, at least a portion of each capacitor (CAP) may overlap with a corresponding contact pad (PAD) or at least a portion of a corresponding contact pad (PAD).

[0149] A plurality of capacitors (CAP) may be arranged in a matrix configuration. A plurality of capacitors (CAP) may be arranged in a matrix configuration relative to an array of contact pads (PADs). A plurality of capacitors (CAP) may be arranged in a matrix configuration relative to or aligned with an array of contact pads (PADs). Although for ease of description, Figure 2A The contact pads (PAD) and capacitors (CAP) shown in FIG. 5 are arranged in a matrix structure including 20 rows and 20 columns, but other embodiments are possible. It should be noted that a plurality of capacitors (CAP) may be arranged in a shape having the highest integration.

[0150] The second region (R2) may be a region in which a contact portion included in the first gate (G1) or the second gate (G2) is disposed.

[0151] The contact portions may be connected to conductive lines that provide a control signal to the first gate (G1) or the second gate (G2), respectively. The semiconductor device may operate based on the control signal.

[0152] A bit line (BL) and a gate (G1, G2) included in the semiconductor device may extend in directions perpendicular to each other. A capacitor (CAP) may be located in a region where the bit line (BL) and the gate (G1, G2) overlap each other.

[0153] Figure 2Bis a cross-sectional view showing the center of the first gate G1 taken along a cutting line parallel to the second direction ( D2 ). Figure 2C is a cross-sectional view showing the center of the second gate (G2) taken along a cutting line parallel to the second direction (D2). Figure 2D is a diagram showing a view taken along a cutting line parallel to the first direction (D1) Figure 1A A cross-sectional view of the center of a bit line (BL).

[0154] Reference Figure 2B , Figure 2C and Figure 2D , a substrate layer 210 , a silicide layer 220 formed on the substrate layer 210 , and a first nitride layer 230 formed on the silicide layer 220 are shown.

[0155] The substrate layer 210 may include a silicon semiconductor material. For example, the substrate layer 210 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, etc.

[0156] The substrate layer 210 may include a plurality of control circuits configured to control the operation of the semiconductor device, and a region where the control circuits are provided may be referred to as a peripheral circuit region.

[0157] The silicide layer 220 formed on the substrate layer 210 may include a metal silicide material such as cobalt silicide (CoSi). The silicide layer 220 is disposed in the semiconductor device so that the operating resistance of the semiconductor device can be reduced. In addition, the silicide layer 220 can be used as a protective layer for the substrate layer 210, thereby preventing damage to the substrate layer 210 during the semiconductor manufacturing process.

[0158] The first nitride layer 230 formed on the silicide layer 220 may refer to a layer including silicon nitride. Since the first nitride layer 230 includes silicon nitride, damage to the substrate layer 210 may be prevented during a high temperature semiconductor manufacturing process.

[0159] Reference Figure 2B , 2C 2D, the first oxide layer 240 may be disposed on the first nitride layer 230. The first oxide layer 240 may be a layer including, for example, silicon oxide, etc. The first oxide layer 240 may function as an insulating layer together with the first nitride layer 230.

[0160] Since the first nitride layer 230 and the first oxide layer 240 are provided in the semiconductor device, the control circuit included in the substrate layer 210 may be electrically isolated from the bit line 250 .

[0161] The bit line 250 disposed on the first oxide layer 240 may include a plurality of layers extending in the first direction (D1). For example, the bit line 250 may include a first bit line layer 252 including titanium nitride (TiN), a second bit line layer 254 including tungsten (W), and a third bit line layer 256 including titanium nitride.

[0162] Since the bit line 250 includes a plurality of layers, the operating resistance of the semiconductor device can be adjusted.

[0163] The first bit line layer 252 and the third bit line layer 256 included in the bit line 250 may prevent the second bit line layer 254 from being oxidized by exposure to oxygen. When the second bit line layer 254 is exposed to oxygen, tungsten (W) may be oxidized, thereby causing disconnection and defects.

[0164] Furthermore, titanium nitride (TiN) included in the first bit line layer 252 may have higher adhesion to silicon oxide than tungsten (W) and is disposed between the first oxide layer 240 and the second bit line layer 254 , thereby improving mechanical stability of the bit line 250 .

[0165] After depositing a plurality of layers, the bit line 250 may be formed through an etching process using a mask.

[0166] Adjacent bit lines 250 may be electrically isolated from each other by second bit line isolation layer 270 and third bit line isolation layer 280. In some embodiments, second bit line isolation layer 270 may include silicon nitride, and third bit line isolation layer 280 may include silicon oxide. Bit line 250 and first gate 290 may be isolated from each other by first bit line isolation layer 260.

[0167] The second bit line isolation layer 270 and the third bit line isolation layer 280 may serve as spacers to electrically isolate adjacent bit lines 250 from each other.

[0168] A first bit line isolation layer 260 may be disposed over each bit line 250 to electrically isolate the bit line 250 from the first gate 290. The first bit line isolation layer 260 may include silicon oxide containing carbon (SiCO).

[0169] Reference Figure 2C and 2D , an active region 320 electrically connected to at least a portion of the bit line 250 may be disposed above the bit line 250 . The active region 320 may be electrically isolated from the second gate 340 by the second gate oxide layer 330 .

[0170] The first gate 290 and the second gate 340 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof For example, the first gate 290 and the second gate 340 may include titanium nitride.

[0171] Reference Figure 2D , the first gate oxide layer 310 may be disposed not only on the first bit line isolation layer 260 but also at the sidewall of the first gate 290. Figures 2B to 2D Although not shown in the figure, at least a portion of the first gate oxide layer 310 may be disposed on the third bit line isolation layer 280 .

[0172] The first gate oxide layer 310 may electrically isolate the first gate 290 from the bit line 250 or the active region 320. The first gate oxide layer 310 may include an insulating material, such as silicon oxide.

[0173] The second nitride layer 300 may be disposed over the first gate 290 to electrically isolate the first gate 290 and the contact pad 370 from each other.

[0174] Adjacent second gates 340 may be electrically isolated from each other by the third nitride layer 350. In addition, the second gates 340 and the contact pads 370 may be isolated from each other by the third nitride layer 350.

[0175] The second oxide layer 360 may be disposed on the third nitride layer 350 between the second gate electrodes 340. A contact connected to the second gate electrode 340 and a conductive line may be formed in the second gate electrode 340 using an etching rate difference between the second oxide layer 360 and the third nitride layer 350.

[0176] like Figure 2A As shown, the contact portions corresponding to the first gate G1 or the contact portions corresponding to the second gate G2 may be sparsely arranged in a zigzag pattern in the first direction (D1). The gates (G1, G2) may be electrically connected to wires that transmit control signals through the contacts.

[0177] The active region 320 may include a horizontal portion and a vertical portion, the horizontal portion being formed to contact the bit line 250, and the vertical portion being formed to extend in the vertical direction (D3) and disposed between the first gate 290 and the second gate 340. The active region 320 may include, for example, an oxide semiconductor material, and the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0178] In another embodiment, the active region 320 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0179] Since IGZO has a low leakage current characteristic and the active region 320 is formed of IGZO, a semiconductor device with low standby power may be implemented.

[0180] In addition, since the active region 320 includes IGZO, the manufacturing process difficulty may be reduced, and the active region 320 having a three-dimensional (3D) structure including vertical and horizontal portions may be easily formed.

[0181] One end of the vertical portion included in the active region 320 may contact a contact pad 370 connecting the capacitor (CAP) and the active region 320 to each other.

[0182] The contact pad 370 may include a plurality of layers to reduce the contact resistance between the active region 320 and the capacitor (CAP).

[0183] Reference Figure 2C and 2D , the width of the contact pad 370 may be greater than the width of the vertical portion. Since the width of the contact pad 370 is greater than the width of the vertical portion, the contact area between the capacitor (CAP) and the contact pad 370 may be ensured, thereby ensuring the mechanical stability of the semiconductor device.

[0184] The contact pad 370 may include a first pad layer 372 and a second pad layer 374 .

[0185] The first pad layer 372 includes the same material as the active region 320 to reduce the interface resistance between the contact pad 370 and the active region 320. For example, the first pad layer 372 may include an oxide semiconductor material such as IGZO.

[0186] In another embodiment, the first pad layer 372 may include indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0187] The second pad layer 374 formed on the first pad layer 372 may include titanium nitride (TiN). Since the second pad layer 374 is formed, the interface resistance between the contact pad 370 and the capacitor (CAP) may be reduced.

[0188] The capacitor (CAP) disposed over the contact pad 370 may be arranged such that at least a portion thereof overlaps the contact pad 370 .

[0189] The fourth nitride layer 380 may electrically isolate adjacent contact pads 370 from each other. The fourth nitride layer 380 may be disposed to surround the contact pads 370. In other words, the fourth nitride layer 380 may be disposed between adjacent contact pads 370.

[0190] Capacitors (CAP) may be provided in the memory element layer 400. The capacitors (CAP) may be electrically isolated from each other by an insulating layer, and each capacitor (CAP) may operate as a data storage unit to write or read data according to a control signal applied to the semiconductor device.

[0191] Each capacitor (CAP) may include a capacitor dielectric layer and a plurality of storage electrodes. According to the control signal provided to the first gate 290 and the second gate 340, it may be determined whether a voltage is provided to the capacitor (CAP), and the magnitude of the voltage provided to the capacitor (CAP) may also be determined. The semiconductor device may read out the stored data based on a signal corresponding to the voltage of the capacitor (CAP).

[0192] The capacitor (CAP) may have a shape extending in a vertical direction (i.e., a third direction D3) relative to the substrate layer 210 within the storage element layer 400. More specifically, the capacitor (CAP) may be formed in a cylindrical or columnar shape. Since the capacitor (CAP) has a cylindrical or columnar shape, the density of the capacitor (CAP) may be increased within the same area. As the density of the capacitor (CAP) increases, the data storage capacity of the semiconductor device may also increase. Each capacitor (CAP) may correspond to one contact pad 370, and one contact pad 370 may contact one capacitor (CAP).

[0193] Reference Figures 2A to 2D In the semiconductor device of the embodiment of the present invention, the ground voltage can be provided to the first gate 290 at the data read / write time point, and the word line driving voltage can be provided to the second gate 340 at the data write / read time point. When the ground voltage is provided to the first gate 290, the first gate 290 can provide a reverse bias voltage to the semiconductor device.

[0194] The first gate 290 may be disposed between adjacent two second gates 340. When a local voltage is supplied to the first gate 290, adjacent second gates 340 may be electrically isolated from each other.

[0195] Such electrical isolation between adjacent second gates 340 may mean that electrical interference between adjacent second gates 340 is blocked.

[0196] As the size of the semiconductor device decreases, the distance between the second gates 340 may become shorter. When the distance between the second gates 340 is shortened, a coupling phenomenon may occur between adjacent second gates 340 due to a word line driving voltage supplied to each second gate 340. Due to the coupling phenomenon, unexpected errors may occur during data read / write operations of the semiconductor device.

[0197] In some embodiments, the first gate 290 is disposed between the second gates 340, and the ground voltage is provided to the first gate 290, so that the coupling phenomenon between the second gates 340 is prevented, thereby improving the operating characteristics of the semiconductor device. In addition, since the ground voltage is provided to the first gate 290, the coupling phenomenon between the adjacent active regions 320 can be prevented during the operation of the semiconductor device.

[0198] In addition, the first gate 290 provided with the ground voltage can provide a reverse bias voltage to the semiconductor device, thereby effectively suppressing leakage current (e.g., gate induced drain leakage (GIDL)) and improving the electrical characteristics of the semiconductor device. In addition, the first gate 290 can control the threshold voltage characteristics of the semiconductor device by providing the semiconductor device with a reverse bias voltage.

[0199] Figure 2E is a schematic diagram showing a layout structure of a semiconductor device according to another embodiment of the present disclosure.

[0200] and Figure 2A different, Figure 2E A plurality of capacitors (CAP) included in the semiconductor device shown in FIG. 4 may be arranged in a zigzag shape with respect to a plurality of contact pad (PAD) arrays arranged in a matrix structure within the first region ( R1 ).

[0201] More specifically, at least a portion of each capacitor (CAP) may overlap with the contact pad (PAD). The capacitors (CAP) may be repeatedly arranged in a zigzag pattern with respect to a plurality of contact pads (PAD) overlapping with one second gate (G2). Since the capacitors (CAP) are arranged in a zigzag shape, the spacing distance between adjacent capacitors (CAP) may be ensured.

[0202] Since the spacing distance between the capacitors (CAP) is ensured, noise that may be generated by adjacent capacitors (CAP) can be reduced.

[0203] Figure 3A is a schematic diagram illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 3B is shown along Figure 3A A cross-sectional view of the semiconductor device taken along line B1-B1' shown in FIG. Figure 3C is shown along Figure 3A A cross-sectional view of the semiconductor device taken along line B2-B2' shown in FIG. Figure 3D It is shown along Figure 3A 0 is a cross-sectional view of the semiconductor device taken along line B3 - B3 ′ shown in FIG.

[0204] The layout structure of the semiconductor device observed from the third direction (D3) is Figure 3A is shown in .

[0205] A semiconductor device may include a plurality of regions within a substrate (LS).

[0206] For example, the semiconductor device may include a first region (R1) and a second region (R2) adjacent to the first region (R1), wherein a plurality of contact pads (PAD) and a plurality of capacitors (CAP) overlapping the contact pads (PAD) are provided in the first region. In the second region (R2), the gates (G1, G2) are connected to the signal lines.

[0207] The plurality of capacitors (CAP) disposed in the first region (R1) may overlap the contact pads (PAD) disposed in a matrix structure.

[0208] A plurality of capacitors (CAP) may be arranged in a form having the highest integration density.

[0209] Figure 3A The pad areas may be arranged in a matrix structure having 20 rows and 20 columns, but this is merely an example.

[0210] The second region (R2) may be a region in which a contact portion included in the first gate (G1) or the second gate (G2) is disposed.

[0211] Each contact may be connected to a conductive line that provides a control signal to the first gate (G1) or the second gate (G2). The semiconductor device may operate based on the control signal.

[0212] A bit line (BL) and a gate (G1, G2) included in the semiconductor device may extend in directions perpendicular to each other, and a capacitor (CAP) may be located in a region where the bit line (BL) and the gate (G1, G2) overlap each other.

[0213] and Figure 2A The embodiments are different. Figure 3A In the embodiment of the present invention, two first gates (G1) may be disposed between two adjacent second gates (G2). The contact portions of the first gates (G1) may be commonly connected to a wire connected to a contact portion of a second gate (G2) adjacent to the first gates G1.

[0214] Figure 3B is a cross-sectional view showing the center of the first gate G1 taken along a cutting line parallel to the second direction ( D2 ). Figure 3C is a cross-sectional view showing the center of the second gate (G2) taken along a cutting line parallel to the second direction (D2). Figure 3D is a diagram showing a view taken along a cutting line parallel to the first direction (D1) Figure 1B A cross-sectional view of the center of a bit line (BL).

[0215] Reference Figure 3B, 3C and 3D , showing a substrate layer 510 , a silicide layer 520 formed on the substrate layer 510 , and a first nitride layer 530 formed on the silicide layer 520 .

[0216] The substrate layer 510 may include a silicon semiconductor material. For example, the substrate layer 510 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, etc.

[0217] The substrate layer 510 may include a plurality of control circuits configured to control the operation of the semiconductor device, and a region in which the control circuits are provided may be referred to as a peripheral circuit region.

[0218] The silicide layer 520 formed on the substrate layer 510 may include a metal silicide material (e.g., cobalt silicide (CoSi)). The silicide layer 520 is disposed in the semiconductor device so that the operating resistance of the semiconductor device can be reduced. In addition, the silicide layer 520 can be used as a protective layer for the substrate layer 510, thereby preventing damage to the substrate layer 510 during the semiconductor manufacturing process.

[0219] The first nitride layer 530 formed on the silicide layer 520 may refer to a layer including silicon nitride. Since the first nitride layer 530 includes silicon nitride, damage to the substrate layer 510 may be prevented during a high-temperature semiconductor manufacturing process.

[0220] Reference Figure 3B , 3C 3D, the first oxide layer 540 may be disposed on the first nitride layer 530. The first oxide layer 540 may be a layer including, for example, silicon oxide, etc. The first oxide layer 540 may function as an insulating layer together with the first nitride layer 530.

[0221] Since the first nitride layer 530 and the first oxide layer 540 are provided in the semiconductor device, the control circuit included in the substrate layer 510 may be electrically isolated from the bit line 550 .

[0222] The bit line 550 may be disposed on the first oxide layer 540 and may include a plurality of layers extending in the first direction (D1). For example, the bit line 550 may include a first bit line layer 552 including titanium nitride (TiN), a second bit line layer 554 including tungsten (W), and a third bit line layer 556 including titanium nitride (TiN).

[0223] Since the bit line 550 includes a plurality of layers, the operating resistance of the semiconductor device can be adjusted.

[0224] The first bit line layer 552 and the third bit line layer 556 included in the bit line 550 may prevent the second bit line layer 554 from being oxidized due to exposure to oxygen. When the second bit line layer 554 is exposed to oxygen, tungsten (W) may be oxidized, thereby causing disconnection and defects.

[0225] In addition, titanium nitride (TiN) included in the first bit line layer 552 may have higher adhesion to silicon oxide than tungsten (W), and the first bit line layer 552 is disposed between the first oxide layer 540 and the second bit line layer 554, thereby improving the mechanical stability of the bit line 550. After depositing a plurality of layers, the bit line 550 may be formed by an etching process using a mask.

[0226] Adjacent bit lines 550 may be electrically isolated from each other by second and third bit line isolation layers 570 and 580. In some embodiments, the second bit line isolation layer 570 may include silicon nitride, and the third bit line isolation layer 580 may include silicon oxide.

[0227] An isolation oxide layer 592 may be disposed between two adjacent first gates 590. The two first gates 590 and the isolation oxide layer 592 may be disposed on the first bit line isolation layer 560.

[0228] In addition, the first gate oxide layer 610 may be disposed to surround the adjacent two first gates 590 and the isolation oxide layer 592. The first gate oxide layer 610 may electrically isolate the active region 620 and the first gate 590 from each other, and may include an insulating material such as silicon oxide.

[0229] The first gate 590 and the bit line 550 may be electrically isolated from each other by a first bit line isolation layer 560 .

[0230] The second bit line isolation layer 570 and the third bit line isolation layer 580 may serve as spacers to electrically isolate adjacent bit lines 550 from each other.

[0231] A first bit line isolation layer 560 may be disposed over each bit line 550 to electrically isolate the bit line 550 from the first gate 590. The first bit line isolation layer 560 may include silicon oxide containing carbon (SiCO).

[0232] Reference Figure 3C and 3D , an active region 620 electrically connected to at least a portion of the bit line 550 may be disposed above the bit line 550 . The active region 620 may be electrically isolated from the second gate 640 by the second gate oxide layer 630 .

[0233] The first gate 590 and the second gate 640 may include a metal, a metal mixture, a metal alloy, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first gate 590 and the second gate 640 may include titanium nitride.

[0234] Reference Figure 3D , an isolation oxide layer 592 may be disposed between two adjacent first gates 590. The isolation oxide layer 592 may be formed before the first gate 590 is deposited on the bit line 550. The isolation oxide layer 592 may extend in a direction parallel to a direction in which the first gate 590 extends (eg, direction D2).

[0235] The isolation oxide layer 592 may be formed by etching an oxide layer disposed on the bit line 550 and the bit line isolation layer 580 after forming the bit line 550 , the first bit line isolation layer 560 , the second bit line isolation layer 570 , and the third bit line isolation layer 580 .

[0236] A titanium nitride layer may be formed over the isolation oxide layer 592, and the titanium nitride layer may be etched so that the isolation oxide layer 592 is disposed between the first gates 590. Adjacent first gates 590 may be electrically isolated from each other by the isolation oxide layer 592.

[0237] Adjacent second gates 640 may be electrically isolated from each other by the third nitride layer 650 .

[0238] The second oxide layer 660 may be disposed on the third nitride layer 650 between the second gates 640 .

[0239] A contact connecting the first gate 590 and the wire may be formed in the first gate 590 using an etching rate difference between the second oxide layer 660 and the third nitride layer 650. A contact through which the second gate 640 and the wire are connected may be formed in the second gate 640.

[0240] In some embodiments, the contact portions of the adjacent first gate 590 and the contact portions of the second gate 640 may be connected to one conductive line.

[0241] like Figure 3A As shown, the contact portions corresponding to the first gate 590 or the contact portions corresponding to the second gate 640 may be sparsely arranged in a zigzag pattern in the first direction ( D1 ).

[0242] The active region 620 may include a horizontal portion and a vertical portion, the horizontal portion being formed to contact the bit line 550, and the vertical portion being formed to extend in the vertical direction (D3) and disposed between the first gate 590 and the second gate 640. The active region 620 may include, for example, an oxide semiconductor material, and the oxide semiconductor material may include indium gallium zinc oxide (IGZO).

[0243] In another embodiment, the active region 620 may include doped polysilicon, undoped polysilicon, amorphous silicon, indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0244] Since IGZO has a low leakage current characteristic and the active region 620 is formed of IGZO, a semiconductor device with low standby power may be implemented.

[0245] In addition, since the active region 620 includes IGZO, the manufacturing process difficulty may be reduced, and the active region 620 having a three-dimensional (3D) structure including vertical and horizontal portions may be easily formed.

[0246] One end of the vertical portion included in the active region 620 may contact the contact pad 670 , which connects the capacitor (CAP) and the active region 620 to each other.

[0247] The contact pad 670 may include a plurality of layers to reduce the contact resistance between the active region 620 and the capacitor (CAP).

[0248] Reference Figure 3C and 3D , the width of the contact pad 670 may be greater than the width of the vertical portion. Since the width of the contact pad 670 is greater than the width of the vertical portion, the contact area between the capacitor (CAP) and the contact pad 670 may be ensured, thereby ensuring the mechanical stability of the semiconductor device.

[0249] The contact pad 670 may include a first pad layer 672 and a second pad layer 674 .

[0250] Since the first pad layer 672 includes the same material as the active region 620, an interface resistance between the contact pad 670 and the active region 620 may be reduced. For example, the first pad layer 672 may include an oxide semiconductor material such as IGZO.

[0251] In another embodiment, the first pad layer 672 may include indium zinc oxide (IZO), indium tin oxide (ITO), indium oxide (InO 3 ), or the like.

[0252] The second pad layer 674 formed on the first pad layer 672 may include titanium nitride (TiN). Since the second pad layer 674 is formed, the interface resistance between the contact pad 670 and the capacitor (CAP) may be reduced.

[0253] The capacitor (CAP) disposed over the contact pad 670 may be arranged such that at least a portion thereof overlaps the contact pad 670 .

[0254] The fourth nitride layer 680 may electrically isolate adjacent contact pads 670 from each other. The fourth nitride layer 680 may be disposed to surround the contact pads 670. The fourth nitride layer 680 may be disposed between adjacent contact pads 670.

[0255] Capacitors (CAP) may be provided in the memory element layer 700. The capacitors (CAP) may be electrically isolated from each other by an insulating layer, and each capacitor (CAP) may operate as a data storage unit to write or read data according to a control signal applied to the semiconductor device.

[0256] Each capacitor (CAP) may include a capacitor dielectric layer and a plurality of storage electrodes. According to the control signal provided to the first gate 590 and the second gate 640, it may be determined whether a voltage is provided to the capacitor (CAP), and the magnitude of the voltage provided to the capacitor (CAP) may also be determined. The semiconductor device may read out the stored data based on a signal corresponding to the voltage of the capacitor (CAP).

[0257] The capacitor (CAP) may have a shape extending in a vertical direction (i.e., a third direction D3) relative to the substrate layer 510 within the storage element layer 700. More specifically, the capacitor (CAP) may be formed in a cylindrical or columnar shape. Since the capacitor (CAP) has a cylindrical or columnar shape, the density of the capacitor (CAP) may be increased within the same area. As the density of the capacitor (CAP) increases, the data storage capacity of the semiconductor device may also increase. Each capacitor (CAP) may correspond to one contact pad 670, and one contact pad 670 may contact one capacitor (CAP).

[0258] Reference Figures 3A to 3D In the semiconductor device of the embodiment, a word line driving voltage may be provided to the first gate 590 and the second gate 640 adjacent to the first gate 590 at a data read / write time point.

[0259] When a word line driving voltage is applied to the first gate 590 and the second gate 640 adjacent to the first gate 590 , two channel regions may be formed at both side surfaces of the active region 620 .

[0260] Since two channel regions are formed, electron mobility may increase, and the semiconductor device may be easily controlled with a low driving voltage.

[0261] A semiconductor device according to another embodiment may include the first gate 590 and the second gate 640 , thereby realizing an evolved semiconductor device having improved operating current characteristics and higher electron mobility.

[0262] Figure 3Eis a schematic diagram showing a layout structure of a semiconductor device according to another embodiment of the present disclosure.

[0263] and Figure 3A different, Figure 3E A plurality of capacitors (CAP) included in the semiconductor device shown in FIG. 4 may be arranged in a zigzag shape with respect to a plurality of contact pad (PAD) arrays arranged in a matrix structure within the first region ( R1 ).

[0264] More specifically, at least a portion of each capacitor (CAP) may overlap with the contact pad (PAD). The capacitors (CAP) may be repeatedly arranged in a zigzag pattern with respect to a plurality of contact pads (PAD) overlapping with one second gate (G2). Since the capacitors (CAP) are arranged in a zigzag shape, the spacing distance between adjacent capacitors (CAP) may be ensured.

[0265] Since the spacing distance between the capacitors (CAP) is ensured, noise that may be generated by adjacent capacitors (CAP) can be reduced.

[0266] FIG. 4A to FIG. 19C is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0267] Figure 4A is a perspective view 1000 a showing a method for manufacturing a semiconductor device, in which a bit line 250 is formed on a first oxide layer 240 .

[0268] Referring to the perspective view 1000 a , the bit lines 250 may extend in a first direction ( D1 ) on a first oxide layer 240 formed over a substrate layer 210 , and may be continuously arranged in a second direction ( D2 ).

[0269] Figure 4B is shown along Figure 4A A cross-sectional view of the semiconductor device taken along line C1-C1' shown in FIG. Figure 4C It is shown along Figure 4A 0 is a cross-sectional view of the semiconductor device taken along line C2 - C2 ′ shown in FIG.

[0270] Reference Figure 4B and Figure 4C ( Figure 4B shows a cross-sectional view showing adjacent bit lines 250, Figure 4C 2 ), the bit lines (each of which includes a first bit line layer 252, a second bit line layer 254, and a third bit line layer 256) may be arranged to be spaced apart from each other at a preset interval over the first oxide layer 240. A bit line isolation layer 260 may be disposed over the bit line 250.

[0271] The layout structure of the bit line 250 may vary according to the shape of a mask used in the etching process.

[0272] Figure 5A is a perspective view 1000 b showing a method for manufacturing a semiconductor device, in which a first gate 290 is formed over a first bit line isolation layer 260 , a second bit line isolation layer 270 , and a third bit line isolation layer 280 .

[0273] Figure 5B is shown along Figure 5A A cross-sectional view of the semiconductor device taken along line D1-D1' shown in FIG. Figure 5C is shown along Figure 5A 0 is a cross-sectional view of the semiconductor device taken along line D2 - D2 ′ shown in FIG.

[0274] Reference Figure 5B and Figure 5C ( Figure 5B 2 shows a cross-sectional view of the semiconductor device taken along the center of the first gate 290, Figure 5C 2 ), a second bit line isolation layer 270 and a third bit line isolation layer 280 may be formed between the bit lines 250 to electrically isolate the adjacent bit lines 250 from each other.

[0275] After forming a second bit line isolation layer 270 including silicon nitride over the bit line 250 and the first bit line isolation layer 260, and forming a third bit line isolation layer 280 including silicon oxide over the second bit line isolation layer 270, a chemical planarization process such as a chemical mechanical polishing (CMP) process may be performed so that the second bit line isolation layer 270 and the third bit line isolation layer 280 may be formed between the bit lines.

[0276] The second bit line isolation layer 270 and the third bit line isolation layer 280 may serve as spacers to electrically isolate adjacent bit lines 250 from each other.

[0277] The method for forming the first gate 290 is as follows. A titanium nitride (TiN) layer, a silicon nitride layer, and a silicon oxide layer are sequentially formed on the first bit line isolation layer 260, the second bit line isolation layer 270, and the third bit line isolation wall 280, and then etched using a mask including a spin-on carbon (SoC) layer and a silicon oxynitride (SiON) layer, thereby forming the first gate 290.

[0278] The layout structure of the first gate 290 may vary according to the shape of a mask used in the etching process.

[0279] Since the silicon nitride layer and the silicon oxide layer are formed over the titanium nitride (TiN) layer, damage to the titanium nitride (TiN) layer during an etching process may be prevented.

[0280] After etching the silicon nitride layer and the silicon oxide layer, the silicon nitride layer may be used as the second nitride layer 300 , and the silicon oxide layer may be used as the protective oxide layer 302 .

[0281] The second nitride layer 300 and the protective oxide layer 302 may prevent damage to the first gate 290 during a semiconductor manufacturing process and may electrically isolate the first gate 290 from other components (eg, an active region) included in a semiconductor device.

[0282] Fig. 6A 1000 c is a perspective view illustrating a method for manufacturing a semiconductor device, in which a first gate oxide layer 310 and a protective silicon layer 312 are formed over a first gate 290 .

[0283] Figure 6B is shown along Fig. 6A A cross-sectional view of the semiconductor device taken along line E1-E1' shown in FIG. Figure 6C is shown along Fig. 6A 0 is a cross-sectional view of the semiconductor device taken along line E2 - E2 ′ shown in FIG.

[0284] Reference Figure 6B and Figure 6C ( Figure 6B 2 shows a cross-sectional view of the semiconductor device taken along the center of the first gate 290, Figure 6C ), showing a cross-sectional view of a semiconductor device taken along first gates 290 adjacent to each other, a second nitride layer 300 and a protective oxide layer 302 may be formed over the first gate, and a first gate oxide layer 310 and a protective silicon layer 312 may be formed to overlap with the protective oxide layer 301, the first bit line isolation layer 260, and the third bit line isolation layer 280.

[0285] Since the protection silicon layer 312 is disposed in the semiconductor device, the first gate oxide layer 310 disposed under the protection silicon layer 312 may be protected during the etching process.

[0286] The protective silicon layer 312 may be a layer including polysilicon. Since the protective silicon layer 312 is disposed in the semiconductor device, the first bit line isolation layer 260 disposed above the bit line 250 may be etched to form an active region 320 contacting at least a portion of the bit line 250. In this case, damage to the first gate oxide layer 310 may be prevented.

[0287] When the protective silicon layer 312 is not provided, the first gate oxide layer 310 may be directly exposed to plasma during the etching process, and side effects such as a reduction in the thickness of the first gate oxide layer 310 and surface defects caused by plasma may occur.

[0288] Fig. 7A is a perspective view 1000d showing a method for manufacturing a semiconductor device, in which at least a portion of the protective silicon layer 312, at least a portion of the first gate oxide layer 310, and at least a portion of the first bit line isolation layer 260 are etched.

[0289] Figure 7B is shown along Fig. 7A A cross-sectional view of the semiconductor device taken along line F1-F1' shown in FIG. Figure 7C is shown along Fig. 7A 0 is a cross-sectional view of the semiconductor device taken along line F2 - F2 ′ shown in FIG.

[0290] Reference Figure 7B and Figure 7C ( Figure 7B 2 shows a cross-sectional view of the semiconductor device taken along the center of the first gate 290, Figure 7C 290 ), after the plasma etching process is completed, the first gate oxide layer 310 can be disposed along the sidewalls of the first gate 290 and the first bit line isolation layer 260 disposed under the first gate 290, and the protective silicon layer 312 can be retained on the first gate oxide layer 310 along the sidewalls of the first gate 290.

[0291] The first gate oxide layer 310 disposed between the protective silicon layer 312 and the first gate 290 may be protected from the plasma by the remaining protective silicon layer 312. Thereafter, the remaining protective silicon layer 312 may be selectively removed by a separate silicon etching process.

[0292] The silicon etching process may include, for example, a wet etching process.

[0293] Fig. 8A is a perspective view illustrating a method for manufacturing a semiconductor device, in which a pre-active region layer 322 is formed over a first gate 290 and a bit line 250 .

[0294] Figure 8B is shown along Fig. 8A A cross-sectional view of the semiconductor device taken along line G1-G1' shown in FIG. Figure 8C is shown along Fig. 8A 0 is a cross-sectional view of the semiconductor device taken along line G2 - G2 ′ shown in FIG.

[0295] Reference Figure 8B ( Figure 8B 290) and Figure 8C ( Figure 8CA cross-sectional view of a semiconductor device taken along first gate electrodes 290 adjacent to each other is shown), a second nitride layer 300 is formed on the first gate electrode 290, a protective oxide layer 302 may be formed on the second nitride layer 300, and a pre-active region layer 322 containing indium gallium zinc oxide (IGZO) may be formed on the protective oxide layer 302.

[0296] The pre-active region layer 322 may be formed to overlap the first gate 290 and the exposed bit line 250 .

[0297] For example, the pre-active region layer 322 may be formed of an amorphous oxide semiconductor material, and may be formed by an atomic layer deposition (ALD) method.

[0298] When the pre-active region layer 322 is formed by atomic layer deposition (ALD), the thickness of the pre-active region layer 322 may be easily adjusted, and the film quality of the pre-active region layer 322 may be uniformly formed, thereby improving electrical characteristics of the semiconductor device.

[0299] Fig.9A 1000 f is a perspective view illustrating a method for manufacturing a semiconductor device, in which an active region 320 is selectively formed over a first gate 290 and a bit line 250 .

[0300] Fig. 9B is shown along Fig.9A A cross-sectional view of the semiconductor device taken along line H1-H1' shown in FIG. Fig. 9C is shown along Fig. 9A 0 is a cross-sectional view of the semiconductor device taken along line H2 - H2 ′ shown in FIG.

[0301] Reference Fig. 9B ( Fig. 9B 290) and Fig. 9C ( Fig. 9C 290 , each active region 320 may be arranged along a first gate oxide layer 310 , the first gate oxide layer 310 including a horizontal portion formed to contact the bit line 250 and a vertical portion arranged along a sidewall of the first gate 290 .

[0302] Adjacent active regions 320 may be preferentially isolated from each other in the second direction (D2) in which the first gate 290 extends. After the second gate 340 is formed, the second gate 340 is then etched so that the second gates 340 may be isolated from each other in the first direction (D1).

[0303] The width of the active region 320 viewed from the first direction ( D1 ) may be equal to or smaller than the width of the bit line 250 viewed from the first direction ( D1 ).

[0304] A mask including a spin-on carbon (SoC) layer and a silicon oxynitride (SiON) layer may be formed over the pre-active region layer 322 , and the pre-active region layer 322 may be selectively etched so that the active region 320 may be selectively formed in some regions.

[0305] In some embodiments, the formation of the active region 320 may be performed using two masks having different etching characteristics.

[0306] Fig. 10A 1000g is a perspective view showing a method for manufacturing a semiconductor device, in which a second gate oxide layer 330, a pre-second gate layer 342, and a contact mask 344 are formed.

[0307] Fig. 10B is shown along Fig. 10A A cross-sectional view of the semiconductor device taken along line I1-I1' shown in FIG. Fig. 10C is shown along Fig. 10A A cross-sectional view of the semiconductor device taken along line I2-I2' shown in FIG. Fig. 10D is shown along Fig. 10A 0 is a cross-sectional view of the semiconductor device taken along line I3 - I3 ′ shown in FIG.

[0308] Reference Fig. 10B ( Fig. 10B 290) and Fig. 10C ( Fig. 10C 290 , the second gate oxide layer 330 may be disposed on the active region 320 , and the active region 320 and the pre-second gate layer 342 may be electrically isolated from each other by the second gate oxide layer 330 .

[0309] The second gate 340 may be formed by etching the second gate layer 342 .

[0310] Fig. 10D is a diagram showing the semiconductor manufacturing process during Figure 2A A cross-sectional view of the region corresponding to the second region (R2) shown in FIG.

[0311] Reference Fig. 10D The contact mask 344 may be used to form a contact 346 of the second gate 340 by selectively etching the pre-second gate layer 342. By preventing the pre-second gate layer 342 formed to overlap the contact mask 344 from being etched, a contact 346 for connecting the second gate 340 to a conductive line may be formed.

[0312] The active region 320 is not formed in the second region ( R2 ). The bit line 250 and the first bit line isolation layer 260 are not formed in the second region ( R2 ) so that the first gate 290 and the first gate oxide layer 310 may be disposed on the third bit line isolation layer 280 .

[0313] In some embodiments, the contact mask 344 may include a spin-on-carbon (SoC) material, and the SoC doping layer may be etched such that only the contact mask 344 remains.

[0314] Fig.11A 1000h is a perspective view showing a method for manufacturing a semiconductor device, in which a second gate layer 340 and a contact 346 are formed.

[0315] Fig. 11B is shown along Fig.11A A cross-sectional view of the semiconductor device taken along the line J1-J1' shown in FIG. Fig. 11C is shown along Fig.11A A cross-sectional view of the semiconductor device taken along line J2-J2' shown in FIG. Fig.11D is shown along Fig.11A 0 is a cross-sectional view of the semiconductor device taken along line J3 - J3 ′ shown in FIG.

[0316] Reference Fig. 11B ( Fig. 11B 290) and Fig. 11C ( Fig. 11C 2 shows a cross-sectional view of a semiconductor device taken along the first gates 290 adjacent to each other), the second gate 340 may be formed by selectively etching the pre-second gate layer 342.

[0317] The second gate 340 may include titanium nitride (TiN), and only the second gate 340 may be selectively etched using an etching rate difference between the titanium nitride (TiN) layer and the second gate oxide layer 330. Adjacent second gates 340 may be physically / electrically isolated from each other by an etching process.

[0318] Fig.11D 3 is a cross-sectional view showing a contact portion 346 formed at one side of the second gate 340. Fig.11D The contact portion 346 may be physically isolated from another adjacent second gate 340 by an etching process, and may include an edge region having a width greater than that of the second gate 34 to facilitate connection with a wire.

[0319] After selectively etching the contacts 346 , the contact mask 344 may be removed.

[0320] Fig. 12A1000i is a perspective view showing a method for manufacturing a semiconductor device, in which a third nitride layer 350 and a second oxide layer 360 are formed.

[0321] Fig. 12B is shown along Fig. 12A A cross-sectional view of the semiconductor device taken along line K1-K1' shown in FIG. Fig. 12C is shown along Fig. 12A A cross-sectional view of the semiconductor device taken along line K2-K2' shown in FIG. Fig.12D is shown along Fig. 12A 0 is a cross-sectional view of the semiconductor device taken along line K3 - K3 ′ shown in FIG.

[0322] Reference Fig. 12B ( Fig. 12B 290) and Fig. 12C ( Fig. 12C 290 , which are adjacent to each other, the third nitride layer 350 may be formed to surround the adjacent second gate and the second gate oxide layer 330 , and the second oxide layer 360 may be formed on the third nitride layer 350 .

[0323] Since the silicon nitride layer and the silicon oxide layer are sequentially deposited and then a CMP (chemical mechanical polishing) process is performed on the resultant structure, the third nitride layer 350 and the second oxide layer 360 may have Figures 12A to 12C Shape shown.

[0324] Fig.12D 3 is a cross-sectional view showing a third nitride layer 350 and a second oxide layer 360 formed at one side of the contact portion 346. When the contact portion 346 is provided, the doping shape of the silicon nitride may be different from that of the Fig. 12C doping shape.

[0325] The following will refer to Figures 13 to 15 Described in Figure 2A 1 and 2. A process for isolating adjacent second gate electrodes 340 from each other in the second region R2 shown in FIG.

[0326] like Fig.11A As shown, two adjacent second gate electrodes 340 may be formed to contact each other in the second region ( R2 ) and surround one end of the first gate electrode 290 adjacent to the second gate electrode 340 .

[0327] In order for each second gate 340 to be driven as a word line, adjacent two second gates 340 should be electrically isolated from each other. Isolating adjacent second gates 340 from each other in the second region R2 allows the second gates 340 to operate individually.

[0328] Fig.13 is a perspective view 1000 j showing a method for manufacturing a semiconductor device, in which a portion of the second oxide layer 360 is etched.

[0329] Reference Fig.13 , a portion of the second oxide layer 360 may be removed by wet etching so that one end of the second gate 340 may be easily separated.

[0330] Fig.14 is a perspective view 1000 k showing a method for manufacturing a semiconductor device, in which a mask is formed over the etched second oxide layer 360 .

[0331] A mask is formed, and both ends of the second gate 340 are selectively etched using the mask so that adjacent second gates 340 can be isolated from each other.

[0332] The mask may include a SOC layer and a SiON layer. The mask may be used to define a region in which one end of the second gate 340 is separated.

[0333] Fig.15 10001 is a perspective view showing a method for manufacturing a semiconductor device, in which the mask is removed after both ends of the second gate 340 are selectively etched.

[0334] Reference Fig.15 , one end of the second gate 340 is separated, and the third nitride layer 350 of the corresponding region is etched, so that adjacent second gates 34 can be electrically isolated from each other.

[0335] Fig.16A is a perspective view 1000 m illustrating a method for manufacturing a semiconductor device, in which adjacent active regions 320 are isolated from each other in a first direction ( D1 ).

[0336] Fig. 16B is shown along Fig.16A A cross-sectional view of the semiconductor device taken along line L1-L1' shown in FIG. Fig. 16C is shown along Fig.16A A cross-sectional view of the semiconductor device taken along line L2-L2' shown in FIG. Fig.16D is shown along Fig.16A 0 is a cross-sectional view of the semiconductor device taken along line L3 - L3 ′ shown in FIG.

[0337] Reference Fig. 16B ( Fig. 16B 290) and Fig. 16C ( Fig. 16C), showing a cross-sectional view of a semiconductor device taken along first gates 290 adjacent to each other, a portion of the third nitride layer 350, a portion of the second gate oxide layer 330, a portion of the active area 320, a portion of the first gate oxide layer 310, and the protective oxide layer 302 may be removed by etching or a CMP (chemical mechanical polishing) process.

[0338] Reference Fig.16D , similar to Fig. 16C , a portion of third nitride layer 350 , a portion of second gate oxide layer 330 , a portion of first gate oxide layer 310 , and protective oxide layer 302 (not shown) may be removed by an etching process, and at least a portion of contact 346 may be exposed.

[0339] Fig.17A 3 is a perspective view illustrating a method for manufacturing a semiconductor device, in which a contact pad contacting one end of a vertical portion included in an active region 320 is formed.

[0340] Fig. 17B is shown along Fig.17A A cross-sectional view of the semiconductor device taken along the line M1-M1' shown in FIG. Fig. 17C is shown along Fig.17A 0 is a cross-sectional view of the semiconductor device taken along line M2 - M2 ′ shown in .

[0341] Reference Fig. 17B ( Fig. 17B 290) and Fig. 17C ( Fig. 17C ), a first pad layer 372, a second pad layer 374, a first hard mask layer 371, and a second hard mask layer 373 may be sequentially formed on the second nitride layer 300. Here, the first pad layer 372 has the same material as the active area 320 and is connected to the active area 320. The second pad layer 374 is disposed on the first pad layer 372 and includes a conductive material. The first hard mask layer 371 is disposed on the second pad layer 374 and includes a hard mask for etching the first pad layer 372 and the second pad layer 374. The second hard mask layer 373 is disposed on the first hard mask layer 371 and includes a hard mask for etching the first pad layer 372 and the second pad layer 374.

[0342] The first hard mask layer 371 may be a silicon nitride layer, and the second hard mask layer 372 may be a silicon oxide layer.

[0343] In addition, the first SoC (spin-on carbon) layer 375, the first SiON layer 376 and the first mask (MASK1) may be sequentially disposed on the second hard mask layer 373. The first mask (MASK1) may include a plurality of linear masks extending in the first direction (D1) and arranged continuously in the second direction (D2) at regular intervals. The first mask (MASK1) may be disposed to overlap with the region where the contact pad 370 (372, 374) is formed.

[0344] More specifically, the first mask (MASK1) may be arranged such that the contact pad 370 is formed in a region where the vertical portions of the bit line 250 and the active region 320 overlap each other.

[0345] Fig.17D is a diagram showing the etching process of the second hard mask layer 373 after the etching process. Fig.17A A cross-sectional view of a semiconductor taken along the line M1-M1' shown in FIG. Fig.17E is a diagram showing the etching process of the second hard mask layer 373 after the etching process. Fig.17A 0 is a cross-sectional view of the semiconductor device taken along line M2 - M2 ′ shown in .

[0346] Reference Fig.17D and 17E , the second hard mask layer 373 may be etched to form a plurality of main hard masks 373 a , each of which is etched to extend in the first direction ( D1 ) and is repeatedly disposed in the second direction ( D2 ).

[0347] Fig.18A 1000 o is a perspective view illustrating a method for manufacturing a semiconductor device, in which a contact pad contacting one end of a vertical portion included in an active region is formed.

[0348] Fig.18B is shown along Fig.18A A cross-sectional view of the semiconductor device taken along line N1-N1' shown in FIG. Fig.18C is shown along Fig.18A 0 is a cross-sectional view of the semiconductor device taken along line N2 - N2 ′ shown in FIG.

[0349] Reference Fig.18B ( Fig.18B 290) and Fig.18C ( Fig.18C ), showing a cross-sectional view of a semiconductor device taken along first gates 290 adjacent to each other, a second SoC layer 377 , a second SiON layer 378 , and a second mask (MASK2 ) may be sequentially disposed on a main hard mask 373 a formed by a second hard mask layer 373 .

[0350] The second mask (MASK2) may extend in a direction (D2) perpendicular to the first mask (MASK1). The second mask (MASK2) may include a plurality of masks repeatedly arranged at regular intervals in the first direction (D1). Since the main hard mask 373a is etched using the second mask (MASK2), hard masks repeatedly arranged in a matrix structure may be formed.

[0351] Fig.19A 1000P is a perspective view illustrating a method for manufacturing a semiconductor device, in which a contact pad contacting one end of a vertical portion included in an active region 320 is formed.

[0352] Fig.19B is shown along Fig.19A A cross-sectional view of the semiconductor device taken along line O1-O1' shown in FIG. Fig.19C It is shown Fig.19A A cross-sectional view of the semiconductor device taken along line O2 - O2 ' is shown in FIG.

[0353] Reference Fig.19B At least one secondary hard mask 373b formed by the two etching processes may have the same width in the first direction (D1) and the second direction (D2), and may be arranged to have a layout structure in which the secondary hard masks 373b are repeatedly arranged in a matrix shape.

[0354] The layout structure of the contact pads may vary according to the shape of the secondary hard mask 373b. In addition, the shape of the secondary hard mask 373b may vary according to the number of storage elements (eg, capacitors) provided in the semiconductor device.

[0355] Reference Fig.19B ( Fig.19B 290) and Fig.19C ( Fig.19C 1 shows a cross-sectional view of a semiconductor device taken along first gate electrodes 290 adjacent to each other), and shows a cross-sectional view of a secondary hard mask 373 b for forming a contact pad 370. The secondary hard mask 373 b may be repeatedly arranged in a matrix structure and may be formed to overlap one end of a vertical portion of the active region 320.

[0356] Thereafter, the first pad layer 372 and the second pad layer 374 are selectively etched using the secondary hard mask 373 b , so that the contact pad 370 arranged in a matrix structure and contacting one end of the vertical portion of the active region 320 may be formed.

[0357] In some embodiments, an additional insulation layer pattern may be formed over the secondary hard mask 373 b , and the first pad layer 372 and the second pad layer 374 may be selectively etched using the insulation layer pattern and the secondary hard mask 373 b .

[0358] The additional insulating layer pattern may include an ultra low temperature oxide (ULTO).

[0359] Since the contact pads 370 are formed using the additional insulating layer pattern and the secondary hard mask 373 b , the area of ​​each contact pad 370 may be greater than the secondary hard mask 373 b .

[0360] After the contact pads 370 are etched, a fourth nitride layer 380 may be formed between the contact pads 370 to electrically isolate adjacent contact pads 370 from each other. The fourth nitride layer 380 may be formed to have a Figure 2C , 2D The shape surrounding the contact pad 370 is shown.

[0361] FIG. 20A to FIG. 25C is a diagram illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0362] Fig. 20A 1000 q is a perspective view illustrating a method for manufacturing a semiconductor device, in which an isolation oxide layer 592 is formed over a first bit line isolation layer 560 , a second bit line isolation layer 570 , and a third bit line isolation layer 580 .

[0363] Fig. 20B is shown along Fig. 20A A cross-sectional view of the semiconductor device taken along line P1-P1' shown in FIG. Fig. 20C is shown along Fig. 20A 0 is a cross-sectional view of the semiconductor device taken along line P2 - P2 ′ shown in FIG.

[0364] Reference Fig. 20B ( Fig. 20B 5 shows a cross-sectional view of a semiconductor device taken along a plurality of bit lines 550) and Fig. 20C ( Fig. 20C ), illustrating a cross-sectional view of a semiconductor device taken along the center of a bit line 550 , the isolation oxide layer 592 may extend in a direction ( D2 ) perpendicular to a first direction ( D1 ) in which the bit line 550 extends.

[0365] The isolation oxide layer 592 may include silicon oxide, and may be formed by etching an oxide layer formed over the first bit line isolation layer 560 , the second bit line isolation layer 570 , and the third bit line isolation layer 580 .

[0366] Fig.21A1000 r is a perspective view illustrating a method for manufacturing a semiconductor device, wherein a pre-first gate layer 594 is formed on an isolation oxide layer 592 .

[0367] Fig. 21B is shown along Fig.21A A cross-sectional view of the semiconductor device taken along line Q1-Q1' shown in FIG. Fig. 21C is shown along Fig.21A 0 is a cross-sectional view of the semiconductor device taken along line Q2 - Q2 ′ shown in FIG.

[0368] Reference Fig. 21B ( Fig. 21B 592) and Fig. 21C ( Fig. 21C ), a pre-first gate layer 594 including a conductive material such as titanium nitride (TiN) may be formed to overlap the isolation oxide layer 595 and the first bit line isolation layer 560 .

[0369] Fig.22A 1000 s is a perspective view illustrating a method for manufacturing a semiconductor device, wherein a first gate 590 is formed by etching a pre-first gate layer 594 , and a first gate oxide layer 610 is formed over the first gate 590 .

[0370] Fig. 22B is shown along Fig.22A A cross-sectional view of the semiconductor device taken along line R1-R1' shown in FIG. Fig. 22C is shown along Fig.22A 0 is a cross-sectional view of the semiconductor device taken along line R2 - R2 ′ shown in FIG.

[0371] Reference Fig. 22B ( Fig. 22B 592) and Fig. 22C ( Fig. 22C 550), a first gate 590 (see Figure 3C and Figure 3D ) can be formed to extend along the sidewall of the isolation oxide layer 592 by an etching process, and the first gate oxide layer 610 can be formed to overlap with the first gate 590.

[0372] The first gate oxide layer 610 may include silicon oxide, and may be disposed to surround the first gates 590 and the isolation oxide layer 592 disposed between the first gates 590 .

[0373] Fig.23Ais a perspective view illustrating a method for manufacturing a semiconductor device, in which a protective silicon layer 612 is formed over a first gate oxide layer 610 .

[0374] Fig. 23B is shown along Fig.23A A cross-sectional view of the semiconductor device taken along the line S1-S1' shown in FIG. Fig.23C is shown along Fig.23A 0 is a cross-sectional view of the semiconductor device taken along line S2 - S2 ′ shown in FIG.

[0375] Reference Fig. 23B ( Fig. 23B 592) and Fig.23C ( Fig.23C 5 ), a protective silicon layer 612 may be formed over the first gate oxide layer 610 .

[0376] During the etching process, the protection silicon layer 612 may protect the first gate oxide layer 610 located below the protection silicon layer 612 .

[0377] The protective silicon layer 612 may be a layer including polysilicon. Since the protective silicon layer 612 is disposed in the semiconductor device, the first bit line isolation layer 560 disposed above the bit line 550 may be etched to form an active region 320 contacting at least a portion of the bit line 550. At this time, damage to the first gate oxide layer 610 may be prevented.

[0378] Fig.24A is a perspective view 1000u showing a method for manufacturing a semiconductor device, in which at least a portion of the protective silicon layer 612, at least a portion of the first gate oxide layer 610, and at least a portion of the first bit line isolation layer 560 are etched.

[0379] Fig. 24B is shown along Fig.24A A cross-sectional view of the semiconductor device taken along line T1-T1' shown in FIG. Fig.24C is shown along Fig.24A 0 is a cross-sectional view of the semiconductor device taken along line T2 - T2 ′ shown in FIG.

[0380] Reference Fig. 24B ( Fig. 24B 592) and Fig.24C ( Fig.24C), showing a cross-sectional view of a semiconductor device taken along the center of a bit line 550, after the plasma etching process is completed, a first gate oxide layer 610 may be disposed along the side walls of the first gate 590 and a first bit line isolation layer 560 disposed under the first gate 590, and a protective silicon layer 612 may remain on the first gate oxide layer 610 along the side walls of the first gate 590.

[0381] The first gate oxide layer 610 disposed between the protective silicon layer 612 and the first gate 590 may be protected from plasma by the remaining protective silicon layer 610. Thereafter, the remaining protective silicon layer 612 may be selectively removed by a separate silicon etching process. The silicon etching process may include, for example, a wet etching process.

[0382] Fig.25A 1000 v is a perspective view illustrating a method for manufacturing a semiconductor device, wherein a pre-active region layer 622 is formed over the first gate oxide layer 610 and the bit line 550 .

[0383] Fig.25B is shown along Fig.25A A cross-sectional view of the semiconductor device taken along the line U1-U1' shown in FIG. Fig.25C It is shown along Fig.25A A cross-sectional view of the semiconductor device taken along line U2 - U2 ′.

[0384] Reference Fig.25B ( Fig.25B 592) and Fig.25C ( Fig.25C ), showing a cross-sectional view of a semiconductor device taken along the center of a bit line 550 , a first gate oxide layer 610 may be formed over the first gate 590 and the isolation oxide layer 592 .

[0385] A pre-active region layer 622 including indium gallium zinc oxide (IGZO) may be formed on the first gate oxide layer 610. The pre-active region layer 622 may be formed to overlap the exposed bit line 550.

[0386] For example, the pre-active region layer 622 may be formed of an amorphous oxide semiconductor. The pre-active region layer 622 may be formed by atomic layer deposition (ALD).

[0387] When the pre-active region layer 622 is formed by atomic layer deposition (ALD), the thickness of the pre-active region layer 622 may be easily adjusted, and the film quality of the pre-active region layer 622 may be uniformly formed, thereby improving electrical characteristics of the semiconductor device.

[0388] The subsequent manufacturing process of the semiconductor device according to another embodiment of the present disclosure can be the same as that of the above-mentioned Figures 9A to 19C The process described is essentially the same.

[0389] Active region 620 may be formed by selectively etching first gate 590 , isolation oxide layer 592 , and pre-active region layer 622 formed over first gate oxide layer 610 , and second gate oxide layer 630 and at least one second gate 640 may be formed over active region 620 .

[0390] In addition, a third nitride layer 650 that electrically isolates the second gates 640 from each other may be formed between the second gates 640 , and a contact pad contacting one side of the vertical portion included in the active region 620 may be formed.

[0391] As apparent from the above description, semiconductor devices according to some embodiments of the present disclosure include a three-dimensional (3D) channel to improve integration.

[0392] Furthermore, the semiconductor device according to some embodiments of the present disclosure includes a plurality of gates, so that the integration degree can be improved and the interference between adjacent gates can be minimized.

[0393] The embodiments of the present disclosure may provide various advantageous effects that can be recognized directly or indirectly.

[0394] Those skilled in the art will appreciate that the embodiments of the present disclosure may be implemented in other specific ways than those described herein. In addition, claims not explicitly proposed in the appended claims may be proposed as embodiments in a combined form, or may be proposed as new claims through subsequent amendments after filing an application.

[0395] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be designed based on what is described and / or shown in this disclosure. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; an active region including a horizontal portion and a vertical portion, the horizontal portion contacting the bit line, the vertical portion contacting the horizontal portion and extending in a third direction, the third direction being perpendicular to each of the first direction and the second direction; and a second gate which overlaps at least a portion of the horizontal portion and extends along the second direction, in, The vertical portion of the active region is disposed between the first gate and the second gate.

2. The semiconductor device according to claim 1, wherein: The first gate does not overlap the horizontal portion.

3. The semiconductor device according to claim 1, further comprising: A contact pad contacts the vertical portion of the active region and is spaced apart from the horizontal portion in the third direction.

4. The semiconductor device according to claim 3, wherein: The contact pad connects a capacitive element and the vertical portion of the active region to each other.

5. The semiconductor device according to claim 3, wherein: The contact pad has a width greater than the vertical portion of the active region.

6. The semiconductor device according to claim 4, wherein: The capacitive element is a capacitor.

7. The semiconductor device according to claim 4, wherein: The contact pad includes a plurality of layers, and in, A layer of the plurality of layers that is in contact with the vertical portion includes an oxide semiconductor material.

8. The semiconductor device according to claim 7, wherein: The contact pad includes a plurality of layers, and in, A layer in contact with the capacitive element among the plurality of layers includes metal or metal nitride.

9. The semiconductor device according to claim 1, wherein: The active region includes an oxide semiconductor material.

10. The semiconductor device according to claim 9, wherein: The oxide semiconductor material includes indium gallium zinc oxide (IGZO).

11. The semiconductor device according to claim 1, wherein: The control signal received by the first gate is different from the control signal received by the second gate.

12. The semiconductor device according to claim 11, wherein: A first gate is disposed between the active region and another active region adjacent to the active region.

13. The semiconductor device according to claim 1, wherein: The control signal received by the first gate is the same as the control signal received by the second gate.

14. The semiconductor device according to claim 13, wherein: A pair of the first gates is disposed between the active region and another active region adjacent to the active region.

15. The semiconductor device according to claim 1, wherein The second gate comprises: At least one contact portion connected to the conductor.

16. The semiconductor device according to claim 15, wherein: The contact portions are arranged in a zigzag pattern with respect to the first direction and are spaced apart from each other by a predetermined distance.

17. A semiconductor device comprising: A bit line extending along a first direction; a first gate extending along a second direction perpendicular to the first direction; a second grid extending along the second direction and facing the first grid or being opposite to the first grid; and an active region including a vertical portion and a horizontal portion, the vertical portion being disposed between the first gate and the second gate and extending along a third direction perpendicular to each of the first direction and the second direction, and the horizontal portion contacting the bit line and extending along the first direction, in, The first gate is disposed between the vertical portions respectively included in different active regions adjacent to each other.

18. The semiconductor device according to claim 17, wherein: The first gate does not overlap the horizontal portion; and The second gate overlaps the horizontal portion.

19. The semiconductor device according to claim 18, further comprising: A contact pad contacts the vertical portion of the active region and is spaced apart from the horizontal portion in the third direction.

20. The semiconductor device according to claim 19, wherein: The contact pad connects the capacitive element and the vertical portion of the active region to each other.

21. The semiconductor device according to claim 20, wherein: The contact pad comprises a plurality of layers, in, A layer of the plurality of layers in contact with the vertical portion includes an oxide semiconductor material; and Among the plurality of layers, the layer in contact with the capacitor element comprises metal or metal nitride.

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