Through-silicon-via-assisted perovskite single crystal array and method for interconnecting with CMOS (Complementary Metal-Oxide-Semiconductor Transistor) chip

Abstract

The invention discloses a through-silicon-via-assisted perovskite single crystal array and a CMOS chip interconnection method, the perovskite single crystal array comprises a silicon substrate, an isolation layer, a perovskite single crystal, a common electrode and a pixelated metal electrode, the silicon substrate is provided with arrayed through holes, the perovskite single crystal is located in the through holes, and the through holes are formed in the bottom of the through holes. The common electrode is deposited on the surfaces of the silicon substrate and the perovskite single crystal, and the pixelated metal electrode is deposited on the surfaces of the sides, far away from the common electrode, of the silicon substrate and the perovskite single crystal; in the application process, the perovskite single crystal array and the CMOS chip are interconnected through the flip-chip bonding technology. According to the invention, the high-precision processing capability of the through-silicon via is combined with the excellent performance of the perovskite material, so that the compatibility with the CMOS technology is ensured, and pixelation of the high-quality perovskite single crystal array and high-density integrated interconnection with the CMOS read-out chip at the bottom layer are realized; therefore, an innovative technical path is provided for manufacturing of low-cost and high-performance X-ray imaging devices.

Description

Technical Field

[0001] The present invention relates to the technical field of X-ray imaging chips, and in particular to a through silicon via-assisted perovskite single crystal array and a method for interconnecting the array with a CMOS chip. Background Art

[0002] X-ray detection and imaging technology has important applications in medical imaging, industrial non-destructive testing, safety inspection and scientific research. As information-based production and life put forward higher requirements for detection accuracy, imaging resolution and radiation dose, halide perovskite materials have attracted widespread attention due to their excellent optoelectronic properties. Halide perovskite materials have excellent properties such as high absorption coefficient, long carrier diffusion length, low defect density and can be prepared by low-temperature solution method. It is expected to reduce the required radiation dose while improving detection performance, realizing a new generation of intelligent X-ray detection imaging.

[0003] CMOS (complementary metal oxide semiconductor) chips are one of the core components of modern electronic devices, not only used for image sensors, but also for processing and transmitting data. The integration of perovskite single crystals with CMOS chips aims to combine the advantages of both and build high-performance X-ray detectors. However, the integrated interconnection of perovskite single crystals and CMOS chips still faces many challenges, which hinders the further development of perovskite single crystal X-ray detectors.

[0004] In an X-ray detector, each pixel needs to work independently, so effective isolation measures are needed to prevent signal crosstalk. For perovskite materials, it is difficult to perform fine patterning using conventional methods because traditional photolithography processes involve chemical materials such as photoresists and developers. Planarization is very important to ensure optical and electrical consistency, but when processing perovskites, keeping the surface flat without destroying the integrity of the material itself is a difficult problem. Therefore, due to the material properties of perovskites themselves (poor thermal and chemical stability), they have poor compatibility with CMOS processes such as photolithography and chemical mechanical polishing, making it difficult to achieve precise pixel isolation and planarization.

[0005] At the same time, some integrated interconnect schemes involve multiple complex processing steps, such as multi-layer stacking, welding, etc. These additional steps not only increase manufacturing costs, but also increase the risk of failure, especially when temperature-sensitive perovskite materials are involved. The integration of perovskite single crystals with CMOS chips may lead to a decrease in the reliability of the overall system. Any slight change or defect may cause the entire device to fail, especially when used for a long time or in harsh environments. Therefore, some current integrated interconnect methods require high-temperature processing or complex subsequent processing steps, which can easily destroy the performance of perovskite materials or cause CMOS chips to fail. Summary of the invention

[0006] The present invention proposes a through silicon via assisted perovskite single crystal array and a method for interconnecting the array with a CMOS chip to solve the problem of poor compatibility between the inherent properties of the perovskite single crystal and CMOS processes such as photolithography and chemical mechanical polishing during the integration and interconnection of the perovskite single crystal and the CMOS chip. The present invention combines the high-precision processing capability of through silicon vias with the excellent performance of perovskite materials to ensure compatibility with CMOS processes, achieve pixelation of high-quality perovskite single crystal arrays and high-density integrated interconnection with the underlying CMOS readout chip, thereby providing an innovative technical path for the manufacture of low-cost, high-performance X-ray imaging devices.

[0007] To achieve the above-mentioned objectives, the present invention provides a silicon through-hole-assisted perovskite single crystal array, comprising a silicon substrate, an isolation layer, a perovskite single crystal, a common electrode and a pixelated metal electrode, wherein the silicon substrate has an arrayed through-hole, the perovskite single crystal is located inside the through-hole, the common electrode is deposited on the surface of the silicon substrate and the perovskite single crystal, and the pixelated metal electrode is deposited on the surface of the silicon substrate and the perovskite single crystal away from the common electrode.

[0008] The present invention also provides a method for preparing a through silicon via-assisted perovskite single crystal array, comprising the following steps: S1. Silicon substrate selection: Select a silicon wafer with controllable thickness as the silicon substrate; S2, photolithography patterning: coating the surface of the silicon wafer with photoresist, and defining the graphic structure of the through hole on the silicon substrate through photolithography technology; S3, deep silicon etching: etching the silicon wafer by deep reactive ion etching technology to form arrayed through holes; S4, insulation isolation: depositing an isolation layer material on the through hole and the surface of the silicon wafer to achieve electrical insulation isolation; S5. Perovskite single crystal growth: growing perovskite single crystal material in the through hole of the silicon substrate; S6, depositing a common electrode: depositing a layer of conductive electrode on the surface of the silicon substrate and the perovskite single crystal filled with the through-hole as a common electrode; S7, perovskite patterning: etching the perovskite single crystal on the side away from the common electrode by wet etching or plasma etching process until the height of the perovskite single crystal is lower than the height of the silicon substrate surface; S8, metal electrode deposition: on the surface of the silicon substrate and the perovskite single crystal on one side etched in step S7, a metal electrode is deposited by evaporation or sputtering technology as a pixelated metal electrode; S9. Leveling the metal electrode: The surface of the pixelated metal electrode is leveled by chemical mechanical polishing technology to reduce the thickness of the surface metal until the isolation layer deposited on the surface of the silicon wafer is exposed, thereby obtaining a silicon through-via-assisted perovskite single crystal array.

[0009] Further, in step S1 , a silicon wafer with a thickness of 50 μm to 500 μm is selected.

[0010] Further, in step S3 , the ratio of the length (depth) of the through hole to the width of the through hole is greater than 2:1.

[0011] Further, in step S4, an isolation layer material is deposited by atomic layer deposition technology.

[0012] Further, in step S5, the perovskite single crystal material is a halide perovskite selected from MAPbBr3, CsPbBr3 or FA x MA 1-x One of PbI3, perovskite single crystals are prepared by solution-assisted method, chemical vapor deposition method or Bridgman method Further, in step S6, the conductive electrode is ITO or FTO.

[0013] Further, in step S8, the metal electrode is gold or copper.

[0014] The present invention also provides an X-ray imaging chip, which is manufactured by integrating a perovskite single crystal array assisted by a through silicon via with an underlying CMOS chip, wherein the spacing and diameter of the through silicon vias correspond to the size of the surface pads of the underlying CMOS chip.

[0015] Furthermore, the chip preparation method is: interconnecting the perovskite single crystal array and the CMOS chip through flip-chip welding technology.

[0016] The present invention adopts the above-mentioned through silicon via assisted perovskite single crystal array and the method for interconnecting with a CMOS chip, which has the following beneficial effects: 1. The present invention realizes the preparation of high-quality halide perovskite single crystal arrays. Specifically, the present invention provides a template for the directional growth of perovskite single crystals through silicon via (TSV) technology, and uses deep silicon etching technology to form a through-hole structure with a high aspect ratio, thereby realizing high-quality directional growth of perovskite single crystal materials.

[0017] 2. The present invention uses precise photolithography patterning and etching technology to pixelate the perovskite single crystal array to form a high-resolution, independent pixel structure. The present invention significantly improves the pixel density by optimizing the through-hole diameter and spacing, which can meet the needs of high-resolution X-ray imaging applications.

[0018] 3. The present invention achieves the compatibility of perovskite single crystal materials and CMOS chips through reasonable process design, avoiding high-temperature steps in traditional processes that may damage the performance of perovskite materials and CMOS chips.

[0019] 4. The present invention utilizes flip-chip welding technology to achieve large-scale high-density interconnection between the perovskite single crystal array and the CMOS chip, ensuring efficient coupling between the readout circuit and the detection pixel.

[0020] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the preparation process of the perovskite single crystal array and the X-ray imaging chip of the present invention.

[0022] Figure 2 is a SEM image of the perovskite single crystal array prepared in Example 1; Figure 3 This is a structural diagram of the perovskite single crystal array of Example 1. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is further described below through the accompanying drawings and embodiments.

[0024] Unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] The present invention will be further described below. It should be noted that this embodiment is based on the technical solution and provides a detailed implementation method and a specific operation process, but the present invention is not limited to this embodiment.

[0026] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0027] Example 1 This embodiment provides a through silicon via assisted perovskite single crystal array, such as Figure 3As shown, the perovskite single crystal array includes a silicon substrate, an isolation layer, a perovskite single crystal, a common electrode and a pixelated metal electrode. The silicon substrate has an arrayed through-hole, the perovskite single crystal is located inside the through-hole, the common electrode is deposited on the surface of the silicon substrate and the perovskite single crystal, and the pixelated metal electrode is deposited on the surface of the silicon substrate and the perovskite single crystal away from the common electrode.

[0028] Example 2

[0029] This embodiment provides a method for preparing a perovskite single crystal array assisted by through silicon vias, which is used to prepare the perovskite single crystal array of Example 1.

[0030] like Figure 1 FIG. 1 is a schematic diagram of the preparation process of a perovskite single crystal array. The preparation method comprises the following steps: S1. Silicon substrate selection: Select a 300 μm thick silicon wafer as the silicon substrate; S2, photolithography patterning: coating photoresist on the surface of the silicon wafer, and defining the graphic structure of the through-holes on the silicon substrate by photolithography technology. In this embodiment, the square hole array has a side length of 50 μm, a pitch of 20 μm, and an array size of 288*288, achieving a high-density array layout; S3, deep silicon etching: The silicon wafer is deeply etched by deep reactive ion etching (DRIE) technology to form arrayed through holes that penetrate the silicon wafer. The aspect ratio of the through holes is 6:1. The formed through holes provide a structural basis for subsequent processes. In the deep silicon etching process using deep reactive ion etching technology, SF6 is used as the etching gas, and the etching rate is 2.5um / min; S4, insulation isolation: Deposit isolation layer materials on the through-holes and the surface of the silicon wafer, and use atomic layer deposition technology to deposit 100nm thick Al2O3 as an isolation layer to achieve electrical insulation isolation; In the process of depositing the isolation layer by atomic layer deposition technology, trimethylaluminum TMA and water vapor H2O are used as reaction gases, and the process temperature is 250 ℃; S5, perovskite single crystal growth: prepare the CsPbBr3 precursor solution in advance, introduce the precursor solution into the through-hole, and grow the CsPbBr3 perovskite single crystal material in the through-hole of the silicon substrate array by solution epitaxy; The specific process of the solution epitaxy method is as follows: prepare the CsPbBr3 precursor solution in advance, immerse the pre-prepared large-size perovskite single crystal seed crystal close to the back of the through hole into the precursor solution, heat the solution to 120°C for two hours, and then slowly cool it to room temperature at a temperature gradient of 1°C / h. After taking it out, rinse it with anhydrous ethanol and dry it. S6. Depositing a common electrode: depositing a transparent conductive oxide ITO with a thickness of 200 nm on the surface of the silicon substrate and the perovskite single crystal filled with the through-hole by magnetron sputtering to form a common electrode; During the magnetron sputtering deposition process, the magnetron sputtering power was 30 W and the time was 1200 s; S7, Perovskite patterning: The perovskite single crystal on the side away from the common electrode is etched by a wet etching process; specifically, 100 μL of DMSO solution is spin-coated to wet dissolve the surface perovskite crystal to achieve the purpose of etching, and the height of the perovskite single crystal is lower than the height of the silicon substrate surface. After the etching is completed, anneal at 120 °C to remove the remaining solvent and promote surface recrystallization; S8, metal electrode deposition: on the surface of the silicon substrate and the perovskite single crystal etched on one side in step S7, 1 um of Au metal is deposited by evaporation technology to completely cover the surface of the silicon substrate and the perovskite single crystal, as a pixelated metal electrode; the deposition rate during the evaporation process is 5 Å / s; S9. Leveling the metal electrode: Perform chemical mechanical polishing (CMP) to flatten the surface of the metal electrode to reduce the thickness of the surface metal until the isolation layer deposited on the surface of the silicon wafer is exposed to obtain a silicon through-via-assisted perovskite single crystal array.

[0031] from Figure 1 It can be seen that the through-silicon-via-assisted perovskite single crystal array has been successfully synthesized.

[0032] Example 3 This embodiment provides a method for preparing a perovskite single crystal array assisted by through silicon vias, which is used to prepare the perovskite single crystal array of Example 1.

[0033] like Figure 1 FIG. 1 is a schematic diagram of the preparation process of a perovskite single crystal array. The preparation method comprises the following steps: S1. Silicon substrate selection: Select a 300 μm thick silicon wafer as the silicon substrate; S2, photolithography patterning: coating photoresist on the surface of the silicon wafer, and defining the graphic structure of the through-holes on the silicon substrate by photolithography technology. In this embodiment, the square hole array has a side length of 50 μm, a pitch of 20 μm, and an array size of 288*288, achieving a high-density array layout; S3, deep silicon etching: The silicon wafer is deeply etched by deep reactive ion etching (DRIE) technology to form arrayed through holes that penetrate the silicon wafer. The aspect ratio of the through holes is 6:1. The formed through holes provide a structural basis for subsequent processes. In the deep silicon etching process using deep reactive ion etching technology, SF6 is used as the etching gas, and the etching rate is 2.5um / min; S4, insulation isolation: Deposit isolation layer materials on the through-holes and the surface of the silicon wafer, and use atomic layer deposition technology to deposit 100nm thick Al2O3 as an isolation layer to achieve electrical insulation isolation; In the process of depositing the isolation layer by atomic layer deposition technology, trimethylaluminum TMA and water vapor H2O are used as reaction gases, and the process temperature is 250 ℃; S5. Perovskite single crystal growth: configure FA in advance x MA 1-x PbI3 precursor solution is introduced into the through-holes, and FA is grown in the through-holes of the silicon substrate array by solution epitaxy. x MA 1-x PbI3 perovskite single crystal material; The specific process of solution epitaxy is: configure FA in advance x MA 1-x PbI3 precursor solution, immerse the pre-prepared large-size perovskite single crystal seed crystal close to the back of the through hole into the precursor solution, heat the solution to 120 °C for two hours, then slowly cool it to room temperature at a temperature gradient of 1 °C / h, take it out and rinse it with anhydrous ethanol and dry it; S6. Depositing a common electrode: depositing a transparent conductive oxide FTO with a thickness of 200 nm on the surface of the silicon substrate and the perovskite single crystal filled with the through-hole by magnetron sputtering to form a common electrode; During the magnetron sputtering deposition process, the magnetron sputtering power was 30 W and the time was 1200 s; S7, perovskite patterning: The perovskite single crystal on the side away from the common electrode is etched by a plasma etching process; specifically, Ar gas is introduced to generate a high-energy ion beam to bombard the perovskite surface to achieve the purpose of etching, and the etching power is set to 50 W for 5 min; S8, metal electrode deposition: on the surface of the silicon substrate and the perovskite single crystal etched on one side in step S7, 1 um of Cu metal is deposited by sputtering technology to completely cover the surface of the silicon substrate and the perovskite single crystal, as a pixelated metal electrode; the deposition rate during the evaporation process is 5 Å / s; S9. Leveling the metal electrode: Perform chemical mechanical polishing (CMP) to flatten the surface of the metal electrode to reduce the thickness of the surface metal until the isolation layer deposited on the surface of the silicon wafer is exposed to obtain a silicon through-via-assisted perovskite single crystal array.

[0034] Application Example 1 This application example uses the silicon-through-via-assisted perovskite single crystal array prepared in Example 2 to integrate with the underlying CMOS chip to prepare an X-ray imaging chip, wherein the spacing and diameter of the silicon-through-vias correspond to the size of the surface pads of the underlying CMOS chip.

[0035] like Figure 1 As shown, the specific preparation method is to use the micro-bump welding technology of flip-chip soldering, deposit 5 μm indium pillars on the surface pads of the CMOS chip in advance as solder joints, and perform high-density flip-chip interconnection between the perovskite single crystal array prepared in Example 2 and the CMOS chip to ensure that each pixel unit is accurately connected to the readout circuit of the CMOS chip. The specific welding process is: after aligning the chip pad with the single crystal array electrode, hot pressing welding is performed, the welding temperature is 160 ° C, and the pressure is 20 MPa.

[0036] An X-ray imaging chip prepared was tested under 50 kVp X-rays and showed good X-ray response characteristics and high-resolution imaging features.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solution of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solution to deviate from the spirit and scope of the technical solution of the present invention.

Claims

1. A through silicon via assisted perovskite single crystal array, characterized in that: It includes a silicon substrate, an isolation layer, a perovskite single crystal, a common electrode and a pixelated metal electrode. The silicon substrate has an array of through holes, the perovskite single crystal is located inside the through holes, the common electrode is deposited on the surface of the silicon substrate and the perovskite single crystal, and the pixelated metal electrode is deposited on the surface of the silicon substrate and the perovskite single crystal away from the common electrode.

2. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: The steps include: S1. Silicon substrate selection: Select a silicon wafer with controllable thickness as the silicon substrate; S2, photolithography patterning: coating the surface of the silicon wafer with photoresist, and defining the graphic structure of the through hole on the silicon substrate through photolithography technology; S3, deep silicon etching: etching the silicon wafer by deep reactive ion etching technology to form arrayed through holes; S4, insulation isolation: depositing an isolation layer material on the through hole and the surface of the silicon wafer to achieve electrical insulation isolation; S5. Perovskite single crystal growth: growing perovskite single crystal material in the through hole of the silicon substrate; S6, depositing a common electrode: depositing a layer of conductive electrode on the surface of the silicon substrate and the perovskite single crystal filled with the through-hole as a common electrode; S7, perovskite patterning: etching the perovskite single crystal on the side away from the common electrode by wet etching or plasma etching process until the height of the perovskite single crystal is lower than the height of the silicon substrate surface; S8, metal electrode deposition: on the surface of the silicon substrate and the perovskite single crystal on one side etched in step S7, a metal electrode is deposited by evaporation or sputtering technology as a pixelated metal electrode; S9. Leveling the metal electrode: The surface of the pixelated metal electrode is leveled by chemical mechanical polishing technology to reduce the thickness of the surface metal until the isolation layer deposited on the surface of the silicon wafer is exposed, thereby obtaining a silicon through-via-assisted perovskite single crystal array.

3. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S1 , a silicon wafer with a thickness of 50 μm to 500 μm is selected.

4. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S3 , the ratio of the length of the through hole to the width of the through hole is greater than 2:

1.

5. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S4, an isolation layer material is deposited by atomic layer deposition technology.

6. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S5, the perovskite single crystal material is a halide perovskite selected from MAPbBr3, CsPbBr3 or FA x MA 1-x One of PbI3, perovskite single crystals are prepared by solution-assisted method, chemical vapor deposition method or Bridgman method.

7. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S6 , the conductive electrode is ITO or FTO.

8. The method for preparing a TSV-assisted perovskite single crystal array according to claim 1, characterized in that: In step S8 , the metal electrode is gold or copper.

9. An X-ray imaging chip, characterized in that: A silicon through-hole via (TSV)-assisted perovskite single crystal array as described in claim 1 is integrated with an underlying CMOS chip for manufacturing, wherein the spacing and diameter of the TSVs correspond to the size of the surface pads of the underlying CMOS chip.

10. The X-ray imaging chip according to claim 9, characterized in that: The chip is prepared by interconnecting a perovskite single crystal array with a CMOS chip through flip-chip welding technology.

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