Quantum well infrared photoelectric detector with back barrier and manufacturing method thereof

Abstract

The invention belongs to the technical field of infrared photoelectric detectors, and particularly relates to a quantum well infrared photoelectric detector with a back barrier and a manufacturing method of the quantum well infrared photoelectric detector. The quantum well infrared photoelectric detector with the back barrier comprises a GaAs substrate, an active layer, a dielectric layer, a first metal electrode and a second metal electrode, and the active layer comprises an emitter conducting layer, a back barrier layer, a functional layer, a collector conducting layer and an infrared detection layer. The manufacturing method provided by the invention comprises the following steps: sequentially performing epitaxial growth on a semi-insulating GaAs substrate to form an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer; removing a part of material in a first specified area on the wafer; depositing a dielectric layer on the surface of the wafer; removing the dielectric layer in the second specified area; and depositing a metal electrode in the second specified area from which the dielectric layer is removed, and performing heat treatment. According to the invention, the specific detection rate of the infrared photoelectric detector can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared photoelectric detectors, and in particular is a quantum well infrared photoelectric detector with a back barrier and a manufacturing method thereof. Background Art

[0002] Gallium arsenide (GaAs), as a III-V semiconductor material, has become an ideal material for infrared photodetectors due to its high electron mobility, adjustable band gap, and mature material and device processing technology. GaAs-based quantum well infrared photodiode (QWIP) uses electron well transitions in the quantum well structure to detect long-wavelength light signals. This structure can effectively expand the spectral response range of photodetectors and improve their performance. QWIP improves the specific detection rate of infrared detectors by utilizing electron well transitions in quantum wells, so it has been widely used in the field of infrared detection. The detection light band of GaAs QWIP covers two atmospheric low-loss transmission windows of 3-5 and 8-12 μm, and because of its high sensitivity and mature material and device processing technology, it has been widely studied and applied in remote control, remote sensing, optical coupling and other fields. With the growing demand for infrared information detection and intelligent perception in fields such as artificial intelligence, big data, and smart cities, higher requirements are placed on the performance of infrared photodetectors, including reduction in size, weight, power consumption, and price, as well as improvement in performance.

[0003] Due to the influence of dark current, the specific detection rate of commercial QWIP is generally less than 10 when tested at low temperature in liquid nitrogen environment (79K). 8 cm·Hz 1 / 2 / W, the detection rate of QWIP is not ideal enough, which affects the detection effect of the device. Summary of the invention

[0004] In view of this, the present invention provides a quantum well infrared photodetector with a back barrier and a manufacturing method thereof to solve the technical problem in the prior art that the QWIP device is affected by dark current and causes the specific detection rate to drop.

[0005] The technical solution adopted by the present invention is:

[0006] In a first aspect, the present invention provides a quantum well infrared photodetector with a back barrier, the quantum well infrared photodetector comprising a GaAs substrate, an active layer, a dielectric layer, a first metal electrode and a second metal electrode, the active layer comprising an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer, the emitter conductive layer, the back barrier layer, the functional layer, the collector conductive layer and the infrared detection layer are sequentially stacked on the GaAs substrate, at least a portion of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer, the dielectric layer covers the surface of the active layer, the first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer.

[0007] In a second aspect, the present invention provides a method for manufacturing a quantum well infrared photodetector with a back barrier, which is used to manufacture the quantum well infrared photodetector with a back barrier described in the first aspect, and the method comprises:

[0008] S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer on a semi-insulating GaAs substrate in sequence;

[0009] S2: removing part of the material in a first designated area on the wafer to expose the emitter conductive layer in the area, wherein the first designated area is an area in the infrared detection layer that needs to be electrically connected to the metal electrode;

[0010] S3: depositing a dielectric layer on the entire wafer surface;

[0011] S4: removing the dielectric layer located in the second designated area, wherein the second designated area is an area in the emitter conductive layer that needs to be electrically connected to the metal electrode;

[0012] S5: Depositing a metal electrode in the second designated area where the dielectric layer is removed and performing heat treatment Beneficial effect: The quantum well infrared photodetector with a back barrier and the method for manufacturing the same of the present invention are formed by sequentially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer on a GaAs substrate. The quantum well infrared photodetector can generate a back barrier on one side electrode of the quantum well infrared photodetector, and utilize the limiting effect of the back barrier on carriers to effectively reduce the dark current generated by carrier drift, thereby significantly improving the specific detection rate of the quantum well infrared photodetector. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings required for use in the embodiment of the present invention will be briefly introduced below. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work, and these are all within the protection scope of the present invention.

[0014] Figure 1 It is a schematic diagram of the structure of a quantum well infrared photodetector with a back barrier of the present invention;

[0015] Figure 2 It is a schematic flow chart of a method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0016] Figure 3 It is a schematic diagram of the first step in the method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0017] Figure 4 It is a schematic diagram of the second step in the method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0018] Figure 5 It is a schematic diagram of the third step in the method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0019] Figure 6 It is a schematic diagram of the fourth step in the method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0020] Figure 7 It is a schematic diagram of the fifth step in the method for manufacturing a quantum well infrared photodetector with a back barrier of the present invention;

[0021] Figure 8 It is a curve diagram of dark current test of the present invention and the prior art;

[0022] Fig. 9 It is a curve diagram of the responsiveness test of the present invention and the prior art;

[0023] Fig.10 It is a curve diagram of the detection rate test between the present invention and the prior art.

[0024] Figure number and description:

[0025] GaAs substrate 100, emitter conductive layer 200, n-doped GaAs layer 301, first non-doped GaAs layer 302, p + doped GaAs layer 303, second non-doped GaAs layer 304, functional layer GaAs layer 401, In x Ga 1-xAs layer 402, the third non-doped GaAs layer 501, the second n + Doped GaAs layer 502 , infrared detection layer 503 , dielectric layer 600 , and metal electrode 700 . DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described in combination with the embodiment of the present invention. It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. In the description of the present invention, it should be understood that the orientation or position relationship indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, the elements defined by the phrase "comprising..." do not exclude the existence of other identical elements in the process, method, article or device comprising the elements. If there is no conflict, the embodiments of the present invention and the various features in the embodiments can be combined with each other, all within the protection scope of the present invention.

[0027] Example 1

[0028] like Figure 1 As shown, this embodiment provides a quantum well infrared photodetector with a back barrier, including a GaAs substrate 100, an active layer, a dielectric layer 600 and two metal electrodes 700, namely a first metal electrode and a second metal electrode.

[0029] The active layer includes an emitter conductive layer 200, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer, and the emitter conductive layer, the back barrier layer, the functional layer, the collector conductive layer and the infrared detection layer 03 are sequentially stacked on the GaAs substrate. That is, the emitter conductive layer 200 is located above the GaAs substrate 100, the back barrier layer is located above the emitter conductive layer, the functional layer is located above the back barrier layer, the collector conductive layer is located above the functional layer, and the infrared detection layer is located above the functional layer.

[0030] The semi-insulating GaAs has an extremely high resistivity, which enables it to effectively isolate the current and prevent parasitic current and leakage current in the device. This ensures that the photocurrent in the quantum well structure is not disturbed by the substrate material, thereby improving the signal quality and response sensitivity of the detector.

[0031] The emitter conductive layer is mainly responsible for providing an electron source for the device, ensuring that the electron injection in the quantum well can be carried out efficiently. A good ohmic contact is formed between the emitter conductive layer and the external electrode, thereby optimizing the current transmission efficiency of the device.

[0032] The back barrier layer reduces the dark current by forming a barrier structure. The dark current in the QWIP is caused by thermally excited carriers. In the absence of a light signal, the dark current will reduce the signal-to-noise ratio of the detector and affect its detection performance. The back barrier layer used in this embodiment can effectively prevent thermally excited electrons from entering the quantum well, thereby reducing the dark current.

[0033] The quantum well structure formed in the functional layer captures infrared photons and excites electrons to jump from the quantum well to the conduction band, generating photoelectric signals. The collector conductive layer is used to collect the photogenerated electrons generated in the functional layer and transmit them to the external circuit.

[0034] The infrared detection layer is specially used to absorb infrared light. This layer captures incident infrared photons, excites electrons to enter the quantum well, and generates photocurrent signals through the action of other layers.

[0035] At least a portion of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer, that is, a portion of the emitter conductive layer is not covered by other layers in the active layer.

[0036] The dielectric layer covers the surface of the active layer, the first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer. The two metal electrodes electrically connect the quantum well infrared photodetector to an external circuit.

[0037] In this embodiment, a back barrier layer is used to generate a back barrier on one side electrode of the QWIP device to effectively reduce the dark current generated by carrier drift, thereby further improving the specific detection rate of the QWIP device.

[0038] In this embodiment, the thickness of the GaAs substrate is 50 μm to 1000 μm, and the bulk resistivity of the GaAs substrate is greater than 10 7 Ω·cm; the GaAs substrate adopting the aforementioned thickness can not only provide sufficient mechanical support for the device, but also effectively suppress leakage current and parasitic current, and prevent the current conduction in the device from being disturbed by the substrate.

[0039] In this embodiment, the emitter conductive layer is a single layer or multiple layers of n + Doped GaAs layer, where n + The doping concentration is greater than 10 18 cm -3 , the thickness of the emitter conductive layer is 1nm to 1000nm; for the convenience of distinction, the n + The doped GaAs layer is also referred to as the first n-doped GaAs layer in this embodiment. + Doped GaAs layer.

[0040] n + The GaAs layer is doped with n + Doping can introduce a large number of electrons as the main carriers. 18 cm -3 ) can make the layer have a sufficiently high carrier concentration, thereby significantly reducing the resistivity of the layer. Low resistivity helps to reduce the series resistance of the emitter layer, ensuring that electrons can be quickly and efficiently injected into the quantum well, enhancing the response speed and efficiency of the device.

[0041] Under high temperature or high current conditions, the electrons in the QWIP device may be thermally excited and affect the performance. + The doping layer can improve the injection efficiency of electrons. At the same time, combined with the aforementioned thickness setting, it can reduce the interference of hot electrons on the quantum well, reduce the dark current of the device, and improve the stability of the detector.

[0042] The back barrier layer at least includes an n-doped GaAs layer 301, a first non-doped GaAs layer 302, and a p-doped GaAs layer 303, which are stacked in sequence in a direction facing away from the emitter conductive layer. + The doped GaAs layer 303 and the second non-doped GaAs layer 304, wherein the thickness of the n-doped GaAs layer is 1nm to 1000nm, and the doping concentration of n is 10 16 ~10 18 cm -3 , p + The thickness of the doped GaAs layer is 1nm~100nm, p + The doping concentration is greater than 10 17 cm -3 , the thickness of the first non-doped GaAs layer is 1 nm to 100 nm, and the thickness of the second non-doped GaAs layer is 1 nm to 100 nm;

[0043] The back barrier layer in this embodiment has at least two non-doped layers, which are respectively referred to as a first non-doped GaAs layer 302 and a second non-doped GaAs layer 303 for the sake of distinction.

[0044] The back barrier layer adopts the above structure to optimize the transmission of electrons and the formation of potential barriers. The thickness and doping concentration of these four layers of materials ensure the formation of potential barriers and the control of current, so that the back barrier layer can provide good electron transmission characteristics while suppressing dark current. The back barrier formed by the above structure can effectively control the flow of electrons and reduce dark current.

[0045] In this embodiment, the functional layer is a plurality of cycles of In x Ga 1-x The multi-quantum well structure is composed of As and GaAs, and the number of cycles is 3 to 15 times, and the In x Ga 1-x The thickness of the As layer 402 is the same as the In composition and is 1 nm to 10 nm, the range of x is 0.1 to 0.7, the thickness of the GaAs layer in each cycle is the same and is 1 nm to 100 nm; for ease of description, the GaAs layer in each cycle is also referred to as the functional layer GaAs layer 401 in this article.

[0046] One of the loops consists of a layer of In x Ga 1-x As and a GaAs layer. The quantum well structure is achieved by placing a narrow bandgap material (such as In x Ga 1-x As) and wide bandgap materials (such as GaAs) are grown alternately. When photons excite electrons in the quantum well, the electrons jump from the quantum well to the conduction band, generating photoelectric signals. The multiple cycles of the terminal quantum well structure of this embodiment increase the light absorption area and improve the response of the photodetector to infrared light in a specific band. This embodiment can also control the intensity of the quantum confinement effect by the thickness of the quantum well. This embodiment uses In x Ga 1-x The In component in As controls the bandgap width of the material, and thus controls the device's response to infrared light of different wavelengths. When x changes in the range of 0.1 to 0.7, the bandgap of the material will adjust the peak wavelength of the quantum well's absorption of infrared light, thereby covering different infrared detection needs. For example, a higher In component (x close to 0.7) corresponds to longer wavelength infrared detection, while a lower In component (x close to 0.1) is suitable for shorter wavelength detection.

[0047] The functional layer in the QWIP of this embodiment is designed to be multiple cycles of In x Ga 1-x As and GaAs quantum well structures, combined with a multilayer design of the collector conductive layer, can provide flexible wavelength adjustment capabilities while optimizing the performance of the photodetector. The aforementioned structure can be used to control the thickness of the quantum well and barrier, In x Ga 1-xThe As component, combined with the aforementioned structure of the multi-layer collector conductive layer, can achieve efficient infrared light absorption, low dark current, high sensitivity and good electron collection efficiency.

[0048] In this embodiment, the collector conductive layer at least includes a third non-doped GaAs layer 501, a second n-doped GaAs layer 502, and a second n-doped GaAs layer 503. + doped GaAs layer 502; the infrared detection layer 503 includes n + In doping x Ga 1-x As layer, wherein the thickness of the third non-doped GaAs layer is 1nm to 1000nm, n + The thickness of the doped GaAs layer is 1nm~1000nm, n + Doping concentration greater than 10 18 cm -3 , n + In doping x Ga 1-x The thickness of the As layer is 1nm~100nm, n + Doping concentration greater than 10 18 cm -3 , the range of x is 0.1~0.9.

[0049] The undoped GaAs layer (third undoped GaAs layer) in the collector conductive layer can serve as a buffer layer, which can effectively isolate the functional layer (quantum well structure) from the n + The doping layer prevents the doping layer from having too much influence on the behavior of electrons in the quantum well. In addition, the undoped GaAs layer can also prevent electrons from directly tunneling into the collector conductive layer, ensuring the effective transition of electrons in the quantum well and increasing the photoelectric conversion efficiency.

[0050] The aforementioned thickness of the non-doped GaAs layer can effectively control the degree of electron isolation and tunneling effect, maintain sensitivity, and reduce dark current. + The doped GaAs layer has a high carrier concentration, which ensures that electrons can be effectively collected from the quantum well, reduces the resistance in current transmission, maintains a high conductivity, thereby improving the response speed of the device, reducing the series resistance, and enhancing the current output capacity of the detector.

[0051] n + In doping x Ga 1-x As layer has a narrow band gap, which is similar to the quantum well material (In x Ga 1-xAs) can more effectively collect electrons and improve the overall response efficiency of the device. By adjusting the In component x (0.1 to 0.9), the electron collection ability of the device can be further optimized to ensure that the electrons in the quantum well can be efficiently transmitted to the external circuit. x Ga 1-x The As layer not only improves the conductivity but also reduces the energy loss of electrons by reducing the band gap difference, thus enhancing the overall performance of the device.

[0052] Example 2

[0053] like Figure 2 As shown, this embodiment provides a method for manufacturing a quantum well infrared photodetector with a back barrier. The method is used to manufacture the quantum well infrared photodetector with a back barrier described in Embodiment 1. The method comprises:

[0054] S1: epitaxially grow an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer on a semi-insulating GaAs substrate in sequence; after this step, the structure is as follows Figure 3 shown.

[0055] As an example, the back barrier layer at least includes an n-doped GaAs layer, a first non-doped GaAs layer, a p+-doped GaAs layer, and a second non-doped GaAs layer stacked in sequence in a direction facing away from the emitter conductive layer;

[0056] As another example, the back barrier layer includes an n-doped GaAs layer, a transition layer, a p-doped GaAs layer, and a transition layer. + a doped GaAs layer and a second non-doped GaAs layer;

[0057] The transition layer is doped with n and p +

[0058] The doping concentration of n in the transition layer decreases gradually from the direction toward the back emitter conductive layer. + The doping increases step by step from the direction of the back emitter conductive layer. The n-doping concentration in the first transition layer gradually decreases from the preset concentration of the n-doping source to 0, and the p+ doping concentration in the second transition layer gradually increases from 0 to the preset concentration of the p+ doping source;

[0059] The above structure of this embodiment can avoid direct contact between the n-type layer and the p-type layer in the back barrier, so as to prevent the introduction of higher barrier mismatch and carrier scattering at the interface. This embodiment can form a smooth energy band transition region by introducing doping gradient between the n-layer and the p-layer, which is conducive to reducing the backscattering of electrons in the transition region, thereby improving the current transmission characteristics and quantum efficiency of the device.

[0060] As an example, p + The starting position of doping is at a position where the doping concentration of n is as low as 0, and the doping concentration of n in the transition layer is gradually reduced from the direction of the back emitter conductive layer, and the p+ doping is gradually increased from the direction of the back emitter conductive layer. This structure can gradually reduce the n-type concentration, and then slowly introduce p-type doping, so that the energy band structure presents a smooth potential change in this area.

[0061] During the epitaxial growth process, a real-time adjustable doping source supply system is used for dynamic regulation. This can be divided into several growth sub-stages: S142: According to the parameters of the back barrier layer, the evaporated As source, Ga source, and p source are controlled in a vacuum environment. + The doping source and the n-doping source move toward the emitter conductive layer and are deposited on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer:

[0062] S1421: determining an initial flow rate of the n-doping source according to a preset concentration of the n-doping source in the n-doped GaAs layer;

[0063] The flow rate of the n-doping source is proportional to the concentration of the n-doping source. The preset concentration of the n-doping source in the n-doped GaAs layer is the ideal concentration of the n-doping source in the GaAs layer that meets the requirements, and the concentration is set by the designer.

[0064] S1422: determining a flow rate variation rule of the n-doping source according to a preset concentration variation rule of the n-doping source of the first transition layer and an initial flow rate of the n-doping source, wherein the preset concentration variation rule of the n-doping source is gradually reduced from the initial concentration to 0;

[0065] Since the flow rate of the n-doping source is proportional to the concentration of the n-doping source, the flow rate of the n-doping source corresponding to each doping concentration during the deposition process can be obtained through the preset concentration variation law of the n-doping source, thereby forming the flow variation law of the n-doping source.

[0066] S1423: controlling the flow rate of the n-doping source during the deposition of the first transition layer according to the initial flow rate of the n-doping source and the flow rate variation rule of the n-doping source;

[0067] S1424: According to p + The p-doped GaAs layer + The preset doping concentration of the doping source determines p + The final flow rate of the doping source;

[0068] The flow rate of the p+ doping source is proportional to the concentration of the p+ doping source. The preset concentration of the p+ doping source in the p+ doped GaAs layer is the ideal concentration of the n-doping source in the GaAs layer that meets the requirements, and the concentration is set by the designer.

[0069] S1425: According to the transition layer p + The change rule of the preset concentration of the doping source and p + The final flow rate of the doping source determines p + The flow rate variation rule of the doping source, wherein the preset concentration variation rule of the p+ doping source is gradually increased from 0 to the final flow rate;

[0070] S1426: According to p + The final flow rate of the doping source and p + The flow rate variation law of the doping source controls the p + The flow rate of the doping source.

[0071] This embodiment fine-tunes the flow rate of the doping source multiple times so that the p-type doping reaches the expected high doping level at the end of the transition zone. After the gradual doping transition zone growth is completed in the above manner, the back barrier layer will have a smoother energy band transition zone. This region reduces the carrier backscattering and interface recombination caused by doping mutations, improves the carrier transport efficiency of the device, and thus provides better electron injection and blocking conditions for the quantum well structure of the subsequent functional layer, indirectly improving the photoelectric conversion efficiency and detection sensitivity.

[0072] Said S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer in sequence on a semi-insulating GaAs substrate comprises:

[0073] S11: cleaning the semi-insulating GaAs substrate to remove organic matter, particles and a surface oxide layer on the surface of the semi-insulating GaAs substrate;

[0074] S12: polishing the cleaned GaAs substrate;

[0075] This step can also be carried out by high temperature (about 700℃) 2 Gas treatment of the wafer surface improves surface flatness and provides a high-quality foundation for subsequent growth.

[0076] S131: Ga source and n + The doping source is loaded into a source furnace of a molecular beam epitaxy device;

[0077] In specific implementation, silicon (Si) can be used as a doping source to control high carrier concentration.

[0078] S132: Ga source and n +The doping source is heated to evaporate and deposit onto the surface of the GaAs substrate to form an emitter conductive layer;

[0079] S141: For As source, Ga source, p + The doping source and the n-doping source material are heated to evaporate;

[0080] S142: Control the evaporated As source, Ga source, and p in a vacuum environment according to the parameters of the back barrier layer. + The doping source and the n-doping source move toward the emitter conductive layer and are deposited on the emitter conductive layer to form a back barrier layer, wherein the parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer, wherein the thickness is positively correlated with the deposition time, and the doping concentration is positively correlated with the flow rate of each material source.

[0081] During the growth of the back barrier layer, the uniformity of the layer can be ensured by adjusting the growth rate and temperature.

[0082] S151: heating the As source, Ga source and In source materials to evaporate them to form As source, Ga source and In source gas flows;

[0083] S152: controlling the As source, the Ga source and the In source to flow toward the back barrier layer and depositing on the back barrier layer to form a functional layer according to the parameters of the functional layer, wherein the parameters of the functional layer include the thickness of each layer in the functional layer;

[0084] During the growth of the functional layer, the growth conditions can be precisely controlled to ensure the uniformity and defect-freeness of the entire multi-quantum well structure and maximize the photoelectric conversion efficiency. The thickness is positively correlated with the deposition time, and the doping concentration is positively correlated with the flow rate of each material source.

[0085] S161: For As source, Ga source, In source and n + The doping source material is heated to evaporate it;

[0086] S162: Control the As source, Ga source, In source and n according to the collector layer parameters + The doping source gas flow flows toward the functional layer and is deposited on the functional layer to form a collector conductive layer, wherein the parameters of the collector conductive layer include the thickness and doping concentration of each layer of the collector conductive layer;

[0087] After the collector layer is grown, the crystal quality is checked, using testing techniques such as X-ray diffraction (XRD) and scanning electron microscopy (SEM) to ensure the quality of the layer and the absence of defects at the interface.

[0088] S171: For As source, Ga source, In source and n + The doping source material is heated to evaporate to form As source, Ga source, In source and n + dopant source gas flow;

[0089] S172: Control the As source, Ga source, In source and n according to the infrared detection layer parameters + The doping source gas flow flows toward the back barrier layer and deposits an infrared detection layer on the back barrier layer, and the infrared detection layer parameters include the thickness and doping concentration of each layer of the infrared detection layer, wherein the thickness is positively correlated with the deposition time, and the doping concentration is positively correlated with the flow rate of each material source.

[0090] S2: removing part of the material in the first designated area on the wafer to expose the emitter conductive layer in the area;

[0091] In the specific implementation, the material above the emitter conductive layer in the first designated area, i.e., the back barrier layer, the functional layer, the collector conductive layer and the infrared detection layer, can be removed, so that the upper surface of the emitter conductive layer in the first designated area will not be blocked by other layers and can be exposed to the outside, so as to facilitate the implementation of subsequent manufacturing processes. The structure after this step is completed is as follows Figure 4 shown.

[0092] S3: Deposit a dielectric layer on the entire wafer surface to form electrical insulation, ensure isolation between different electrodes and conductive layers, and avoid short circuits or parasitic currents. In addition, this embodiment can also use the dielectric layer to protect the underlying structure from subsequent process contamination to ensure long-term stable performance of the device. The structure after this step is completed is as follows Figure 5 shown.

[0093] S4: removing the dielectric layer located in the second designated area on the surface of the dielectric layer;

[0094] The second designated area is the area in the emitter conductive layer that needs to be electrically connected to the metal electrode. In this step, the dielectric layer in this area is first removed to leave space for the subsequent metal electrode deposition. The structure after this step is completed is as follows Figure 6 shown.

[0095] S5: depositing a metal electrode on the second designated area where the dielectric layer is removed and performing a heat treatment. The structure after this step is completed is as follows Figure 7 shown.

[0096] This embodiment performs epitaxial growth on a semi-insulating GaAs substrate, and each layer of material grows according to the designed thickness and doping concentration, including an emitter conductive layer (providing electron injection), a back barrier layer (suppressing dark current), a functional layer (quantum well structure for infrared light absorption), a collector conductive layer (electron collection) and an infrared detection layer (absorbing infrared light). By precisely controlling the thickness and doping concentration of each layer, the electrical performance and matching between the layer structures are ensured, providing a basis for realizing devices with high detection performance. The aforementioned method can improve the photoelectric conversion efficiency and signal-to-noise ratio of the device, especially the design of the back barrier layer can effectively suppress dark current. In this embodiment, heat treatment after the metal electrode is deposited can improve the contact performance between the metal electrode and the emitter conductive layer, reduce the contact resistance, and form a stable ohmic contact.

[0097] The deposition of the dielectric layer not only provides electrical insulation, but also protects the quantum well structure, back barrier layer and conductive layer, ensuring that the device is not disturbed by the external environment during long-term operation.

[0098] The first designated area is a continuous area or a combination of multiple discontinuous areas, which is not limited here.

[0099] The second designated area is a continuous area or a combination of multiple discontinuous areas, which is not limited here.

[0100] The method for removing part of the material in the first designated area on the wafer is plasma dry etching and / or wet etching.

[0101] In specific implementation, plasma dry etching may be used alone, wet etching may be used alone, or a combination of plasma dry etching and wet etching may be used.

[0102] The use of plasma etching to remove the dielectric layer is to use high-energy ions to impact the surface of the dielectric layer to remove material atoms layer by layer, which can achieve submicron to nanometer etching accuracy, and can perform precision processing on complex structures in precision QWIP devices, thereby effectively ensuring the quality of QWIP devices. In addition, the use of plasma etching has strong directionality and can achieve vertical etching without lateral expansion. For the material removal processing of the stacked structure in this embodiment, the first designated area can be accurately etched without affecting the surrounding area, thereby reducing damage to the surrounding materials and ensuring the structural integrity of the detector. The use of plasma etching in this embodiment can also quickly remove dielectric layers of oxide materials such as silicon oxide and silicon nitride.

[0103] The wet etching method used in this embodiment can utilize chemical solution to react with the material to dissolve and remove the material. The above method can be used to quickly etch and increase the processing rate, thereby significantly shortening the processing time.

[0104] In addition, the present embodiment may also adopt a combination of plasma dry etching and wet etching. For example, a larger amount of material may be removed by wet etching first, and then a specific area may be finely processed by dry etching. This can effectively reduce the processing time of dry etching, reduce costs, and ensure etching accuracy.

[0105] The method for removing the dielectric layer in the second designated area is plasma dry etching and / or wet etching. In specific implementation, plasma dry etching can be used alone, wet etching can be used alone, or a combination of plasma dry etching and wet etching can be used.

[0106] The dielectric layer material includes an oxide film, the thickness of the oxide film is 1nm to 1000nm, and the oxide film is formed by vapor deposition. This embodiment can form a uniform and dense thin film deposition by vapor deposition. The dielectric layer generated by vapor deposition has a smooth surface and a uniform internal structure, thereby reducing the introduction of defects. The high-quality thin film provided by vapor deposition can effectively isolate the layers, avoid leakage or short circuit problems, and ensure the long-term and stable operation of the detector.

[0107] In this embodiment, the metal electrode includes a metal layer formed of Ni and / or Ge and / or Au, each metal layer has a thickness of 1 nm to 1000 nm, and the metal electrode is deposited by sputtering and / or evaporation. The metal electrode can be deposited by sputtering, or by evaporation, or by a combination of sputtering and evaporation.

[0108] The temperature of the heat treatment is 350°C to 550°C, the heat treatment time is 1 to 3600s, and the heat treatment method is rapid annealing. This embodiment realizes high temperature treatment in a very short time and cools rapidly after the heat treatment is completed. The characteristics of rapid heating and cooling are used to reduce the heat diffusion effect, reduce the impact on other layers of the device (such as quantum well layer, back barrier layer), and avoid material diffusion or crystal structure damage caused by long-term heating. Rapid annealing effectively avoids excessive high temperature exposure, reduces material migration and interface diffusion, maintains the structural integrity of each layer, and improves the stability of the device. The high temperature of rapid annealing used in this embodiment can promote atomic diffusion between the metal electrode and the emitter conductive layer, thereby enhancing the bonding force between the electrode and the semiconductor, reducing the contact resistance, and forming a good ohmic contact. In the process of depositing the metal electrode, certain mechanical stresses will be generated between the materials, and rapid annealing can release these stresses under a short period of high temperature treatment, thereby eliminating the stress between the film and the substrate. Stress elimination can effectively avoid film cracking, warping, etc. caused by temperature changes in subsequent use, ensure the mechanical stability and long-term reliability of the electrode, and thus extend the service life of the QWIP device. Rapid annealing can improve the crystal quality of metal films, make the atomic arrangement in metal films more uniform, and reduce grain boundaries and defects. This lattice rearrangement can improve the conductivity of metal electrodes and make current flow through the electrodes more smoothly. High-quality metal crystal structures can reduce the resistance of electrodes, reduce signal transmission losses, and improve the electrical performance and response speed of detectors. The high temperature of rapid annealing helps to remove impurities or residual gases in the material, while repairing defects that may occur during the metal deposition process and optimizing the overall quality of the electrode layer. Figure 8 , Fig. 9 and Fig.10 It can be seen from the comparative experiments that the QWIP device of this embodiment has obvious advantages over the prior art in suppressing dark current, improving device responsiveness and improving device specific detection rate.

[0109] In this embodiment, the step S2: removing part of the material in the first designated area on the wafer to expose the emitter conductive layer in the area includes:

[0110] S21: placing the cleaned wafer in a plasma etching device;

[0111] Clean the wafer surface to remove dust, oil and organic pollutants. Use a photolithography process to form an etching mask layer (such as a photoresist or silicon oxide layer) on the wafer surface. The mask material covers the non-designated area and exposes the first designated area. The mask pattern is formed by photolithography exposure and development processes. The resolution of the mask edge should meet the process requirements. Ensure that the shape, size and position of the first designated area are consistent with the design. The designated area can be a continuous area or a combination of multiple discontinuous areas. Place the cleaned wafer in a plasma etching device (such as RIE or ICP equipment).

[0112] S22: adjusting the type and flow rate of etching gas;

[0113] For example, using chlorine gas Cl 2 , argon Ar, etc.) to ensure that the gas can effectively react and etch the target material.

[0114] Gas flow rate: controlled within the range of 10-100 sccm. Chamber pressure: maintained within the range of 10-200 mTorr.

[0115] S23: Start the plasma source to generate high-energy ions;

[0116] S24: using high-energy ions to perform physical bombardment and chemical reaction on a first designated area, where the first designated area is a continuous area or a combination of multiple discontinuous areas.

[0117] During the etching process, the etching depth and progress are judged by an optical monitoring system (such as End-point detection), ensuring that the integrity of the target area is maintained during the etching process while avoiding over-etching that damages the underlying emitter conductive layer.

[0118] In this embodiment, the step S4: removing the dielectric layer located in the second designated area includes:

[0119] S41: preparing a wet etching solution;

[0120] In this step, a suitable wet etching solution is selected according to the target material.

[0121] S42: adjusting the temperature and concentration of the wet etching solution according to the etching rate;

[0122] S43: placing the wafer in a wet etching tank so that the second designated area is in full contact with the etching solution, wherein the second designated area is a continuous area or a combination of multiple discontinuous areas;

[0123] S44: monitoring the etching progress in real time until the dielectric layer in the second designated area is completely removed;

[0124] S45: Use deionized water to clean the etched area. After cleaning, blow dry or low-temperature dry the wafer to ensure that there is no liquid residue on the surface. Ensure that the surface is clean after etching.

[0125] 7. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that said S5: said depositing a metal electrode in the second designated area where the dielectric layer is removed and performing a heat treatment comprises;

[0126] S51: cleaning the wafer to be deposited;

[0127] Use standard wet cleaning processes (e.g., acetone, isopropyl alcohol, deionized water) to remove surface dust, organic contaminants, and particles. Use a dilute HF solution to remove surface oxides and residues to achieve high cleanliness. Use nitrogen (N 2 ) Blow dry or low temperature drying to ensure that there is no residual liquid on the wafer surface

[0128] S52: placing the clean and dry wafer on a sample stage of a deposition device;

[0129] S53: Start the vacuum pump to evacuate the reaction chamber to a preset vacuum level;

[0130] S54: introducing precursor gas and oxidizing gas at set flow rates;

[0131] S55: Start the radio frequency power supply to generate plasma and excite the gas to undergo a chemical reaction;

[0132] S56: Generate an oxide film with a thickness of 1 nm to 1000 nm on the surface of the wafer through a plasma enhanced chemical reaction.

[0133] After the deposition is completed, the precursor gas and plasma are stopped, and the RF power is turned off. Nitrogen (N 2 ) for cleaning, discharge the reaction product chamber back to atmospheric pressure, and take out the wafer after deposition

[0134] In this embodiment, the step S3: depositing a dielectric layer on the entire wafer surface includes:

[0135] S31: Clean the surface of the wafer to remove any oxide layer that may exist;

[0136] Before depositing the electrode, the wafer surface is cleaned to remove dust, organic matter or residual oxide layer on the surface. Use dilute hydrofluoric acid (HF) solution to remove the possible oxide layer and ensure good contact between the metal layer and the emitter conductive layer.

[0137] S32: After rinsing the wafer with deionized water, use high-purity nitrogen to blow dry;

[0138] S33: fixing the cleaned wafer on a sample stage of the evaporation chamber;

[0139] S34: evacuate to the target vacuum degree;

[0140] Use high vacuum evaporation equipment, configure the evaporation source, and load metal targets of Ni, Ge and Au respectively.

[0141] S35: Start the evaporation source heating device and heat it to the evaporation temperature of nickel. The evaporated nickel atoms diffuse in the vacuum chamber and deposit on the surface of the wafer to form the first thin film. Control the coating time to achieve the target thickness of 5nm, and measure it in real time through the film thickness monitor.

[0142] S36: Replace the evaporation source with germanium, heat it to its evaporation temperature, and evaporated germanium atoms cover the nickel layer to form a second thin film; evaporated germanium atoms cover the nickel layer to form a second thin film with a thickness controlled to be 15nm.

[0143] S37: Replace the evaporation source with nickel, heat it to its evaporation temperature, evaporate the nickel atoms to cover the germanium layer, and form a third thin film. Control the coating time to deposit a 50nm thick nickel layer.

[0144] S38: The evaporation source is replaced with gold, and heated to its evaporation temperature. The evaporated gold atoms cover the gold layer to form a fourth thin film.

[0145] The step S5: depositing a metal electrode on the second designated area where the dielectric layer is removed and performing a heat treatment comprises:

[0146] S501: Rapidly heat the sample to be processed to 420°C;

[0147] Use a rapid annealing device (RTA) with a heating temperature of 420°C and an annealing time of 60 seconds. High-purity nitrogen (N 2 ) or inert gas (such as argon Ar) to prevent the metal layer from being oxygenated at high temperatures.

[0148] S502: Maintain the temperature at 420°C for 60 seconds; during this process, Ge and Ni react to form nickel-germanium alloy (NiGe), further reducing the contact resistance between the electrode and the conductive layer

[0149] S503: After annealing is completed, stop heating and allow the sample to cool to room temperature.

[0150] After annealing is completed, heating is stopped immediately and the sample is cooled to room temperature quickly. Rapid cooling can avoid excessive diffusion or wafer stress accumulation caused by high temperature.

[0151] Said S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer in sequence on a semi-insulating GaAs substrate comprises:

[0152] S11: Obtain the spectrum range of the infrared light detected by the detector;

[0153] Depending on different detection requirements, the spectral range of infrared light detected by the detector may be different.

[0155] This embodiment uses an optimized design strategy to produce an infrared detector that can meet the set detection spectrum range.

[0156] The spectral range of infrared light includes but is not limited to medium-wave infrared, long-wave infrared or a specific narrow band). In this embodiment, the spectral range of the detector can be met by the design parameters of the multi-quantum well structure. These parameters at least include the material selection, thickness and component ratio of the quantum well and barrier layer.

[0157] S12: Perform theoretical simulation using semiconductor physics simulation software according to the spectral range of the infrared light to x Ga- x The parameter ranges of As and GaAs layer thickness, In composition (x) and number of cycles are limited once to obtain the parameter space of the functional layer;

[0158] In x Ga 1-x The thickness of As affects the quantum confinement effect. Too thin a thickness will lead to an enhanced tunneling effect and increase the dark current; too thick a thickness will reduce the quantum confinement effect and weaken the sensitivity to the target wavelength.

[0159] The GaAs layer is the barrier layer of the quantum well, and its thickness determines the probability of electron tunneling between quantum wells. Too thin a thickness will enhance electron tunneling and increase dark current; too thick a thickness may weaken the coupling between quantum wells and reduce light absorption efficiency.

[0160] The number of cycles (3 to 15 times) determines the length of the light absorption path of the quantum well. Too few cycles will reduce the number of interactions between photons and quantum wells, resulting in a decrease in light absorption efficiency; too many cycles will increase the thickness of the device and the complexity of processing.

[0161] The content of In component x determines the value of In x Ga 1-x The bandgap width of the As layer. The higher the x value, the smaller the bandgap width, and the quantum well is more sensitive to the long-wave infrared (LIR); the lower the x value, the larger the bandgap width, which is more suitable for the mid-wave infrared (MIR) or short-wave infrared (SWIR).

[0162] Specifically, it includes: using simulation software (such as Silvaco TCAD, Nextnano, COMSOL Multiphysics or other semiconductor physics simulation tools) to build a quantum well model.

[0163] Input the spectral range of infrared light into the model. The software simulates the energy band structure and electronic energy levels, compares the matching degree of transition energy with the infrared spectral range (photon energy = hc / λ), and selects the transition energy of the quantum well that can match the detected spectral range. Select the energy level distribution of electrons in the quantum well according to the transition energy. Then, the In is given according to the energy level distribution. x Ga- x Parameter ranges for As and GaAs layer thickness, In composition (x) and number of cycles. Generate parameter space using given parameter ranges.

[0164] S13: randomly generate a set of initial sampling points in the parameter space;

[0165] S14: Obtaining performance data corresponding to each initial sampling point;

[0166] This step can be performed by taking the initial sampling point as the design parameter to conduct preliminary experiments or simulation calculations to obtain the performance data of the detector obtained by taking the initial sampling point as the design parameter, such as the dark current size, responsiveness, noise, specific detection rate, electron collection efficiency and other performance data of the detector.

[0167] S15: sorting each of the initial sampling points according to the performance evaluation standard of the infrared detector and the performance corresponding to each of the initial sampling points;

[0168] In this step, each sampling point is sorted by performance using a performance evaluation standard, thereby obtaining the pros and cons of each sampling point.

[0169] S16: Sampling point distribution optimization process: Based on the performance data of the sampling points and the ranking results of the sampling points, the sampling distribution is adjusted by an adaptive algorithm to obtain the sampling points after distribution optimization; the adaptive algorithm can use a Gaussian mixture model. This step adjusts the sampling distribution by an adaptive algorithm to concentrate the sampling more in the area with better performance;

[0170] S17: Sampling point search optimization process: Based on the physical model or experimental experience, heuristic rules are used to guide the search direction to search for the sampling points after distribution optimization to obtain the search optimized sampling points;

[0171] This step uses heuristic rules to guide the search, which can focus on sampling within certain known effective parameter ranges and perform local fine-tuning to improve optimization efficiency.

[0172] S18: Determine whether the detector corresponding to the optimized sampling point meets the preset conditions. If yes, output the optimized sampling point. If not, repeat the sampling point distribution optimization process and the sampling point search optimization process in sequence until the detector corresponding to the optimized sampling point meets the preset conditions.

[0173] This step gradually improves the performance by repeatedly updating the sampling strategy and optimizing the search direction until the predetermined optimization goal or convergence condition is reached. When the performance improvement is less than a preset threshold (meets the preset condition), the optimization process is considered to have converged and the optimal parameter combination is output as the final solution. The above method can quickly find the optimal In in the early design stage. x Ga 1-x As thickness, x value, GaAs layer thickness and number of cycles to meet the requirements of the detection spectral range and detection effect.

[0174] The following is an introduction based on a specific example. In this example, the substrate material is a semi-insulating GaAs substrate with a thickness of 435 μm and a bulk resistivity of 3×10 8 Ω·cm. The preparation process includes the following steps:

[0175] (1) Epitaxial growth of 300 nm thick and 2×10 8 cm -3 n + -GaAs emitter conductive layer 200, thickness is 500nm, doping concentration is 5×10 17 cm -3 The back barrier layer n-GaAs layer 301 with a thickness of 50nm, the back barrier layer non-doped GaAs layer 302 with a thickness of 10nm and a doping concentration of 5×10 17 cm -3 The back barrier layer p + -GaAs layer 303, back barrier layer non-doped GaAs layer 304 with a thickness of 50nm, 10 cycles of In 0.3 Ga 0.7 As layer 401 and GaAs layer 402 with a thickness of 40nm, a multi-quantum well structure, a collector conductive layer non-doped GaAs layer 501 with a thickness of 100nm, and a GaAs layer with a thickness of 500nm and a doping concentration of 5×10 17 cm -3 The collector conductive layer n + -GaAs layer 502, thickness is 20nm and doping concentration is 2×10 8 cm -3 The collector conductive layer n + -In 0.2 Ga0.8 As layer;

[0176] (2) using plasma dry etching to make the unetched area a circle with a diameter of 300 μm, and the etched area to expose the emitter conductive layer 200, and the remaining thickness of the emitter conductive layer is greater than 400 nm;

[0177] (3) using chemical vapor deposition to deposit a silicon oxide dielectric film 600 with a thickness of 100 nm;

[0178] (4) In step (2), the unetched area and the etched area are respectively formed into a circle with a diameter of 50 μm, and the dielectric material 600 in the circular area is removed by plasma dry etching;

[0179] (5) Ni / Ge / Ni / Au electrodes with thicknesses of 5 / 15 / 50 / 300 nm were deposited in sequence by evaporation, and after deposition, rapid annealing was performed at 420°C for 60s.

[0180] In this embodiment, the step S2: removing part of the material in the first designated area on the wafer to expose the emitter conductive layer in the area includes:

[0181] S21: placing the cleaned wafer in a plasma etching device;

[0182] In this step, the wafer surface can be cleaned to remove dust, oil and organic pollutants. A photolithography process is used to form an etching mask layer on the wafer surface. The mask material covers the non-designated area and exposes the first designated area. The mask pattern can be formed by photolithography exposure and development process, and the resolution of the mask edge should meet the process requirements. Ensure that the shape, size and position of the first designated area are consistent with the design. The designated area can be a continuous area or a combination of multiple discontinuous areas.

[0183] S22: Adjust the type and flow rate of etching gas; ensure that the gas can effectively react and etch the target material. Chlorine gas can be used. 2 , argon Ar, etc.

[0184] S23: Start the plasma source to generate high-energy ions;

[0185] In this step, the following working parameters can be set before starting:

[0186] RF power: The energy used to control the plasma, usually ranging from 50W to 500W.

[0187] Gas flow rate: controlled within the range of 10 to 100 sccm.

[0188] Chamber pressure: maintained within the range of 10 to 200 mTorr.

[0189] Etching time: adjusted according to material thickness and etching rate, usually tens of seconds to several minutes.

[0190] S24: using high-energy ions to perform physical bombardment and chemical reaction on a first designated area, where the first designated area is a continuous area or a combination of multiple discontinuous areas.

[0191] In this step, the material in the first designated area is removed by physical bombardment and chemical reaction. After the etching is completed, the ion source is stopped, the chamber is cleaned, and the wafer is taken out.

[0192] The above is a detailed introduction to the method for manufacturing the quantum well infrared photodetector with back barrier provided by an embodiment of the present invention.

[0193] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figure. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiment, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention. The functional blocks shown in the structural block diagram described above can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, plug-in, function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or communication link via a data signal carried in a carrier. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, and the like. The code segments can be downloaded via a computer network such as the Internet, an intranet, etc. It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0194] The above is only a specific implementation of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the system, module and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.

Claims

1. A quantum well infrared photodetector with a back barrier, characterized in that: The invention comprises a GaAs substrate, an active layer, a dielectric layer, a first metal electrode and a second metal electrode, wherein the active layer comprises an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer, wherein the emitter conductive layer, the back barrier layer, the functional layer, the collector conductive layer and the infrared detection layer are sequentially stacked on the GaAs substrate, at least a part of the surface of the emitter conductive layer facing away from the GaAs substrate is exposed outside the back barrier layer, the dielectric layer covers the surface of the active layer, the first metal electrode is connected to the emitter conductive layer exposed outside the back barrier layer, and the second metal electrode is connected to the collector conductive layer.

2. The quantum well infrared photodetector with back barrier according to claim 1, characterized in that: The thickness of the GaAs substrate is 50 μm to 1000 μm, and the volume resistivity of the GaAs substrate is greater than 10 7 Ω·cm; The emitter conductive layer includes a single layer or multiple layers of a first n + Doped GaAs layer, where n + The doping concentration is greater than 10 18 cm -3 , the thickness of the emitter conductive layer is 1nm to 1000nm; The back barrier layer at least includes an n-doped GaAs layer, a first non-doped GaAs layer, a p-doped GaAs layer, and a + doped GaAs layer, a second non-doped GaAs layer; wherein the thickness of the n-doped GaAs layer is 1nm to 1000nm, and the doping concentration of n is 10 16 ~10 18 cm -3 ; p + The thickness of the doped GaAs layer is 1nm~100nm, p + The doping concentration is greater than 10 17 cm -3 ; The thickness of the first non-doped GaAs layer is 1 nm to 100 nm, and the thickness of the second non-doped GaAs layer is 1 nm to 100 nm; The collector conductive layer at least includes a third non-doped GaAs layer, a second n-doped GaAs layer, and a second n-doped GaAs layer. + doped GaAs layer; the infrared detection layer includes n + In doping x Ga 1-x As layer, wherein the thickness of the third non-doped GaAs layer is 1nm to 1000nm, n + The thickness of the doped GaAs layer is 1nm~1000nm, n + Doping concentration greater than 10 18 cm -3 , n + In doping x Ga 1-x The thickness of the As layer is 1nm~100nm, n + Doping concentration greater than 10 18 cm -3 , the range of x is 0.1~0.

9.

3. The quantum well infrared photodetector with back barrier according to claim 1, characterized in that: The functional layer is In x Ga 1-x As and GaAs composed of 3 to 15 cycles of the multi-quantum well structure, each cycle of In x Ga 1-x The thickness of the As layer and the In x Ga 1-x The In composition in the As layer is the same, and the In x Ga 1-x The thickness of the As layer is 1 nm to 10 nm, wherein the range of x is 0.1 to 0.7, the thickness of the GaAs layer in each cycle is the same and the thickness of the GaAs layer in each cycle is 1 nm to 100 nm.

4. A method for manufacturing a quantum well infrared photodetector having a back barrier, characterized in that: For manufacturing a quantum well infrared photodetector with a back barrier according to any one of claims 1 to 3, the method comprising: S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer on a semi-insulating GaAs substrate in sequence; S2: removing part of the material in a first designated area on the wafer to expose the emitter conductive layer in the area, wherein the first designated area is an area in the infrared detection layer that needs to be electrically connected to the metal electrode; S3: depositing a dielectric layer on the entire wafer surface; S4: removing the dielectric layer located in the second designated area, wherein the second designated area is an area in the emitter conductive layer that needs to be electrically connected to the metal electrode; S5: depositing a metal electrode on the second designated area where the dielectric layer is removed and performing a heat treatment.

5. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: Said S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer in sequence on a semi-insulating GaAs substrate comprises: S11: cleaning the semi-insulating GaAs substrate to remove organic matter, particles and a surface oxide layer on the surface of the semi-insulating GaAs substrate; S12: polishing the cleaned GaAs substrate; S131: Ga source and n + The doping source is loaded into a source furnace of a molecular beam epitaxy device; S132: Ga source and n + The doping source is heated to evaporate and deposit onto the surface of the GaAs substrate to form an emitter conductive layer; S141: For As source, Ga source, p + The doping source and the n-doping source material are heated to evaporate; S142: Control the evaporated As source, Ga source, and p in a vacuum environment according to the parameters of the back barrier layer. + The doping source and the n-doping source move toward the emitter conductive layer and are deposited on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer. S151: heating the As source, Ga source and In source materials to evaporate them to form As source, Ga source and In source gas flows; S152: controlling the As source, the Ga source and the In source to flow toward the back barrier layer and depositing on the back barrier layer to form a functional layer according to the parameters of the functional layer, wherein the parameters of the functional layer include the thickness of each layer in the functional layer; S161: For As source, Ga source, In source and n + The doping source material is heated to evaporate it; S162: Control the As source, Ga source, In source and n according to the collector layer parameters + The doping source gas flow flows toward the functional layer and is deposited on the functional layer to form a collector conductive layer, wherein the parameters of the collector conductive layer include the thickness and doping concentration of each layer of the collector conductive layer; S171: For As source, Ga source, In source and n + The doping source material is heated to evaporate to form As source, Ga source, In source and n + dopant source gas flow; S172: Control the As source, Ga source, In source and n according to the infrared detection layer parameters + The doping source gas flow flows toward the collector conductive layer and deposits an infrared detection layer on the collector conductive layer. The infrared detection layer parameters include the thickness and doping concentration of each layer of the infrared detection layer.

6. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: The back barrier layer includes an n-doped GaAs layer, a first transition layer, a second transition layer, a p-doped GaAs layer, and a second transition layer. + a doped GaAs layer and a second non-doped GaAs layer; The n-doping concentration in the first transition layer is gradually reduced from the preset concentration of the n-doping source to 0, and the p-doping concentration in the second transition layer is gradually reduced from the preset concentration of the n-doping source to 0. + The doping concentration increases gradually from 0 to p + a preset concentration of the doping source; S142: Controlling the evaporated As source, Ga source, and p source in a vacuum environment according to the parameters of the back barrier layer + The doping source and the n-doping source move toward the emitter conductive layer and are deposited on the emitter conductive layer to form a back barrier layer. The parameters of the back barrier layer include the thickness and doping concentration of each layer in the back barrier layer: S1421: determining an initial flow rate of the n-doping source according to a preset concentration of the n-doping source in the n-doped GaAs layer; S1422: determining a flow rate variation rule of the n-doping source according to a preset concentration variation rule of the n-doping source of the first transition layer and an initial flow rate of the n-doping source, wherein the preset concentration variation rule of the n-doping source is gradually reduced from the initial concentration to 0; S1423: controlling the flow rate of the n-doping source during the deposition of the first transition layer according to the initial flow rate of the n-doping source and the flow rate variation rule of the n-doping source; S1424: According to p + The p-doped GaAs layer + The preset doping concentration of the doping source determines p + The final flow rate of the doping source; S1425: According to the transition layer p + The change rule of the preset concentration of the doping source and p + The final flow rate of the doping source determines p + The flow rate variation law of the doping source, the p + The preset concentration variation rule of the doping source is to gradually increase from 0 to the final flow rate; S1426: According to p + The final flow rate of the doping source and p + The flow rate variation law of the doping source controls the p + The flow rate of the doping source.

7. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: S2: removing part of the material in the first designated area on the wafer to expose the emitter conductive layer in the area, wherein the first designated area is an area in the infrared detection layer that needs to be electrically connected to the metal electrode and includes: S21: placing the cleaned wafer in a plasma etching device; S22: adjusting the type and flow rate of etching gas; S23: Start the plasma source to generate high-energy ions; S24: using high-energy ions to physically bombard a first designated area and cause it to produce a chemical reaction, wherein the first designated area is a continuous area or a combination of multiple discontinuous areas.

8. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: S5: depositing a metal electrode on the second designated area where the dielectric layer is removed and performing heat treatment comprises: S51: cleaning the wafer to be deposited; S52: placing the clean and dry wafer on a sample stage of a deposition device; S53: Start the vacuum pump to evacuate the reaction chamber to a preset vacuum level; S54: introducing precursor gas and oxidizing gas at set flow rates; S55: Start the radio frequency power supply to generate plasma and excite the oxidizing gas to perform a chemical reaction; S56: Generate an oxide film with a thickness of 1 nm to 1000 nm on the surface of the wafer through a plasma enhanced chemical reaction.

9. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: The step S3: depositing a dielectric layer on the entire wafer surface comprises: S31: cleaning the surface of the wafer to remove the oxide layer; S32: After rinsing the wafer with deionized water, use high-purity nitrogen to blow dry; S33: fixing the dried wafer on a sample stage of the evaporation chamber; S34: evacuate to the target vacuum degree; S35: starting the evaporation source heating device to heat to the evaporation temperature of nickel, and the evaporated nickel atoms diffuse in the vacuum chamber and deposit on the wafer surface to form a first thin film; S36: replacing the evaporation source with germanium, heating it to its evaporation temperature, and the evaporated germanium atoms cover the nickel layer to form a second thin film; S37: replacing the evaporation source with nickel, heating it to its evaporation temperature, and evaporating the nickel atoms to cover the germanium layer to form a third thin film; S38: The evaporation source is replaced with gold, and heated to its evaporation temperature. The evaporated gold atoms cover the nickel layer to form a fourth thin film.

10. The method for manufacturing a quantum well infrared photodetector with a back barrier according to claim 4, characterized in that: Said S1: epitaxially growing an emitter conductive layer, a back barrier layer, a functional layer, a collector conductive layer and an infrared detection layer in sequence on a semi-insulating GaAs substrate comprises: S11: Obtain the spectrum range of the infrared light detected by the detector; S12: performing theoretical simulation using semiconductor physics simulation software according to the spectral range of the infrared light, limiting the parameter ranges of the InxGa-xAs layer thickness and the GaAs layer thickness, the In component (x) and the number of cycles, and obtaining a parameter space of the functional layer; S13: randomly generate a set of initial sampling points in the parameter space; S14: Obtaining performance data corresponding to each initial sampling point; S15: sorting each of the initial sampling points according to the performance evaluation standard of the infrared detector and the performance data corresponding to each of the initial sampling points; S16: Sampling point distribution optimization process: based on the performance data of the sampling points and the sorting results of the sampling points, the sampling distribution is adjusted by an adaptive algorithm to obtain the sampling points with optimized distribution; S17: Sampling point search optimization process: Based on the physical model or experimental experience, heuristic rules are used to guide the search direction to search for the sampling points after distribution optimization to obtain the search optimized sampling points; S18: Determine whether the detector corresponding to the optimized sampling point meets the preset conditions. If yes, output the optimized sampling point. If not, repeat the sampling point distribution optimization process and the sampling point search optimization process in sequence until the detector corresponding to the optimized sampling point meets the preset conditions.

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