Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel has a display area and a non-display area, and comprises a substrate, an isolation structure arranged on one side of the substrate and located in the display area and the non-display area, the isolation structure is surrounded to form a plurality of isolation openings and has at least one recess, the plurality of isolation openings are located in the display area, the at least one recess is located in the non-display area, and the at least one recess is recessed from the side of the isolation structure away from the substrate to the substrate. A plurality of light emitting devices are arranged in the isolation openings. The recess can relieve the stress in the isolation film group, thereby solving the problem that the adjacent film layers in the non-display area are prone to abnormality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are organic thin-film electroluminescent devices. They have attracted great attention and are widely used in electronic display products due to their advantages such as low power consumption, high brightness, wide viewing angle, high contrast, and the ability to realize flexible displays.

[0003] However, there are still anomalies between the film layers in current display panels. Summary of the Invention

[0004] The purpose of this invention is to provide a display panel and display device to solve the abnormal phenomena of the film layer in current display panels.

[0005] To achieve the above objectives, the present invention provides a display panel having a display area and a non-display area connected to the display area. The display panel includes a substrate, an isolation structure, and a plurality of light-emitting devices. The isolation structure is disposed on one side of the substrate and has at least one recess, a plurality of isolation openings are located in the display area, and the at least one recess is located in the non-display area. The at least one recess is recessed into the substrate from a side of the isolation structure opposite to the substrate. At least a portion of the light-emitting devices is located within the isolation openings.

[0006] Further, the substrate includes a driving layer and a pixel defining layer. The driving layer is disposed on one side of the substrate, located in the display area and the non-display area, and includes at least one power signal line located in the non-display area. The pixel defining layer is disposed on the side of the driving layer opposite to the substrate, located in the display area and the non-display area. The pixel defining layer encloses a plurality of pixel openings and has at least one first via. The plurality of pixel openings are located in the display area and communicate with corresponding isolation openings. The at least one first via is located in the non-display area. A portion of the surface of the at least one power signal line opposite to the substrate is exposed through the at least one first via. A portion of the isolation structure extends into the at least one first via and is electrically connected to the at least one power signal line. Preferably, the driving layer further includes a planarization layer disposed between the at least one power signal line and the pixel defining layer. The planarization layer has at least one second via, and the orthographic projection of the at least one first via on the substrate is located within the orthographic projection of the at least one second via on the substrate. Preferably, the at least one first via includes a plurality of first vias, and the at least one second via includes a plurality of second vias, wherein the plurality of first vias and the plurality of second vias are configured in a one-to-one correspondence. Preferably, the material of the planarization layer includes an organic material. Preferably, the isolation structure is located on the side of the pixel defining layer opposite to the substrate. Preferably, the pixel defining layer covers the side of the planarization layer facing the at least one first via.

[0007] Furthermore, the orthographic projection of the at least one recessed portion on the substrate is located outside the orthographic projection range of the at least one first via on the substrate. Preferably, the at least one first via includes a plurality of first vias, and the at least one recessed portion includes one or more recessed portions, the recessed portion being disposed between two adjacent first vias.

[0008] Furthermore, the orthographic projection of the recessed portion on the substrate lies within the orthographic projection of the pixel defining layer on the substrate. Preferably, the orthographic projection of the recessed portion on the substrate lies within the orthographic projection of the planarization layer on the substrate.

[0009] Furthermore, the recess does not penetrate the isolation structure. Preferably, the isolation structure has a first surface facing the pixel defining layer, and the bottom wall of the recess is located on the side of the first surface facing away from the substrate.

[0010] Further, the recessed portion penetrates the isolation structure. Preferably, a portion of the surface of the pixel defining layer facing away from the substrate is exposed through the recessed portion. Preferably, the pixel defining layer has a plurality of third vias, each of which communicates with a corresponding recessed portion. Preferably, the plurality of third vias and the plurality of recessed portions are provided in a one-to-one correspondence. Preferably, a portion of the surface of the planarization layer facing away from the substrate is exposed through the third via. Preferably, in a cross-section perpendicular to the substrate, the width of the third via is smaller than the width of the recessed portion.

[0011] Further, the orthographic projection of the at least one recessed portion on the substrate lies within the orthographic projection range of the at least one first via on the substrate. Preferably, the at least one first via comprises a plurality of first vias, and the at least one recessed portion comprises a plurality of recessed portions, wherein the width of the recessed portion is smaller than the width of the first via in a cross-section perpendicular to the substrate. Preferably, the orthographic projection of the recessed portion on the substrate lies within the orthographic projection range of the corresponding first via on the substrate.

[0012] Further, the plurality of recesses include adjacent first and second recesses, and the portion of the pixel defining layer projected onto the substrate is located between the projected projections of the first and second recesses onto the substrate. Preferably, the plurality of recesses and the plurality of first vias are provided in a one-to-one correspondence. Preferably, the recess penetrates the isolation structure. Preferably, a portion of the surface of the at least one power signal line facing away from the substrate is exposed from the recess. Preferably, the recess does not penetrate the isolation structure. Preferably, the isolation structure has a second surface facing the pixel defining layer, and the bottom wall of the recess is located on the side of the second surface facing away from the substrate.

[0013] Further, the orthographic projections of at least two of the recesses on the substrate are located within the orthographic projection range of the same first via on the substrate. Preferably, the recesses penetrate the isolation structure. Preferably, a portion of the surface of the at least one power signal line facing away from the substrate is exposed from the recess. Further, the at least one recess includes a plurality of recesses, and the spacing between two adjacent recesses is no greater than 200 nanometers.

[0014] Further, the isolation structure includes a support layer and a barrier layer. The support is disposed on one side of the substrate. The barrier layer is disposed on the side of the support layer opposite to the substrate, and the orthographic projection of the barrier layer on the substrate overlaps the orthographic projection of the support layer on the substrate. Preferably, the at least one recessed portion is recessed into the substrate from the side of the isolation structure opposite to the substrate to a first depth, and the barrier layer has a first film thickness in a cross section perpendicular to the substrate, the first depth being greater than the first film thickness. Preferably, the at least one recessed portion penetrates the barrier layer. Preferably, the at least one recessed portion is recessed into the substrate from the side of the support layer opposite to the substrate to a second depth, the support layer having a second film thickness, the second depth being less than or equal to the second film thickness. Preferably, the material of the support layer includes aluminum, and / or the material of the barrier layer includes titanium.

[0015] Furthermore, the isolation structure includes an isolation portion and an overlapping portion. The isolation portion is located in the display area and encloses to form the plurality of isolation openings. The overlapping portion is located in the non-display area, and the at least one recessed portion is disposed on the overlapping portion. Preferably, the isolation portion and the overlapping portion are an integral structure.

[0016] The present invention also provides a display device, which includes a display panel as described above.

[0017] The advantages of the present invention are: the display panel and display device of the present invention alleviate the stress in the isolation structure by setting a recess in the non-display area of ​​the display panel, thereby solving the problem that abnormalities are prone to occur between adjacent film layers in the non-display area and improving the reliability of the display panel. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the partitioning of the display panel in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the layered structure of the display panel in the display area of ​​an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the layered structure of the display panel in the non-display area in an embodiment of the present invention;

[0022] Figure 4This is a schematic diagram of the layered structure of the display panel in the non-display area in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the layered structure of the display panel in the non-display area in other embodiments of the present invention;

[0024] Figure 6 This is a schematic diagram of the layered structure of the display panel in the non-display area in another embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the layered structure of the display panel in the non-display area in another embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of the layered structure of the display panel in the non-display area in other embodiments of the present invention.

[0027] The components in the diagram are shown below:

[0028] Display panel 1; Display area AA;

[0029] Non-display area NA; Substrate 10;

[0030] Driving layer 11; Conductive layer 12;

[0031] Planarization layer 13; Power and data cables 14;

[0032] Pixel confinement layer 20; Pixel aperture 21

[0033] First via 23;

[0034] Isolation structure 30; Isolation section 30A;

[0035] Overlap 30B; Support layer 31;

[0036] Barrier layer 32; Isolation opening 33;

[0037] Page 1, page 34; Page 2, page 35;

[0038] Light-emitting device 40; First electrode 41;

[0039] Light-emitting layer 42; Second electrode 43;

[0040] Recess 50; First recess 50A;

[0041] Second recess 50B; First opening 51;

[0042] Second opening 52; First through hole 60;

[0043] Second via 70; Third via 80. Detailed Implementation

[0044] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0045] In related display technologies, to achieve high resolution and color in OLED (Organic Light-Emitting Diode) and to better address issues such as low resolution of OLED electrode films and low device yield, electrode isolation structures have been introduced. This involves fabricating an isolation structure on the driving layer before depositing the organic thin film and metal electrode layer, instead of using a metal mask during device fabrication. This isolation structure separates different pixels, creating a pixel array. However, the inventors discovered in actual production that film peeling frequently occurs in the non-display areas of the display panel.

[0046] Example 1

[0047] Based on the technical problems raised by the aforementioned related display technologies, this embodiment of the invention provides a display panel 1. For example... Figure 1 As shown, the display panel 1 has a display area AA and a non-display area NA connected to the display area AA. The display area AA is used to display the image and has multiple light-emitting devices 40. Each light-emitting device 40 can be lit by control. The outermost light-emitting device 40 is considered to be the boundary between the display area AA and the non-display area NA. When the multiple light-emitting devices 40 include both non-virtual light-emitting devices and virtual light-emitting devices, the outermost non-virtual light-emitting device is considered to be the boundary between the display area AA and the non-display area NA. The non-display area NA is arranged around the display area AA and has multiple signal lines. The devices in the display area AA are electrically connected to the bonding component through the signal lines to obtain the control signal output by the bonding component and light up the corresponding light-emitting device 40 according to the control signal. The bonding component may include at least one of the following electronic devices: flexible printed circuit (FPC), driver chip, etc.

[0048] like Figure 2 and Figure 3As shown, the display panel 1 includes a substrate 10, an isolation structure 30, and multiple light-emitting devices 40. The isolation structure 30 is disposed on one side of the substrate 10 and includes an isolation portion 30A located in the display area AA and an overlapping portion 30B located in the non-display area NA. The isolation portion 30A and the overlapping portion 30B are an integral structure. The isolation portion 30A encloses multiple isolation openings 33 in the display area AA to block vapor-deposited material and disconnect the vapor-deposited material in adjacent isolation openings 33, thereby isolating the multiple light-emitting devices 40. The overlapping portion 30B has multiple recesses 50 in the non-display area NA to solve the problem of peeling between the isolation structure 30 and adjacent film layers. At least a portion of the light-emitting device 40 is disposed within the corresponding isolation opening 33. The light-emitting device 40, as an independent light-emitting unit, can be turned on or off according to a corresponding display signal under the drive of the substrate 10. (The composition and preparation of the isolation structure 30 mentioned below are specified in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072.) Further descriptions can be found in CN117979755A, CN117998900A, CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, and CN117500332A for reference.

[0049] Furthermore, the display panel 1 also includes a driving layer 11, which is disposed on one side of the substrate 10 and located in the display area AA and the non-display area NA. In the display area AA, the driving layer 11 has a plurality of arrayed thin-film transistors (TFTs) for controlling the conduction of corresponding circuits, and each light-emitting device 40 is electrically connected to at least one TFT. The driving layer 11 also includes a conductive layer 12. This conductive layer 12 includes at least one power signal line located in the non-display area NA, which is used to provide a power signal to the light-emitting devices 40 in the display area AA. The conductive layer 12 also includes other signal traces for transmitting signals, such as data signal lines, compensation signal lines, etc. In the conductive layer 12, at least some of the signal traces have one end located in the display area AA and electrically connected to the TFTs located in the display area AA; the other end of these signal traces extends from the display area AA to the non-display area NA and is electrically connected to the bonding components. The signal traces in the conductive layer 12 are used to transmit the signals output by the bonding component to the corresponding thin film transistors. The thin film transistors conduct the corresponding circuits according to the received signals, thereby lighting up the corresponding light-emitting devices 40 to realize the display of images. At the same time, the bonding component can also realize the switching of display images by sending different display signals.

[0050] In the driving layer 11, at least one insulating layer can be provided between adjacent conductive film layers to isolate and prevent short circuits in the circuit of the substrate 10. Furthermore, different insulating layers may have other functions besides preventing short circuits, such as a planarization layer 13 for planarizing the surface of the substrate 10, located between the power signal line and the isolation structure 30. The material of the insulating layer may include at least one of inorganic or organic materials, and the materials of different insulating layers may be different. The planarization layer 13 includes an organic material.

[0051] The display panel 1 also includes a pixel defining layer 20 disposed on the side of the driving layer 11 facing away from the substrate 10. The pixel defining layer 20 is located in the display area AA and the non-display area NA, and encloses a plurality of pixel openings 21 in the display area AA. At least a portion of the light-emitting device 40 is disposed in the pixel openings 21. An isolation structure 30 is disposed on the side of the pixel defining layer 20 facing away from the substrate 10, and its isolation opening 33 in the display area AA communicates with the corresponding pixel opening 21, enabling the material in the light-emitting device 40 to be deposited in the pixel openings 21.

[0052] The light-emitting device 40 includes a first electrode 41, a light-emitting layer 42, and a second electrode 43. The first electrode 41 is disposed on one side of the driving layer 11 and is located between the pixel defining layer 20 and the driving layer 11, with a portion of its surface exposed in the corresponding pixel opening 21. The light-emitting layer 42 is disposed in the corresponding pixel opening 21, covering the exposed surface of the first electrode 41 in the corresponding pixel opening 21, and extends from the surface of the first electrode 41 to the side of the pixel defining layer 20 facing away from the substrate 10. The second electrode 43 is stacked on the side of the light-emitting layer 42 facing away from the substrate 10 and extends from the surface of the light-emitting layer 42 facing away from the substrate 10 to the surface of the isolation structure 30 facing the isolation opening 33, thereby allowing the second electrode 43 to overlap with the isolation structure 30. The first electrode 41 of the light-emitting device 40 is electrically connected to the thin-film transistor in the substrate 10, and its second electrode 43 is electrically connected to the power signal line through the isolation structure 30. After the first electrode 41 and the second electrode 43 are turned on, they respectively transmit electrons and holes to the light-emitting layer 42. The electrons and holes combine in the light-emitting layer 42 to form excitons, thereby converting electrical energy into light energy, causing the light-emitting layer 42 to emit light and light up the corresponding light-emitting device 40.

[0053] Specifically, the isolation structure 30 includes a support layer 31 and a barrier layer 32, which surround the isolation opening 33. The support layer 31 is disposed on the side of the pixel limiting layer 20 facing away from the substrate 10, and the barrier layer 32 is stacked and disposed on the side of the support layer 31 facing away from the substrate 10. The support layer 31 is made of a conductive material, and the barrier layer 32 is made of a metallic material; preferably, the support layer 31 can be made of aluminum, and the barrier layer 32 can be made of titanium.

[0054] Furthermore, in the isolation opening 33, the coverage area of ​​the second electrode 43 is larger than the coverage area of ​​the light-emitting layer 42. That is, the orthographic projection of the light-emitting layer 42 on the substrate 10 is within the orthographic projection range of the second electrode 43 on the substrate 10, and the second electrode 43 extends from the light-emitting layer 42 to the sidewall of the support layer 31, thereby enabling the second electrode 43 to be electrically connected to the support layer 31. The second electrode 43 can obtain power signals through the support layer 31. The cross-sectional profile of the support layer 31 located between two adjacent pixel openings 21 is trapezoidal, and the width of the support layer 31 near the barrier layer 32 is smaller than its width near the substrate 10, so as to facilitate the climbing of the second electrode 43 and reduce the difficulty of overlapping between the second electrode 43 and the support layer 31.

[0055] The barrier layer 32 protrudes from the support layer 31 at one end facing the isolation opening 33. That is, the orthogonal projection of the barrier layer 32 on the substrate 10 covers the orthogonal projection of the support layer 31 on the substrate 10, and the orthogonal projection area of ​​the barrier layer 32 on the substrate 10 is larger than the orthogonal projection area of ​​the support layer 31 on the substrate 10. This allows the barrier layer 32 to completely block the support layer 31, thereby preventing the material of the light-emitting layer 42 from being deposited onto the support layer 31 when the light-emitting layer 42 is prepared. When the second electrode 43 is prepared, the deposition angle of the material of the second electrode 43 can be adjusted to make the coverage area of ​​the second electrode 43 larger than the coverage area of ​​the light-emitting layer 42, so as to form a light-emitting layer 42 and a second electrode 43 with different coverage areas, thereby improving the bonding yield between the second electrode 43 and the support layer 31.

[0056] like Figure 3 As shown, in the non-display area NA, the isolation structure 30 has multiple (i.e., at least two) recesses 50, the pixel defining layer 20 has multiple (i.e., at least two) first vias 60, and the planarization layer 13 has multiple (i.e., at least two) second vias 70. The first vias 60 penetrate the pixel defining layer 20, and the second vias 70 penetrate the planarization layer 13. The first vias 60 and second vias 70 are arranged in a one-to-one correspondence, meaning that the first via 60 on the substrate 10 lies within the orthographic projection range of the corresponding second via 70 on the substrate 10. The support layer 31 in the isolation structure 30 is electrically connected to the power signal lines in the conductive layer 12 through the first vias 60 and the second vias 70, and transmits the VSS power signal through the power signal traces. Furthermore, the pixel defining layer 20 covers the surface of the planarization layer 13 facing away from the conductive layer 12 and the side of the planarization layer 13 facing the first via 60. At least one recess 50 is provided between two adjacent first vias 60 and second vias 70. The recess 50 penetrates the isolation structure 30, and the orthogonal projection of the recess 50 on the substrate 10 is outside the orthogonal projection range of the first vias 60 and second vias 70 on the substrate 10. That is, the orthogonal projection of the recess 50 on the substrate 10 is within the orthogonal projection range of the pixel defining layer 20 on the substrate 100 and the orthogonal projection range of the planarization layer 13 on the substrate 10. The spacing between two adjacent recesses 50 is less than or equal to 200 nanometers, and the width of the first vias 60 and second vias 70 is less than 200 nanometers. For example, the spacing between two adjacent recesses 50 can be 150 nanometers, 100 nanometers, or 50 nanometers, and the width of the first vias 60 and second vias 70 can be 150 nanometers, 100 nanometers, or 50 nanometers.

[0057] like Figure 3 or Figure 4As shown, the recessed portion 50 is recessed into the substrate 10 from the side of the isolation structure 30 away from the substrate 10, and its recessed depth is a first depth d1. On a cross-section perpendicular to the substrate 10, the barrier layer 32 has a first film thickness T1, and the first depth d1 is greater than the first film thickness T1, that is, the recessed portion 50 penetrates the barrier portion 32. The recessed portion 50 is recessed into the substrate 10 from the side of the support layer 31 away from the substrate 10, and its recessed depth is a second depth d2. The support layer 31 has a second film thickness T2, and the second depth d2 is less than or equal to the second film thickness T2, that is, the recessed portion 50 may or may not penetrate the isolation structure 30.

[0058] Specifically, each recess 50 includes a first opening 51 and a second opening 52 communicating with the first opening 51. The first opening 51 is located on the side of the support layer 31 facing away from the substrate 10, such as... Figure 3 and Figure 4 As shown, the depth of the first opening 51 (i.e., the second depth d2) is less than or equal to the thickness of the support layer 31 (i.e., the second film thickness T2), meaning the first opening 51 can be as follows: Figure 3 The surface of the support layer 31 facing away from the substrate 10, as shown, can also be... Figure 4 The first opening 51 completely penetrates the support layer 31. The isolation structure 30 has a first surface 34 facing the pixel defining layer 20. When the first opening 51 penetrates the support layer 31, the bottom wall of the first opening 51 and the first surface 34 are in the same plane, causing a portion of the surface of the pixel defining layer 20 facing away from the substrate 10 to be exposed in the recess 50. When the first opening 51 does not penetrate the support layer 31, the bottom wall of the recess 50 is not coplanar with the first surface 34 and is located on the side of the first surface 34 facing away from the substrate 10. The second opening 52 penetrates the barrier layer 32, and the orthographic projection of the second opening 52 on the substrate 10 is within the orthographic projection range of the first opening 51 on the substrate 10, allowing the second opening 52 to communicate with the first opening 51. Preferably, the depth of the first opening 51 is less than the thickness of the support layer 31, causing the recess 50 to not penetrate the support layer 31. A portion of the support layer 31 can be retained at the bottom of the recess 50, and retaining more support layer material can reduce the overall resistance value of the support layer 31, thereby reducing the power consumption of the display panel 1.

[0059] To meet the bonding requirements between the support layer 31 and the power signal line, a large area of ​​support layer 31 is prepared in the non-display area NA. However, in subsequent processes, the film layer (e.g., barrier layer 32) prepared in the non-display area NA is prone to peeling with the large area of ​​support layer 31, which can lead to abnormalities in the film layer in the non-display area NA. Therefore, in this embodiment of the invention, a recessed portion 50 is provided in the non-display area NA to relieve the stress in the support layer 31 and the barrier layer 32, thereby solving the problem of easy peeling between the large area of ​​support layer 31 in the non-display area NA and the film layer prepared in subsequent processes, and improving the bonding effect between the support layer 31 and other film layers in the non-display area NA.

[0060] It is understood that in other embodiments of the present invention, the isolation structure 30 may also have only one recess 50. By providing a single recess 50, the problem of easy peeling between the large area support layer 31 in the non-display area NA and the film layer prepared in the subsequent process can also be solved. Therefore, this embodiment does not specifically limit the number of recesses 50, that is, the number of recesses 50 can be one, two or more.

[0061] Furthermore, the recessed portion 50 can be fabricated simultaneously with the isolation opening 33 in the display area AA. Therefore, the maximum width of the second opening 52 in the recessed portion 50 is less than the minimum width of its first opening 51. That is, the orthographic projection of the second opening 52 on the substrate 10 is within the orthographic projection range of the first opening 51 on the substrate 10, and the orthographic projection area of ​​the second opening 52 on the substrate 10 is less than the orthographic projection area of ​​the first opening 51 on the substrate 10. At the same time, the cross-sectional shape of the first opening 51 in the thickness direction of the display panel 1 is trapezoidal, and the width of the first opening 51 near the substrate 10 is less than the width away from the substrate 10.

[0062] Furthermore, in other embodiments of the present invention, the display panel 1, such as... Figure 5 As shown, the display panel 1 also includes a plurality of third vias 80, which penetrate the pixel defining layer 20, causing a portion of the surface of the planarization layer 13 facing away from the substrate 10 to be exposed through the third vias 80. The plurality of third vias 80 and the plurality of recesses 50 are provided in a one-to-one correspondence, and the third vias 80 communicate with the corresponding recesses 50. In a cross-section perpendicular to the substrate 10, the width of the third via 80 is smaller than the width of the recess 50. The layered structure of this display panel 1 is similar to that of the display panel 1 provided in the embodiments of the present invention, and therefore will not be described in detail here. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0063] This invention also provides a display device, which can be an OLED display device, including the display panel 1 as described above. The display device can be any display device with display functionality, such as a mobile phone, laptop computer, or tablet computer.

[0064] In the display panel and display device provided in the embodiments of the present invention, by creating a recess in the isolation structure located in the non-display area NA, the stress in the isolation structure is relieved, thereby solving the problem of easy peeling between adjacent film layers of the isolation structure and improving the reliability of the display panel.

[0065] On the other hand, based on the technical problems raised by the aforementioned related display technologies, another embodiment of the present invention also provides a display panel 1. For example... Figure 1 As shown, the display panel 1 has a display area AA and a non-display area NA connected to the display area AA. The display area AA is used to display images and has multiple light-emitting devices 40, each of which can be lit by control. The non-display area NA is arranged around the display area AA and has multiple signal lines. The devices in the display area AA are electrically connected to the bonding component through the signal lines, thereby obtaining the control signals output by the bonding component and lighting up the corresponding light-emitting device 40 according to the control signals. The bonding component may include at least one of electronic devices such as a flexible printed circuit (FPC) and a driver chip.

[0066] The display panel 1 provided in this embodiment of the invention includes a substrate 10, an isolation structure 30, and a plurality of light-emitting devices 40. In the display area AA, the layered structure of the display panel 1 in this embodiment is similar to the layered structure of the display panel 1 provided in the above embodiments of the invention, and therefore will not be described in detail.

[0067] like Figure 6As shown, in the non-display area NA, the isolation structure 30 has multiple (i.e., at least two) recesses 50, the pixel defining layer 20 has at least one first via 60, and the planarization layer 13 has at least one second via 70. The first via 60 penetrates the pixel defining layer 20, and the second via 70 penetrates the planarization layer 13. The first via 60 and the second via 70 are arranged in a one-to-one correspondence, meaning that the first via 60 on the substrate 10 lies within the orthographic projection range of the corresponding second via 70 on the substrate 10. The support layer 31 in the isolation structure 30 is electrically connected to the power signal lines in the conductive layer 12 through the first via 60 and the second via 70, and transmits the VSS power signal through the power signal traces. Furthermore, the pixel defining layer 20 covers the surface of the planarization layer 13 facing away from the conductive layer 12 and the side of the planarization layer 13 facing the second via 70. Multiple recesses 50, multiple first vias 60, and multiple second vias 70 are provided in a one-to-one correspondence. Each first via 60 and second via 70 is fitted with a recess 50, meaning that the orthographic projection of the recess 50 on the substrate 10 lies within the orthographic projection range of the first via 60 and second via 70 on the substrate 10. In a cross-section perpendicular to the substrate 10, the width of the recess 50 is smaller than the width of the first via 60 and second via 70, thereby ensuring that a portion of the support layer 31 can extend into the first via 60 and second via 70 and be electrically connected to the conductive layer 12. The spacing between two adjacent recesses 50 is less than or equal to 200 nanometers, and the spacing between two adjacent second vias 70 is less than 200 nanometers. For example, the spacing between two adjacent recesses 50 can be 150 nanometers, 100 nanometers, or 50 nanometers, and the width between two adjacent second vias 70 can be 150 nanometers, 100 nanometers, or 50 nanometers. Furthermore, the plurality of recesses 50 include adjacent first recesses 50A and second recesses 50B, the portion of the pixel defining layer 20 projected onto the substrate 10, located between the projected image of the first recess 50A onto the substrate 10 and the projected image of the second recess 50B onto the substrate 10.

[0068] like Figure 6 or Figure 7 As shown, the recessed portion 50 is recessed into the substrate 10 from the side of the isolation structure 30 away from the substrate 10, and its recessed depth is a first depth d1. On a cross-section perpendicular to the substrate 10, the barrier layer 32 has a first film thickness T1, and the first depth d1 is greater than the first film thickness T1, that is, the recessed portion 50 penetrates the barrier portion 32. The recessed portion 50 is recessed into the substrate 10 from the side of the support layer 31 away from the substrate 10, and its recessed depth is a second depth d2. The support layer 31 has a second film thickness T2, and the second depth d2 is less than or equal to the second film thickness T2, that is, the recessed portion 50 may or may not penetrate the isolation structure 30.

[0069] Specifically, each recess 50 includes a first opening 51 and a second opening 52 communicating with the first opening 51. The first opening 51 is located on the side of the support layer 31 facing away from the substrate 10, such as... Figure 6 and Figure 7 As shown, the depth of the first opening 51 (i.e., the second depth d2) is less than or equal to the thickness of the support layer 31 (i.e., the second film thickness T2), meaning the first opening 51 can be as follows: Figure 6 The surface of the support layer 31 facing away from the substrate 10, as shown, can also be... Figure 7 The first opening 51 completely penetrates the support layer 31. The isolation structure 30 has a first surface 34 facing the power signal line. When the first opening 51 penetrates the support layer 31, the bottom wall of the first opening 51 and the second surface 35 are in the same plane, causing a portion of the surface of the power signal line facing away from the substrate 10 to be exposed in the recess 50. When the first opening 51 does not penetrate the support layer 31, the bottom wall of the recess 50 is not coplanar with the first surface 34 and is located on the side of the second surface 35 facing away from the substrate 10. The second opening 52 penetrates the barrier layer 32, and the orthographic projection of the second opening 52 on the substrate 10 is within the orthographic projection range of the first opening 51 on the substrate 10, allowing the second opening 52 to communicate with the first opening 51. Preferably, the depth of the first opening 51 is less than the thickness of the support layer 31, causing the recess 50 to not penetrate the support layer 31. A portion of the support layer 31 can be retained at the bottom of the recess 50, and retaining more support layer material can reduce the overall resistance value of the support layer 31, thereby reducing the power consumption of the display panel 1.

[0070] Furthermore, in the display panel 1 provided in other embodiments of the present invention, such as Figure 8 As shown, at least two recesses 50 can be fitted into the same first via 60 and second via 70. That is, the orthographic projections of at least two recesses 50 on the substrate 10 are located within the orthographic projection range of the same first via 60 and second via 70 on the substrate 10, and the width of the recess 50 is smaller than the width of the second via 70. The layered structure of this display panel 1 is similar to that of the display panel 1 provided in the embodiments of the present invention, and therefore will not be described in detail here. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0071] To meet the bonding requirements between the support layer 31 and the conductive layer 12, a large area of ​​support layer 31 is usually prepared in the non-display area NA. However, in subsequent processes, the film layer (e.g., barrier layer 32) prepared in the non-display area NA is prone to peeling with the large area of ​​support layer 31, which can lead to abnormalities in the film layer in the non-display area NA. Therefore, in this embodiment of the invention, a recess 50 is provided in the non-display area NA to relieve the stress in the support layer 31 and the barrier layer 32, thereby solving the problem of easy peeling between the large area of ​​support layer 31 in the non-display area NA and the film layer prepared in subsequent processes, and improving the bonding effect between the support layer 31 and other film layers in the non-display area NA.

[0072] In the display panel and display device provided in the embodiments of the present invention, by creating a recess in the isolation film group located in the non-display area NA, the stress in the isolation structure is relieved, thereby solving the problem of easy peeling between adjacent film layers of the isolation structure and improving the reliability of the display panel.

[0073] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. substrate; An isolation structure is disposed on one side of the substrate, located in the display area and the non-display area. The isolation structure encloses and forms a plurality of isolation openings and has at least one recessed portion. The plurality of isolation openings are located in the display area, and the at least one recessed portion is located in the non-display area. The at least one recessed portion is recessed into the substrate from the side of the isolation structure away from the substrate. A driving layer is disposed on one side of the substrate, located in the display area and the non-display area, and includes at least one power signal line, wherein the at least one power signal line is located in the non-display area; A pixel defining layer is disposed on the side of the driving layer opposite to the substrate, located in the display area and the non-display area. The pixel defining layer encloses and forms a plurality of pixel openings and has at least one first via. The plurality of pixel openings are located in the display area and communicate with the corresponding isolation opening. The at least one first via is located in the non-display area. A portion of the surface of the at least one power signal line opposite to the substrate is exposed from the at least one first via. A portion of the isolation structure extends into the at least one first via and is electrically connected to the at least one power signal line. Multiple light-emitting devices, at least a portion of which are located within the isolation opening; Wherein, at least a portion of the at least one recessed portion has its orthographic projection on the substrate located outside the orthographic projection range of the at least one first via on the substrate.

2. The display panel as described in claim 1, characterized in that, The driving layer further includes a planarization layer disposed between the at least one power signal line and the pixel defining layer. The planarization layer has at least one second via, and the orthographic projection of the at least one first via on the substrate is located within the orthographic projection of the at least one second via on the substrate. The material of the planarization layer includes organic materials; The isolation structure is located on the side of the pixel defining layer opposite to the substrate.

3. The display panel as described in claim 2, characterized in that, The at least one first via includes a plurality of first vias, and the at least one second via includes a plurality of second vias, wherein the plurality of first vias and the plurality of second vias are configured in a one-to-one correspondence.

4. The display panel as described in claim 2, characterized in that, The pixel-defining layer covers the side of the planar layer facing the at least one first via.

5. The display panel as described in claim 1, characterized in that, The at least one first via includes a plurality of first vias, and the at least one recess includes one or more recesses, the recess being disposed between two adjacent first vias.

6. The display panel as described in claim 1, characterized in that, The driving layer further includes a planarization layer, which is disposed between the at least one power signal line and the pixel defining layer, wherein: The orthographic projection of the recess on the substrate is located within the orthographic projection of the pixel defining layer on the substrate; and / or, the orthographic projection of the recess on the substrate is located within the orthographic projection of the planarization layer on the substrate.

7. The display panel as described in claim 1, characterized in that, The recessed portion does not penetrate the isolation structure; The isolation structure has a first surface facing the pixel defining layer, and the bottom wall of the recess is located on the side of the first surface facing away from the substrate.

8. The display panel as described in claim 1, characterized in that, The recessed portion penetrates the isolation structure.

9. The display panel as described in claim 8, characterized in that, A portion of the surface of the pixel defining layer facing away from the substrate is exposed from the recess; or... The pixel defining layer has a plurality of third vias, the third vias being connected to the corresponding recesses; the plurality of third vias and the plurality of recesses are provided in a one-to-one correspondence; the driving layer further includes a planarization layer, the planarization layer being disposed between the at least one power signal line and the pixel defining layer, and a portion of the surface of the planarization layer facing away from the substrate being exposed through the third vias.

10. The display panel as claimed in claim 9, characterized in that, In a cross-section perpendicular to the substrate, the width of the third via is smaller than the width of the recess.

11. The display panel as claimed in claim 1, characterized in that, The orthographic projection of a portion of the at least one recessed portion onto the substrate is outside the orthographic projection range of the at least one first via onto the substrate, while the orthographic projection of another portion of the at least one recessed portion onto the substrate is within the orthographic projection range of the at least one first via onto the substrate.

12. The display panel as claimed in claim 11, characterized in that, The at least one first via includes a plurality of first vias, and the at least one recess includes a plurality of recesses. In a cross section perpendicular to the substrate, the width of the recess is smaller than the width of the first via. The orthographic projection of the recessed portion on the substrate is located within the orthographic projection range of the corresponding first via on the substrate.

13. The display panel as claimed in claim 11, characterized in that, The plurality of recesses include adjacent first recesses and second recesses, and the portion of the pixel defining layer projected onto the substrate is located between the projected image of the first recess on the substrate and the projected image of the second recess on the substrate.

14. The display panel as claimed in claim 11, characterized in that, The plurality of recesses and the plurality of first through holes are provided in a one-to-one correspondence.

15. The display panel as claimed in claim 11, characterized in that, The recess extends through the isolation structure; a portion of the surface of the at least one power signal line facing away from the substrate protrudes from the recess; or... The recess does not penetrate the isolation structure; the isolation structure has a second surface facing the pixel defining layer, and the bottom wall of the recess is located on the side of the second surface away from the substrate.

16. The display panel as claimed in claim 11, characterized in that, At least two of the recesses have orthogonal projections on the substrate that are located within the orthogonal projection range of the same first via on the substrate. The recessed portion penetrates the isolation structure; The portion of the surface of at least one power signal line facing away from the substrate is exposed from the recess.

17. The display panel as claimed in claim 1, characterized in that, The at least one recess includes a plurality of recesses, and the distance between two adjacent recesses is no greater than 200 nanometers.

18. The display panel as claimed in claim 1, characterized in that, The isolation structure includes: A support layer is disposed on one side of the substrate; A barrier layer is disposed on the side of the support layer opposite to the substrate, and the orthogonal projection of the barrier layer on the substrate covers the orthogonal projection of the support layer on the substrate; The material of the support layer includes aluminum, and / or the material of the barrier layer includes titanium.

19. The display panel as claimed in claim 18, characterized in that, The at least one recessed portion is recessed into the substrate from the side of the isolation structure away from the substrate to a first depth, and the barrier layer has a first film thickness in a cross section perpendicular to the substrate, the first depth being greater than the first film thickness.

20. The display panel as claimed in claim 18, characterized in that, The at least one recess penetrates the barrier layer; and / or The at least one recessed portion is recessed into the substrate from the side of the support layer away from the substrate to a second depth, the support layer having a second film thickness, and the second depth being less than or equal to the second film thickness.

21. The display panel as claimed in claim 1, characterized in that, The isolation structure includes: An isolation section is located in the display area, and the isolation section encloses and forms the plurality of isolation openings; An overlapping portion is located in the non-display area, and at least one recessed portion is provided on the overlapping portion; The isolation section and the overlapping section are an integral structure.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1-21.

Images