Display panel and its manufacturing method, display device

Abstract

This application relates to a display panel, its manufacturing method, and a display device. The display panel includes: a substrate; signal lines disposed on one side of the substrate; a first insulating layer disposed on one side of the substrate, wherein a via is formed in the first insulating layer, and a portion of the signal lines is exposed through the via; a first electrode disposed on the side of the first insulating layer away from the substrate; and a second insulating layer disposed on the side of the first electrode away from the substrate. The second insulating layer includes a first flat portion, the dimension of which along the thickness direction of the substrate is a first dimension H1, and the distance between the surface of the first insulating layer near the substrate and the surface of the first insulating layer away from the substrate is a first distance L1. The ratio of the first dimension H1 to the first distance L1 is not less than 0.8. This solution can improve the yield rate of the finished display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels are currently one of the hottest research topics in the field of display panels. Compared with liquid crystal displays, OLED display panels have advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed. The subpixels of OLED display panels are usually fabricated using FMM (Fine Metal Mask) vapor deposition.

[0003] Currently, a vapor deposition process that eliminates the open-mold (FMM) has become a focus of attention in the industry. However, the yield rate of OLED display panels manufactured using this process is currently low. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel, its manufacturing method, and a display device that can improve the yield of finished display panels, in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display panel, including:

[0006] substrate,

[0007] Signal lines are disposed on one side of the substrate;

[0008] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via.

[0009] A first electrode is disposed on the side of the first insulating layer away from the substrate. The orthographic projection of the first electrode on the first insulating layer covers the via. The first electrode includes a first electrode portion connected to a signal line portion. The orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via.

[0010] A second insulating layer is disposed on the side of the first electrode away from the substrate, and the orthographic projection of the second insulating layer onto the first insulating layer covers the via.

[0011] The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer near the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0012] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. This reduces the step difference between the second insulating layer at the via and the non-via location, allowing for uniform film formation on the second insulating layer, such as forming an isolation structure. This avoids the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the display panel.

[0013] In one embodiment, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0014] Optionally, the first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second insulating layer further includes a second flat portion disposed on the side of the second electrode portion of the first electrode facing away from the substrate;

[0015] The second flat portion has a second dimension H2 along the thickness direction of the substrate, and the second dimension H2 is smaller than the first dimension H1;

[0016] Optionally, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0017] Optionally, the distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, wherein the ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0018] Optionally, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0019] In one embodiment, the second insulating layer defines a pixel opening, and a portion of the first electrode is exposed from the pixel opening;

[0020] Optionally, the display panel further includes an isolation structure disposed on the side of the second insulating layer away from the substrate. The orthographic projection of the isolation structure on the first insulating layer covers the via and defines an isolation opening that communicates with the pixel opening.

[0021] Optionally, the surface of the isolation structure away from the substrate has no step.

[0022] Optionally, the outer contour of the isolation opening projected onto the substrate is located outside the outer contour of the pixel opening projected onto the substrate.

[0023] Optionally, the orthographic projection of the isolation structure onto the substrate is a grid.

[0024] Optionally, the isolation structure includes a first isolation portion and a second isolation portion stacked along a direction away from the substrate, wherein the orthographic projection of the second isolation portion on the substrate covers the orthographic projection of the first isolation portion on the substrate;

[0025] Optionally, the first isolation portion includes a conductive material;

[0026] Optionally, the first isolation portion includes at least one metal layer;

[0027] Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the first metal layer on the substrate is located outside the outer contour of the orthographic projection of the second metal layer on the substrate;

[0028] Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum, copper, or silver.

[0029] In one embodiment, the second insulating layer further includes a third flat portion, the orthographic projection of the third flat portion on the substrate not overlapping the orthographic projection of the first electrode on the substrate;

[0030] The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2;

[0031] Optionally, the distance between the side surface of the third flat portion away from the substrate and the side surface of the substrate near the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3;

[0032] Optionally, the surface of the second insulating layer on the side away from the substrate has no step.

[0033] In one embodiment, the display panel further includes a light-emitting functional layer and a second electrode;

[0034] The light-emitting functional layer is disposed on the side of the first electrode away from the substrate, and is disposed at the pixel opening;

[0035] The second electrode is disposed on the side of the light-emitting functional layer away from the substrate;

[0036] Optionally, the second electrode is electrically connected to the first isolation section.

[0037] In one embodiment, the display panel further includes an encapsulation layer disposed on the side of the second electrode away from the substrate.

[0038] In one embodiment, the sidewall of the via is a plane or a curved surface.

[0039] Secondly, this application provides a display panel, including:

[0040] substrate,

[0041] Signal lines are disposed on one side of the substrate;

[0042] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via.

[0043] A first electrode is disposed on the side of the first insulating layer away from the signal line. The orthographic projection of the first electrode on the first insulating layer covers the via. The first electrode includes a first electrode portion connected to the signal line portion. The orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via.

[0044] A pixel definition layer is disposed on the side of the first electrode away from the substrate. The orthographic projection of the pixel definition layer on the first insulating layer covers the via and defines a pixel opening. A portion of the first electrode is exposed from the pixel opening.

[0045] An isolation structure is disposed on the side of the pixel definition layer away from the substrate. The orthographic projection of the isolation structure on the first insulating layer covers the via, and the isolation structure defines an isolation opening that communicates with the pixel opening.

[0046] A light-emitting functional layer is disposed on the side of the first electrode away from the substrate and at the pixel opening;

[0047] The pixel definition layer includes a first flat portion and a second flat portion that are in contact with the first electrode portion of the first electrode. The orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the first electrode portion on the substrate. The dimension of the first flat portion along the thickness direction of the substrate is greater than the dimension of the second flat portion along the thickness direction of the substrate.

[0048] In this embodiment, the dimension of the first flat portion along the thickness direction of the substrate is greater than that of the second flat portion along the thickness direction of the substrate. This reduces the step difference between the pixel definition layer at the via and the non-via location, making the film formation area of ​​the isolation structure relatively smooth. This results in a uniform film thickness for the isolation structure, thereby avoiding pixel dark spot problems caused by the isolation structure being easily damaged during the pixel opening stage, and thus improving the yield of the display panel.

[0049] In one embodiment, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer near the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0050] Optionally, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0051] Optionally, the first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second flat portion contacts the second electrode portion of the first electrode;

[0052] The second flat portion has a second dimension H2 along the thickness direction of the substrate, and the second dimension H2 is smaller than the first dimension H1;

[0053] Optionally, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0054] Optionally, the distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, wherein the ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0055] Optionally, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0056] In one embodiment, the surface of the isolation structure on the side away from the substrate has no step.

[0057] Optionally, the outer contour of the isolation opening projected onto the substrate is located outside the outer contour of the pixel opening projected onto the substrate.

[0058] Optionally, the orthographic projection of the isolation structure onto the substrate is a grid.

[0059] Optionally, the isolation structure includes a first isolation portion and a second isolation portion stacked along a direction away from the substrate, wherein the orthographic projection of the second isolation portion on the substrate covers the orthographic projection of the first isolation portion on the substrate;

[0060] Optionally, the first isolation portion includes a conductive material;

[0061] Optionally, the first isolation portion includes at least one metal layer;

[0062] Optionally, the first isolation portion includes a first metal layer and a second metal layer stacked along a direction away from the substrate, wherein the outer contour of the orthographic projection of the first metal layer on the substrate is located outside the outer contour of the orthographic projection of the second metal layer on the substrate;

[0063] Optionally, the material of the second isolation portion includes titanium or molybdenum; the material of the first metal layer includes molybdenum or titanium; and the material of the second metal layer includes aluminum, copper, or silver.

[0064] In one embodiment, the pixel definition layer further includes a third flat portion, the orthographic projection of the third flat portion on the substrate not overlapping the orthographic projection of the first electrode on the substrate;

[0065] The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, and the third dimension H3 is greater than the second dimension H2;

[0066] Optionally, the distance between the side surface of the third flat portion away from the substrate and the side surface of the substrate near the signal line is a fourth distance L4, and the fourth distance L4 is equal to the third distance L3;

[0067] Optionally, the surface of the second insulating layer on the side away from the substrate has no step.

[0068] In one embodiment, the display panel further includes a light-emitting functional layer and a second electrode. The light-emitting functional layer is disposed on the side of the first electrode away from the substrate and at the pixel opening. The second electrode is disposed on the side of the light-emitting functional layer away from the substrate.

[0069] Optionally, the second electrode is electrically connected to the first isolation section.

[0070] In one embodiment, the display panel further includes an encapsulation layer disposed on the side of the second electrode away from the substrate.

[0071] Thirdly, this application provides a display panel, including:

[0072] substrate,

[0073] Signal lines are disposed on one side of the substrate;

[0074] A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via.

[0075] A first electrode is disposed on the side of the first insulating layer away from the substrate. The orthographic projection of the first electrode on the first insulating layer covers the via. The first electrode includes a first electrode portion and a second electrode portion connected to the signal line portion. The orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via. The orthographic projection of the second electrode portion on the first insulating layer does not overlap with the via.

[0076] A second insulating layer is disposed on the side of the first electrode away from the substrate, and the orthographic projection of the second insulating layer onto the first insulating layer covers the via.

[0077] The second insulating layer includes a first flat portion and a second flat portion that are in contact with the first electrode portion and the second electrode portion of the first electrode, respectively; the distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0078] In this embodiment, the ratio of the second distance L2 to the third distance L3 is not less than 0.8. This reduces the step difference between the second insulating layer at the via and the non-via location, allowing for uniform film formation on the second insulating layer, such as forming an isolation structure. This avoids the pixel dark spot problem caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the display panel.

[0079] In one embodiment, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2;

[0080] Optionally, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer close to the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0081] Optionally, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0082] Optionally, the dimension of the second flat portion along the thickness direction of the substrate is a second dimension H2, and the second dimension H2 is smaller than the first dimension H1;

[0083] Optionally, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A.

[0084] Fourthly, this application provides a method for manufacturing a display panel, the method comprising:

[0085] Provide substrate,

[0086] A signal line is formed on one side of the substrate.

[0087] A first insulating layer is formed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via.

[0088] A first electrode is formed on the side of the first insulating layer away from the substrate, wherein the orthographic projection of the first electrode on the first insulating layer covers the via, and the first electrode includes a first electrode portion connected to the signal line portion, and the orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via;

[0089] A second insulating layer is formed on the side of the first electrode away from the substrate, wherein the orthographic projection of the second insulating layer onto the first insulating layer covers the via.

[0090] The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer near the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0091] In one embodiment, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2;

[0092] Optionally, the first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second insulating layer further includes a second flat portion disposed on the side of the second electrode portion of the first electrode facing away from the substrate;

[0093] The second flat portion has a second dimension H2 along the thickness direction of the substrate, and the second dimension H2 is smaller than the first dimension H1;

[0094] Optionally, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0095] Optionally, the distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, wherein the ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0096] Optionally, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0097] In one embodiment, forming a second insulating layer on the side of the first electrode away from the substrate includes:

[0098] An insulating material layer is formed on the side of the first electrode away from the substrate; and a photoresist layer is formed on the insulating material layer;

[0099] The photoresist layer is exposed using a halftone mask, wherein the halftone mask includes a first region, a second region, and a third region; the transmittance of the first region is less than that of the second region; the transmittance of the second region is less than that of the third region;

[0100] The photoresist layer is developed to form a first partial removal region, a second partial removal region, and a completely removed region, wherein the first partial removal region corresponds to the first region, the second partial removal region corresponds to the second region, and the completely removed region corresponds to the third region.

[0101] The photoresist in the completely removed area is removed, a portion of the photoresist in the first partially removed area is removed, and a portion of the photoresist in the second partially removed area is removed, wherein the thickness of the remaining photoresist in the first partially removed area is greater than the thickness of the remaining photoresist in the second partially removed area.

[0102] The insulating material layer exposed in the completely removed area is etched to form a pixel opening;

[0103] Remove a portion of the remaining photoresist in the first local removal area, retaining the insulating material layer covered by the photoresist in the first local removal area to form the first planar portion;

[0104] The photoresist in the second local removal area is etched away, and the insulating material layer in the second local removal area is etched to form the second planar portion.

[0105] In one embodiment, forming a second insulating layer on the side of the first electrode away from the substrate includes:

[0106] An insulating material layer is formed on the side of the first electrode away from the substrate, and the ratio of the dimension of the insulating material layer on the first electrode portion of the first electrode along the thickness direction of the substrate to the first distance L1 is not less than 0.8;

[0107] A photoresist layer is formed on the insulating material layer;

[0108] The photoresist layer is exposed using a first mask, wherein the first mask includes a blocking area and a light-transmitting area; the blocking area corresponds to the first electrode portion, and the light-transmitting area corresponds to the second electrode portion;

[0109] The photoresist layer is developed to form a retention area and a removal area, wherein the retention area corresponds to the first electrode portion and the removal area corresponds to the second electrode portion;

[0110] Remove the photoresist from the removal area and etch the insulating material layer in the removal area to form the second planar portion and pixel opening;

[0111] The photoresist in the reserved area is retained to form the first flat portion.

[0112] In one embodiment, forming a second insulating layer on the side of the first electrode away from the substrate includes:

[0113] A first insulating material layer is formed on the side of the first electrode portion of the first electrode away from the substrate, and the ratio of the dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate to the first distance L1 is not less than 0.8, so as to form the first flat portion.

[0114] A second insulating material layer is formed on the side of the second electrode portion of the first electrode that is away from the substrate, and the dimension of the second insulating material layer on the second electrode portion along the thickness direction of the substrate is smaller than the dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate, so as to form the second flat portion.

[0115] Fifthly, this application provides a display device comprising a display panel as described in any one of the first, second, or third aspects above. Attached Figure Description

[0116] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0117] Figure 1 This is a cross-sectional schematic diagram of the display panel in one embodiment;

[0118] Figure 2 This is a cross-sectional schematic diagram of the display panel in another embodiment;

[0119] Figure 3 This is a cross-sectional schematic diagram of the display panel in yet another embodiment;

[0120] Figure 4 This is a cross-sectional schematic diagram of the isolation structure in one embodiment;

[0121] Figure 5 This is a top view of the isolation structure in one embodiment;

[0122] Figure 6 This is a cross-sectional schematic diagram of the isolation structure in another embodiment;

[0123] Figure 7 This is a cross-sectional schematic diagram of a sub-pixel in one embodiment;

[0124] Figure 8 This is a cross-sectional schematic diagram of the encapsulation layer in one embodiment;

[0125] Figure 9 This is a schematic flowchart illustrating a method for fabricating a display panel in one embodiment.

[0126] Explanation of reference numerals in the attached figures:

[0127] 101. Substrate; 102. Signal line; 103. First insulating layer; P. Via;

[0128] 104a, First electrode; 1041, First electrode portion; 1042, Second electrode portion; 104b, Light-emitting functional layer; 104c, Second electrode;

[0129] 105 - Second insulating layer; 1051 - First flat portion; 1052 - Second flat portion; 105a - Pixel opening;

[0130] 401, Isolation structure; 4011, First isolation section; 4012, Second isolation section; 401a, Isolation opening; 4011a, First metal layer; 4011b, Second metal layer; 801, Encapsulation layer. Detailed Implementation

[0131] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0132] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0133] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0134] In related technologies, OLED display panels use photolithography to achieve pixel-level encapsulation without the need for FMM evaporation, which improves the pixel aperture ratio of the display panel. In order to further maximize the pixel aperture ratio, the vias corresponding to the anodes of the first sub-pixel (e.g., red R), the second sub-pixel (e.g., green G), and the third sub-pixel (e.g., blue B) are usually designed below the isolation pillars.

[0135] However, the applicant discovered that the via step was large, resulting in a thinner film on the isolation structure at this point. Furthermore, during the dry etching of the encapsulation layer of the first sub-pixel, over-etching during the dry etching process could easily damage the top Ti layer of the isolation structure. Subsequently, when opening vias for the second and third sub-pixels, the chemical solution from the wet etching process could easily enter through the over-etched area, damaging the isolation structure and causing Al voids in the isolation structure, thereby triggering pixel dark spots and resulting in a low yield of OLED display panels.

[0136] Furthermore, by increasing the thickness of the pixel definition layer at the via, the applicant makes the film-forming area of ​​the isolation structure more gradual, resulting in a uniform film thickness for the isolation structure. This avoids the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the finished display panel.

[0137] The composition and preparation of the isolation structure mentioned below are further described in patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 100935, PCT / CN2024 / 102785, PCT / CN2024 / 099419, PCT / CN2024 / 099072, and CN116685174A for reference.

[0138] Specifically, refer to Figure 1 As shown, this application provides a display panel, which can be an OLED display panel or a QLED (Quantum Dot Light Emitting Diodes) display panel.

[0139] The display panel includes a substrate 101, a signal line 102, a first insulating layer 103, a first electrode 104a, and a second insulating layer 105.

[0140] Signal line 102 is disposed on one side of substrate 101. First insulating layer 103 is disposed on one side of substrate 101, and a portion of the first insulating layer 103 is located on the side of signal line 102 away from substrate 101. A via P is formed on the first insulating layer 103, and a portion of signal line 102 is exposed through the via P.

[0141] The first electrode 104a is disposed on the side of the first insulating layer 103 away from the substrate 101. The orthogonal projection of the first electrode 104a on the first insulating layer 103 covers the via P. The first electrode 104a includes a first electrode portion 1041 that is partially connected to the signal line 102. The orthogonal projection of the first electrode portion 1041 on the first insulating layer 103 covers the bottom wall of the via P.

[0142] The second insulating layer 105 is disposed on the side of the first electrode 104a away from the substrate 101, and the orthogonal projection of the second insulating layer 105 on the first insulating layer 103 covers the via P.

[0143] The second insulating layer 105 includes a first flat portion 1051. The orthographic projection of the first flat portion 1051 on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101. The dimension of the first flat portion 1051 along the thickness direction of the substrate 101 is a first dimension H1. The distance between the side surface of the first insulating layer 103 close to the substrate 101 and the side surface of the first insulating layer 103 away from the substrate 101 is a first distance L1. The ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0144] Wherein, the first dimension H1 can be the average distance or the maximum distance of the first flat portion 1051 away from the substrate 101; the first distance L1 can be the average distance of the surface of the first insulating layer 103 away from the substrate 101; when the first dimension H1 is the average distance, the first distance L1 is also the average distance, and when the first dimension H1 is the maximum distance, the first distance L1 is also the maximum distance.

[0145] The substrate 101 includes a driving circuit composed of multiple metal layers and multiple insulating layers. The signal line 102 is electrically connected to the first electrode 104a, and the side of the signal line 102 facing away from the first electrode 104a is connected to the output terminal of the driving circuit to transmit an electrical signal to the first electrode 104a.

[0146] The first insulating layer 103 can be a planarization layer to achieve planarization. The material of the first insulating layer 103 can be insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride, or combinations thereof, or it can be a resin material such as photoresist. The stacked substrate 101, signal line 102, and first insulating layer 103 constitute an array substrate. A via P is formed in the first insulating layer 103, allowing a portion of the signal line 102 to be exposed through the via P, so that the first electrode 104a can be electrically connected to the signal line 102 through the via P. The sidewall of the via P can be planar or curved, and is not limited here. Figure 1 The sidewall of the via P is used as an example of a curved surface.

[0147] The first electrode 104a can be an anode. The first electrode 104a includes a first electrode portion 1041, a second electrode portion 1042, and a third electrode portion (not shown in the figure). The orthographic projection of the first electrode portion 1041 onto the first insulating layer 103 covers the bottom wall of the via P. The orthographic projection of the second electrode portion 1042 onto the first insulating layer 103 does not overlap with the via P. The second electrode portion 1042 mainly contacts the light-emitting functional layer. The third electrode portion is the electrode portion connecting the first electrode portion 1041 and the second electrode portion 1042, that is, the electrode portion attached to the side wall of the via P. It should be noted that, for the sake of clear explanation of the first electrode portion 1041, the second electrode portion 1042, and the third electrode portion, in… Figure 1 In the diagram, the first electrode section 1041, the second electrode section 1042, and the third electrode section are distinguished by using dashed lines for isolation.

[0148] The second insulating layer 105 can be a pixel definition layer, and the material of the second insulating layer 105 can be an inorganic material. The second insulating layer 105 defines the light-emitting area of ​​each sub-pixel, avoiding the diffusion and color mixing of light-emitting functional materials between sub-pixels.

[0149] The second insulating layer 105 includes a first flat portion 1051, a second flat portion 1052, and a third insulating portion (not shown in the figure). The first flat portion 1051 refers to the portion that contacts the first electrode portion 1041 of the first electrode 104a, and is also the portion where the orthographic projection on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101. The second flat portion 1052 refers to the portion disposed on the side of the second electrode portion 1042 of the first electrode 104a facing away from the substrate, and is also the portion that contacts the second electrode portion 1042 of the first electrode 104a. The third insulating portion refers to the portion attached to the third electrode portion, connecting the first flat portion 1051 and the second flat portion 1052. It should be noted that, for the sake of clear explanation of the first flat portion 1051, the second flat portion 1052, and the third insulating portion, in… Figure 1 In the diagram, dashed lines are used to separate the first flat portion 1051, the second flat portion 1052, and the third insulating portion.

[0150] In addition, Figure 1 The first dimension H1 and the first distance L1 are marked. The first dimension H1 is the dimension of the first flat portion 1051 along the thickness direction of the substrate 101, which is also the thickness of the second insulating layer 105 at the via P. The first distance L1 is the distance between the side surface of the first insulating layer 103 close to the substrate 101 and the side surface of the first insulating layer 103 away from the substrate 101, which is also the maximum thickness of the first insulating layer 103.

[0151] The ratio of the first dimension H1 to the first distance L1 is not less than 0.8. Specifically, the ratio of the first dimension H1 to the first distance L1 can be a specific value such as 0.8, 0.9, 1.1, 1.2, 1.3, 1.4, 1.5, etc., or a range with any two of the above specific values ​​as endpoints.

[0152] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. This reduces the step difference between the second insulating layer 105 at the via P and the non-via P, allowing for uniform film formation on the second insulating layer 105, such as forming an isolation structure. This avoids the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the display panel.

[0153] In one embodiment, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2, that is, the ratio of the first dimension H1 to the first distance L1 is close to 1. This reduces the step difference of the second insulating layer 105 between the via P and the non-via location. (Refer to...) Figure 2 The diagram shows a cross-sectional view of the display panel when the ratio of the first dimension H1 to the first distance L1 is 1.1.

[0154] In addition, the ratio of the first dimension H1 to the first distance L1 being greater than or equal to 0.8 and less than or equal to 1.2 refers to specific values ​​such as 0.8, 0.9, 1.1, and 1.2, as well as the range with any two of the above specific values ​​as endpoints.

[0155] In one embodiment, reference Figure 2 As shown, the second flat portion 1052 has a dimension H2 along the thickness direction of the substrate 101. The second dimension H2 is smaller than the first dimension H1, which reduces the step difference between the second insulating layer 105 at the via P and the non-via location. Preferably, the second dimension H2 is greater than or equal to 3000 Å and less than or equal to 5000 Å, which reduces the thickness of the display panel. The second dimension H2 being greater than or equal to 3000 Å and less than or equal to 5000 Å refers to the second dimension H2 being a specific value such as 3000 Å, 3500 Å, 4000 Å, 4500 Å, 5000 Å, etc., and a range with any two of the above specific values ​​as endpoints.

[0156] In one embodiment, reference Figure 3As shown, the distance between the side surface of the first flat portion 1051 away from the substrate 101 and the side surface of the substrate 101 near the signal line 102 is the second distance L2, and the distance between the side surface of the second flat portion 1052 away from the substrate 101 and the side surface of the substrate 101 near the signal line 102 is the third distance L3. The ratio of the second distance L2 to the third distance L3 is not less than 0.8. In this way, the step difference between the second insulating layer 105 at the via P and the non-via P is reduced, so that a film with uniform thickness can be formed on the second insulating layer 105, such as the film forming of the isolation structure. This can avoid the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the display panel.

[0157] Preferably, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2, that is, the ratio of the second distance L2 to the third distance L3 is close to 1. This can reduce the step difference of the second insulating layer 105 between the via P and the non-via P. In addition, the ratio of the second distance L2 to the third distance L3 being between 0.8 and 1.2 refers to specific values ​​of the ratio of the second distance L2 to the third distance L3 such as 0.8, 0.9, 1.1, 1.2, etc., and the range with any two of the above specific values ​​as endpoints.

[0158] In one embodiment, reference Figure 4 As shown, the second insulating layer 105 defines a pixel opening 105a, and a portion of the first electrode 104a is exposed through the pixel opening 105a. Further, a second electrode portion 1042 of the first electrode 104a is exposed through the pixel opening 105a. The sidewalls of the pixel opening 105a can be planar or curved. Figure 4 A planar example.

[0159] In one embodiment, the second insulating layer 105 further includes a third flat portion, the orthographic projection of the third flat portion on the substrate 101 not overlapping the orthographic projection of the first electrode 104a on the substrate 101; the third flat portion is disposed between adjacent first electrodes 104a and in direct contact with the first insulating layer 103; the dimension of the third flat portion along the thickness direction of the substrate 101 is a third dimension H3, the third dimension H3 is greater than the second dimension H2, the second dimension H2 is the dimension of the second flat portion 1052 along the thickness direction of the substrate 101, thus reducing the step difference between the third flat portion and the second flat portion 1052 caused by the first electrode 104a.

[0160] In one embodiment, the distance between the surface of the third flat portion away from the substrate 101 and the surface of the substrate 101 near the signal line 102 is a fourth distance L4, which is equal to the third distance L3. This achieves that the surface of the third flat portion away from the substrate 101 and the surface of the second flat portion 1052 away from the substrate 101 are on the same plane, and achieves no step difference between the third flat portion and the second flat portion 1052.

[0161] In one embodiment, the surface of the second insulating layer 105 away from the substrate 101 is without step, so that a film of uniform thickness can be formed on the second insulating layer 105.

[0162] In one embodiment, reference Figure 4 As shown, the display panel also includes an isolation structure 401. The isolation structure 401 is disposed on the side of the second insulating layer 105 away from the substrate. The orthographic projection of the isolation structure 401 on the first insulating layer 103 covers the via P, and the isolation structure 401 defines an isolation opening 401a. The isolation opening 401a communicates with the pixel opening 105a, so that a portion of the first electrode 104a is also exposed from the isolation opening 401a.

[0163] The outer contour of the isolation opening 401a projected onto the substrate 101 is located outside the outer contour of the pixel opening 105a projected onto the substrate.

[0164] The orthographic projection of the isolation structure 401 on the substrate covers the first flat portion 1051 of the second insulating layer 105, the portion of the second flat portion 1052 near the first flat portion 1051, the orthographic projection of the third insulating portion on the substrate, and the orthographic projection of the third flat portion on the substrate; the isolation opening 401a exposes a portion of the second flat portion 1052.

[0165] In this embodiment, the isolation structure 401 refers to a structure that can separate the light-emitting functional layers of adjacent sub-pixels during the deposition of the light-emitting functional layer of the sub-pixel. By setting the isolation structure 401, this embodiment can separate the light-emitting functional layers of adjacent sub-pixels during deposition, which is beneficial for fabricating sub-pixels using pixel patterning technology and freeing them from the constraints of FMM (Fixed Mirror Model). In one example, the isolation structure 401 can be a single-layer structure; in another example, the isolation structure 401 can be a multi-layer structure.

[0166] In one embodiment, reference Figure 5 As shown, the orthographic projection of the isolation structure 401 onto the substrate 101 is a grid pattern. This achieves the purpose of isolating the light-emitting functional layers of adjacent sub-pixels during the deposition of the sub-pixel's light-emitting functional layer. Furthermore, it should be noted that the arrangement of sub-pixels R, G, and B is not limited in this application. Figure 5This is just one example.

[0167] In one embodiment, reference Figure 4 As shown, the isolation structure 401 includes a first isolation portion 4011 and a second isolation portion 4012 stacked along the direction away from the substrate 101, and the orthographic projection of the second isolation portion 4012 on the substrate covers the orthographic projection of the first isolation portion 4011 on the substrate.

[0168] The material of the second isolation section 4012 includes metals, such as titanium (Ti) or molybdenum (Mo).

[0169] The first isolation portion 4011 includes a conductive material. In one example, all the materials constituting the first isolation portion 4011 are conductive materials. In another example, the materials constituting the first isolation portion 4011 include insulating materials and conductive materials.

[0170] Specifically, the first isolation section 4011 includes at least one metal layer, as shown in the reference. Figure 4 As shown, the first isolation portion 4011 includes a first metal layer 4011a and a second metal layer 4011b stacked along a direction away from the substrate 101. In one example, the outer contour of the orthographic projection of the first metal layer 4011a on the substrate 101 is located outside the outer contour of the orthographic projection of the second metal layer 4011b on the substrate 101. The material of the first metal layer 4011a includes molybdenum or titanium; the material of the second metal layer 4011b includes aluminum, copper, or silver.

[0171] It is understood that the first metal layer 4011a and the second metal layer 4011b in the second isolation section 4012 and the first isolation section 4011 form an I-shaped structure. In this way, by setting up three stacked metal layers, the resistance of the isolation structure 401 can be reduced, thereby reducing the power consumption of the display panel.

[0172] It is understandable that the isolation structure 401 can be as follows: Figure 4 As shown, the surfaces of the first isolation portion 4011 and the second isolation portion 4012 away from the substrate 101 are both curved surfaces, and the isolation structure 401 can also be as follows: Figure 6 As shown, the surfaces of the first isolation portion 4011 and the second isolation portion 4012 that are away from the substrate 101 are both flat, that is, the surface of the isolation structure 401 that is away from the substrate 101 has no step.

[0173] In one embodiment, reference Figure 7As shown, the display panel also includes a light-emitting functional layer 104b and a second electrode 104c; the light-emitting functional layer 104b is disposed on the side of the first electrode 104a away from the substrate 101 and is disposed at the pixel opening 105a; the second electrode 104c is disposed on the side of the light-emitting functional layer 104b away from the substrate 101.

[0174] In this design, the first electrode 104a, the light-emitting functional layer 104b, and the second electrode 104c, which are stacked together, constitute a sub-pixel. Each sub-pixel is disposed in an isolation opening 401a, and the area to which the isolation opening 401a belongs is also called the light-emitting area.

[0175] It is understood that the first electrode 104a can be an anode, and the second electrode 104c can be a cathode. The light-emitting functional layer 104b includes at least an emission layer (EML), and may also include one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole block layer (HBL), and an electron block layer (EBL). Alternatively, the light-emitting functional layer 104b may also be a stacked light-emitting layer, that is, it includes at least two light-emitting layers and a charge generation layer (CGL) located between each adjacent light-emitting layer.

[0176] In one example, the second electrode 104c is electrically connected to the first isolation portion 4011. (Continue to refer to...) Figure 7 As shown, the second electrode 104c includes an overlapping portion (not shown in the figure) that covers at least a portion of the sidewall of the first isolation portion 4011. Specifically, the overlapping portion is connected to both the first metal layer 4011a and the second metal layer 4011b in the first isolation portion 4011. It can be understood that the second electrode 104c also includes a main body portion (not shown in the figure) that at least covers the light-emitting functional layer 104b.

[0177] By covering the side wall of the first isolation portion 4011 with the overlapping portion, the electrical connection resistance between the overlapping portion and the first isolation portion 4011 can be reduced, thereby reducing the electrical connection resistance between the overlapping portion and the isolation structure 401, which is beneficial to improving display uniformity.

[0178] In one embodiment, reference Figure 8As shown, the display panel also includes an encapsulation layer 801, which is disposed on the side of the second electrode 104c away from the substrate 101.

[0179] Optionally, the encapsulation layer 801 can be a single-layer inorganic film layer or multiple inorganic film layers, and the inorganic film layers can be silicon oxide layers, silicon nitride layers, etc. The encapsulation layer 801 can also be composed of a mixture of organic and inorganic film layers. The encapsulation layer 801 can prevent the sub-pixels from being corroded by moisture.

[0180] Since the ratio of the first dimension H1 to the first distance L1 is not less than 0.8, the step difference between the second insulating layer 105 at the via P and the non-via is reduced, making the film-forming area of ​​the isolation structure 401 relatively flat. This results in a uniform film thickness of the isolation structure, and the film layer of the encapsulation layer 801 is also more continuous, which can effectively protect the underlying film layer.

[0181] In one embodiment, such as Figure 9 As shown, this application also provides a method for manufacturing a display panel, which can be used to manufacture the display panel in the above-described display panel embodiments.

[0182] The manufacturing method of this display panel includes:

[0183] Step 901, Provide substrate 101,

[0184] Step 902: A signal line 102 is formed on one side of the substrate 101.

[0185] Step 903: A first insulating layer 103 is formed on one side of the substrate 101, and a portion of the first insulating layer 103 is located on the side of the signal line 102 away from the substrate 101. A via P is formed on the first insulating layer 103, and a portion of the signal line 102 is exposed through the via P.

[0186] Step 904: A first electrode 104a is formed on the side of the first insulating layer 103 away from the substrate 101. The orthogonal projection of the first electrode 104a on the first insulating layer 103 covers the via P. The first electrode 104a includes a first electrode portion 1041 that is partially connected to the signal line 102. The orthogonal projection of the first electrode portion 1041 on the first insulating layer 103 covers the bottom wall of the via P.

[0187] Step 905: A second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101, wherein the orthographic projection of the second insulating layer 105 on the first insulating layer 103 covers the via P.

[0188] The second insulating layer 105 includes a first flat portion 1051. The orthographic projection of the first flat portion 1051 on the substrate 101 overlaps with the orthographic projection of the via P on the substrate 101. The dimension of the first flat portion 1051 along the thickness direction of the substrate 101 is a first dimension H1. The distance between the side surface of the first insulating layer 103 close to the substrate 101 and the side surface of the first insulating layer 103 away from the substrate 101 is a first distance L1. The ratio of the first dimension H1 to the first distance L1 is not less than 0.8.

[0189] Optionally, the ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.2.

[0190] Optionally, the first electrode 104a further includes a second electrode portion 1042, the orthographic projection of the second electrode portion 1042 on the first insulating layer 103 not overlapping with the via P; the second insulating layer 105 further includes a second flat portion 1052 that contacts the second electrode portion 1042 of the first electrode 104a; the second flat portion 1052 has a second dimension H2 along the thickness direction of the substrate 101, and the second dimension H2 is smaller than the first dimension H1;

[0191] Optionally, the second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A;

[0192] Optionally, the distance between the side surface of the first flat portion 1051 away from the substrate 101 and the side surface of the substrate 101 near the signal line 102 is the second distance L2, and the distance between the side surface of the second flat portion 1052 away from the substrate 101 and the side surface of the substrate 101 near the signal line 102 is the third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.8.

[0193] Optionally, the ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.2.

[0194] In this embodiment, the ratio of the first dimension H1 to the first distance L1 is not less than 0.8. This reduces the step difference between the second insulating layer 105 at the via P and the non-via P, allowing for uniform film formation on the second insulating layer 105, such as forming an isolation structure. This avoids the problem of pixel dark spots caused by the isolation structure being easily damaged during the pixel opening stage, thereby improving the yield of the display panel.

[0195] In one embodiment, the formation of the second insulating layer 105 on the side of the first electrode 104a away from the substrate 101 can be achieved in several ways:

[0196] In one example, a second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101, including the following steps:

[0197] Step 11: An insulating material layer is formed on the side of the first electrode 104a away from the substrate 101; and a photoresist layer is formed on the insulating material layer;

[0198] Step 12: Expose the photoresist layer using a halftone mask, wherein the halftone mask includes a first region, a second region, and a third region; the transmittance of the first region is less than that of the second region; the transmittance of the second region is less than that of the third region.

[0199] Step 13: The photoresist layer is developed to form a first partial removal area, a second partial removal area, and a completely removed area. The first partial removal area corresponds to the first area, the second partial removal area corresponds to the second area, and the completely removed area corresponds to the third area.

[0200] Step 14: Remove the photoresist from the completely removed area, remove a portion of the photoresist from the first partial removed area, and remove a portion of the photoresist from the second partial removed area, wherein the thickness of the remaining photoresist in the first partial removed area is greater than the thickness of the remaining photoresist in the second partial removed area.

[0201] Step 15: Etch the insulating material layer exposed in the completely removed area to form pixel opening 105a;

[0202] Step 16: Remove part of the remaining photoresist in the first local removal area, and retain the insulating material layer covered by the photoresist in the first local removal area to form the first planar portion 1051;

[0203] Step 17: Etch away the photoresist in the second local removal area, and continue etching the insulating material layer in the second local removal area to form the second planar portion 1052.

[0204] In this embodiment, the halftone mask, designed with different transmittance, allows for varying film thicknesses in different areas. Therefore, during the formation of the second insulating layer 105, the process involves applying photoresist, exposing with the halftone mask, developing, and etching, resulting in a thicker insulating material layer in the hole area, thus obtaining the second insulating layer 105. Using a halftone mask to obtain the second insulating layer does not increase the fabrication complexity of the display panel.

[0205] In another example, a second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101, including the following steps:

[0206] Step 21: An insulating material layer is formed on the side of the first electrode 104a away from the substrate 101, and the ratio of the dimension of the insulating material layer on the first electrode portion 1041 of the first electrode 104a along the thickness direction of the substrate 101 to the first distance L1 is not less than 0.8. In other words, the thickness of the insulating material layer at the via P is not less than 0.8.

[0207] Step 22: Form a photoresist layer on the insulating material layer;

[0208] Step 23: Exposure the photoresist layer using a first mask. The first mask includes a blocking area and a light-transmitting area. The blocking area corresponds to the first electrode 1041, and the light-transmitting area corresponds to the second electrode 1042. The first mask is a common mask, that is, a mask with different transmittance.

[0209] Step 24: The photoresist layer is developed to form a retention area and a removal area. The retention area corresponds to the first electrode portion 1041 and the removal area corresponds to the second electrode portion 1042.

[0210] Step 25: Clean the photoresist in the removal area and etch the insulating material layer in the removal area to form the second flat portion 1052 and the pixel opening 105a.

[0211] Step 25: Retain the photoresist in the reserved area to form the first planar portion 1051.

[0212] In this embodiment, the first mask is a regular mask that is not a halftone mask. Only the non-via area is exposed, which is the area where the second electrode part 1042 is located. This achieves etching only the non-via area to obtain the second insulating layer 105.

[0213] In yet another example, a second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101, including the following steps:

[0214] Step 31: A first insulating material layer is formed on the side of the first electrode portion 1041 of the first electrode 104a away from the substrate 101, and the ratio of the dimension of the first insulating material layer on the first electrode portion 1041 along the thickness direction of the substrate 101 to the first distance L1 is not less than 0.8, so as to form a first flat portion 1051.

[0215] Step 32: A second insulating material layer is formed on the side of the second electrode portion 1042 of the first electrode 104a away from the substrate 101, and the dimension of the second insulating material layer on the second electrode portion 1042 along the thickness direction of the substrate 101 is smaller than the dimension of the first insulating material layer on the first electrode portion 1041 along the thickness direction of the substrate 101, so as to form a second flat portion 1052.

[0216] In this embodiment, the second insulating layer 105 is fabricated in steps by forming a first flat portion 1051 on the first electrode portion 1041 and then forming a second flat portion 1052 on the second electrode portion 1042.

[0217] In yet another example, a second insulating layer 105 is formed on the side of the first electrode 104a away from the substrate 101, including the following steps:

[0218] Step 41: A first insulating material layer is formed on the side of the first electrode portion 1041 of the first electrode 104a away from the substrate 101.

[0219] Step 42: A third insulating material layer (i.e., a whole insulating material layer) is formed on the side of the first electrode portion 1041 away from the substrate 101 and the side of the second electrode portion 1042 away from the substrate 101 to form the first flat portion 1051 and the second flat portion 1052.

[0220] Step 43: Pixel openings 105a are patterned and etched on the third insulating material layer.

[0221] In one embodiment, the method further includes forming an isolation structure 401 on the side of the second insulating layer 105 away from the substrate 101, wherein the isolation structure 401 defines an isolation opening 401a.

[0222] In one embodiment, this application provides a display device, which includes the display panel described in any of the above-described display panel embodiments.

[0223] The display device can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display (e.g., odometer display), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0224] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0225] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0226] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate, Signal lines are disposed on one side of the substrate; A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via. A first electrode is disposed on the side of the first insulating layer away from the substrate. The orthographic projection of the first electrode on the first insulating layer covers the via. The first electrode includes a first electrode portion connected to the signal line portion. The orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via. A second insulating layer is disposed on the side of the first electrode away from the substrate, and the orthographic projection of the second insulating layer onto the first insulating layer covers the via. The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer close to the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.

8.

2. The display panel according to claim 1, characterized in that, The ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.

2.

3. The display panel according to claim 1, characterized in that, The first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second insulating layer further includes a second flat portion disposed on the side of the second electrode portion of the first electrode facing away from the substrate; The second flat portion has a second dimension H2 along the thickness direction of the substrate, and the second dimension H2 is smaller than the first dimension H1.

4. The display panel according to claim 3, characterized in that, The distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.

8.

5. The display panel according to claim 1, characterized in that, The display panel further includes an isolation structure disposed on the side of the second insulating layer away from the substrate. The orthographic projection of the isolation structure onto the first insulating layer covers the via and defines an isolation opening.

6. The display panel according to claim 4, characterized in that, The second insulating layer further includes a third flat portion, wherein the orthographic projection of the third flat portion on the substrate does not overlap with the orthographic projection of the first electrode on the substrate; The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, which is greater than the second dimension H2.

7. The display panel according to claim 6, characterized in that, The distance between the surface of the third flat portion away from the substrate and the surface of the substrate near the signal line is a fourth distance L4, which is equal to the third distance L3.

8. The display panel according to claim 1, characterized in that, The surface of the second insulating layer on the side away from the substrate has no step.

9. The display panel according to claim 1, characterized in that, The sidewall of the via is either a plane or a curved surface.

10. A display panel, characterized in that, include: substrate, Signal lines are disposed on one side of the substrate; A first insulating layer is disposed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via. A first electrode is disposed on the side of the first insulating layer away from the signal line. The orthographic projection of the first electrode on the first insulating layer covers the via. The first electrode includes a first electrode portion connected to the signal line portion. The orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via. A pixel definition layer is disposed on the side of the first electrode away from the substrate. The orthographic projection of the pixel definition layer on the first insulating layer covers the via and defines a pixel opening. A portion of the first electrode is exposed from the pixel opening. An isolation structure is disposed on the side of the pixel definition layer away from the substrate. The orthographic projection of the isolation structure on the first insulating layer covers the via and defines an isolation opening that communicates with the pixel opening. The pixel definition layer includes a first flat portion and a second flat portion that contact the first electrode portion of the first electrode. The orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the first electrode portion on the substrate. The dimension of the first flat portion along the thickness direction of the substrate is larger than the dimension of the second flat portion along the thickness direction of the substrate.

11. The display panel according to claim 10, characterized in that, The dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer near the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.

8.

12. The display panel according to claim 11, characterized in that, The ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.

2.

13. The display panel according to claim 10, characterized in that, The first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second flat portion contacts the second electrode portion of the first electrode; The second flat portion has a second dimension H2 along the thickness direction of the substrate. The second dimension H2 is greater than or equal to 3000 Å and less than or equal to 5000 Å.

14. The display panel according to claim 13, characterized in that, The distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.

8.

15. The display panel according to claim 14, characterized in that, The ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.

2.

16. The display panel according to claim 10, characterized in that, The surface of the isolation structure away from the substrate has no step.

17. The display panel according to claim 14, characterized in that, The pixel definition layer further includes a third flat portion, the orthographic projection of the third flat portion on the substrate not overlapping the orthographic projection of the first electrode on the substrate.

18. The display panel according to claim 17, characterized in that, The dimension of the third flat portion along the thickness direction of the substrate is a third dimension H3, which is greater than the second dimension H2.

19. The display panel according to claim 18, characterized in that, The distance between the surface of the third flat portion away from the substrate and the surface of the substrate near the signal line is a fourth distance L4, which is equal to the third distance L3.

20. The display panel according to claim 19, characterized in that, The pixel definition layer has no step on the side of the surface away from the substrate.

21. A method for manufacturing a display panel, characterized in that, The preparation method includes: Provide substrate; A signal line is formed on one side of the substrate; A first insulating layer is formed on one side of the substrate, and a portion of the first insulating layer is located on the side of the signal line away from the substrate. A via is formed in the first insulating layer, and a portion of the signal line is exposed through the via. A first electrode is formed on the side of the first insulating layer away from the substrate, wherein the orthographic projection of the first electrode on the first insulating layer covers the via, and the first electrode includes a first electrode portion connected to the signal line portion, and the orthographic projection of the first electrode portion on the first insulating layer covers the bottom wall of the via; A second insulating layer is formed on the side of the first electrode away from the substrate, wherein the orthographic projection of the second insulating layer onto the first insulating layer covers the via. The second insulating layer includes a first flat portion, the orthographic projection of the first flat portion on the substrate overlaps with the orthographic projection of the via on the substrate, the dimension of the first flat portion along the thickness direction of the substrate is a first dimension H1, the distance between the side surface of the first insulating layer close to the substrate and the side surface of the first insulating layer away from the substrate is a first distance L1, and the ratio of the first dimension H1 to the first distance L1 is not less than 0.

8.

22. The preparation method according to claim 21, characterized in that, The ratio of the first dimension H1 to the first distance L1 is greater than or equal to 0.8 and less than or equal to 1.

2.

23. The preparation method according to claim 21, characterized in that, The first electrode further includes a second electrode portion, the orthographic projection of the second electrode portion on the first insulating layer not overlapping with the via; the second insulating layer further includes a second flat portion disposed on the side of the second electrode portion of the first electrode facing away from the substrate; The second flat portion has a second dimension H2 along the thickness direction of the substrate, and the second dimension H2 is smaller than the first dimension H1.

24. The preparation method according to claim 23, characterized in that, The second dimension H2 is greater than or equal to 3000A and less than or equal to 5000A.

25. The preparation method according to claim 23, characterized in that, The distance between the side surface of the first flat portion away from the substrate and the side surface of the substrate near the signal line is a second distance L2, and the distance between the side surface of the second flat portion away from the substrate and the side surface of the substrate near the signal line is a third distance L3, and the ratio of the second distance L2 to the third distance L3 is not less than 0.

8.

26. The preparation method according to claim 25, characterized in that, The ratio of the second distance L2 to the third distance L3 is greater than or equal to 0.8 and less than or equal to 1.

2.

27. The preparation method according to claim 23, characterized in that, The formation of a second insulating layer on the side of the first electrode away from the substrate includes: An insulating material layer is formed on the side of the first electrode away from the substrate; and a photoresist layer is formed on the insulating material layer; The photoresist layer is exposed using a halftone mask, wherein the halftone mask includes a first region, a second region, and a third region; the transmittance of the first region is less than that of the second region; the transmittance of the second region is less than that of the third region; The photoresist layer is developed to form a first partial removal region, a second partial removal region, and a completely removed region, wherein the first partial removal region corresponds to the first region, the second partial removal region corresponds to the second region, and the completely removed region corresponds to the third region. The photoresist in the completely removed area is removed, a portion of the photoresist in the first partially removed area is removed, and a portion of the photoresist in the second partially removed area is removed, wherein the thickness of the remaining photoresist in the first partially removed area is greater than the thickness of the remaining photoresist in the second partially removed area. The insulating material layer exposed in the completely removed area is etched to form a pixel opening; Remove a portion of the remaining photoresist from the first local removal area, leaving the insulating material covered by the photoresist in the first local removal area to form the first flat portion; The photoresist in the second local removal area is etched away, and the insulating material layer in the second local removal area is etched to form the second planar portion.

28. The preparation method according to claim 23, characterized in that, The formation of a second insulating layer on the side of the first electrode away from the substrate includes: An insulating material layer is formed on the side of the first electrode away from the substrate, and the ratio of the dimension of the insulating material layer on the first electrode portion of the first electrode along the thickness direction of the substrate to the first distance L1 is not less than 0.8; A photoresist layer is formed on the insulating material layer; The photoresist layer is exposed using a first mask, wherein the first mask includes a blocking area and a light-transmitting area; the blocking area corresponds to the first electrode portion, and the light-transmitting area corresponds to the second electrode portion; The photoresist layer is developed to form a retention area and a removal area, wherein the retention area corresponds to the first electrode portion and the removal area corresponds to the second electrode portion; Remove the photoresist from the removal area and etch the insulating material layer in the removal area to form the second planar portion and pixel opening; The photoresist in the reserved area is retained to form the first flat portion.

29. The preparation method according to claim 23, characterized in that, The formation of a second insulating layer on the side of the first electrode away from the substrate includes: A first insulating material layer is formed on the side of the first electrode portion of the first electrode away from the substrate, and the ratio of the dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate to the first distance L1 is not less than 0.8, so as to form the first flat portion. A second insulating material layer is formed on the side of the second electrode portion of the first electrode that is away from the substrate, and the dimension of the second insulating material layer on the second electrode portion along the thickness direction of the substrate is smaller than the dimension of the first insulating material layer on the first electrode portion along the thickness direction of the substrate, so as to form the second flat portion.

30. A display device, characterized in that, Includes the display panel as described in any one of claims 1-20.

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