FPGA-based on-board file storage system and method

Abstract

The application relates to the technical field of spaceborne data storage, and discloses a spaceborne file storage system based on FPGA, which comprises an FPGA processing unit used for performing file information management, storage control, file indexing, parallel read-write operation and error correction coding; and a NandFlash storage unit; and a storage method applied to the system, which comprises the following steps: S1, initializing the system, and configuring the FPGA processing unit and the NandFlash storage unit; S2, allocating a physical block when a file is created and caching information in the FPGA; S3, performing multi-channel parallel writing on the NandFlash storage unit; S4, recording index information in a linked list module; S5, after receiving a stop instruction, writing file information into a NandFlash information table; and S6, reading a block in an index linked list and performing error correction and checking. The application improves the high-concurrency file operation performance through the FPGA parallel processing architecture, solves the efficiency bottleneck of the traditional CPU serial architecture, combines a three-module redundancy and a multi-level error correction mechanism, ensures high-reliable storage of data in a harsh environment, and overcomes the data integrity problem caused by hardware failure and cosmic ray interference.

Description

Technical Field

[0001] This invention relates to the field of spaceborne data storage technology, specifically to a spaceborne file storage system and method based on FPGA. Background Technology

[0002] Traditional file systems based on general-purpose processors (CPUs) primarily rely on a serial processing model. While this can meet basic data storage needs in ordinary scenarios, its performance becomes significantly insufficient when faced with large-scale, high-speed data processing tasks. This is especially true in spaceborne applications, where tasks requiring rapid, high-concurrency storage of telemetry and orbital data suffer. The CPU's single-task serial nature leads to a significant increase in data storage and access latency. The continuous growth in data volume further exacerbates this performance bottleneck.

[0003] Furthermore, existing technologies often employ simple parity checks or basic redundancy mechanisms to ensure data integrity. However, in complex spaceborne environments, such as under cosmic ray radiation and extreme temperature conditions, these mechanisms have limited error correction capabilities and struggle to cope with multi-bit errors or storage cell damage. Therefore, the data integrity of storage devices is difficult to guarantee under extreme environments.

[0004] Meanwhile, the limited write / erase life of NandFlash storage media places higher design requirements on file systems. Traditional wear leveling strategies lack real-time dynamic adjustment capabilities, leading to excessive wear in some areas and affecting storage reliability. Furthermore, file index management often employs simple linked lists or partitioned structures, which can easily cause storage fragmentation and linked list access latency when handling large files or high-frequency file operations, reducing the overall system efficiency.

[0005] Therefore, existing CPU-based file systems have significant limitations in handling high-concurrency tasks, ensuring storage reliability, and optimizing hardware resource utilization, making it difficult to meet the efficiency and stability requirements of spaceborne missions. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides an FPGA-based on-board file storage system and method, which solves the problems of traditional CPU-based file systems in terms of high-concurrency storage of large data, reliability assurance, and storage efficiency optimization.

[0007] To achieve the above objectives, the present invention provides the following technical solution: an FPGA-based onboard file storage system, comprising:

[0008] The FPGA processing unit is used to perform file information management, storage control, file indexing, parallel read and write operations, and error correction coding; the NandFlash storage unit is used to store file data and file information, and the NandFlash storage unit is divided into multiple physical blocks, each physical block including multiple pages;

[0009] The file linked list module is used to store the index relationship between file blocks and records the storage location of file data in each physical block through linked list pointers.

[0010] The error correction and redundancy module is used for error correction encoding, redundant storage, and fault recovery of file information and data;

[0011] The scheduling and control module is used to schedule parallel read and write operations of files and control the read and write order of data blocks based on priority.

[0012] The file information table management module is used to cache file information in the FPGA's internal RAM and store the file information in a specific area of ​​NandFlash according to the write strategy.

[0013] Preferably, the FPGA processing unit includes multiple independent read / write control units, which are used to perform parallel operations on different channels of the NandFlash. Each read / write control unit includes:

[0014] The data caching module is used to control the parallel read and write operations of multiple physical blocks;

[0015] The encoding and decoding module is used to perform error correction encoding on file data, generate check codes when writing data, and perform error detection and correction when reading data.

[0016] The Flash interface control module is used to realize communication between the FPGA and NandFlash, and to control the coordination of physical address mapping, page operations and data transmission.

[0017] Preferably, the NandFlash storage unit includes:

[0018] The file data storage area is used to store the actual data blocks of the file.

[0019] The file information storage area is used to store basic file information and index lists;

[0020] The three-mode redundancy area is used to redundantly store file information to ensure reliability;

[0021] The error correction and verification area is used to store verification codes to support data error correction and recovery.

[0022] Preferably, the file linked list module includes:

[0023] The file start pointer unit is used to record the address of the file's starting physical block.

[0024] Block index unit, used to record the address of the next physical block for each physical block to build a linked list;

[0025] The linked list maintenance unit is used to dynamically allocate physical blocks and update the linked list pointer when a file is created, reclaim the corresponding physical blocks and clear the linked list index when a file is deleted, and reallocate physical blocks and update the linked list when a file is moved.

[0026] Preferably, the error correction and redundancy module includes:

[0027] Triple redundancy storage unit is used to store file information as three redundant copies, which are stored in different physical blocks to prevent single block failure;

[0028] Error correction coding unit, used to perform error correction coding on file data before writing, generate check codes and append them to file data blocks;

[0029] An error detection unit is used to verify the checksum when reading data and detect errors in the data block;

[0030] The data recovery unit is used to recover damaged data blocks based on triple redundancy storage information and error correction verification results.

[0031] Preferably, the scheduling control module includes:

[0032] The task priority allocation unit is used to allocate storage resources based on real-time requirements and file operation priorities;

[0033] The parallel processing scheduling unit is used to schedule the FPGA parallel control unit to perform read and write operations on multiple channels;

[0034] The storage resource optimization unit is used to dynamically allocate storage space.

[0035] An FPGA-based on-board file storage method includes the following steps:

[0036] S1. Initialize the file storage system, including configuring the FPGA processing unit and the NandFlash storage unit;

[0037] S2. When creating a file, allocate physical blocks and cache file information in the FPGA's internal RAM;

[0038] S3. Write the file data in blocks to the NandFlash storage unit in parallel through multiple channels;

[0039] S4. Record the index information of file blocks in the linked list module to form a file linked list;

[0040] S5. After receiving the recording stop command, write the file information from the FPGA internal RAM to the NandFlash file information table and store it in a three-mode redundancy manner;

[0041] S6. During file reading, file blocks are read sequentially through the indexed linked list, and the read data is corrected and verified.

[0042] Preferably, the file reading in step S6 includes the following steps:

[0043] Locate the physical address of the starting block of the file in the file information table based on the file number;

[0044] The physical addresses of each data block in the file are obtained sequentially using a linked list structure;

[0045] Read data from multiple physical blocks in parallel;

[0046] Perform error correction and verification on the read data;

[0047] The file data is concatenated according to the linked list order until the reading is complete.

[0048] This invention provides an FPGA-based on-board file storage system and method. It offers the following advantages:

[0049] 1. By adopting a storage architecture based on FPGA parallel processing, multiple independent read / write control units and scheduling control modules are designed, which can simultaneously execute file read / write operations in multiple channels, achieving high-throughput data storage. Compared with the existing file systems based on CPU serial architecture, which suffer from bottleneck problems due to low single-task execution efficiency in big data processing scenarios, this invention solves the shortcomings of traditional systems in supporting high-concurrency file operations.

[0050] 2. This invention achieves highly reliable data storage in harsh environments by designing a triple-redundant storage and multi-level error correction coding mechanism, combined with a dynamic maintenance strategy for file linked list indexes. It achieves the technical effect of being able to recover data under various failure scenarios. Compared with the problem that single redundancy or simple verification mechanisms in the prior art are prone to data loss when storage devices fail, this invention solves the problem of data integrity loss caused by hardware damage or cosmic ray radiation. Attached Figure Description

[0051] Figure 1 This is a system framework diagram of the present invention;

[0052] Figure 2 This is a schematic diagram of the read / write control unit of the present invention;

[0053] Figure 3This is a schematic diagram of the NandFlash storage unit of the present invention;

[0054] Figure 4 This is a framework diagram of the file linked list module of the present invention;

[0055] Figure 5 This is a framework diagram of the error correction and redundancy module of the present invention;

[0056] Figure 6 This is a framework diagram of the scheduling and control module of the present invention;

[0057] Figure 7 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0058] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Please see the appendix Figure 1 This invention provides an FPGA-based onboard file storage system, comprising: an FPGA processing unit for performing file information management, storage control, file indexing, parallel read / write operations, and error correction coding; and a NandFlash storage unit for storing file data and file information, wherein the NandFlash storage unit is divided into multiple physical blocks, and each physical block includes multiple pages.

[0060] The file linked list module is used to store the index relationship between file blocks and records the storage location of file data in each physical block through linked list pointers.

[0061] The error correction and redundancy module is used for error correction encoding, redundant storage, and fault recovery of file information and data;

[0062] The scheduling and control module is used to schedule parallel read and write operations of files and control the read and write order of data blocks based on priority.

[0063] The file information table management module is used to cache file information in the FPGA's internal RAM and store the file information in a specific area of ​​NandFlash according to the write strategy.

[0064] Specifically, the modules in this invention cooperate with each other to complete the overall operation of the spaceborne file storage system. The modules have close interaction relationships, each capable of independently performing its function or collaboratively optimizing the overall system performance.

[0065] Generally, the coordination between modules is uniformly scheduled by the FPGA processing unit, which is mainly responsible for task allocation, data management, and fault tolerance. Other modules, such as the NandFlash storage unit, file list module, and error correction and redundancy module, mainly focus on efficient data storage and access, especially in spaceborne environments, emphasizing radiation resistance and high reliability. The file information table management module caches file information through the FPGA's internal RAM to improve read and write speeds and reduce frequent erasures and writes to the NandFlash.

[0066] In this embodiment, the FPGA processing unit performs file information management, storage control, file indexing, parallel read / write, and error correction coding through its internal logic resource allocation. The FPGA adopts a modular design, and the modules communicate with each other through on-chip interconnection.

[0067] Specifically, the FPGA processing unit includes multiple independent read / write control units, each responsible for the operation of one memory channel. Each read / write control unit is further subdivided into the following modules:

[0068] Data caching module: Used for temporary storage and management of file data. The data caching module employs a double-buffered design, where one buffer handles encoding operations while the other receives the next set of data during writing. This design ensures the continuity of the data stream.

[0069] The encoding / decoding module generates error correction codes and appends them to data blocks during data writing, and performs error detection and repair based on the verification information during reading. Generally, the error correction algorithm used is the Reed-Solomon code, with the specific formula as follows:

[0070] C(x) = M(x)·G(x)

[0071] Where C(x) is the generated check code, M(x) is the polynomial representation of the input data block, and G(x) is the generator polynomial. The generator polynomial of the Reed-Solomon code can be expressed as:

[0072] G(x)=(x+α 1 (x+α) 2 )…(x+α 2t )

[0073] Where α is a primitive element in a finite field, and t is the maximum number of erroneous symbols that can be corrected.

[0074] The Flash interface control module is responsible for the physical address translation and operation control of NandFlash storage units. It achieves fast mapping between logical and physical addresses through an address mapping table. Alternatively, physical addresses are managed using a linked list structure for dynamic allocation and fast lookup.

[0075] In one possible implementation, each read / write control unit of the FPGA is connected to a different NandFlash memory cell via a dedicated hardware channel. During file writing, multiple channels can operate in parallel, significantly improving file storage speed.

[0076] In this embodiment, the NandFlash storage unit is divided into multiple physical blocks, and each block is further divided into pages. Each page is 8640 bytes in size, of which 8192 bytes are used to store file data and 448 bytes are used to store linked list index information and checksum.

[0077] As an option, NandFlash can be divided into the following parts:

[0078] File data storage area: Primarily used to store actual file data. Each file data block is stored according to a fixed block size, and there is no overlap between data blocks.

[0079] File information storage area: Used to store file metadata, including file number, file size, starting address, etc.

[0080] Triple redundancy area: Used to store redundant copies of file information. Generally, triple redundancy copies are stored in different physical blocks to avoid the impact of single points of failure.

[0081] Verification area: Used to store checksums and other auxiliary information. The checksum is generated by the FPGA's encoding module and used for subsequent error detection and repair.

[0082] In some embodiments, to further improve storage efficiency, the physical block allocation of NandFlash follows a dynamic adjustment strategy. Specifically, when the number of times a block is used approaches its erase / write limit, the system automatically marks it as a read-only block and reallocates a new storage block through a linked list module.

[0083] The main function of the file linked list module is to maintain the logical relationship between file blocks and provide fast file location functionality. In this embodiment, the file linked list module records the index information of each file block through a linked list structure.

[0084] Specifically, each linked list node includes the following:

[0085] Current physical block address.

[0086] Address of the next physical block. This field is empty if the file ends.

[0087] Verification information is used to verify the integrity of linked list nodes.

[0088] During file writing, linked list nodes are dynamically created as file blocks are added. The FPGA's linked list maintenance unit updates the linked list information after each file write or deletion operation.

[0089] As one possible implementation, the linked list module also supports skip list structures to accelerate file searches. For example, when reading large files, the system can quickly locate the target block using a skip list, thereby reducing linear search time.

[0090] In this embodiment, the error correction and redundancy module is mainly used to ensure data reliability, especially in a spaceborne environment. The module's main functions include error correction coding, error detection, and data recovery.

[0091] During file writing, the FPGA generates a checksum using its encoding module and appends it to the data block. Typically, the checksum length is 10% of the data block length to balance storage overhead and error correction capability.

[0092] During file reading, the error correction module parses the checksum. If an error is detected, the system will recover in the following two ways:

[0093] If it is a single-bit error, it can be repaired directly using the checksum; if it is a multi-bit error, it can be recovered using redundant copies.

[0094] In one possible implementation, the error correction module also supports a tiered recovery mechanism. That is, it first attempts to correct the error using the checksum; if that fails, it switches to a redundant replica recovery mode.

[0095] In this embodiment, the scheduling control module is responsible for task priority allocation and multi-channel scheduling. Internally, the module uses a FIFO queue to store tasks and adjusts their priorities based on real-time requirements.

[0096] During file write operations, the system prioritizes tasks with higher real-time requirements. For example, real-time recording of satellite observation data will be assigned a higher scheduling priority. During file read operations, the scheduling module strives to balance read latency with storage channel utilization.

[0097] In this embodiment, the file information table management module mainly caches file information through the FPGA's internal RAM to reduce frequent access to the NandFlash.

[0098] Specifically, when a file is created, its information is first stored in RAM. Only when a recording stop instruction is triggered will the cached file information be written to NandFlash. Simultaneously, the module dynamically adjusts the write strategy based on the file's storage state. For example, metadata from multiple small files may be merged and written together to reduce the frequency of write operations.

[0099] As an option, the file information table also supports version control. When file information is updated, the system retains an older version as a backup to address potential data errors.

[0100] Please see the appendix Figure 2 The FPGA processing unit includes multiple independent read / write control units, which are used to perform parallel operations on different channels of the NandFlash. Each read / write control unit includes:

[0101] The data caching module is used to control the parallel read and write operations of multiple physical blocks;

[0102] The encoding and decoding module is used to perform error correction encoding on file data, generate check codes when writing data, and perform error detection and correction when reading data.

[0103] The Flash interface control module is used to realize communication between the FPGA and NandFlash, and to control the coordination of physical address mapping, page operations and data transmission.

[0104] Specifically, in this invention, the modules within the FPGA processing unit are interconnected through on-chip FPGA resources, and the NandFlash storage units are uniformly managed through scheduling logic. The data caching module is primarily responsible for temporary data storage and parallel management; the encoding / decoding module provides efficient error correction coding support; and the Flash interface control module is used for NandFlash physical address mapping and page control. These three modules work together to achieve a high-throughput and high-reliability storage architecture.

[0105] In this embodiment, the data caching module is designed to provide buffering support during data transmission. Its main functions include temporarily storing external input data, maintaining the continuity of the data stream, and coordinating multi-channel parallel operations. Typically, the data caching module employs a double-buffered structure. This design allows data to be written or read in one buffer while the other buffer is used to receive or send the next set of data.

[0106] Specifically, the data caching module works in conjunction with the FPGA's on-chip RAM. External input data is first written to the caching module and then transferred to RAM after verification. In RAM, the data is divided into multiple physical blocks, which are written to the NandFlash by the Flash interface control module according to the logical address mapping table.

[0107] As an alternative, the data caching module can dynamically adjust the buffer capacity based on the size of the file data blocks. For example, when processing large data files, the buffer capacity can be appropriately increased to reduce the number of data transfer fragments; while when processing small data streams, the buffer capacity can be reduced to save on-chip RAM resources.

[0108] In one possible implementation, the data caching module supports multi-task operation scheduling. For example, in a high-concurrency write scenario, the caching module can prioritize processing high-priority data streams based on the real-time requirements of the tasks, while low-priority tasks are temporarily stored in a queue and processed after the high-priority tasks are completed.

[0109] In this embodiment, the encoding / decoding module is mainly used for data error correction. Its functions include generating checksums when writing data and performing error detection and repair when reading data. Generally, the encoding / decoding module uses the Reed-Solomon code algorithm, which can effectively handle single-bit and multi-bit errors.

[0110] During the data writing process, the encoding / decoding module represents the input data block in polynomial form and generates the corresponding checksum. The checksum generation process can be represented as follows:

[0111] C(x) = M(x)·G(x)

[0112] Where C(x) represents the generated encoded data block, M(x) is the polynomial representation of the original data block, and G(x) is the generator polynomial. One possible form of the generator polynomial is:

[0113] G(x)=(x+α 1 (x+α) 2 )…(x+α 2t )

[0114] Here, α is the finite field GF(2 m In the original equation, t represents the maximum number of error symbols that can be corrected. When reading data, the encoding / decoding module detects errors by calculating the remainder polynomial of the received data:

[0115] R(x)=C ′ (x)mod G(x)

[0116] If the remainder R(x) = 0, it means that there is no error in the data block; otherwise, the module locates the error sign based on the remainder polynomial and repairs the error through reverse operation.

[0117] In some embodiments, the encoding and decoding modules also support a layered error correction strategy. When there are few data errors, the module prioritizes using simple parity check codes or Hamming codes for fast repair; when there are many errors, it switches to more complex Reed-Solomon codes for deep repair.

[0118] In this embodiment, the Flash interface control module is responsible for communication between the FPGA and the NandFlash memory cells. Its main functions include physical address mapping, page operation control, and coordination of multi-channel data transmission. Generally, the Flash interface control module translates logical addresses into NandFlash physical addresses using an address mapping table and performs write or read operations on data blocks.

[0119] The address mapping table is constructed based on the relationship between the logical number of the file block and the physical block of NandFlash. For example, each logical address consists of the following three parts:

[0120] Logical block number: corresponds to the physical block in NandFlash;

[0121] Page number: Indicates the specific page within a physical block;

[0122] Offset address: Indicates the specific location of data within the page.

[0123] In one possible implementation, the Flash interface control module supports dynamic address mapping. When a physical block fails or approaches its erase / write lifespan, the module automatically updates the address mapping table, reallocating logical addresses to other free physical blocks. Furthermore, the module supports a jump mechanism, allowing data from a single logical block to be distributed across multiple physical blocks, achieving contiguous storage through linked list indexing.

[0124] As an alternative, the Flash interface control module also integrates page operation optimization features. For example, in high-frequency write scenarios, the module will prioritize writing to idle pages to avoid erase / write operations; while in low-frequency write scenarios, it will use overwrite to reduce page fragmentation.

[0125] In this embodiment, the data caching module, encoding / decoding module, and Flash interface control module collaborate through the FPGA's internal logic resources. During the file data writing process, the data flow path is as follows:

[0126] The data caching module receives external input data and stores it in blocks in the on-chip RAM;

[0127] The encoding and decoding module performs error correction encoding on each data block, generates a checksum, and appends it to the end of the data block.

[0128] The Flash interface control module maps the encoded data blocks to the physical address of the NandFlash and writes them in parallel through multiple channels.

[0129] During the file data reading process, the data flow path proceeds in reverse:

[0130] The Flash interface control module extracts data blocks from the NandFlash according to the logical address;

[0131] The encoding and decoding module verifies the extracted data blocks, corrects errors, and outputs the data that has passed the verification.

[0132] The data caching module temporarily stores the repaired data blocks and eventually passes them to the external interface.

[0133] Please see the appendix Figure 3 The NandFlash storage unit includes:

[0134] The file data storage area is used to store the actual data blocks of the file.

[0135] The file information storage area is used to store basic file information and index lists;

[0136] The three-mode redundancy area is used to redundantly store file information to ensure reliability;

[0137] The error correction and verification area is used to store verification codes to support data error correction and recovery.

[0138] Specifically, NandFlash storage units are typically managed in physical blocks, each 1MB in size, further divided into multiple pages. Each page is 8640 bytes in size, with most of the space used for actual data storage and the remainder for storing linked list indexes and verification information. This hierarchical design simplifies storage management and improves system reliability and efficiency.

[0139] In this embodiment, the file data storage area is used to store the actual data content of the file. To improve storage efficiency and read performance, this area is allocated in units of physical blocks, with each block containing a fixed number of pages.

[0140] Specifically, file data is stored in blocks, each 1MB in size, with each page measuring 8640 bytes. The first 8192 bytes of the file data storage area are used to store the actual file data, while the remaining 448 bytes are used to store file linked list information and checksums. This design maximizes the use of page capacity while providing the necessary support for file indexing and data verification.

[0141] As one possible implementation, when the file size exceeds one physical block, the file data storage area uses a linked list structure to divide the file into multiple physical blocks. The linked list index information is stored in a 448-byte area of ​​each page, recording the physical address of the next page corresponding to the current page. In this way, during file reading, the system can quickly locate and sequentially read all data blocks of the file.

[0142] In some embodiments, the file data storage area also supports dynamic allocation and reclamation. When a file is deleted, its corresponding physical block is marked as free and added to the available block pool for use by subsequent file storage tasks.

[0143] In this embodiment, the file information storage area is used to store the file's metadata and index list. This area reserves a specific number of physical blocks specifically for managing file information to ensure file reliability and fast location.

[0144] Specifically, each physical block in the file information storage area contains 128 pages, with each page storing complete information about a file. The file information includes, but is not limited to:

[0145] File Number: A unique identifier for the file;

[0146] Creation time: Records the file's creation timestamp;

[0147] File size: Indicates the total size of the file;

[0148] Starting address: The address of the first physical block of file data;

[0149] Indexed linked list: A linked list of information pointing to file data blocks.

[0150] As an alternative, to improve file access speed, data in the file information storage area is first cached in the FPGA's internal RAM when a file is created or modified. Only when the file operation is complete is this information written to the NandFlash in batches, thereby reducing the need for erase and write operations on the Flash.

[0151] In one possible implementation, the file information storage area also supports multi-version management. For example, when file information is updated, the system retains the old version as a backup to prevent information loss due to update failure.

[0152] In this embodiment, the triple redundancy area is dedicated to redundant storage of file information to improve the system's fault tolerance. This area stores file information as three copies and writes them to different physical blocks, ensuring that data can still be recovered from the remaining two copies even if a single physical block fails.

[0153] Specifically, the data storage mechanism in the triple redundancy zone is as follows:

[0154] When writing file information, the system simultaneously writes three redundant copies of the information.

[0155] When reading file information, the system will read three copies simultaneously and select the matching version by comparison;

[0156] If an error occurs in one of the copies, the system will repair the data based on the other two copies and rewrite the repaired data to the faulty location.

[0157] As one possible implementation, the triple redundancy area and the error correction and verification area work together to further improve data reliability. For example, when an error in a copy cannot be corrected through simple comparison, the system will use the verification information in the error correction and verification area to perform a higher level of error correction.

[0158] In this embodiment, the error correction and verification area is used to store the verification information corresponding to each data block to support error detection and correction operations. Generally, the verification information stored in this area is generated by the FPGA's encoding and decoding module, including the checksum of the file data and the checksum of the file information.

[0159] Specifically, the process of generating and using the verification information in the error correction verification area is as follows:

[0160] During the data writing process, the FPGA's encoding module represents the data block in polynomial form and generates a checksum. For example, for the input data block M(x), the generated checksum C(x) can be expressed as:

[0161] C(x) = M(x)·G(x)

[0162] G(x) is the generator polynomial, which is usually generated by Reed-Solomon codes or Hamming codes.

[0163] During data reading, the FPGA's decoding module detects errors by calculating the remainder polynomial R(x) of the received data block. If R(x) ≠ 0, it indicates an error in the data block. The module locates the error sign based on the remainder polynomial and corrects the error.

[0164] The error correction and verification area is designed to account for the high single-bit error rate that may occur in spaceborne environments. For example, in some high-radiation scenarios, the error correction and verification area can detect and correct more than 50% of multi-bit errors, thereby significantly improving the reliability of the system.

[0165] In this embodiment, the functional areas of the NandFlash storage unit cooperate through the internal logic resources of the FPGA. During the storage and access of file data, the roles of each functional area are as follows:

[0166] The file data storage area is responsible for storing the actual data blocks;

[0167] The file information storage area provides file metadata and fast location support;

[0168] The three-mode redundancy zone ensures the reliability of file information through redundant storage and repair mechanisms;

[0169] The error correction and verification area uses check codes to detect and repair errors in file data and file information.

[0170] During file reading operations, the system first obtains the file's metadata from the file information storage area, then locates the data blocks using linked list indexes, and reads the data sequentially from the file data storage area. During the reading process, the triple redundancy area and the error correction and verification area work together to ensure the integrity of the read data.

[0171] Please see the appendix Figure 4 The file linked list module includes:

[0172] The file start pointer unit is used to record the address of the file's starting physical block.

[0173] Block index unit, used to record the address of the next physical block for each physical block to build a linked list;

[0174] The linked list maintenance unit is used to dynamically allocate physical blocks and update the linked list pointer when a file is created, reclaim the corresponding physical blocks and clear the linked list index when a file is deleted, and reallocate physical blocks and update the linked list when a file is moved.

[0175] Specifically, this invention records the relationships between file data blocks using a linked list. The file linked list module enables efficient file storage and access, and provides the ability to dynamically allocate, delete, and move files.

[0176] Generally, the file linked list module works collaboratively through the file start pointer unit, block index unit, and linked list maintenance unit to dynamically manage file creation, reading, deletion, and movement. During file creation, the linked list module dynamically allocates physical blocks for the file and records the logical order between data blocks using linked list pointers. When reading a file, the linked list module sequentially searches for the start block and the positions of subsequent data blocks until the end of the file. Simultaneously, when a file is deleted or moved, the module updates the linked list pointers to ensure data consistency.

[0177] In this embodiment, the file start pointer unit is used to record the address of the starting physical block of each file. The start pointer is the entry point of the file linked list, stored in the file information storage area, and is used to quickly locate the first data block of the file.

[0178] Specifically, when a file is created, the file start pointer unit allocates a physical block address from the free physical block pool as the file's starting address. This address is stored in the corresponding record in the file information storage area and serves as the first node in the linked list for subsequent file storage and retrieval operations.

[0179] During file reading, the system first extracts the starting address of the file from the file information storage area. Using this address, the system can directly access the first physical block of the file and then gradually retrieve subsequent data blocks through the linked list module.

[0180] As one possible implementation, the file start pointer unit can also support fast file location. For example, in scenarios storing a large number of files, the start pointer can accelerate the file location process through hash table indexing or a two-level skip list, thereby reducing file search time.

[0181] In this embodiment, the block index unit is used to record the address of the next physical block for each physical block, in order to construct a linked list. In this way, the system can organize the data blocks of a file into a logical linked list, thereby supporting the block storage and sequential reading of files.

[0182] Specifically, the index information of the block index unit is stored in the linked list area of ​​each physical block (the last 448 bytes of each page), and its content includes:

[0183] The address of the current physical block; the address of the next physical block; the checksum of the data block (used to verify data integrity).

[0184] During file writing, the block index unit updates the linked list information after each data block of the file is written. For example, when the file writes the second physical block, the block index unit updates the "next physical block address" field of the first physical block to the address of the second physical block; when the file writes the third physical block, the same process continues to update the linked list.

[0185] During file reading, the linked list structure of the block index units enables the system to read the file's data blocks sequentially in logical order. The start pointer provides the address of the first physical block of the file, while the block index units are responsible for locating the addresses of subsequent data blocks until the end of the linked list (the end-of-file marker).

[0186] As an alternative, block index units can also support skip list structures to optimize access efficiency for large files. For example, in large file storage scenarios, block indexes can introduce skip list mechanisms, setting a skip index node every few physical blocks to reduce the performance overhead of linear lookups.

[0187] In this embodiment, the linked list maintenance unit is responsible for dynamically maintaining the linked list structure during file creation, deletion, and movement, ensuring the integrity and consistency of the linked list. Its functions include dynamically allocating physical blocks, clearing linked list indexes, and updating linked list pointers.

[0188] Specifically, the working mechanism of the linked list maintenance unit is as follows, under different file operation scenarios:

[0189] File creation: During file creation, the linked list maintenance unit allocates sufficient physical blocks from the free physical block pool and constructs the linked list sequentially according to the order in which the file data is written. For example, assuming a file needs to be stored in three physical blocks, the linked list maintenance unit will:

[0190] Allocate the first physical block and record it as the starting address;

[0191] Allocate the second physical block and update the "next physical block address" field of the first physical block to the address of the second physical block;

[0192] Allocate the third physical block and update the "next physical block address" field of the second physical block to the address of the third physical block;

[0193] Write the "end of file" flag in the third physical block.

[0194] File Deletion: When a file is deleted, the linked list maintenance unit reclaims all physical blocks corresponding to the file and clears the linked list index. For example, when a user requests to delete a file, the module retrieves the starting address of the file from the file information storage area, releases all physical blocks of the file one by one through the linked list index, and marks its status as free.

[0195] File movement: During file movement, the linked list maintenance unit reallocates the file's physical blocks and updates the linked list structure. For example, when a file needs to be moved from its current storage area to another area, the module will:

[0196] Allocate a new physical block in the target storage area; copy the data of each node in the original linked list to the new physical block; update the starting pointer in the file information storage area; clear the old linked list and release its physical blocks.

[0197] As one possible implementation, the linked list maintenance unit can also support linked list defragmentation. Over long-term use, linked lists may experience physical block fragmentation due to file creation and deletion. The linked list maintenance unit can periodically defragment the linked list, rearranging scattered data blocks into contiguous physical blocks, thereby improving storage efficiency and access speed.

[0198] In this embodiment, the three units of the file linked list module work together, respectively responsible for managing the file's starting address, indexing data blocks, and dynamically maintaining the linked list. During file operations, the file linked list module works closely with other system modules (such as the FPGA processing unit and the NandFlash storage unit) to complete the storage and management of the file.

[0199] For example, in a file write operation:

[0200] The file start pointer unit allocates the starting physical block for the file; the block index unit records the linked list relationship of each data block; the linked list maintenance unit dynamically updates the linked list pointer to ensure the integrity of the linked list structure.

[0201] In file reading operations:

[0202] The system quickly locates the first physical block of the file using the file start pointer unit; the block index unit obtains the addresses of subsequent data blocks sequentially through a linked list; and the data blocks are read and transmitted to the outside in turn.

[0203] Please see the appendix Figure 5 The error correction and redundancy module includes:

[0204] Triple redundancy storage unit is used to store file information as three redundant copies, which are stored in different physical blocks to prevent single block failure;

[0205] Error correction coding unit, used to perform error correction coding on file data before writing, generate check codes and append them to file data blocks;

[0206] An error detection unit is used to verify the checksum when reading data and detect errors in the data block;

[0207] The data recovery unit is used to recover damaged data blocks based on triple redundancy storage information and error correction verification results.

[0208] Specifically, in general, error correction and redundancy modules achieve data protection by combining hardware and algorithms. Triple redundancy storage units provide basic fault tolerance through a multi-copy mechanism; error correction coding units generate checksums based on algorithms to support error detection and repair; error detection units monitor data integrity in real time; and data recovery units recover data using redundancy and error correction information when errors occur.

[0209] In this embodiment, the triple redundancy storage unit is used to store file information as three copies, and these three copies are stored in different physical blocks to prevent data loss due to failure of a single physical block.

[0210] Specifically, during the file writing process, the triple-redundant storage unit stores copies of the same file information on three independent physical blocks. These physical blocks are typically distributed across different storage areas to minimize the impact of hardware failures on the data. For example, the starting address of the file information is in the first physical block, copy one is stored in the second physical block, and copy two is stored in the third physical block.

[0211] When reading file information, the system simultaneously extracts copies from these three physical blocks and performs consistency checks on them. If a copy is found to be inconsistent with the other two, the system automatically selects the two consistent copies as the correct data and updates the incorrect copy.

[0212] In one possible implementation, the triple-modular redundancy storage unit also supports a dynamic redundancy repair mechanism. During system operation, if a data error is detected in a physical block and the error is successfully repaired, the triple-modular redundancy storage unit will automatically regenerate the copy and write it into a new free block, thereby ensuring that the three copies always remain synchronized.

[0213] In this embodiment, the error correction coding unit is used to perform error correction coding on file data before it is written. This unit generates a checksum and appends it to the file data block, thereby providing support for subsequent data verification and recovery.

[0214] Specifically, the error-correcting coding unit employs Reed-Solomon codes or other efficient error-correcting algorithms. The file data block is treated as a polynomial M(x) over a finite field, and a check code C(x) is generated by multiplying it with the generator polynomial G(x):

[0215] C(x) = M(x)·G(x)

[0216] Where: M(x) is the polynomial representation of the file data block; G(x) is the generator polynomial, usually in the following form:

[0217] G(x)=(x+α 1 (x+α) 2 )…(x+α 2t )

[0218] α is a primitive element in a finite field, and t is the maximum number of erroneous symbols that can be corrected.

[0219] In some embodiments, the error correction coding unit dynamically adjusts the parameter t of the generator polynomial to adapt to different data protection requirements. For example, in a high-radiation environment, a larger t value can be selected to enhance error correction capability; while in a low-interference environment, a smaller t value can be selected to reduce storage overhead.

[0220] In this embodiment, the error detection unit verifies the checksum during file data reading to detect potential errors in the data block. The error detection unit compares the received file data block with its checksum to determine whether the data contains errors.

[0221] Specifically, the error detection unit detects errors by calculating the remainder polynomial R(x) of the received data block:

[0222] R(x)=C ′ (x)mod G(x)

[0223] Where: C ′ G(x) is the polynomial corresponding to the received data block containing errors; G(x) is the generator polynomial.

[0224] If the remainder R(x) = 0, it means that there is no error in the data block; if R(x) ≠ 0, it means that there is an error in the data block, and the remainder polynomial R(x) can be used to locate the error symbol.

[0225] In one possible implementation, the error detection unit also supports error level assessment. When an error occurs, the unit categorizes it based on its type and quantity, triggering corresponding error correction or recovery procedures. For example:

[0226] If a single-bit error is detected, the error correction process is triggered directly.

[0227] If a multi-bit error is detected, data recovery is performed using a redundancy mechanism.

[0228] In this embodiment, the data recovery unit is used to recover data based on triple-modulus redundancy storage information and error correction verification results when data is corrupted. The data recovery unit is an important guarantee for ensuring data integrity, and its main function is to recover lost or damaged content when file data or file information is physically damaged or subjected to radiation interference.

[0229] Specifically, when the error detection unit detects an error in a data block, the data recovery unit will process it according to the following steps:

[0230] Error correction and recovery: If the error detection unit reports a single-bit or multi-bit error and the checksum can be used to repair it, the data recovery unit will directly repair the data block using an error correction algorithm. For example, the error symbol can be located and the corresponding bit can be repaired using the remainder polynomial R(x).

[0231] Redundancy recovery: If the error is severe and cannot be repaired through error correction verification, the data recovery unit will switch to redundancy mode and extract a consistent copy from the triple-redundant storage unit as replacement data.

[0232] Dynamic update: After data recovery is completed, the data recovery unit will regenerate the checksum and write the repaired data block and checksum back to storage.

[0233] In one possible implementation, the data recovery unit also supports real-time monitoring and proactive recovery mechanisms. For example, when the system is idle, the data recovery unit periodically scans the data blocks in storage and pre-recovers data blocks with hidden errors that have not yet triggered read requests, in order to reduce data recovery latency in future operations.

[0234] In this embodiment, the various units of the error correction and redundancy module work together to form a complete data protection process: during the data writing process, the error correction coding unit generates a check code and stores it in the error correction check area, and the three-modulus redundancy storage unit generates three redundant copies at the same time.

[0235] During the data reading process, the error detection unit verifies the checksum. If an error is found, the data recovery unit is triggered. The data recovery unit repairs the erroneous data using the checksum or redundant information and provides the repaired data to the calling program.

[0236] Please see the appendix Figure 6 The scheduling and control module includes:

[0237] The task priority allocation unit is used to allocate storage resources based on real-time requirements and file operation priorities;

[0238] The parallel processing scheduling unit is used to schedule the FPGA parallel control unit to perform read and write operations on multiple channels;

[0239] The storage resource optimization unit is used to dynamically allocate storage space.

[0240] Specifically, in this embodiment, the task priority allocation unit is used to allocate system resources according to the real-time requirements and priority of file operations, so as to ensure that important tasks can be executed first, thereby improving the overall performance and responsiveness of the system.

[0241] Specifically, the task priority allocation unit divides file operation tasks into different priorities, for example:

[0242] High-priority tasks include data writing tasks with high real-time requirements, such as recording satellite observation data;

[0243] Medium priority tasks: These include file reading operations, such as reading data files for transmission or processing;

[0244] Low-priority tasks include background file operations such as data backup, file information updates, or garbage collection.

[0245] During scheduling, the task priority allocation unit dynamically adjusts task priorities based on task type and real-time requirements. For example, when a high-priority data write task arrives, the system pauses the currently executing low-priority task and allocates storage resources preferentially to the high-priority task. After the high-priority task completes, the low-priority task resumes execution.

[0246] As one possible implementation, the task priority allocation unit uses a time-slice-based scheduling algorithm, where each task is allocated a certain time slice, and the task's priority determines how frequently it receives a time slice. For example:

[0247] High-priority tasks receive 50% of the time slice, medium-priority tasks receive 30%, and low-priority tasks receive 20%.

[0248] When the system is idle, low-priority tasks can monopolize time slices to improve storage utilization.

[0249] In this embodiment, the parallel processing scheduling unit coordinates the multi-channel control unit of the FPGA to achieve parallel read and write operations on multiple file blocks. By fully utilizing the hardware parallel processing capabilities of the FPGA, the scheduling unit significantly improves the system's data throughput and storage efficiency.

[0250] Specifically, the parallel processing scheduling unit implements parallel read and write operations through the following steps:

[0251] Task decomposition: File operation tasks are divided into multiple subtasks, each corresponding to the read / write operation of a physical block; Channel allocation: Subtasks are allocated to independent control units of the FPGA, with each control unit responsible for the read / write of a physical block; Resource monitoring: The resource usage of each channel is monitored in real time, and the task allocation strategy is dynamically adjusted to avoid channel overload or resource waste.

[0252] Alternatively, the parallel processing scheduling unit can optimize the allocation of read and write operations based on the file size and storage location. For example:

[0253] For large files, the scheduling unit divides the task into multiple subtasks and assigns these subtasks to different channels to achieve parallel writing;

[0254] For small files, the scheduling unit can merge the operations of multiple small files and batch allocate them to the same channel to reduce switching overhead.

[0255] In one possible implementation, the parallel processing scheduling unit also supports dynamic load balancing. For example, when the load on a certain channel is too high, the scheduling unit will automatically transfer some tasks to other idle channels to balance resource usage and avoid performance bottlenecks.

[0256] In this embodiment, the storage resource optimization unit is responsible for dynamically allocating storage space to improve system storage efficiency and device lifespan. This unit optimizes the allocation strategy of physical blocks and pages by combining task priorities and the current state of the storage space.

[0257] Specifically, the storage resource optimization unit achieves resource optimization in the following ways:

[0258] Dynamic block allocation: Based on the file size and write frequency, suitable free blocks are selected from the physical block pool for allocation. For example:

[0259] For high-frequency write tasks, physical blocks with fewer erase / write cycles should be selected first to reduce wear.

[0260] For low-frequency write tasks, physical blocks closer to the current task are selected first to improve read-write continuity.

[0261] Wear leveling: The storage resource optimization unit periodically counts the number of erases and writes for each physical block and balances the usage frequency of different physical blocks through a migration mechanism. For example:

[0262] If the number of erase / write cycles for a physical block is close to its usage limit, the system will migrate its contents to other free blocks and mark that block as a low-priority block.

[0263] Defragmentation: During file creation and deletion, storage space may become fragmented. The storage resource optimization unit improves storage efficiency by reorganizing linked lists and reallocating physical blocks, merging scattered storage spaces into contiguous blocks.

[0264] As an option, the storage resource optimization unit also supports tiered management of hot and cold data. For example:

[0265] For cold data that has not been accessed for a long time, migrate it to a low-priority block in the storage area;

[0266] For frequently accessed hot data, it is prioritized to be allocated to high-performance storage areas to speed up access.

[0267] In this embodiment, the three units of the scheduling and control module cooperate with each other to ensure that file operation tasks can be executed in an efficient and stable manner:

[0268] The task priority allocation unit is responsible for allocating resources and determining the execution order of tasks;

[0269] The parallel processing scheduling unit allocates operations to different channels according to the priority of tasks, thereby realizing the parallel processing of multiple tasks;

[0270] The storage resource optimization unit dynamically adjusts the storage space allocation strategy to ensure efficient utilization and long-term reliability of storage devices.

[0271] For example, in high-concurrency file writing scenarios:

[0272] The task priority allocation unit prioritizes high-priority write tasks based on real-time requirements.

[0273] The parallel processing scheduling unit decomposes the write task into multiple subtasks and allocates them to different channels for parallel execution;

[0274] The storage resource optimization unit selects a suitable storage location for each subtask based on the status of the physical blocks.

[0275] Please see the appendix Figure 7 An FPGA-based on-board file storage method includes the following steps:

[0276] S1. Initialize the file storage system, including configuring the FPGA processing unit and the NandFlash storage unit;

[0277] S2. When creating a file, allocate physical blocks and cache file information in the FPGA's internal RAM;

[0278] S3. Write the file data in blocks to the NandFlash storage unit in parallel through multiple channels;

[0279] S4. Record the index information of file blocks in the linked list module to form a file linked list;

[0280] S5. After receiving the recording stop command, write the file information from the FPGA internal RAM to the NandFlash file information table and store it in a three-mode redundancy manner;

[0281] S6. During file reading, file blocks are read sequentially through the indexed linked list, and the read data is corrected and verified.

[0282] The file reading process in step S6 includes the following steps:

[0283] Locate the physical address of the starting block of the file in the file information table based on the file number;

[0284] The physical addresses of each data block in the file are obtained sequentially using a linked list structure;

[0285] Read data from multiple physical blocks in parallel;

[0286] Perform error correction and verification on the read data;

[0287] The file data is concatenated according to the linked list order until the reading is complete.

[0288] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based onboard file storage system, characterized in that, include: The FPGA processing unit is used to perform file information management, storage control, file indexing, parallel read and write operations, and error correction coding. NandFlash storage units are used to store file data and file information. The NandFlash storage units are divided into multiple physical blocks, and each physical block includes multiple pages. The file linked list module is used to store the index relationship between file blocks and records the storage location of file data in each physical block through linked list pointers. The error correction and redundancy module is used for error correction encoding, redundant storage, and fault recovery of file information and data; The scheduling and control module is used to schedule parallel read and write operations of files and control the read and write order of data blocks based on priority. The file information table management module is used to cache file information in the FPGA's internal RAM and store the file information in a specific area of ​​NandFlash according to the write strategy. The FPGA processing unit includes multiple independent read / write control units, which are used for parallel operations on different channels of the NandFlash. Each read / write control unit includes: The data caching module is used to control the parallel read and write operations of multiple physical blocks; The encoding and decoding module is used to perform error correction encoding on file data, generate check codes when writing data, and perform error detection and correction when reading data. The Flash interface control module is used to realize communication between the FPGA and NandFlash, and to control the coordination of physical address mapping, page operations and data transmission. The NandFlash storage unit includes: The file data storage area is used to store the actual data blocks of the file. The file information storage area is used to store basic file information and index lists; The three-mode redundancy area is used to redundantly store file information to ensure reliability; The error correction and verification area is used to store verification codes to support data error correction and recovery; The error correction and redundancy module includes: Triple redundancy storage unit is used to store file information as three redundant copies, which are stored in different physical blocks to prevent single block failure; Error correction coding unit, used to perform error correction coding on file data before writing, generate check codes and append them to file data blocks; An error detection unit is used to verify the checksum when reading data and detect errors in the data block; The data recovery unit is used to recover damaged data blocks based on triple redundancy storage information and error correction verification results.

2. The FPGA-based spaceborne file storage system according to claim 1, characterized in that, The file linked list module includes: The file start pointer unit is used to record the address of the file's starting physical block. Block index unit, used to record the address of the next physical block for each physical block to build a linked list; The linked list maintenance unit is used to dynamically allocate physical blocks and update the linked list pointer when a file is created, reclaim the corresponding physical blocks and clear the linked list index when a file is deleted, and reallocate physical blocks and update the linked list when a file is moved.

3. The FPGA-based spaceborne file storage system according to claim 1, characterized in that, The scheduling control module includes: The task priority allocation unit is used to allocate storage resources based on real-time requirements and file operation priorities; The parallel processing scheduling unit is used to schedule the FPGA parallel control unit to perform read and write operations on multiple channels; The storage resource optimization unit is used to dynamically allocate storage space.

4. An FPGA-based spaceborne file storage method, applied to an FPGA-based spaceborne file storage system as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S1. Initialize the file storage system, including configuring the FPGA processing unit and the NandFlash storage unit; S2. When creating a file, allocate physical blocks and cache file information in the FPGA's internal RAM; S3. Write the file data in blocks to the NandFlash storage unit in parallel through multiple channels; S4. Record the index information of file blocks in the linked list module to form a file linked list; S5. After receiving the recording stop command, write the file information from the FPGA internal RAM to the NandFlash file information table and store it in a three-mode redundancy manner; S6. During file reading, file blocks are read sequentially through the indexed linked list, and the read data is corrected and verified.

5. The FPGA-based spaceborne file storage method according to claim 4, characterized in that, The file reading in step S6 includes the following steps: Locate the physical address of the starting block of the file in the file information table based on the file number; The physical addresses of each data block in the file are obtained sequentially using a linked list structure; Read data from multiple physical blocks in parallel; Perform error correction and verification on the read data; The file data is concatenated according to the linked list order until the reading is complete.

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