Memory resource dynamic allocation method, device, electronic device and storage medium

Abstract

One or more embodiments of the present disclosure provide a method, device, electronic device, and storage medium for dynamic allocation of memory resources. The method includes: obtaining memory behavior characteristic data, the memory behavior characteristic data reflecting the behavioral characteristics of the system or process in terms of memory usage; encoding the memory behavior characteristic data to obtain a state code for the memory behavior characteristic data; dynamically selecting a target prediction model based on actual memory usage operations at historical moments, the actual memory usage operations representing information reflecting the policy effect and system status generated after the execution of the memory allocation strategy at the historical moment; obtaining a memory allocation strategy based on the state code and the target prediction model; and dynamically allocating memory resources based on the memory allocation strategy. Through the present disclosure, memory can be reasonably allocated, resource utilization can be effectively improved, and cost and energy consumption can be reduced.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to the field of communication technologies, and in particular, to a method, device, electronic device, and storage medium for dynamically allocating memory resources. Background Art

[0002] As industrial automation continues to advance, industrial control terminals, such as load-controlled terminals and other edge controllers, play a crucial role in industrial production systems. They are widely used in various industrial scenarios, from precision manufacturing production lines to complex industrial monitoring systems. The stable operation of these terminal devices is essential. Because industrial control terminals must operate continuously in demanding environments requiring high real-time performance and high stability, their memory management becomes a key factor affecting device performance and system reliability.

[0003] The complexity of industrial workloads presents unprecedented challenges for memory management. On the one hand, production line operations exhibit significant cyclical characteristics, like a precision clock running at a fixed rhythm. Equipment load fluctuates regularly with the production process. On the other hand, tasks such as equipment anomaly detection exhibit sudden and unpredictable demands for memory resources. This combination of cyclical and sudden load characteristics limits the practical application of single prediction models in memory management. Summary of the Invention

[0004] In view of this, an object of one or more embodiments of the present disclosure is to provide a method, apparatus, electronic device, and storage medium for dynamically allocating memory resources to solve the problems of the background technology.

[0005] Based on the above objectives, one or more embodiments of the present disclosure provide a method for dynamically allocating memory resources, including:

[0006] Acquiring memory behavior characteristic data, wherein the memory behavior characteristic data reflects behavioral characteristics of a system or process in terms of memory usage;

[0007] Encoding the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data;

[0008] Dynamically select a target prediction model based on actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting the policy effects and system status generated after the memory allocation policy at the historical moment is executed;

[0009] Obtaining a memory allocation strategy according to the state code and the target prediction model;

[0010] Dynamically allocate memory resources according to the memory allocation strategy;

[0011] The target prediction model is dynamically selected based on the actual memory usage at the historical moment, including:

[0012] Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment;

[0013] Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy;

[0014] In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, the first prediction model being used to cope with periodic tasks;

[0015] In response to the evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the second prediction model is used to cope with the sudden task.

[0016] Optionally, in response to determining that the target prediction model is the first prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes:

[0017] The state code is input into the first prediction model to obtain a memory allocation strategy output by the first prediction model; wherein the first prediction model is a long short-term memory network model that takes a time series consisting of the state code at the current moment and the state code at the historical moment as input and takes the memory allocation strategy as output.

[0018] Optionally, in response to determining that the target prediction model is the second prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes:

[0019] Obtaining a state transition probability matrix at a current moment, wherein the state transition probability matrix is determined according to the memory behavior characteristic data;

[0020] The state code and the state transition probability matrix are input into the second prediction model to obtain the memory allocation strategy output by the second prediction model; wherein the second prediction model is a Markov chain model with the current state code and the state transition probability matrix as input and the memory allocation strategy as output.

[0021] Optionally, obtaining an evaluation result of the memory allocation policy at the historical moment based on the memory allocation policy at the historical moment and the actual memory usage operation at the historical moment includes:

[0022] quantifying the memory allocation strategy at the historical moment into predicted memory usage operations at the historical moment, wherein the predicted memory usage operations include predicted memory request actions, memory release actions, and memory fragment cleanup actions;

[0023] Calculating the mean absolute error between the actual memory usage operations at the historical moment and the predicted memory usage operations at the historical moment, the actual memory usage operations including actual memory request actions, memory release actions, and memory fragmentation cleanup actions;

[0024] The mean absolute error is taken as the evaluation result.

[0025] Optionally, it also includes:

[0026] The memory allocation efficiency corresponding to the memory allocation strategy is determined based on at least one indicator of memory fragmentation rate, allocation delay, and pre-allocation waste;

[0027] updating the value of the state-action pair according to the memory allocation efficiency, wherein the value of the state-action pair represents the long-term value of evaluating a certain action in a specific state;

[0028] The prediction model is guided to select a candidate memory allocation strategy according to the value of the state-action pair.

[0029] Optionally, the memory allocation strategy includes:

[0030] For predicted memory requests whose predicted request amount is less than or equal to a preset threshold, direct them to the two-stage split adapter allocator;

[0031] For predicted memory requests whose predicted request volume is greater than a preset threshold, the system is used to directly manage them.

[0032] Optionally, the dynamically allocating memory resources according to the memory allocation policy includes:

[0033] Determine the memory allocation amount for each process in the memory allocation strategy, and the memory margin corresponding to each process;

[0034] In response to a ratio of the memory allocation amount to the memory margin of any process being greater than a preset threshold, the allocation action of the process in the memory allocation strategy is deleted.

[0035] Based on the same inventive concept, one or more embodiments of the present disclosure further provide a device for dynamically allocating memory resources, including:

[0036] an acquisition module configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of a system or process in terms of memory usage;

[0037] an encoding module configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data;

[0038] a model selection module configured to dynamically select a target prediction model based on actual memory usage operations at a historical moment, wherein the actual memory usage operations represent information reflecting policy effects and system status generated after the execution of a memory allocation policy at a historical moment;

[0039] A generation module is configured to obtain a memory allocation strategy according to the state code and the target prediction model;

[0040] an allocation module, configured to dynamically allocate memory resources according to the memory allocation policy;

[0041] The target prediction model is dynamically selected based on the actual memory usage at the historical moment, including:

[0042] Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment;

[0043] Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy;

[0044] In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, the first prediction model being used to cope with periodic tasks;

[0045] In response to the evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the second prediction model is used to cope with the sudden task.

[0046] Based on the same inventive concept, one or more embodiments of the present disclosure also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein when the processor executes the program, the method for dynamically allocating memory resources as described in any one of the above items is implemented.

[0047] Based on the same inventive concept, one or more embodiments of the present disclosure further provide a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute any of the above-mentioned methods for dynamically allocating memory resources.

[0048] From the above description, it can be seen that the method for dynamic allocation of memory resources provided by one or more embodiments of the present disclosure first obtains memory behavior feature data reflecting the memory usage behavior characteristics of the system or process and encodes it to obtain a state code; then, the memory allocation strategy at the historical moment is evaluated based on the memory allocation strategy at the historical moment and its corresponding actual memory usage operation (that is, information reflecting the policy effect and system status after the policy is executed) to obtain an evaluation result reflecting the prediction error; then, the target prediction model is dynamically selected based on the evaluation result. If the evaluation result meets the preset conditions, the first prediction model for responding to periodic tasks is selected; if not, the second prediction model for responding to sudden tasks is selected, and then the memory allocation strategy is derived by combining the state code and the target prediction model; finally, memory resources are dynamically allocated based on the strategy.

[0049] The implementation of this disclosure can adapt to the load characteristics of complex industrial control terminals, overcoming the limitations of a single model by dynamically selecting a prediction model to address different load conditions. Furthermore, the implementation of this disclosure, based on the encoding of memory behavior characteristic data and the evaluation results of historical memory allocation operations, makes memory allocation decisions more scientific and reasonable. This disclosure enables the rational allocation of memory, effectively improving resource utilization and reducing costs and energy consumption.

[0050] The memory resource dynamic allocation device, electronic device and computer-readable storage medium provided in the present disclosure are all capable of implementing the steps of the above-mentioned memory resource dynamic allocation method, and therefore also have the beneficial effects of the above-mentioned memory resource dynamic allocation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate one or more embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 A flowchart of a method for dynamically allocating memory resources according to one or more embodiments of the present disclosure;

[0053] Figure 2 A schematic diagram of a process for dynamically selecting a target prediction model according to one or more embodiments of the present disclosure;

[0054] Figure 3 A schematic diagram of the structure of a memory resource dynamic allocation device according to one or more embodiments of the present disclosure;

[0055] Figure 4 A schematic diagram of the hardware structure of an electronic device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0057] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in one or more embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0058] refer to Figure 1 The method for dynamically allocating memory resources according to one or more embodiments of the present disclosure includes the following steps:

[0059] Step S101: Acquire memory behavior characteristic data, where the memory behavior characteristic data reflects the behavior characteristics of a system or process in terms of memory usage;

[0060] Step S102: Encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data;

[0061] Step S103: Dynamically select a target prediction model based on actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting the policy effects and system status generated after the memory allocation policy at the historical moment is executed;

[0062] Step S104: obtaining a memory allocation strategy based on the state code and the target prediction model;

[0063] Step S105: dynamically allocating memory resources according to the above memory allocation strategy;

[0064] Among them, such as Figure 2 As shown in the figure, the target prediction model is dynamically selected based on the actual memory usage operation at the historical moment, including:

[0065] Step S201: Obtain the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment;

[0066] Step S201: obtaining an evaluation result of the memory allocation strategy at the historical moment based on the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy;

[0067] Step S203: In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, wherein the first prediction model is used to cope with periodic tasks;

[0068] Step S204: In response to the above evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the above second prediction model is used to deal with the sudden task.

[0069] In the implementation of the present disclosure, the above-mentioned memory behavior characteristics may include one or more of memory usage behavior characteristics, process attribute characteristics, resource constraint characteristics and memory access efficiency characteristics.

[0070] Among them, the above-mentioned memory usage behavior characteristics can reflect the dynamic patterns and granularity characteristics of memory usage; the above-mentioned process attribute characteristics can reflect characteristics such as the priority attributes of the process in system scheduling; the above-mentioned resource constraint characteristics can reflect the system's hard constraints on process memory usage; the above-mentioned memory access efficiency characteristics can reflect the locality of memory access and system memory pressure.

[0071] In an embodiment of the present disclosure, a dynamic detection mechanism (such as kprobe) can be used to inject monitoring probes into memory mapping mechanism functions (such as the do_mmap function) and memory unmapping mechanism functions (such as the do_munmap function) to capture the process virtual memory area (VMA) request sequence, thereby obtaining dynamic pattern characteristics reflecting memory usage; it is also possible to divide the requested memory size of 16-2048 bytes into a preset number of intervals (such as 32) on a logarithmic scale, and dynamically merge low-frequency intervals based on the threshold adjusted by the configuration file path (such as / proc / sys / vm / mdp_bucket_merge) in the system virtual memory for adjusting the memory request interval merging threshold to obtain granular characteristics of memory usage. The above-mentioned dynamic pattern characteristics and granular characteristics of memory usage can be regarded as memory usage behavior characteristics.

[0072] In an embodiment of the present disclosure, the static priority (static_prio) and the control group memory limit (memory.low) can also be extracted from the task structure (task_struct) to obtain the priority attributes of the process in the system scheduling and the hard constraints of the system on the process memory usage as process attribute characteristics and resource constraint characteristics.

[0073] In the embodiment of the present disclosure, the historical page fault rate can also be obtained by collecting Performance Monitoring Unit (PMU) events through the perf_event_open function, so as to understand the efficiency of process memory access and system memory pressure and obtain memory access efficiency characteristics.

[0074] Although the preferred embodiment of obtaining memory behavior characteristic data of the present invention is disclosed as above, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the claims.

[0075] In order to facilitate the calculation of the prediction model, the implementation of the present disclosure also needs to encode the memory behavior feature data. The original memory behavior feature data often presents high-dimensional, complex and diverse format characteristics. Directly inputting the prediction model will not only increase the computational burden, but may also make it difficult for the model to effectively learn and extract key information. Through encoding, these raw data can be converted into a more regular, low-dimensional and semantically clear form, thereby significantly improving the efficiency and accuracy of the prediction model in processing data.

[0076] In an embodiment of the present disclosure, a fast hash algorithm may be used to generate a state code of a preset length (eg, an 8-bit state code).

[0077] In the implementation of the present disclosure, the state code can be obtained and stored in a preset location. For example, the state code can be stored in a radix tree (radix_tree) to provide real-time input for the prediction model.

[0078] The key part of the technical solution disclosed in the present invention is to dynamically select the target prediction model based on the actual memory usage operation at the historical moment.

[0079] As mentioned earlier, industrial workloads present significant complexity. On the one hand, production line operations are cyclical, and their memory requirements fluctuate regularly throughout the production process. On the other hand, tasks such as device anomaly detection are often sudden, often creating urgent and unpredictable demands on memory resources.

[0080] Related technologies typically use a single prediction model to allocate memory resources in industrial scenarios. However, this approach has significant limitations, as no single prediction model can adequately address both the cyclical and sudden nature of industrial workloads. This makes it difficult to align memory resource allocation with actual needs, leading to issues such as irrational memory allocation, wasted or insufficient resources, and other issues.

[0081] In the implementation of this disclosure, the target prediction model is dynamically selected based on the actual memory usage at that historical moment. Specifically, the memory allocation strategy used at that historical moment is evaluated based on the actual memory usage at that moment. This determines the actual performance of the selected prediction model at that moment and, in turn, determines the prediction model to be used in the current round.

[0082] Given that the prediction model of the present disclosure needs to handle two different types of loads, periodic tasks and sudden tasks, the prediction model settings will also be carried out according to these two characteristics. That is to say, in the implementation of the present disclosure, the selection range of the prediction model covers two models: one is a first prediction model specifically used to deal with periodic tasks, and the other is a second prediction model designed for sudden tasks. Through such model settings and dynamic selection mechanisms, it is possible to better adapt to the complex and changing memory requirements in industrial scenarios and improve the rationality and effectiveness of memory resource allocation.

[0083] In an embodiment of the present disclosure, the first prediction model may be constructed based on a Long Short-Term Memory network (LSTM), and the second prediction model may be constructed based on a Markov chain.

[0084] The LSTM model's unique gating mechanism effectively handles long-term dependencies. In periodic tasks, information from past cycles is crucial for predicting future trends. The LSTM model accurately captures the cyclical characteristics of data such as memory usage in periodic tasks. For example, in typical periodic tasks like industrial production lines, the LSTM model can accurately predict memory requirements for the next cycle based on memory usage patterns accumulated over multiple cycles.

[0085] The Markov chain model offers significant advantages in addressing emergencies. It determines the probability distribution of the next state based solely on the current state, eliminating the need to consider complex historical state sequences and enabling rapid responses to emergencies.

[0086] In an embodiment of the present disclosure, the first prediction model can be deployed in the drivers / misc directory. The model is initialized by loading the lstm_weights.bin weight file in FP16 format through sysfs (a virtual file system provided by the Linux kernel for data exchange between user space and kernel space). During the inference phase, the corresponding instruction set is used for acceleration based on the hardware architecture. If the architecture is ARM, the kernel_neon_begin / end functions are called to enable the NEON instruction set (NEON is the SIMD instruction set of ARM processors, which can significantly improve data processing speed) for inference acceleration. If the platform is x86, the AVX2 instruction set (AVX2 is the Advanced Vector Extensions instruction set of Intel processors, which can improve floating-point performance) is used instead. After the first prediction model completes inference, the prediction result is stored in current->mdp_prediction (where current generally represents the structure of the current process, and mdp_prediction is a member variable within the structure used to store the prediction result) for subsequent pre-allocation decisions.

[0087] Specifically, in the technical solution disclosed in the present invention, a dynamic prediction device / dev / predict_ctrl can be constructed based on the character device framework, which provides a basic device interface for the prediction function of the system, and uses a ring buffer to efficiently manage the input timing data. At the same time, DMA-coherent memory is used to ensure that alignment can be maintained when using NEON or AVX instructions for data access, thereby improving the efficiency of data processing. In addition, a weight loading interface file / sys / class / misc / predict / load_weights can be defined to facilitate users to load the weights required for the model. In order to support concurrent prediction requests, a multi-producer single-consumer mode can also be implemented through kfifo, so that multiple requests can be processed in an orderly manner.

[0088] The FP16 weight loading subsystem undertakes the important task of processing weight files. First, it developed a binary parser to parse the weight file header, which contains key information such as the number of layers, dimensions, and quantization flags. In terms of weight data conversion, SIMD accelerated conversion from FP16 to FP32 is implemented. Different conversion instructions are used for different hardware platforms: under the ARMv8.2 architecture, the vcvt_f32_f16 instruction is used (CONFIG_ARM64_FP16 needs to be enabled); on the x86 platform, the vcvtph2ps instruction is used in conjunction with the AVX512-FP16 extension. For weight memory, a CMA pre-allocated pool is used for management, and device mapping is established through dma_map_single to ensure that the device can efficiently access the weight data.

[0089] The heterogeneous computing acceleration layer leverages the strengths of different hardware architectures, providing optimized kernels for both ARM and x86 platforms. On the ARM platform, the lstm_neon_kernel function serves as the core acceleration module. It uses the kernel_neon_begin() and kernel_neon_end() functions to enable and disable the use of the NEON instruction set. Within this function, assembly instructions such as VMLA.F16 are used to implement the SIMD implementation of the LSTM cell. On the x86 platform, the lstm_avx2_kernel function is the core of the optimization. It uses the kernel_fpu_begin() and kernel_fpu_end() functions to manage the FPU state and utilize AVX2 instructions such as _mm256_fmadd_ps to expand computations, improving LSTM computation performance. These optimizations enable the system to achieve efficient computation across diverse hardware environments.

[0090] In the embodiment of the present disclosure, the construction and initialization of the state transition matrix of the second prediction model can be achieved by the following steps: calling the kernel initialization function through module_init to construct a sparse state transition matrix in CSR format. The probability of each state transition of the matrix is initialized to 1 / N+1e-5 (where N is the total number of states and 1e-5 is the Laplace smoothing factor), which not only ensures the initial uniform distribution characteristics but also avoids the zero probability problem. In terms of memory management, kmalloc_node is used to allocate matrix storage space locally on the NUMA node, and high-frequency transfer rows are preloaded into the L3Cache through copy_to_user, and prefetch_range is used to optimize data access locality, significantly reducing the cross-node memory access latency of the industrial control board. It should be noted that this step only initializes the probability distribution of the state transition matrix and has nothing to do with the initial state vector of the Markov chain (determined by the system runtime state).

[0091] In an embodiment of the present disclosure, data collection is performed using memory event streaming capture and compression. The specific process may include: inserting tracepoints in the tlsf_malloc and tlsf_free functions to capture state transition events generated by memory allocation and release operations; creating a double-buffered circular queue with 4KB per buffer using relayfs to efficiently store high-frequency memory events in a producer-consumer model; and having the kworker kernel thread compress the event into a four-tuple consisting of a timestamp, process ID, memory block size, and operation type compressed to 16 bits using Delta encoding. The timestamp records the offset relative to the base time, the process ID retains the lower 16 bits of valid data, the memory block size is aligned to 4KB, and the operation type marks allocation or release. The compressed event stream is written to / sys / kernel / debug / mdp_events, which can be directly accessed by user-mode programs through mmap, achieving real-time data acquisition with μs latency. Meanwhile, the Delta encoding of the timestamp compresses the storage volume to 1 / 4 of the original value while maintaining the integrity of the timing information, reducing the data transmission pressure in industrial control scenarios.

[0092] In the disclosed embodiments, state features are extracted in real time using sliding window statistics and dynamic data preprocessing. Real-time statistics of the timing characteristics of memory event streams are used to support state transition probability calculation. The specific process includes: defining a struct sliding_window structure to maintain a circular queue with a capacity of 100, using atomic64_t atomic operations to ensure the atomicity of window count updates in a multi-core environment; implementing incremental mean and variance calculations based on the Welford algorithm (with a time complexity of O(1)), and storing the results in the mdp_stats field of the task_struct; performing LRU eviction on process statistics that have not been updated for more than one second, and managing data timeliness through a bidirectional linked list; and employing the RCU mechanism to ensure multi-core concurrent read and write security. Write operations are updated lock-free through a synchronization mechanism, and read operations obtain the latest data non-blockingly. These statistics (such as the allocation delay mean and fluctuation variance) serve as the core components of the Markov chain state features. Dynamically tracking memory behavior trends through online calculations provides real-time input for subsequent Bayesian matrix updates. Among them, the recursive calculation characteristics of the Welford algorithm ensure that the statistical results reflect the latest memory behavior patterns while maintaining computational efficiency.

[0093] In the embodiment of the present disclosure, when the model prediction error exceeds the threshold, the optimal path solution is achieved by constructing a state transition matrix and combining it with the Viterbi algorithm to provide a reliable prediction continuity guarantee for the system. The specific process may include: first, constructing a Markov state transition matrix based on historical memory event data, where the matrix elements represent the transition probability between states. When the error monitoring system triggers the model switching requirement, the Viterbi algorithm is used to perform dynamic programming calculations, and the recursive formula is used to calculate the optimal path solution. Find the maximum probability path in state k at time t, where Generate observations for state k The emission probability, The path's predecessor state is recorded. After the optimal path calculation is completed, atomic model switching is achieved through the RCU (Read-Copy Update) mechanism, ensuring seamless migration of prediction parameters in a multi-core concurrent environment and avoiding data inconsistencies caused by context switching. This mechanism, through probabilistic modeling of the state transition matrix and optimal path search using the Viterbi algorithm, provides a mathematically rigorous fallback solution for prediction strategies, effectively addressing the risk of model failure in complex industrial control scenarios.

[0094] In the embodiment of the present disclosure, the state transition probability is dynamically adjusted according to the new observation data, so that the model can better adapt to the real-time changes of the system. The specific process may include: every time 100 new events are received, a matrix update operation will be triggered. First, the number of historical state transitions is exponentially decayed, and the decay coefficient λ is 0.9, that is, counts[i][j]*=0.9 is used to reduce the impact of old data on the current transition probability, reflecting the importance of recent data. At the same time, for the newly observed state transition (s→s'), the corresponding transition count is increased by 0.1, that is, counts[i][j]+=0.1 is executed. Afterwards, in order to obtain the effective state transition probability, the normalization calculation is performed asynchronously through the workqueue, and the formula prob[i][j]=counts[i][j] / sum_counts[i] is used to calculate the probability of each state transition. In this process, in order to ensure the security of the update operation in the interrupt context of the industrial control environment, spin_lock_bh is used to protect the row-level update to avoid data inconsistency problems caused by concurrent operations, thereby ensuring that the Markov chain model can accurately reflect the current state transition of the system.

[0095] The following describes in detail how to obtain the evaluation results of the memory allocation strategy at a historical moment. First, the memory allocation strategy in the implementation of the present disclosure represents a predicted memory allocation plan, which can include one or more of the memory area, size, time, priority, and memory recycling strategy allocated to a specific task or process. These memory allocation strategies reflect predicted memory usage operations, which can include one or more of the following: memory request actions, memory release actions, and memory fragmentation cleanup actions. The memory allocation strategy can be implemented based on the prediction of memory requests for a specific task or process.

[0096] The evaluation result of the memory allocation policy is determined based on the difference between the actual memory usage operation and the predicted memory allocation policy. The actual memory usage operation is determined based on the memory request actually generated by a specific task or process.

[0097] The error in the prediction model's prediction results at each historical moment can be determined based on the mean absolute error between the actual memory usage operations and the predicted memory usage operations. Using this error as an evaluation result of the memory allocation strategy reflects the adaptability of the selected prediction model to changes in memory usage in the current scenario. When the prediction model's prediction results have a small error, it can be assumed that the selected prediction model is able to effectively perform memory prediction in the current scenario. When the prediction model's prediction results have a large error, it can be assumed that the selected prediction model is no longer able to effectively perform memory prediction in the current scenario.

[0098] In an embodiment of the present disclosure, when the average absolute error between the actual memory usage operation and the predicted memory usage operation at a historical moment is less than or equal to a preset threshold, it is considered that the first prediction model for periodic tasks can be selected; when the average absolute error is greater than the preset threshold, it can be considered that a sudden task has occurred, and the second prediction model for sudden tasks can be selected.

[0099] In addition to the mean absolute error of actual and predicted memory usage at historical moments, embodiments of the present disclosure may also include other evaluation metrics, such as memory resource utilization, or system performance evaluation metrics such as task execution time and response time. These different evaluation methods do not affect the scope of protection of the present invention as long as they achieve the corresponding objectives.

[0100] In an embodiment of the present disclosure, a dynamic error monitoring system is used to perform rolling statistics on the absolute errors between the predicted values and the actual observed values. The specific process may include: using the Mean Absolute Error Calculator (MAE) and the error state machine of the three states of NORMAL, WARNING, and CRITICAL included in the monitoring system, triggering state migration when the MAE exceeds a preset threshold. To prevent false alarms caused by high-frequency noise, jiffies are used to record the abnormal start timestamp, and the state change is confirmed only when the same state lasts for more than 100ms. These error statistical results are directly used as the triggering conditions of the Markov backoff mechanism. When the state machine enters the CRITICAL state, the system will start the Viterbi algorithm to perform model switching evaluation to ensure dynamic adjustment of the prediction strategy.

[0101] Furthermore, in embodiments of the present disclosure, kernel-level prediction services can be integrated to handle system-level context management and scheduling coordination, providing kernel-level support for prediction strategies throughout the entire process. Specific implementations include extending the mdp_prediction structure in the task_struct process control block to define a joint data field containing the prediction mode (LSTM_MODE / MARKOV_MODE) and the corresponding context. By registering a scheduler notifier, prediction parameters are automatically injected during process switches, ensuring that the context of the LSTM or Markov chain model is bound to the task state. Furthermore, the system creates the / proc / mdp_stats interface via debugfs to expose key metrics such as prediction error and model switching frequency in real time. This mechanism achieves deep coupling between the prediction service and kernel scheduling. When error monitoring triggers Markov fallback, RCU-protected context switching ensures atomic migration of prediction state. Parameter injection during process scheduling ensures prediction continuity, providing industrial real-time control systems with model switching capabilities with μs-level response.

[0102] In order to further improve the prediction accuracy of the prediction model disclosed herein, the Q-Learning strategy can also be used to guide the strategy optimization of the prediction model.

[0103] Specifically, in the implementation of the present disclosure, the reward value may be calculated in a preset manner, and the Q value may be updated according to the reward value to guide the prediction model action.

[0104] In an embodiment of the present disclosure, the reward value can be calculated based on the memory fragmentation rate, allocation delay and pre-allocation waste of executing the memory allocation strategy. In an embodiment of the present disclosure, the above data can be obtained through the perf_event performance monitoring framework.

[0105] In the embodiment of the present disclosure, the calculation formula of the reward value can be defined as:

[0106] ;

[0107] in, Indicates the current timestamp, represents the smoothing factor, which can be set to , Indicates the rate of change of memory fragmentation rate, , Indicates the monitoring window, which can be set through / proc / sys / vm / mdp_window. For example, it can be set to 300 milliseconds. Indicates the memory fragmentation rate, , It represents the number of free page blocks of order k in the partner system. The fraction in the formula represents the largest continuous memory block (calculated based on the highest non-zero order), and the denominator represents the total number of free pages. The closer the ratio is to 1, the lower the fragmentation rate. Indicates allocation delay, , you can use perf_event to monitor the CPU cycle consumption of memory allocation functions (such as kmalloc), Indicates the CPU main frequency, converted to actual delay time ( ), when the actual delay time decreases, the allocation delay optimization item increases and the reward item value increases. Conversely, the allocation delay optimization item decreases and the reward item value decreases. Indicates the amount of pre-allocated waste, , Indicates the memory page size, represents the waste baseline, which can be defined as , which means taking the total system memory The larger of 10% and 64MB is used to prevent excessive penalties on small memory systems.

[0108] In the embodiments of the present disclosure, a weight adaptive mechanism and an emergency state detection mechanism may also be introduced. Specifically, the weight adaptive mechanism may include: when monitoring the real-time task delay exceeding the limit, the weight of the memory fragmentation rate change item is reduced, and the weight of the allocation delay optimization item is increased. The weight can be transitioned through exponential smoothing. The emergency state detection mechanism includes: when the conditions are met: or When , the reward function is set to .in, represents the amount of fragment mutation, , Indicates the comprehensive reward value.

[0109] In the embodiment of the present disclosure, the Q value update formula can be defined as:

[0110] ;

[0111] in, represents the learning rate, In the embodiment of the present disclosure, the initial value of the learning rate can be set to 0.1 and dynamically adjusted during the calculation process, and the discount factor can be set to 0.9.

[0112] The encoding formula of the state-action pair can be defined as:

[0113] ;

[0114] , , .

[0115] In an embodiment of the present disclosure, the eligibility trace may be used to represent the importance of each state-action pair to the current learning process.

[0116] Qualifications The update rule can be defined as: ;

[0117] Among them, you can set constraints: , and elimination strategy: when When from Removed.

[0118] In the process of updating state-action pairs, you can also improve the calculation effect by setting the following conditions.

[0119] In the embodiment of the present disclosure, the above time can be selected The initial value is set to , and use the timer interval dynamic adjustment formula to compensate for the error, . In an embodiment of the present disclosure, a batch update buffer mechanism can be introduced, which can include a kfifo data structure and a batch processing algorithm. Among them, the buffer size of the kfifo data structure can be designed to be N=1024 items. The batch processing algorithm is triggered when the ratio of the number of items in the current buffer to the total buffer size is greater than or equal to a preset threshold (such as 0.8). The principle of the batch processing algorithm can be to use AVX-512 instructions to calculate the update of 256 Q values in parallel.

[0120] In embodiments of the present disclosure, resource-constrained optimization strategies may also be introduced, including a low-power mode, an interrupt context optimization mechanism, and a safe downgrade mechanism. The low-power mode indicates that when the system enters an idle state, the timer interval is set to the maximum of 100 milliseconds and 1.5 times the current timer interval, and updates to the eligibility trace are suspended. The interrupt context optimization mechanism may include: the system employing a per-CPU replica Q table mechanism, with each CPU core maintaining an independent local Q table, Q_local, while retaining a globally unified Q_global table. When multiple CPU cores simultaneously update Q values and a conflict arises, a weighted merge strategy is adopted: Q_merged = 0.7Q_local + 0.3Q_global, which prioritizes retaining 70% of the weight of local updates while merging 30% of the weight of the global table. The safe downgrade mechanism may include: when memory pressure exceeds a preset threshold (e.g., 80%), updating the learning rate to half the current learning rate, updating the eligibility trace decay factor to 0.8 times the current eligibility trace decay factor, disabling AVX acceleration, and using pure software floating-point calculations.

[0121] In order to further improve the efficiency of Q-value calculation, reduce the query delay of multi-axis control tasks, and enhance the performance and response speed of the system in multi-axis control scenarios, the embodiments of the present disclosure can also be configured from the following aspects.

[0122] Convert Q-value floating-point operations to Q8.8 fixed-point format, utilizing the fixed32 type in linux / fixed_point.h. Fixed-point operations are typically faster than floating-point operations in hardware because they don't require complex floating-point representation and operation rules. In embedded systems or environments with limited computing resources, fixed-point operations can significantly reduce computation time. Furthermore, SSE / AVX accelerated matrix multiplication is enabled through kernel_fpu_begin / end. These instruction sets implement single-instruction, multiple-data (SIMD) operations, processing multiple data elements within a single clock cycle. This significantly increases the speed of matrix multiplication, thereby accelerating the Q-value calculation process.

[0123] Q values for the top 20% of high-frequency states are pre-calculated and stored in the shared memory / dev / shm / mdp_qtable. Shared memory allows different processes to directly access the same physical memory area, eliminating data copying and transmission overhead and reducing latency when multi-axis control tasks query Q values. Locking physical pages with mlock ensures that these pre-calculated Q value data always resides in physical memory, avoiding additional latency caused by page swapping (such as page swapping to disk) and ensuring that multi-axis control tasks can quickly obtain the required Q value information.

[0124] In multi-axis control scenarios, it's crucial to quickly and accurately calculate and query Q values to make decisions. The aforementioned hardware acceleration optimization and shared memory design enable Q value calculation and querying to be completed in a shorter timeframe, enabling the system to respond more quickly to multi-axis control tasks and improving overall system performance and stability. This makes it particularly suitable for applications in areas like industrial control where real-time performance is crucial.

[0125] According to the memory allocation strategy obtained in the above steps, dynamic memory resource allocation can be performed. In the embodiment of the present disclosure, the memory allocation strategy can be based on the following principles: in the Linux kernel of the load control terminal, by deeply integrating the two-level separated fit (TLSF) memory pool and the buddy system, a hierarchical memory management architecture is constructed. For high-frequency small memory requests in industrial control scenarios (such as sensor data cache), allocation requests with a request amount less than or equal to a preset threshold (such as 204 bytes) are directed to the TLSF memory pool. At the same time, dma_map_single is used to map the TLSF metadata to the Write Combining memory area, and combined with the prefetchw instruction to preload hot data, the allocation delay of the x86 industrial computer can be measured to be ≤12μs, meeting the real-time requirements of motion control. Among them, the TLSF cache pool can be constructed with 256B first-level blocks (using kmem_cache_create to create a dedicated slab cache) and 16B second-level blocks (bitmap management), achieving O(1) time allocation. This strategy can eliminate the delay jitter caused by cache line contention while ensuring data consistency, fully meeting the stringent real-time requirements of industrial terminals for memory access.

[0126] In the embodiments of the present disclosure, the lazy memory commit strategy can also be used to optimize memory usage and ensure stable system operation. The specific process may include: first, virtual address space management is performed, and the PROT_NONE virtual address area is created using mmap. When the process accesses the area for the first time, a page fault exception is triggered. In handle_mm_fault, mdp_commit_allocation is called to allocate physical pages. At the same time, the pre-allocation hit rate is updated in the mdp_fault function through vma->vm_ops to achieve on-demand memory allocation to avoid waste. Then, the PSI dynamic adjustment algorithm is adopted, and the PSI trigger is registered to monitor memory pressure. In the psi_trigger callback function, the pre-allocation intensity is dynamically adjusted according to the memory pressure level. The intensity is reduced when the pressure is high and increased when the pressure is low. The update_allocation_policy is called to update the page allocation policy to prevent memory overload. Finally, through the statistical indicator visualization interface, debugfs is used to expose statistical information. Users can reset information by writing / sys / kernel / debug / mdp / stats_reset and read / sys / kernel / debug / mdp / prealloc_hit_rate to obtain information such as the preallocation hit rate (PID=1123, HitRate=87.5%, PressureLevel=3). This facilitates monitoring and adjusting system memory usage to ensure stable and efficient Markov chain model calculations.

[0127] In the process of executing the memory allocation strategy, in order to further improve system performance, preprocessing can also be performed before the memory allocation action. Specifically, it may include:

[0128] First, the cgroup memory monitoring subsystem is integrated to obtain real-time memory usage information for each process. Using the cgroup v2 memory.current interface, the kernel can accurately read a process's memory usage. For example, this can be achieved using the code struct page_counter*counter=&memcg->memory; u64 current_usage=page_counter_read(counter). In user mode, the remaining quota is calculated by calculating the difference between / sys / fs / cgroup / memory.high and / sys / fs / cgroup / memory.current. Based on this, when the preallocated memory prealloc_size of an action exceeds 50% of the remaining quota, the action is removed from the candidate set to avoid memory overflows caused by excessive preallocation and ensure system memory security.

[0129] In addition, a red-black tree action set can be used to maintain a filtered set of valid actions. The red-black tree action set defines a struct action_set structure, which contains a red-black tree root node, a spin lock, and a recently used list. When inserting actions, the actions are automatically sorted. For example, in the action_insert function, ordered insertion is achieved by comparing actions and adjusting the positions of red-black tree nodes. Actions can also be added to the recently used list simultaneously. The use of spin locks also ensures the security of action set operations in a multi-core concurrent environment, ensuring data consistency and operational correctness.

[0130] Designing and optimizing the user-mode interface establishes a bridge between the kernel and user-mode, allowing for special handling of critical processes. The custom ioctl command MDP_GET_ACTIONS exposes action lists to user-mode, which can then retrieve relevant information from the struct mdp_action_info structure. For critical processes like the PID controller, the mdp_weight parameter can be set. When a process is determined to have a higher priority, its weight is dynamically adjusted. For example, mdp_weight = clamp(mdp_weight*2, 0, MAX_MDP_WEIGHT) can be set, and reserved memory pages can be increased to guarantee memory quotas for critical processes, ensuring the proper operation of important tasks in the system.

[0131] During system operation, in order to ensure that motion control tasks are performed stably and efficiently, the embodiments of the present disclosure may also adopt the following strategies and mechanisms.

[0132] First, the dual Q-table policy fallback protection mechanism. The system maintains two Q-tables, Active and Shadow. If the average latency monitored through / proc / mdp_stats increases by more than 15% three times in a row, the system uses the atomic_swap operation to switch the current Q-table to the old one to maintain system stability. Simultaneously, a genetic algorithm optimization thread (kthread_run) is launched to perform cross-mutation operations on the Q-table parameters. The mutation results are written to debugfs for offline analysis, ensuring that motion control tasks are not interrupted.

[0133] The second step is DMA-assisted memory defragmentation. When / proc / buddyinfo shows that the percentage of contiguous free page blocks falls below 10%, the system calls dma_engine_alloc to request a DMA channel and uses dma_alloc_coherent to copy scattered pages to a contiguous area. During this process, the cgroup freezer suspends low-priority logging processes to ensure that core control threads (such as the real-time scheduler) continue to run. After defragmentation is complete, the physical mapping of the vm_area_struct is updated.

[0134] Next comes cgroup resource arbitration and reclamation. The mdp_weight parameter has been expanded in the cgroup v2 memory controller, allowing high-weight processes (such as the motion controller) to receive priority approval for pre-allocation requests in the mem_cgroup_threshold callback. 20% of memory (memory.reserve) is reserved for critical subsystems such as system.slice. When excessive requests are made and an out-of-memory (OOM) error is imminent, the pre-allocated cache is reclaimed using the LRU policy.

[0135] Finally, full-stack verification and hot upgrade implementation were performed. KVM-unit-test simulated stress-ng memory pressure scenarios to verify that the slab fragmentation rate was reduced by at least 50%. The mdpctl user-mode tool was developed to support dynamic adjustment of parameters such as the learning rate and discount factor through / sys / module / mdp / parameters. The EFICapsule mechanism was used to implement reboot-free hot updates of Q tables and LSTM models, meeting the 24 / 7 uninterrupted operation requirements of industrial sites.

[0136] It can be understood that the method can be executed by any device, equipment, platform, or device cluster with computing and processing capabilities.

[0137] It should be noted that the methods of one or more embodiments of the present disclosure can be performed by a single device, such as a computer or server. The methods of these embodiments can also be applied in a distributed scenario, performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the methods of one or more embodiments of the present disclosure, and the multiple devices will interact with each other to complete the described methods.

[0138] It should be noted that the above description is of specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0139] Based on the same inventive concept, corresponding to any of the above embodiments and methods, the present disclosure also provides a memory resource dynamic allocation device. Figure 3 As shown, the above device includes:

[0140] An acquisition module 11 is configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of a system or process in terms of memory usage;

[0141] The encoding module 12 is configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data;

[0142] A model selection module 13 is configured to dynamically select a target prediction model based on actual memory usage operations at a historical moment, where the actual memory usage operations represent information reflecting the effect of the memory allocation strategy and the system status generated after the strategy is executed at the historical moment;

[0143] A generation module 14 is configured to obtain a memory allocation strategy based on the state code and the target prediction model;

[0144] an allocation module configured to dynamically allocate memory resources according to the above memory allocation strategy;

[0145] The target prediction model is dynamically selected based on the actual memory usage at the historical moment, including:

[0146] Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment;

[0147] Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy;

[0148] In response to the evaluation result satisfying a preset condition, selecting the first prediction model as the target prediction model, the first prediction model being used to cope with the periodic task;

[0149] In response to the above evaluation result not meeting the preset conditions, the second prediction model is selected as the target prediction model, and the above second prediction model is used to deal with sudden tasks.

[0150] For the convenience of description, the above devices are described as being functionally divided into various modules. Of course, when implementing one or more embodiments of the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0151] The apparatus of the above embodiment is used to implement the corresponding method in the above embodiment and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0152] Figure 4 10 is a schematic diagram showing a more specific hardware structure of an electronic device provided in this embodiment. The device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are communicatively connected to each other within the device via the bus 1050.

[0153] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present disclosure.

[0154] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage devices, dynamic storage devices, etc. The memory 1020 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present disclosure are implemented through software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0155] The input / output interface 1030 is used to connect to input / output modules to enable information input and output. The input / output modules can be configured as components within the device (not shown) or externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, and various sensors. Output devices may include a display, speaker, vibrator, indicator light, and the like.

[0156] The communication interface 1040 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, Wi-Fi, Bluetooth, etc.).

[0157] The bus 1050 comprises a path for transmitting information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0158] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above device may only include the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0159] The electronic devices of the above embodiments are used to implement the corresponding methods in the above embodiments and have the beneficial effects of the corresponding method embodiments, which will not be described in detail here.

[0160] The computer-readable media of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0161] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the above embodiments or technical features in different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0162] Additionally, to simplify the description and discussion, and to avoid obscuring one or more embodiments of the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring one or more embodiments of the present disclosure, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which one or more embodiments of the present disclosure will be implemented (i.e., such details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure can be implemented without or with variations in these specific details. Accordingly, these descriptions should be considered illustrative rather than restrictive.

[0163] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0164] The one or more embodiments of the present disclosure are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the one or more embodiments of the present disclosure should be included within the scope of protection of the present disclosure.

Claims

1. A method for dynamic allocation of memory resources, characterized in that: include: Acquiring memory behavior characteristic data, wherein the memory behavior characteristic data reflects behavioral characteristics of a system or process in terms of memory usage; Encoding the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; Dynamically select a target prediction model based on actual memory usage operations at historical moments, where the actual memory usage operations represent information reflecting the policy effects and system status generated after the memory allocation policy at the historical moment is executed; Obtaining a memory allocation strategy according to the state code and the target prediction model; Performing dynamic allocation of memory resources according to the memory allocation strategy; The target prediction model is dynamically selected based on the actual memory usage at the historical moment, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, the first prediction model being used to cope with periodic tasks; In response to the evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the second prediction model is used to cope with the sudden task.

2. The method according to claim 1, characterized in that In response to determining that the target prediction model is the first prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: The state code is input into the first prediction model to obtain a memory allocation strategy output by the first prediction model; wherein the first prediction model is a long short-term memory network model that takes a time series consisting of the state code at the current moment and the state code at the historical moment as input and takes the memory allocation strategy as output.

3. The method according to claim 1, characterized in that In response to determining that the target prediction model is the second prediction model, obtaining a memory allocation strategy according to the state code and the target prediction model includes: Obtaining a state transition probability matrix at a current moment, wherein the state transition probability matrix is determined according to the memory behavior characteristic data; The state code and the state transition probability matrix are input into the second prediction model to obtain the memory allocation strategy output by the second prediction model; wherein the second prediction model is a Markov chain model with the current state code and the state transition probability matrix as input and the memory allocation strategy as output.

4. The method according to claim 1, wherein Obtaining an evaluation result of the memory allocation strategy at the historical moment based on the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment includes: quantifying the memory allocation strategy at the historical moment into predicted memory usage operations at the historical moment, wherein the predicted memory usage operations include predicted memory request actions, memory release actions, and memory fragment cleanup actions; Calculating the mean absolute error between the actual memory usage operations at the historical moment and the predicted memory usage operations at the historical moment, the actual memory usage operations including actual memory request actions, memory release actions, and memory fragmentation cleanup actions; The mean absolute error is taken as the evaluation result.

5. The method according to claim 2 or 3, characterized in that Also includes: The memory allocation efficiency corresponding to the memory allocation strategy is determined based on at least one indicator of memory fragmentation rate, allocation delay, and pre-allocation waste; updating the value of the state-action pair according to the memory allocation efficiency, wherein the value of the state-action pair represents the long-term value of evaluating a certain action in a specific state; The prediction model is guided to select a candidate memory allocation strategy according to the value of the state-action pair.

6. The method according to claim 1, characterized in that The memory allocation strategy includes: For predicted memory requests whose predicted request amount is less than or equal to a preset threshold, direct them to the two-stage split adapter allocator; For predicted memory requests whose predicted request volume is greater than a preset threshold, the system is used to directly manage them.

7. The method according to claim 6, characterized in that The dynamically allocating memory resources according to the memory allocation strategy includes: Determine the memory allocation amount for each process in the memory allocation strategy, and the memory margin corresponding to each process; In response to a ratio of the memory allocation amount to the memory margin of any process being greater than a preset threshold, the allocation action of the process in the memory allocation strategy is deleted.

8. A memory resource dynamic allocation device, characterized in that: include: an acquisition module configured to acquire memory behavior characteristic data, wherein the memory behavior characteristic data reflects the behavior characteristics of a system or process in terms of memory usage; an encoding module configured to encode the memory behavior characteristic data to obtain a state code of the memory behavior characteristic data; a model selection module configured to dynamically select a target prediction model based on actual memory usage operations at a historical moment, wherein the actual memory usage operations represent information reflecting policy effects and system status generated after the execution of a memory allocation policy at a historical moment; A generation module is configured to obtain a memory allocation strategy according to the state code and the target prediction model; an allocation module, configured to dynamically allocate memory resources according to the memory allocation policy; The target prediction model is dynamically selected based on the actual memory usage at the historical moment, including: Get the memory allocation strategy of the historical moment and the actual memory usage operation of the corresponding historical moment; Obtaining an evaluation result of the memory allocation strategy at the historical moment according to the memory allocation strategy at the historical moment and the actual memory usage operation at the historical moment, wherein the evaluation result reflects a prediction error of the memory allocation strategy; In response to the evaluation result satisfying a preset condition, selecting a first prediction model as a target prediction model, the first prediction model being used to cope with periodic tasks; In response to the evaluation result not meeting the preset condition, a second prediction model is selected as the target prediction model, and the second prediction model is used to cope with the sudden task.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 7.

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