LVS rule detection method and device, equipment and storage medium

Abstract

The invention provides an LVS rule detection method, apparatus and device, and a storage medium. The method comprises the steps of obtaining a to-be-detected layout netlist and a schematic diagram netlist; performing structured text representation on the to-be-detected layout netlist and the schematic diagram netlist, and performing cue word optimization operation to obtain target cue word information; searching an LVS rule related to the layout netlist to be detected and the schematic diagram netlist in a rule database according to the target cue word; and inputting the to-be-detected layout netlist, the schematic diagram netlist and the LVS rule into an LVS rule verification model to determine the consistency of the to-be-detected layout netlist and the schematic diagram netlist. By performing cue word optimization operation on the text representation of the layout netlist and the schematic diagram netlist, the pre-trained large language model can be guided to better understand the semantics of the design text, so that the performance of the LVS verification model is improved. The optimized cue word information can enhance the recognition capability of the model to the design rule, and ensures the adaptability of the model to the new layout design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a method, device, equipment and storage medium for detecting an LVS rule. Background Art

[0002] In the design process of integrated circuits (ICs), it is crucial to ensure that the layout and schematics are consistent. Figure 1 Layout Versus Schematic (LVS) is done manually or through rule-based automated tools. This process requires a detailed comparison of every component, connection, and layout in the design to ensure that every electrical connection is correctly reflected in the layout and schematic. As integrated circuit design becomes increasingly complex, the accuracy and efficiency of LVS verification have become a bottleneck in the design process.

[0003] At present, the LVS verification method mainly relies on the rule-driven detection mechanism, which first matches the predefined rules in the rule database, and then compares whether the connection relationship between the layout and the schematic diagram is consistent. However, due to the large number of component types in complex circuit design and the ever-changing design rules, the method that relies solely on static rule matching faces problems such as poor adaptability to rule updates and new designs. In addition, the traditional LVS verification method lacks flexibility and intelligence, and cannot effectively deal with unknown problems that arise in complex designs.

[0004] In summary, the problems existing in the prior art need to be solved urgently. Summary of the invention

[0005] The present invention provides a method, device, equipment and storage medium for detecting an LVS rule, so as to solve the defects in the prior art and improve the efficiency and flexibility of LVS rule detection.

[0006] The present invention provides a method for detecting an LVS rule, comprising:

[0007] Obtain the layout netlist and schematic netlist to be tested;

[0008] Representing the to-be-tested layout netlist and the schematic netlist in structured text;

[0009] Performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0010] Retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0011] The layout netlist to be tested, the schematic netlist and the LVS rule are input into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0012] According to a method for detecting LVS rules provided by the present invention, the step of performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information specifically includes:

[0013] Inputting the text representation of the to-be-tested layout netlist and the schematic netlist into a prompt word optimization model to obtain target prompt word information;

[0014] The prompt word optimization model uses the following loss model to optimize prompt word parameters, specifically by minimizing the loss function to guide the LVS rule verification model to complete the LVS verification task:

[0015]

[0016] Among them, θ represents the parameters of the LVS rule verification model, N is the number of training samples, and x i is the layout netlist text or schematic netlist text, y i is the corresponding token sequence, p i is the input prompt word; p θ (y i |x i ,p i ) means that given the input text x i and the prompt word p i Under the condition of , the model generates the target token sequence y i The conditional probability, logp θ (y i |x i ,p i ) represents the generation sequence y described by natural logarithm i The log-likelihood probability.

[0017] According to a method for detecting LVS rules provided by the present invention, the step of retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in the rule database according to the target prompt word is implemented in the following manner:

[0018] h q =Encoder(q)

[0019]

[0020]

[0021] p(ri |q)=softmax(score i )

[0022] Among them, q is the textual representation of the layout netlist and schematic netlist to be tested, r i is the LVS rule in the rule database, h q is the encoding vector of the text representation of the layout netlist to be tested, is the encoding vector of the schematic netlist, h q =Envoder(q) means encoding q into a fixed-dimensional vector h through the encoder q , Indicates that r is converted by the encoder i Encoded as a fixed-dimensional vector Represents the calculation vector h q and vector The attention score between q and r i The correlation between q and r is obtained by learning the attention matrix W. i The interaction mode between i |q)=softmax(score i ) indicates that r is calculated based on the attention score i The conditional probability given q.

[0023] According to a method for detecting LVS rules provided by the present invention, after the step of searching the rule database for LVS rules related to the layout netlist to be detected and the schematic netlist according to the target prompt word, the method further includes:

[0024] Obtain the annotation data related to the LVS verification task;

[0025] The labeled data is input into the LVS rule verification model for meta-learning.

[0026] According to a method for detecting LVS rules provided by the present invention, the step of inputting the labeled data into the LVS rule verification model for meta-learning is implemented in the following manner:

[0027]

[0028]

[0029] Among them, ф represents the parameters of the LVS rule verification model, p(T) is the task distribution, and T i is the task of sampling from p(T), For task T iThe loss function on ф (x) is the LVS rule verification model with parameter фφ, x j For textual representation of layout and schematic, y j is the corresponding violation label, f ф (x j ) is the probability of model prediction violation, It means taking the expectation of all tasks in the task distribution p(T), that is, the average loss function value on each task.

[0030] According to a method for detecting LVS rules provided by the present invention, the step of inputting the layout netlist to be detected, the schematic netlist and the LVS rules into the LVS rule verification model to determine the consistency between the layout netlist to be detected and the schematic netlist specifically includes:

[0031] Inputting the layout netlist to be tested, the schematic netlist and the LVS rule into the LVS rule verification model to obtain a predicted violation probability;

[0032] When the predicted violation probability is greater than a preset threshold, the layout netlist to be checked is inconsistent with the schematic netlist.

[0033] According to a method for detecting LVS rules provided by the present invention, the step of inputting the layout netlist to be detected, the schematic netlist and the LVS rules into the LVS rule verification model to obtain the predicted violation probability is achieved by the following method:

[0034] p(y|x)=sigmoid(f ф (x)

[0035] The step of determining that the layout netlist to be detected is inconsistent with the schematic netlist when the predicted violation probability is greater than a preset threshold is implemented in the following manner:

[0036]

[0037] Where x is the text representation of the layout netlist and schematic netlist to be checked, y∈(0,1) is the violation label, and f ф (x) is the LVS rule verification model, sigmoid is the activation function, t is the judgment threshold, and I is the indicator function; p(y|x)=sigmoid(f ф (x)) represents the probability of violation predicted by the LVS rule verification model. It means that the final violation prediction result is generated according to the prediction probability p(y|x) and the judgment threshold t.

[0038] The present invention also provides a detection device for LVS rules, comprising:

[0039] A netlist acquisition module is used to obtain the layout netlist and schematic netlist to be tested;

[0040] A text conversion module, used for expressing the to-be-tested layout netlist and the schematic netlist in structured text;

[0041] A prompt word optimization module is used to perform prompt word optimization operations on the text representations of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0042] A rule retrieval module, used for retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0043] The rule verification module is used to input the layout netlist to be tested, the schematic netlist and the LVS rules into the LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0044] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method for detecting any of the above-mentioned LVS rules is implemented.

[0045] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the method for detecting any of the above-mentioned LVS rules is implemented.

[0046] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned LVS rule detection methods.

[0047] The detection method, device, equipment and storage medium of the LVS rule provided by the present invention obtain the layout netlist to be detected and the schematic netlist; perform structured text representation on the layout netlist to be detected and the schematic netlist and perform prompt word optimization operation to obtain target prompt word information; retrieve the LVS rules related to the layout netlist to be detected and the schematic netlist in the rule database according to the target prompt word; then input the layout netlist to be detected, the schematic netlist and the LVS rules into the LVS rule verification model to determine the consistency of the layout netlist to be detected and the schematic netlist. By performing prompt word optimization operation on the text representation of the layout netlist and the schematic netlist, the pre-trained large language model can be guided to better understand the semantics of the design text, thereby improving the performance of the LVS verification model. The optimized prompt word information can enhance the model's recognition ability for design rules and ensure its adaptability to new layout designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 It is a flow chart of the detection method of the LVS rule provided by the present invention;

[0050] Figure 2 It is a structural schematic diagram of the detection device of the LVS rule provided by the present invention;

[0051] Figure 3 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] In order to solve the problems in the prior art, the present invention proposes a detection method for LVS rules to improve the efficiency and flexibility of LVS rule detection. The detection method for LVS rules is described below. Figure 1 As shown, including but not limited to the following steps:

[0054] Step 110: Perform structured text representation on the layout netlist to be tested and the schematic netlist.

[0055] In this step, first obtain the layout netlist and schematic netlist to be tested. The layout netlist and schematic netlist contain the circuit component information, node connection relationship and other electrical properties. In order to enable the model to effectively understand these netlist information, first convert the netlist into a structured text format. This can be achieved in the following ways:

[0056] Layout netlist parsing: Parse the components, nodes, wires and their properties in the layout netlist to generate corresponding structured text. For example, each component can be represented as an object with a unique identifier, type (such as resistor, capacitor, etc.), port (pin) and connection relationship (such as power, ground, signal line, etc.). The connection relationship also needs to be described as the connection between nodes.

[0057] Schematic netlist analysis: Similarly, the components and connection relationships in the schematic netlist also need to be converted into structured text format. Each component and its connection information should be consistent with the layout netlist format to ensure consistency in subsequent processing. The component type, connection relationship and other information in the schematic netlist should also be converted into clear text expression.

[0058] Through this structured text representation, complex circuit design data in layouts and schematics can be simplified into text information that is easy to process and analyze.

[0059] Step 120: Perform prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information.

[0060] The purpose of this step is to guide the pre-trained large language model (such as BERT or GPT, etc.) to better understand the device attribute information and its design logic in the layout netlist and schematic netlist through the prompt word optimization operation. The specific implementation method is as follows:

[0061] The structured text representation obtained in step 110 is input into a prompt word optimization model. The prompt word optimization model aims to optimize prompt words to help the model understand the semantics of the input text more accurately. For example, specific prompt words can be set for different types of components (such as resistors, capacitors, transistors, etc.) so that the model can clearly identify and process the properties and functions of these components.

[0062] The loss function is used to optimize the prompt word parameters of the model. Specifically, the loss function can be minimized.

[0063] After the prompt word optimization, the target prompt word information is finally obtained. This prompt word information can effectively guide the LVS rule verification model to correctly parse the layout and schematic data.

[0064] Step 130: Retrieve LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word.

[0065] The core of this step is to use the target prompt word information to retrieve the relevant LVS rules in the rule database. The specific steps are as follows:

[0066] The rule database stores the rules required for LVS verification, including electrical connection rules, component matching rules, signal integrity rules, etc. Each rule usually contains relevant text descriptions, conditions and constraints.

[0067] The target prompt word information is encoded by the encoder and converted into a vector representation. The text representation of the layout netlist and the schematic netlist is also converted into a vector representation by the encoder.

[0068] Step 140: input the layout netlist to be tested, the schematic netlist and the LVS rule into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0069] In this step, the retrieved LVS rules are used to perform consistency check in combination with the layout netlist and schematic netlist to be tested. The specific steps are as follows:

[0070] The layout netlist and schematic netlist represented by the structured text obtained in step 110 and the LVS rules retrieved in step 130 are input into the LVS rule verification model. The LVS rule verification model uses this information to determine the consistency between the layout netlist and the schematic netlist.

[0071] The LVS rule verification model calculates the consistency of the layout netlist and the schematic netlist under each LVS rule and outputs the probability of violation.

[0072] According to the predicted violation probability, a preset threshold t is set. When the predicted violation probability is greater than the threshold, the layout netlist is considered inconsistent with the schematic netlist, otherwise they are considered consistent. Finally, the consistency verification result is generated.

[0073] As a further optional embodiment, the step of performing prompt word optimization operation on the text representation of the to-be-detected layout netlist and the schematic netlist to obtain target prompt word information specifically includes:

[0074] Inputting the text representation of the to-be-tested layout netlist and the schematic netlist into a prompt word optimization model to obtain target prompt word information;

[0075] The prompt word optimization model uses the following loss model to optimize prompt word parameters, specifically by minimizing the loss function to guide the LVS rule verification model to complete the LVS verification task:

[0076]

[0077] Among them, θ represents the parameters of the LVS rule verification model, N is the number of training samples, and x i is the layout netlist text or schematic netlist text, yi is the corresponding token sequence, p i is the input prompt word; p θ (y i |x i ,p i ) means that given the input text x i and the prompt word p i Under the condition of , the model generates the target token sequence y i The conditional probability, logp θ (y i |x i ,p i ) represents the generation sequence y described by natural logarithm i The log-likelihood probability.

[0078] First, the layout netlist and schematic netlist to be tested are parsed and converted into structured text representations. These structured text representations contain information about circuit components, port connection relationships, and electrical properties. Then, these text representations are input into the prompt word optimization model for processing.

[0079] The prompt word optimization model is a deep learning model based on natural language processing (NLP) technology. During the training process, it learns how to adjust and optimize prompt words according to different types of text content to guide the model to better understand the semantic features of the input text. By optimizing prompt words, the LVS rule verification model can be guided to more accurately process and identify the structure of the layout netlist and schematic netlist, helping the model understand the electrical properties and connection relationships of different components, thereby achieving better performance in the LVS verification process.

[0080] In this embodiment, the training process of the prompt word optimization model realizes the optimization of the prompt words by minimizing the following loss function:

[0081]

[0082] This loss function measures the difference between the token sequence generated by the model and the target token sequence by summing all training samples and calculating their log-likelihood probability. By minimizing this loss function, the model will continuously adjust and optimize the prompt word parameters, thereby more effectively guiding the LVS rule verification model to perform accurate reasoning when performing LVS verification tasks.

[0083] The optimization process of this loss function is designed to enable the prompt words to better represent the electrical and structural information of the netlist text, while helping the LVS rule verification model to identify the correct rule matching relationship when faced with different types of netlists, thereby improving the accuracy and efficiency of verification.

[0084] Specifically, this function is an unbiased estimate of the empirical risk, describing the average performance of the model over the entire training set. The negative sign in front transforms the problem into minimizing the negative log-likelihood, that is, maximizing the log-likelihood. This is because the optimizer usually minimizes the loss function, while in this model the probability of generating the true sequence is maximized. During the training process, most of the parameters θ of the pre-trained model are fixed, and only the newly introduced prompt parameter p is optimized i By minimizing this loss function, the model learns the optimal prompt parameter, which enables it to guide the pre-trained model to complete a specific LVS verification task.

[0085] From the perspective of information theory, minimizing this loss function is equivalent to minimizing the cross entropy between the model distribution and the true data distribution. Cross entropy describes the difference between two probability distributions and is an important indicator for measuring the degree of model fit. By minimizing cross entropy, the model learns parameters that are closer to the true data distribution, and the generated sequence is closer to the true sequence, making the predicted violations more accurate.

[0086] Through the above steps, prompt word optimization can effectively improve the LVS rule verification model's ability to understand the layout netlist and schematic netlist. The optimized target prompt word information can not only improve the semantic expression effect of text input, but also better identify and match related rules in subsequent LVS verification tasks. Finally, the purpose of improving the accuracy of LVS verification tasks is achieved, thus providing a reference for the layout and schematic netlist in the circuit design process. Figure 1 Consistency testing provides an intelligent and automated solution.

[0087] As a further optional embodiment, the step of retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in the rule database according to the target prompt word is implemented in the following manner:

[0088] h q =Encoder(q)

[0089]

[0090]

[0091] p(r i |q)=softmax(score i )

[0092] Among them, q is the textual representation of the layout netlist and schematic netlist to be tested, r i is the LVS rule in the rule database, h q is the encoding vector of the text representation of the layout netlist to be tested, is the encoding vector of the schematic netlist, hq =Encoder(q) means encoding q into a fixed-dimensional vector h through the encoder q , Indicates that r is converted by the encoder i Encoded as a fixed-dimensional vector Represents the calculation vector h q and vector The attention score between q and r i The correlation between q and r is obtained by learning the attention matrix W. i The interaction mode between i |q)=softmax(score i ) indicates that r is calculated based on the attention score i The conditional probability given q.

[0093] First, the text representation q of the layout netlist and schematic netlist to be tested is input into the encoder to obtain the corresponding encoding vector h q ; Next, each LVS rule in the rule database i It is also input into the encoder to obtain its corresponding encoding vector After obtaining the text representation vectors and rule text representation vectors of the layout netlist and schematic netlist to be detected, the correlation between them, i.e., the attention score, is calculated. The specific calculation method is:

[0094]

[0095] Finally, the conditional probability of the given layout netlist and schematic netlist text representation to be detected is calculated according to the attention score rule:

[0096] p(r i |q)=softmax(score i )

[0097] Through the above steps, the model can use the attention mechanism and LVS rules in the rule database to efficiently retrieve the text representation of the layout netlist and schematic netlist to be tested. This method can automatically calculate the correlation between the layout netlist and schematic netlist and the rules, thereby providing accurate rule matching for subsequent LVS verification.

[0098] Specifically, softmax normalization is applied to the attention scores of all rules to obtain a probability distribution that represents the probability of each rule being retrieved. The larger the probability value, the more relevant the rule is to the text representation and the more likely it is to be retrieved. In the inference phase, the top k rules with the largest conditional probabilities are selected as the final retrieval results for subsequent violation judgment. In the training phase, the attention matrix is ​​optimized by maximizing the conditional probability of the true rule so that it can learn a more accurate retrieval strategy.

[0099] The core idea of ​​RAG is to model the correlation between text representation and rules through the attention mechanism, and adaptively retrieve the most relevant rules from the massive rule base. Compared with the traditional retrieval method based on keyword matching, RAG can capture the semantic information of the text and achieve more intelligent and robust retrieval. At the same time, through end-to-end training, the attention matrix can be continuously optimized to continuously improve the retrieval quality.

[0100] As a further optional embodiment, after the step of searching the rule database for LVS rules related to the layout netlist to be detected and the schematic netlist according to the target prompt word, the method further includes:

[0101] Obtain the annotation data related to the LVS verification task;

[0102] The labeled data is input into the LVS rule verification model for meta-learning.

[0103] As a further optional embodiment, the step of inputting the labeled data into the LVS rule verification model for meta-learning is implemented in the following manner:

[0104]

[0105]

[0106] Among them, ф represents the parameters of the LVS rule verification model, p(T) is the task distribution, and T i is the task of sampling from p(T), For task T i The loss function on ф (x) is the LVS rule verification model with parameter фφ, x j For textual representation of layout and schematic, y j is the corresponding violation label, f ф (x j ) is the probability of model prediction violation, It means taking the expectation of all tasks in the task distribution p(T), that is, the average loss function value on each task.

[0107] In this embodiment, after the step of retrieving LVS rules related to the layout netlist and schematic netlist to be tested in the rule database according to the target prompt word, the method further includes obtaining annotation data related to the LVS verification task, and inputting the annotation data into the LVS rule verification model for meta-learning.

[0108] After completing the LVS rule retrieval related to the target prompt word, the next step is to obtain the annotated data related to the LVS verification task. The annotated data mainly contains a series of calibrated text representations of the layout netlist and schematic netlist and their corresponding violation labels (such as consistency violation and non-consistency violation). These annotated data are crucial for training the LVS rule verification model because they provide accurate supervision information for the model.

[0109] The annotation data can be obtained in the following ways:

[0110] Extract layout and schematic netlist text from verified circuit designs;

[0111] Use the existing LVS verification tool to verify the design and generate violation labels for each netlist text based on the verification results;

[0112] Generate labeled data using expert systems or manual labeling.

[0113] The annotated data obtained is usually paired text data (layout netlist text and schematic netlist text) and corresponding violation labels. These data will be used to train the LVS rule verification model.

[0114] After obtaining the labeled data, the next step is to input it into the LVS rule verification model for meta-learning. The goal of meta-learning is to enable the model to quickly adapt to new LVS verification tasks or new design domains when receiving a small amount of labeled data.

[0115] Specifically, meta-learning is trained with a small amount of labeled data, so that the model can learn how to extract key knowledge from new tasks and quickly migrate and adapt. In this embodiment, the LVS rule verification model is trained with labeled data to optimize its adaptability and accuracy to different designs.

[0116] The specific implementation steps of meta-learning can be achieved in the following ways:

[0117] For each LVS verification task, set a loss function Where T i are tasks sampled from the task distribution. For example, in each task, the model needs to learn from a small amount of labeled data. Learn LVS rules from the Schematic Netlist and generate violation predictions based on the input layout netlist and schematic netlist:

[0118]

[0119] By taking the expectation of the loss function of all training tasks, the model can learn more universal parameters so that it can adapt to different LVS verification tasks. Specifically, by calculating the expected loss of all tasks in the task distribution p(T):

[0120] Using the meta-learning framework, the LVS rule verification model will learn how to quickly adapt from different tasks. When encountering a new design or a new LVS verification task, the model can be quickly tuned based on existing experience and a small amount of new annotated data, thereby improving the verification accuracy of the new task.

[0121] The updated model can perform effective transfer learning with a small amount of newly annotated data, which significantly improves the execution speed and accuracy of the LVS verification task.

[0122] During the training process, the meta-learning objective function L(φ) is optimized, and the model parameter φ is updated through a small amount of labeled data so that it can quickly converge to the optimal value on the new task. Specifically, the following meta-learning algorithm is used:

[0123] a. In each meta-training step, a batch of tasks T is sampled from the task distribution p(T) i .

[0124] b. For each task T i , from its labeled data Sampling a support set and a queryset

[0125] c. In the support set Calculate the gradient and update the model parameters to obtain a task-specific model

[0126]

[0127] Among them, α is the meta-learning rate.

[0128] d. In the query set Evaluate task-specific models on Calculate the loss function value

[0129] e. Average the query set loss function values ​​of all tasks to get an estimate of the meta-learning objective function:

[0130]

[0131] f. Compute the gradient of the meta-learning objective function with respect to the model parameters φ and update φ using the meta-optimizer.

[0132] Through meta-learning, the large language LVS model has learned the ability to "learn how to learn new node LVS verification" and can quickly learn new tasks from a small amount of labeled data. This rapid adaptability is crucial for LVS verification, because process nodes and design styles are constantly evolving, and manual adjustment of the model is very costly. Meta-learning enables the model to have adaptive capabilities, greatly reducing the burden of model migration and maintenance.

[0133] Meta-learning is a key technology to enable large language models to quickly adapt to new LVS tasks. By optimizing the meta-learning objective function, the model has mastered the ability to quickly learn from a small amount of labeled data, while also having stronger robustness and generalization. This enables large language models to flexibly respond to various challenges in LVS verification, greatly improving verification efficiency and quality.

[0134] This embodiment introduces a meta-learning method to enable the LVS rule verification model to quickly adapt to and efficiently complete LVS verification tasks when faced with new tasks or new design fields. Through training with a small amount of labeled data, the model can learn key information from different LVS tasks, improving the intelligence and automation level of the verification process.

[0135] As a further optional embodiment, the step of inputting the layout netlist to be tested, the schematic netlist and the LVS rule into the LVS rule verification model to determine the consistency of the layout netlist to be tested and the schematic netlist specifically includes:

[0136] Inputting the layout netlist to be tested, the schematic netlist and the LVS rule into the LVS rule verification model to obtain a predicted violation probability;

[0137] When the predicted violation probability is greater than a preset threshold, the layout netlist to be checked is inconsistent with the schematic netlist.

[0138] As a further optional embodiment, the step of inputting the to-be-checked layout netlist, the schematic netlist and the LVS rule into the LVS rule verification model to obtain the predicted violation probability is implemented in the following manner:

[0139] p(y|x)=sigmoid(f ф (x))

[0140] The step of determining that the layout netlist to be detected is inconsistent with the schematic netlist when the predicted violation probability is greater than a preset threshold is implemented in the following manner:

[0141]

[0142] Where x is the text representation of the layout netlist and schematic netlist to be checked, y∈(0,1) is the violation label, and f ф (x) is the LVS rule verification model, sigmoid is the activation function, t is the judgment threshold, and I is the indicator function; p(y|x)=sigmoid(f ф (x)) represents the probability of violation predicted by the LVS rule verification model. It means that the final violation prediction result is generated according to the prediction probability p(y|x) and the judgment threshold t.

[0143] First, the layout netlist, schematic netlist and LVS rules to be checked are used as input data and input into the LVS rule verification model. After the verification model is trained, it can predict the consistency between the two based on the input layout netlist text, schematic netlist text and LVS rule information, and output the predicted violation probability. The violation probability reflects the possibility of inconsistency between the layout and the schematic.

[0144] Assume that the input data is x (including the text representation of the layout netlist and the schematic netlist) and the corresponding LVS rules, and the LVS rule verification model f ф (x) processes the input data and outputs a violation probability p(y|x), which represents the probability of a violation between the layout netlist and the schematic netlist. This probability is calculated using the output function of the model (e.g., the sigmoid function):

[0145] p(y|x)=sigmoid(f ф (x))

[0146] For the output violation probability, the system will compare it with the preset threshold t. When the predicted violation probability p(y|x) is greater than the threshold, it means that there is an inconsistency between the layout netlist to be tested and the schematic netlist, that is, the verification result shows that they are inconsistent. At this time, the violation prediction result is generated.

[0147]

[0148] Specifically, the text representation x of the layout and schematic is first input into the model to obtain a scalar output f φ (x). The output is compressed into the range of (0,1) through the sigmoid function to obtain the predicted probability of violation p(y|x). The sigmoid function is defined as:

[0149]

[0150] It can map real numbers into the interval (0,1).

[0151] Indicates that the final violation prediction result is generated based on the predicted probability p(y|x) and the judgment threshold T Among them, the indicator function I is defined as:

[0152]

[0153] When the predicted probability is greater than the threshold, it is considered a violation. Otherwise, it is considered as non-violation. The threshold T can be adjusted according to actual needs to balance the recall rate and accuracy of violation detection.

[0154] In the inference phase, the textual representations x of the layout and schematic are fed into the fine-tuned model f φ In the above example, the violation probability p(y|x) is calculated, and the final prediction result is generated according to the judgment threshold T. This process can be efficiently applied to large-scale LVS verification tasks to automatically detect potential violations.

[0155] Compared with the traditional rule-based LVS method, the large language LVS model can learn more complex and implicit violation patterns. Through pre-training on large-scale text data and fine-tuning on specific tasks, the large language model has mastered rich layout and schematic semantic information and design rule knowledge. In the reasoning stage, the model can comprehensively use this knowledge to perform comprehensive violation checks on new designs and capture content that is difficult to cover by rules.

[0156] In addition, the violation judgment method based on probability prediction also brings additional advantages. Unlike deterministic rules, probability prediction can quantify the possibility of violations and provide engineers with more detailed risk assessment. By adjusting the judgment threshold, the strictness of violation detection can be flexibly controlled, the recall rate and accuracy can be balanced, and different design scenarios and requirements can be adapted.

[0157] The detection device of the LVS rule provided by the present invention is described below. Figure 2 As shown, the detection device of the LVS rule described below and the detection method of the LVS rule described above can refer to each other.

[0158] A detection device for LVS rules, comprising:

[0159] The netlist acquisition module 210 is used to acquire the layout netlist and the schematic netlist to be tested;

[0160] A text conversion module 220, used for expressing the to-be-tested layout netlist and the schematic netlist in structured text;

[0161] A prompt word optimization module 230 is used to perform a prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0162] A rule retrieval module 240 is used to retrieve LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0163] The rule checking module 250 is used to input the layout netlist to be checked, the schematic netlist and the LVS rules into the LVS rule checking model to determine the consistency between the layout netlist to be checked and the schematic netlist.

[0164] Figure 3 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 3 As shown, the electronic device may include: a processor 310, a communications interface 320, a memory 330 and a communication bus 340, wherein the processor 310, the communications interface 320 and the memory 330 communicate with each other through the communication bus 340. The processor 310 may call the logic instructions in the memory 330 to execute the detection method of the LVS rule, and the method includes:

[0165] Representing the to-be-tested layout netlist and the schematic netlist in structured text;

[0166] Performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0167] Retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0168] The layout netlist to be tested, the schematic netlist and the LVS rule are input into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0169] In addition, the logic instructions in the above-mentioned memory 330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0170] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored in a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the LVS rule detection method provided by the above methods, the method includes:

[0171] Representing the to-be-tested layout netlist and the schematic netlist in structured text;

[0172] Performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0173] Retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0174] The layout netlist to be tested, the schematic netlist and the LVS rule are input into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0175] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the computer program is executed by a processor to perform the LVS rule detection method provided by the above methods, the method comprising:

[0176] Representing the to-be-tested layout netlist and the schematic netlist in structured text;

[0177] Performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information;

[0178] Retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word;

[0179] The layout netlist to be tested, the schematic netlist and the LVS rule are input into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

[0180] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0181] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting LVS rules, characterized in that: include: Obtain the layout netlist and schematic netlist to be tested; Representing the to-be-tested layout netlist and the schematic netlist in structured text; Performing prompt word optimization operation on the text representation of the layout netlist to be detected and the schematic netlist to obtain target prompt word information; Retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word; The layout netlist to be tested, the schematic netlist and the LVS rule are input into an LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

2. The method for detecting LVS rules according to claim 1, characterized in that: The step of performing prompt word optimization operation on the text representation of the to-be-detected layout netlist and the schematic netlist to obtain target prompt word information specifically includes: Inputting the text representation of the to-be-tested layout netlist and the schematic netlist into a prompt word optimization model to obtain target prompt word information; The prompt word optimization model uses the following loss model to optimize prompt word parameters, specifically by minimizing the loss function to guide the LVS rule verification model to complete the LVS verification task: Among them, θ represents the parameters of the LVS rule verification model, N is the number of training samples, and x i is the layout netlist text or schematic netlist text, y i is the corresponding token sequence, p i is the input prompt word; p θ (y i |x i ,p i ) means that given the input text x i and the prompt word p i Under the condition of , the model generates the target token sequence y i The conditional probability, logp θ (y i |x i ,p i ) represents the generation sequence y described by natural logarithm i The log-likelihood probability.

3. The method for detecting LVS rules according to claim 1, characterized in that: The step of searching the LVS rules related to the to-be-detected layout netlist and the schematic netlist in the rule database according to the target prompt word is implemented in the following manner: h q =Encoder(q) p(r i |q)=softmax(score i ) Among them, q is the textual representation of the layout netlist and schematic netlist to be tested, r i is the LVS rule in the rule database, h q is the encoding vector of the text representation of the layout netlist to be tested, is the encoding vector of the schematic netlist, h q =Encoder(q) means encoding q into a fixed-dimensional vector h through the encoder q , Indicates that r is converted by the encoder i Encoded as a fixed-dimensional vector Represents the calculation vector h q and vector The attention score between q and r i The correlation between q and r is obtained by learning the attention matrix W. i The interaction mode between i |q)=softmax(score i ) indicates that r is calculated based on the attention score i The conditional probability given q.

4. The method for detecting LVS rules according to claim 1, characterized in that: After the step of searching the rule database for LVS rules related to the layout netlist to be tested and the schematic netlist according to the target prompt word, the method further includes: Obtain the annotation data related to the LVS verification task; The labeled data is input into the LVS rule verification model for meta-learning.

5. The method for detecting LVS rules according to claim 4, characterized in that: The step of inputting the labeled data into the LVS rule verification model for meta-learning is achieved in the following manner: Among them, ф represents the parameters of the LVS rule verification model, p(T) is the task distribution, and T i is the task of sampling from p(T), For task T i The loss function on ф (x) is the LVS rule verification model with parameter фφ, x j For textual representation of layout and schematic, y j is the corresponding violation label, f ф (x j ) is the probability of model prediction violation, It means taking the expectation of all tasks in the task distribution p(T), that is, the average loss function value on each task.

6. The method for detecting LVS rules according to claim 1, characterized in that: The step of inputting the layout netlist to be tested, the schematic netlist and the LVS rule into the LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist specifically includes: Inputting the layout netlist to be tested, the schematic netlist and the LVS rule into the LVS rule verification model to obtain a predicted violation probability; When the predicted violation probability is greater than a preset threshold, the layout netlist to be checked is inconsistent with the schematic netlist.

7. The method for detecting LVS rules according to claim 6, characterized in that: The step of inputting the to-be-checked layout netlist, the schematic netlist and the LVS rule into the LVS rule verification model to obtain the predicted violation probability is achieved by: p(y|x)=sigmoid(f ф (x)) The step of determining that the layout netlist to be detected is inconsistent with the schematic netlist when the predicted violation probability is greater than a preset threshold is implemented in the following manner: Where x is the text representation of the layout netlist and schematic netlist to be checked, y∈(0,1) is the violation label, and f ф (x) is the LVS rule verification model, sigmoid is the activation function, t is the judgment threshold, and I is the indicator function; p(y|x)=sigmoid(f ф (x)) represents the probability of violation predicted by the LVS rule verification model. It means that the final violation prediction result is generated according to the prediction probability p(y|x) and the judgment threshold t.

8. A detection device for LVS rules, characterized in that: include: A netlist acquisition module is used to obtain the layout netlist and schematic netlist to be tested; A text conversion module, used for expressing the to-be-tested layout netlist and the schematic netlist in structured text; A prompt word optimization module is used to perform prompt word optimization operations on the text representations of the layout netlist to be detected and the schematic netlist to obtain target prompt word information; A rule retrieval module, used for retrieving LVS rules related to the layout netlist to be detected and the schematic netlist in a rule database according to the target prompt word; The rule verification module is used to input the layout netlist to be tested, the schematic netlist and the LVS rules into the LVS rule verification model to determine the consistency between the layout netlist to be tested and the schematic netlist.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method for detecting the LVS rule according to any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for detecting the LVS rule according to any one of claims 1 to 7 is implemented.

Images