Display panel, display device and equipment

Abstract

The invention provides a display panel, a display device and equipment. The display panel comprises a display area and a non-display area, a plurality of signal lines arranged in the first direction are arranged in the display area, and a plurality of shift register units electrically connected with the signal lines are arranged in the non-display area. The display area comprises a first display area and a second display area which are arranged in the first direction. The second display area comprises a chamfering area, and a boundary line, adjacent to the non-display area, of the chamfering area is a first boundary line. The non-display area comprises a first area and a second area which are adjacent in the first direction, the first area is adjacent to the first display area, the second area is adjacent to the second display area in the second direction, and the second direction intersects with the first direction. The boundary line of the second area adjacent to the display area is a second boundary line, and the first boundary line covers the second boundary line. The projection of the shift register unit in the third direction is not overlapped with the second area, and the third direction is perpendicular to the first direction and the second direction. At least part of the shift register units are arranged in the first area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a display device and equipment. Background Art

[0002] As consumer demand increases, the borders of display panels are required to be narrower and narrower. However, in existing display panels, when the width of the top, bottom, left, and right borders is extremely narrow, the width of the borders at the corners cannot be reduced to the ideal width due to the influence of the circuit layout. Therefore, the circuit layout at the corners of the display panel needs to be further optimized. Summary of the invention

[0003] The purpose of the present application is to provide a display panel, a display device and an apparatus. The present application is to solve the problem in the prior art that the frame width at the corner position of the display panel needs to be further optimized.

[0004] The first aspect of the present application provides a display panel, including a display area and a non-display area, wherein the display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units, and the shift register units are electrically connected to the corresponding signal lines. The display area includes a first display area and a second display area, and the first display area and the second display area are arranged along the first direction. The second display area includes a chamfered area, and the boundary line adjacent to the chamfered area and the non-display area is a first boundary line. The non-display area includes a first area and a second area, the first area is adjacent to the first display area along the second direction, and the second area is adjacent to the second display area along the second direction, the second direction intersects with the first direction, and the first area is adjacent to the second area along the first direction. The boundary line adjacent to the display area of ​​the second area is the second boundary line, and the first boundary line covers the second boundary line. Wherein, the projection of the shift register unit along the third direction does not overlap with the second area, and the third direction is perpendicular to the first direction and the second direction. And at least some of the shift register units among the plurality of shift register units are arranged in the first area.

[0005] In a possible implementation of the first aspect, a plurality of pixel circuits are provided in the display area, the pixel circuits include a plurality of transistors, and the signal line is electrically connected to the gates of at least some of the transistors. A projection of the pixel circuit along a third direction is a first projection, and a length of the first projection along the first direction is a first length. A projection of at least some of the shift register units along the third direction is a second projection, and a length of the second projection along the first direction is a second length. The first length is greater than the second length.

[0006] In a possible implementation of the first aspect, the first area includes a first sub-area and a second sub-area, and the second sub-area is located between the first sub-area and the second area. The projection of the shift register unit located in the first sub-area along the third direction is the first sub-projection. The projection of the shift register unit located in the second sub-area along the third direction is the second sub-projection. The length of the first sub-projection along the first direction is the first sub-length, the length of the second sub-projection along the first direction is the second sub-length, the first sub-length is not equal to the second length, and the first sub-length is less than the first length, and the second sub-length is less than the first length.

[0007] In a possible implementation of the first aspect, the first area includes a third sub-area and a fourth sub-area, and the fourth sub-area is located between the third sub-area and the second area. The projection of the shift register unit located in the third sub-area along the third direction is the first sub-projection. The projection of the shift register unit located in the fourth sub-area along the third direction is the second sub-projection. The distance between two adjacent first sub-projections along the first direction in the first direction is the first distance. The distance between two adjacent second sub-projections along the first direction in the first direction is the second distance. The second distance is less than or equal to the first distance.

[0008] In a possible implementation manner of the first aspect, the first distance is greater than zero, and the second distance is greater than or equal to zero. The second distance is smaller than the first distance.

[0009] In a possible implementation of the first aspect, a plurality of pixel circuits are arranged in the display area, the pixel circuits include a plurality of transistors, and the signal line is electrically connected to the gates of at least some of the transistors; the projection of the pixel circuit along the third direction is a first projection, and the length of the first projection along the first direction is a first length; the first length is the sum of the second length and the first distance.

[0010] In a possible implementation manner of the first aspect, the first distance and the second distance are both zero.

[0011] In a possible implementation manner of the first aspect, a dummy shift register unit is further included, and the dummy shift register unit is located on a side of the shift register unit close to the second area. The dummy shift register unit is electrically insulated from any signal line.

[0012] In a possible implementation of the first aspect, some of the shift register units among the plurality of shift register units are electrically connected to corresponding signal lines through a first connecting line. The first connecting line includes a first connecting portion and a second connecting portion, the first connecting portion is electrically connected to the second connecting portion, the first connecting portion is located in a non-display area, and the second connecting portion is located in a display area. The second connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is electrically connected to the second sub-portion. The first sub-portion extends along the second direction, and the second sub-portion extends along the first direction.

[0013] In a possible implementation manner of the first aspect, one end of the second sub-section is connected to the first sub-section, and the other end of the second sub-section is connected to the corresponding signal line.

[0014] In a possible implementation manner of the first aspect, the second sub-section includes a first node, and the first node is a connection point where the second sub-section is connected to the first sub-section. The first node is located between two endpoints of the second sub-section.

[0015] In a possible implementation of the first aspect, the second connecting portion further includes a third sub-portion, the third sub-portion extends along the second direction, one end of the third sub-portion is connected to the second sub-portion, and the other end of the third sub-portion is electrically connected to the corresponding signal line.

[0016] In a possible implementation of the first aspect, some of the shift register units are electrically connected to the corresponding signal line through a second connecting line. The second connecting line includes a third connecting portion and a fourth connecting portion, and the third connecting portion is electrically connected to the fourth connecting portion. The third connecting portion is located in the first area and is electrically connected to the shift register unit, and the fourth connecting portion is located in the second area and is electrically connected to the signal line.

[0017] In a possible implementation of the first aspect, some of the shift register units in the plurality of shift register units are electrically connected to the corresponding signal line through a third connection line. The third connection line includes a first sub-connection line and a second sub-connection line. The first sub-connection line is electrically connected to the second sub-connection line. The resistivity of the first sub-connection line is different from the resistivity of the second sub-connection line.

[0018] In a possible implementation of the first aspect, some of the shift register units are electrically connected to corresponding signal lines through a common connection line, one end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to the corresponding at least two signal lines.

[0019] In the second aspect, the present application provides a display panel, comprising: a display area and a non-display area. The display area includes a plurality of signal lines arranged along a first direction, and the non-display area includes a plurality of shift register units, and the shift register units are electrically connected to the corresponding signal lines. The display area includes a first display area and a second display area, and the first display area and the second display area are arranged along the first direction. The second display area includes a chamfered area, and the boundary line adjacent to the chamfered area and the non-display area is a first boundary line. The non-display area includes a first area and a second area, the first area is adjacent to the first display area along the second direction and the second area is adjacent to the display area along the second direction, the second direction intersects with the first direction, and the first area and the second area are adjacent to the first direction. The boundary line adjacent to the display area of ​​the second area is a second boundary line, and the second boundary line covers the first boundary line. Among them, a plurality of common connection lines are arranged in the second area, one end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to the corresponding at least two signal lines.

[0020] In a possible implementation of the second aspect, among the plurality of common connection lines, at least some of the common connection lines include a first sub-connection line and a second sub-connection line, the first sub-connection line is electrically connected to the second sub-connection line, and the resistivity of the first sub-connection line is different from the resistivity of the second sub-connection line.

[0021] In a possible implementation manner of the second aspect, the first area includes a plurality of shift register units, and the second area includes a plurality of shift register units.

[0022] In a possible implementation manner of the second aspect, the signal line includes a data writing control scanning signal line, and the common connection line is electrically insulated from any data writing control scanning signal line.

[0023] According to a third aspect, the present application provides a display device, comprising the display panel according to the first aspect or the second aspect.

[0024] In a fourth aspect, the present application provides a device, comprising the display panel of the first aspect or the second aspect or the display device of the third aspect.

[0025] Compared with the prior art, in the present application, no shift register unit is provided in the second area, that is, no shift register unit is provided in the area of ​​the non-display area of ​​the display panel near the corner position of the display area. Since no shift register unit is provided in the second area, the width of the second area at the corner position can be reduced, thereby reducing the width of the area at the corner position. Alternatively, the present application parallels multiple common connection lines located in the second area, which can reduce the total number of common connection lines located in the second area, and then can reduce the width of the second area at the corner position to optimize the width of the area at the corner position. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the corner area of ​​a display panel in the prior art.

[0027] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present application.

[0028] Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application.

[0029] Figure 4 A schematic diagram of a display panel provided in an embodiment of the present application.

[0030] Figure 5 A schematic diagram of a display panel provided in an embodiment of the present application.

[0031] Figure 6 A schematic diagram of a display panel provided in an embodiment of the present application.

[0032] Figure 7 A schematic diagram of a display panel provided in an embodiment of the present application.

[0033] Figure 8 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0034] Fig. 9 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0035] Fig.10 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0036] Fig.11 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0037] Fig.12 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0038] Fig.13 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0039] Fig.14 A schematic diagram of a display panel provided in an embodiment of the present application.

[0040] Fig.15 Provided in the embodiments of this application Fig.14 A partial enlarged view of area B in the middle.

[0041] Fig.16 A schematic diagram of a display panel provided in an embodiment of the present application.

[0042] Fig.17 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the C area in the middle.

[0043] Fig.18 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the C area in the middle.

[0044] Fig.19 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the D area in the middle.

[0045] Fig. 20 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the D area in the middle.

[0046] Fig.21 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the D area in the middle.

[0047] Fig. 22 A schematic diagram of a display device provided in an embodiment of the present application.

[0048] Description of Reference Numerals

[0049] NA-non-display area; NA1-first area; NA11-first sub-area; NA12-second sub-area; NA13-third sub-area; NA131-first sub-area; NA132-second sub-area; NA14-fourth sub-area; NA2-second area; AA display area; AA1-first display area; AA2-second display area; 100, display panel; 101, shift register unit; 102-signal line; 103-dummy Shift register unit; 104-pixel circuit; 110-first connecting line; 111-first connecting part; 112-second connecting part; 1121-first sub-part; 1122-second sub-part; 1123-third sub-part; 120-second connecting line; 121-third connecting part; 122-fourth connecting part; 130-third connecting line; 131-first sub-connecting line; 132-second sub-connecting line; 140-common connecting line; 200-display device. DETAILED DESCRIPTION

[0050] Figure 1It is a schematic diagram of the corner area of ​​a display panel in the prior art.

[0051] See also Figure 1 In order to reduce the width of the corner area, the existing display panel adopts a chamfer design at the corner position of the display area and the non-display area of ​​the display panel, that is, the corners of the display area or the non-display area are chamfered. At the same time, in order to reduce the width of the chamfered position, the shift register circuit in the chamfered area of ​​the non-display area is arranged along the chamfered fan-shaped or arc-shaped arrangement. Based on this, the applicant found that the main reason why the width of the frame of the display panel at the corner position is difficult to reduce is that there are many lines and complex wiring in the corner area of ​​the non-display area, and a shift register unit 101 for driving the pixel circuit 104 at the corner position of the display area is also provided in the area. Both the multiple lines with complex wiring and the shift register unit 101 occupy a large amount of space, and in order to ensure the normal operation of the pixel circuit 104 at the corner position of the display panel, the width of this area cannot be further shortened.

[0052] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present application. Figure 3 A schematic diagram of a display panel provided in an embodiment of the present application.

[0053] like Figures 2 to 3 As shown, the present application provides a display panel 100, including a display area AA and a non-display area NA, wherein the display area AA includes a plurality of signal lines 102 arranged along a first direction X, and the non-display area NA includes a plurality of shift register units 101, and the shift register units 101 are electrically connected to the corresponding signal lines 102. The display area AA includes a first display area AA1 and a second display area AA2, wherein the first display area AA1 and the second display area AA2 are arranged along the first direction X. The second display area AA2 includes a chamfered area, and the boundary line between the chamfered area and the non-display area NA is a first boundary line. The non-display area NA includes a first area NA1 and a second area NA2, wherein the first area NA1 is adjacent to the first display area AA1 along a second direction Y and the second area NA2 is adjacent to the second display area AA2 along a second direction Y, wherein the second direction Y intersects the first direction X, and the first area NA1 and the second area NA2 are adjacent to each other along the first direction X. The boundary line between the second area NA2 and the display area AA is a second boundary line, and the first boundary line covers the second boundary line. The projection of the shift register unit 101 along the third direction does not overlap with the second area NA2 , and the third direction is perpendicular to the first direction X and the second direction Y. At least some of the shift register units 101 are disposed in the first area NA1 .

[0054] like Figure 2 As shown, the shift register unit 101 may be disposed in the first area NA1 on one side of the first display area AA1. Figure 3 As shown, the shift register unit 101101 can be disposed in the first area NA1 on both sides of the first display area AA1.

[0055] Compared with the prior art, the present application does not provide a shift register unit 101 in the second area NA2, that is, the shift register unit 101 is not provided in the area of ​​the non-display area NA of the display panel 100 near the corner position of the display area AA. Since the shift register unit 101 is not provided in the second area NA2, the width of the second area NA2 at the corner position can be reduced, thereby reducing the width of the area at the corner position.

[0056] In some embodiments of the present application, the signal line 102 may be a scanning signal line 102, such as a light-emitting control scanning signal line 102, a reset control scanning signal line 102, and a data writing control scanning signal line 102; the first direction X is perpendicular to the second direction Y. The light-emitting control scanning signal line 102 is electrically connected to the gate of the light-emitting control transistor in the corresponding pixel circuit 104, and is used to control the pixel circuit 104 to turn on so that the light-emitting element emits light. The reset control scanning signal line 102 is electrically connected to the gate of the reset transistor in the corresponding pixel circuit 104, and is used to control the reset of the pixel circuit 104. The data writing control scanning signal line 102 is electrically connected to the gate of the data writing transistor in the corresponding pixel circuit 104, and is used to control the writing of the data voltage. The pixel circuit 104 refers to a driving circuit electrically connected to the light-emitting element, and the light-emitting element can emit light under the drive of the pixel circuit 104.

[0057] In one embodiment of the present application, the first boundary line coincides with the second boundary line.

[0058] In an implementation of this embodiment, the first boundary line is an arc line, and the boundary line of the first area NA1 is a rectangle, that is, the chamfer of the display area AA is a rounded corner, and the chamfered area is a rounded corner area.

[0059] In one embodiment of the present application, among the plurality of shift register units 101 located in the first area NA1, at least some of the shift register units 101 are electrically connected to the signal lines 102 located in the second display area AA2. That is, at least some of the shift register units 101 electrically connected to the signal lines 102 in the second display area AA2 are located in the first area NA1, thereby reducing the number of shift register units 101 in the corner area of ​​the display panel 100, which helps to reduce the width of the display panel 100 at the corner position.

[0060] Figure 4 A schematic diagram of a display panel provided in an embodiment of the present application; Figure 5 A schematic diagram of a display panel provided in an embodiment of the present application.

[0061] like Figures 4 to 5 As shown, in one embodiment of the present application, a plurality of pixel circuits 104 are disposed in the display area AA, the pixel circuits 104 include a plurality of transistors, and the signal line 102 is electrically connected to the gates of at least some of the transistors. The projection of the pixel circuit 104 along the third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least part of the shift register unit 101 along the third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is greater than the second length L2.

[0062] In this embodiment, the first length L1 is greater than the second length L2, which can ensure that there is a difference in the length of the space occupied by the shift register unit 101 and the pixel circuit in the first direction X. This difference can provide space for inserting the shift register unit 101 corresponding to the pixel circuit 104 located in the corner area in the first area NA1.

[0063] In such Figure 4 As shown, in one embodiment of the present application, the first area NA1 includes a first sub-area NA11 and a second sub-area NA12, and the second sub-area NA12 is located between the first sub-area NA11 and the second area NA2. The projection of the shift register unit 101 located in the first sub-area NA11 along the third direction is the first sub-projection. The projection of the shift register unit 101 located in the second sub-area NA12 along the third direction is the second sub-projection. The length of the first sub-projection along the first direction X is the first sub-length L21, and the length of the second sub-projection along the first direction X is the second sub-length L22. The first sub-length L21 is not equal to the second length L2, and the first sub-length L21 is less than the first length L1, and the second sub-length L22 is less than the first length L1.

[0064] In this embodiment, the shift register unit 101 is designed with different sizes, which can help improve space utilization.

[0065] In one embodiment of the present application, a plurality of pixel circuits 104 are disposed in the display area AA, the pixel circuits 104 include a plurality of transistors, and the signal line 102 is electrically connected to the gates of at least some of the transistors. The projection of the pixel circuit 104 along the third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least part of the shift register unit 101 along the third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is less than or equal to the second length L2.

[0066] In a possible implementation of this embodiment, the first sub-length L21 is greater than the second sub-length L22. That is, compared with the shift register circuit that provides the driving signal to the pixel circuit 104 in the first display area AA1, the size of the shift register unit that provides the driving signal to the pixel circuit 104 in the chamfer area is smaller. Since the number of pixel circuits 104 in the chamfer area is small, the size of the shift register unit 101 that provides the driving signal to it (that is, the shift register unit 101 located in the second sub-area NA12) can be made smaller, so that the space can be used more reasonably and the space utilization rate can be improved.

[0067] like Figure 5 As shown, the lengths of the second projections along the first direction X are equal. This design is conducive to process implementation.

[0068] like Figure 5 As shown, in one embodiment of the present application, the first area NA1 includes a third sub-area NA13 and a fourth sub-area NA14, and the fourth sub-area NA14 is located between the third sub-area NA13 and the second area NA2. The projection of the shift register unit 101 located in the third sub-area NA13 along the third direction is the first sub-projection. The projection of the shift register unit 101 located in the fourth sub-area NA14 along the third direction is the second sub-projection. The distance between two adjacent first sub-projections along the first direction X in the first direction X is the first distance D1. The distance between two adjacent second sub-projections along the first direction X in the first direction X is the second distance D2. The second distance D2 is less than or equal to the first distance D1.

[0069] In this embodiment, the third sub-area NA13 is located in the middle of the first area NA1, and the fourth sub-area NA14 is located at the end of the first area NA1. For example, the third sub-area NA13 is located at the periphery of the first display area AA1, and the fourth sub-area NA14 is located on one side of the second display area AA2. Among them, the first display area AA1 is the straight line portion of the display area AA. The second display area AA2 is the side close to the inner corner area of ​​the display area AA. The arrangement density of the first shift register unit 101 in the third sub-area NA13 is less than or equal to the arrangement density of the second shift register unit 101 in the fourth sub-area NA14. This design can facilitate the realization of: without affecting the display effect, all the shift register units 101 are set in the first area NA1.

[0070] In an embodiment of the present application, the first distance D1 is greater than zero, and the second distance D2 is greater than or equal to zero. The second distance D2 is smaller than the first distance D1.

[0071] In this embodiment, the arrangement density of the shift register units 101 is differentiated in the first area NA1: the arrangement density of the shift register units 101 in the middle of the first area NA1 is less than the arrangement density at both ends of the first area NA1. This differentiation can further facilitate the realization of: all the shift register units 101 are arranged in the first area NA1 without affecting the display effect.

[0072] In an embodiment of the present application, the first distance D1 is equal to the second distance D2, and both the first distance D1 and the second distance D2 are greater than zero.

[0073] In this embodiment, the shift register units 101 in the first area NA1 are evenly distributed, which can simplify the manufacturing process and reduce the manufacturing cost.

[0074] In one embodiment of the present application, a plurality of pixel circuits 104 are disposed in the display area AA, the pixel circuits 104 include a plurality of transistors, the signal line 102 is electrically connected to the gates of at least some of the transistors; the projection of the pixel circuit 104 along the third direction is the first projection, and the length of the first projection along the first direction X is the first length. The first length L1 is the sum of the second length L2 and the first distance D1.

[0075] In this embodiment, the first length L1 is the sum of the second length L2 and the first distance D1. This design can achieve: along the first direction X, the shift register unit 101 in the middle of the first area NA1 corresponds to the pixel unit in the first display area AA1 in a one-to-one correspondence. This design facilitates the wiring of the connection line between the shift register unit 101 in the middle of the first area NA1 and the corresponding signal line 102.

[0076] Figure 6 A schematic diagram of a display panel provided in an embodiment of the present application.

[0077] like Figure 6 As shown, in one embodiment of the present application, the first distance D1 and the second distance D2 are both zero.

[0078] In this embodiment, the shift register units 101 in the first area NA1 are closely arranged in the first direction X. The closely arranged arrangement can save occupied area, so as to ensure that the shift register units 101 can be located only in the first area NA1.

[0079] In one embodiment of the present application, any shift register unit 101 in the first area NA1 is electrically connected to the corresponding signal line 102. That is, all shift register units 101 in the first area NA1 are valid and can output valid signals to the corresponding signal line 102. This design can maximize the use of the space in the first area NA1.

[0080] In an embodiment of the present application, the display panel 100 further includes a dummy shift register unit 103 , which is located on a side of the shift register unit 101 close to the second area NA2 . The dummy shift register unit 103 is electrically insulated from any signal line 102 .

[0081] In the embodiment, the dummy shift register does not output a valid signal. The purpose of the dummy shift register unit 103 is to ensure the stability of the working performance of the shift register unit 101 electrically connected to the signal line 102 at the inner edge of the first area NA1.

[0082] Figure 7 A schematic diagram of a display panel provided in an embodiment of the present application.

[0083] like Figure 6 or Figure 7 As shown, in one embodiment of the present application, the display panel 100 further includes a dummy shift register unit 103. The dummy shift register unit 103 is located in the third sub-region NA13 and on a side of the shift register unit 101 close to the fourth sub-region NA14. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0084] In this embodiment, the dummy shift register unit 103 is used to compensate for the difference in total length between the pixel circuit in the first display area AA1 and the shift register unit 101 in the third sub-area NA13 in the first direction X, so as to facilitate the wiring of the shift register in the fourth sub-area.

[0085] In a possible implementation of the present embodiment, in the first direction X, all the shift register units 101 in the third sub-region NA13 are arranged uniformly, and a dummy shift register unit 103 is provided between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The dummy shift register unit 103 can ensure the performance of the shift register unit 101 located near the edge of the fourth sub-region NA14, and improve the stability of the shift register unit 101 when working.

[0086] like Figure 7 As shown, in one embodiment of the present application, the third sub-region NA13 includes: a first sub-region NA131 and a second sub-region NA132, the second sub-region NA132 is located between the third sub-region 1123 and the fourth sub-region NA14, and all the shift register units 101 in the third sub-region NA13 are located in the first sub-region NA131. It can be understood that the shift register unit 101 is not provided in the second sub-region NA132.

[0087] In the present embodiment, the shift register unit 101 is not provided in the second sub-region NA132. This design is conducive to the realization that within the preset length in the first direction X, the shift register unit 101 in the third sub-region NA13 corresponds to the region of the pixel circuit 104 in the first display area AA1. This design can form an isolation between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The arrangement pitch of the shift register unit 101 in the first sub-region NA131 is not necessarily the same as the arrangement pitch of the shift register unit 101 in the fourth sub-region NA14, and this isolation can effectively reduce the adverse effects caused by the different arrangement pitches.

[0088] like Figure 7 As shown, in one implementation of the present embodiment, a dummy shift register unit 103 is provided in the first sub-region NA131, and a dummy shift register unit 103 is provided in the second sub-region NA12. The dummy shift register unit 103 in the first sub-region NA131 is located on the side of the shift register unit 101 (valid shift register unit 101) close to the second sub-region NA132; the dummy shift register unit 103 in the fourth sub-region is located on the side of the shift register unit 101 (valid shift register unit 101) close to the second sub-region NA132. This design can ensure the electrical stability of the valid shift register unit 101 in the first sub-region NA131 and the second sub-region NA12 when they are in working state.

[0089] Figure 8 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A. Fig. 9 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A. Fig.10 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0090] like Figures 8 to 10As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the first connection line 110. The first connection line 110 includes a first connection portion 111 and a second connection portion 112, the first connection portion 111 is electrically connected to the second connection portion 112, the first connection portion 111 is located in the non-display area NA, and the second connection portion 112 is located in the display area AA. The second connection portion 112 includes a first sub-portion 1121 and a second sub-portion 1122, the first sub-portion 1121 is electrically connected to the second sub-portion 1122. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X.

[0091] like Figures 8 to 10 As shown, in one implementation of this embodiment, the first sub-portion 1121 is electrically connected to the second sub-portion 1122 through a via hole.

[0092] In an implementation of this embodiment, the first connection portion 111 is located in the fourth sub-region NA14.

[0093] like Figures 8 to 10 As shown, in this embodiment, the first connection portion 111 is located in the non-display area NA, and the second connection portion 112 is located in the display area AA, so that the first connection line 110 bypasses the second area NA2 and is electrically connected to the corresponding signal line 102, thereby facilitating the reduction of the width of the second area NA2 at the corner position. The first direction X intersects the second direction Y. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X. This design is conducive to wiring and process implementation.

[0094] like Figure 8 As shown, in one embodiment of the present application, one end of the second sub-portion 1122 is connected to the first sub-portion 1121 , and the other end of the second sub-portion 1122 is connected to the corresponding signal line 102 .

[0095] In this embodiment, one end of the first sub-section 1121 is a connection point with the first sub-section 1121, and the other end of the second sub-section 1122 is a connection point with the corresponding signal line 102. One end of the second sub-section 1122 is electrically connected to the first sub-section 1121, and the other end of the second sub-section 1122 is electrically connected to the corresponding signal line 102. The second sub-section 1122 is used entirely to transmit electrical signals, that is, its effective length is equal to its actual length. Among them, the effective length refers to the length used to transmit electrical signals. The second sub-section 1122 is directly electrically connected to the signal line 102, that is, the endpoint of the second sub-section 1122 electrically connected to the signal line 102 can be located between the two endpoints of the signal line 102. Therefore, the solution provided in this embodiment makes the entire length of the second connecting portion 112 an effective length, which is convenient for saving the manufacturing materials of the second sub-section 1122 and is conducive to reducing production costs.

[0096] like Fig. 9 As shown, in one embodiment of the present application, the second sub-section 1122 includes a first node, and the first node is a connection point where the second sub-section 1122 is connected to the first sub-section 1121. The first node is located between two endpoints of the second sub-section 1122.

[0097] In this embodiment, the first node may be a through hole. The second sub-portion 1122 extends from the first node to both ends along the second direction Y, that is, the actual length of the second sub-portion 1122 is greater than the effective length of the second sub-portion 1122. This design can ensure the uniformity of the metal density in the display area AA where the plurality of second sub-portions 1122 are located. The metal density refers to the percentage of the area occupied by the metal per unit area.

[0098] like Fig.10 As shown, in one embodiment of the present application, the second connection portion 112 further includes a third sub-portion 1123 , and the third sub-portion 1123 extends along the second direction Y. One end of the third sub-portion 1123 is connected to the second sub-portion 1122 , and the other end of the third sub-portion 1123 is electrically connected to the corresponding signal line 102 .

[0099] like Fig.10 As shown, in one implementation of this embodiment, the third sub-portion 1123 is electrically connected to the second sub-portion 1122 through a wire via.

[0100] In this embodiment, the third sub-portion 1123 is electrically connected to the signal line 102 through a via hole, and the third sub-portion 1123 extends along the second direction Y, which can facilitate setting the position of the via hole used to electrically connect the third sub-portion 1123 and the signal line 102 at the end of the signal line 102, thereby reducing the process difficulty.

[0101] Fig.11 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0102] like Fig.11 As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the second connection line 120. The second connection line 120 includes a third connection portion 121 and a fourth connection portion 122, and the third connection portion 121 is electrically connected to the fourth connection portion 122. The third connection portion 121 is located in the first area NA1 and is electrically connected to the shift register unit 101, and the fourth connection portion 122 is located in the second area NA2 and is electrically connected to the signal line 102.

[0103] In an implementation of this embodiment, the third connection portion 121 is located in the fourth sub-region NA14, and the fourth connection portion 122 is located in the second region NA2 and close to one side of the first boundary line.

[0104] In this embodiment, some connection lines in the non-display area NA are routed through the second area NA2 near the first boundary line. This design can ensure that the border width is within the target width and improve the utilization rate of the border position area.

[0105] Fig.12 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0106] like Fig.12 As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the third connection line 130. The third connection line 130 includes a first sub-connection line 131 and a second sub-connection line 132. The first sub-connection line 131 is electrically connected to the second sub-connection line 132. The resistivity of the first sub-connection line 131 is different from the resistivity of the second sub-connection line 132.

[0107] In this embodiment, the lengths of the connecting lines between different shift register units 101 and the corresponding signal lines 102 are different, and the resistivity of the first sub-connecting line 131 is different from the resistivity of the second sub-connecting line 132, which can effectively compensate for the resistance difference caused by the length difference of different connecting lines, and make the resistance value difference between multiple shift register units 101 and the corresponding signal lines 102 within the allowable error range, thereby improving the stability of the driving effect of multiple shift register units 101.

[0108] In an implementation of the present embodiment, the first sub-connection line 131 and the second sub-connection line 132 are both located in the non-display area NA. For example, at least one of the first sub-connection line 131 and the second sub-connection line 132 is located in the fourth sub-area NA14.

[0109] In an implementation of the present embodiment, the resistivity of the first sub-connection line 131 is less than the resistivity of the second sub-connection line 132, and among the plurality of third connection lines 130, the longer the length of the third connection line 130 is, the longer the length of the first sub-connection line 131 is. That is, the plurality of third connection lines 130 include the third connection line 130a and the third connection line 130b, the length of the third connection line 130a is greater than the length of the third connection line 130b, and the length of the first sub-connection line 131 among the third connection lines 130a is greater than the length of the first sub-connection line 131 among the third connection lines 130b.

[0110] Fig.13 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0111] like Fig.13 As shown, in one embodiment of the present application, some of the shift register units 101 are electrically connected to the corresponding signal lines 102 through the common connection line 140. One end of the common connection line 140 is electrically connected to at least two shift register units 101, and the other end of the common connection line 140 is electrically connected to the corresponding at least two signal lines 102.

[0112] In this embodiment, among the multiple shift register units 101, at least two shift register units 101 share a common connection line 140. This design can effectively reduce the total number of connection lines between the multiple shift register units 101 and the signal line 102, thereby further reducing the width of the second area NA2 at the corner position to optimize the width of the area at the corner position.

[0113] In an implementation of this embodiment, the signal line 102 includes a data writing control scanning signal line 102. The common connection line 140 is electrically insulated from any data writing control scanning signal line 102.

[0114] In this implementation, the common connection line 140 is electrically insulated from any data writing control scanning signal line 102, which means that the driving signal required for the gate of the writing transistor of each pixel circuit 104 is independent of each other. The gates of the writing transistors of different pixel circuits 104 are connected to different shift register units 101. This design can ensure that the resolution of the display panel 100 is not reduced.

[0115] In the embodiment of the present application, at least two of the first connection line 110, the third connection line 130 and the common connection line 140 may be the same connection line. At least two of the second connection line 120, the third connection line 130 and the common connection line 140 may be the same connection line. Fig.13 As shown, the common connection line 140 and the third connection line 130 are the same connection line.

[0116] Fig.14 A schematic diagram of a display panel provided in an embodiment of the present application; Fig.15 Provided in the embodiments of this application Fig.14 A partial enlarged view of area B in the middle.

[0117] like Figure 14 to Figure 15As shown, the present application also provides a display panel 100, including: a display area AA and a non-display area NA. The display area AA includes a plurality of signal lines 102 arranged along a first direction X, and the non-display area NA includes a plurality of shift register units 101, and the shift register units 101 are electrically connected to the corresponding signal lines 102. The display area AA includes a first display area AA1 and a second display area AA2, and the first display area AA1 and the second display area AA2 are arranged along the first direction X. The second display area AA2 includes a chamfered area, and the boundary line between the chamfered area and the non-display area NA is a first boundary line. The non-display area NA includes a first area NA1 and a second area NA2, the first area NA1 is adjacent to the first display area AA1 along a second direction Y, and the second area NA2 is adjacent to the display area AA along the second direction Y, the second direction Y intersects with the first direction X, and the first area NA1 and the second area NA2 are adjacent to each other along the first direction X. The boundary line between the second area NA2 and the display area AA is a second boundary line, and the second boundary line covers the first boundary line. A plurality of common connection lines 140 are disposed in the second area NA2 , one end of the common connection line 140 is electrically connected to at least two shift register units 101 , and the other end of the common connection line 140 is electrically connected to at least two corresponding signal lines 102 .

[0118] The present application parallels multiple common connection lines 140 located in the second area NA2, which can reduce the total number of common connection lines 140 located in the second area NA2, and further reduce the width of the second area NA2 at the corner position to optimize the width of the area at the corner position.

[0119] In one embodiment of the present application, the first boundary line coincides with the second boundary line.

[0120] In an implementation of this embodiment, the first boundary line is an arc line, and the boundary line of the first area NA1 is a rectangle, that is, the chamfer of the display area AA is a rounded corner, and the chamfered area is a rounded corner area.

[0121] Fig.16 A schematic diagram of a display panel provided in an embodiment of the present application; Fig.17 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the C area in the middle. Fig.14 and Fig.16 The difference is: Fig.14 The shift register units in the second area NA2 are arranged along a fan shape or an arc shape.

[0122] Fig.16 The shift register units in the second area NA2 are arranged in the same manner as the shift register units in the first area NA1: both are arranged in a straight line.

[0123] like Figure 16 to Figure 17 As shown, in one embodiment of the present application, the first area NA1 and / or the display area AA include a common connection line 140. That is, the connection line electrically connected to the register unit in the first area NA1 can be a common connection line 140, and the connection line located in the display area AA (the connection line is used to electrically connect the signal line 102 and the shift register unit 101) can also be a common connection line 140. One end of the common connection line 140 is electrically connected to at least two shift register units 101, and the other end of the common connection line 140 is electrically connected to the corresponding at least two signal lines 102.

[0124] Fig.18 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the C area in the middle.

[0125] like Fig.15 or Fig.18 As shown, in one embodiment of the present application, among the plurality of common connection lines 140, at least some of the common connection lines 140 include a first sub-connection line 131 and a second sub-connection line 132, and the first sub-connection line 131 is electrically connected to the second sub-connection line 132. The resistivity of the first sub-connection line 131 is different from the resistivity of the second sub-connection line 132.

[0126] In an implementation of the present embodiment, the resistivity of the first sub-connection line 131 is less than the resistivity of the second sub-connection line 132, and among the plurality of common connection lines 140, the longer the length of the common connection line 140 is, the longer the length of the first sub-connection line 131 is. That is, the plurality of common connection lines 140 include common connection lines 140a and common connection lines 140b, the length of the common connection line 140a is greater than the length of the common connection line 140b, and the length of the first sub-connection line 131 among the common connection lines 140a is greater than the length of the first sub-connection line 131 among the common connection lines 140b.

[0127] like Fig.14 or Fig.16 As shown, in one embodiment of the present application, the first area NA1 includes a plurality of shift register units 101 , and the second area NA2 includes a plurality of shift register units 101 .

[0128] In an embodiment of the present application, the signal line 102 includes a data writing control scanning signal line. The common connection line 140 is electrically insulated from any data writing control scanning signal line.

[0129] In one embodiment of the present application, the projection of the shift register unit 101 along the third direction does not overlap with the second area NA2 , and the third direction is perpendicular to the first direction X and the second direction Y. At least some of the shift register units 101 are disposed in the first area NA1 .

[0130] In this embodiment, the shift register unit 101 is not provided in the second area NA2 of the present application, that is, the shift register unit 101 is not provided in the area of ​​the non-display area NA close to the corner position of the display area AA of the display panel 100. Since the shift register unit 101 is not provided in the second area NA2, the width of the second area NA2 at the corner position can be reduced, thereby reducing the width of the area at the corner position.

[0131] In some embodiments of the present application, the signal line 102 may be a scanning signal line, such as a light-emitting control scanning signal line, a reset control scanning signal line, and a data writing control scanning signal line; the first direction X is perpendicular to the second direction Y. The light-emitting control scanning signal line is electrically connected to the gate of the light-emitting control transistor in the corresponding pixel circuit 104, and is used to control the pixel circuit to be turned on so that the light-emitting element emits light. The reset control scanning signal line is electrically connected to the gate of the reset transistor in the corresponding pixel circuit 104, and is used to control the reset of the pixel circuit 104. The data writing control scanning signal line is electrically connected to the gate of the data writing transistor in the corresponding pixel circuit 104, and is used to control the writing of the data voltage. The pixel circuit 104 refers to a driving circuit electrically connected to the light-emitting element, and the light-emitting element can emit light under the drive of the pixel circuit 104.

[0132] like Figures 4 to 5 As shown, in one embodiment of the present application, a plurality of pixel circuits 104 are disposed in the display area AA, the pixel circuits 104 include a plurality of transistors, and the signal line 102 is electrically connected to the gates of at least some of the transistors. The projection of the pixel circuit 104 along the third direction is a first projection, and the length of the first projection along the first direction X is a first length L1. The projection of at least part of the shift register unit 101 along the third direction is a second projection, and the length of the second projection along the first direction X is a second length L2. The first length L1 is greater than the second length L2.

[0133] In this embodiment, the first length L1 is greater than the second length L2, which can ensure that there is a difference in the length of the space occupied by the shift register unit 101 and the pixel circuit in the first direction X. This difference can provide space for inserting the shift register unit 101 corresponding to the pixel circuit 104 located in the corner area in the first area NA1.

[0134] like Figure 4As shown, in one embodiment of the present application, the first area NA1 includes a first sub-area NA11 and a second sub-area NA12, and the second sub-area NA12 is located between the first sub-area NA11 and the second area NA2. The projection of the shift register unit 101 located in the first sub-area NA11 along the third direction is the first sub-projection. The projection of the shift register unit 101 located in the second sub-area NA12 along the third direction is the second sub-projection. The length of the first sub-projection along the first direction X is the first sub-length L21, and the length of the second sub-projection along the first direction X is the second sub-length L22. The first sub-length L21 is not equal to the second length L2, and the first sub-length L21 is less than the first length L1, and the second sub-length L22 is less than the first length L1.

[0135] In this embodiment, the shift register unit 101 is designed with different sizes, which can help improve space utilization.

[0136] In a possible implementation of this embodiment, the first sub-length L21 is greater than the second sub-length L22. That is, compared with the shift register circuit that provides the driving signal to the pixel circuit 104 in the first display area AA1, the size of the shift register unit that provides the driving signal to the pixel circuit 104 in the chamfer area is smaller. Since the number of pixel circuits 104 in the chamfer area is small, the size of the shift register unit 101 that provides the driving signal to it (that is, the shift register unit 101 located in the second sub-area NA12) can be made smaller, so that the space can be used more reasonably and the space utilization rate can be improved.

[0137] like Figure 5 As shown, the lengths of the second projections along the first direction X are equal. This design is conducive to process implementation.

[0138] like Figure 5 As shown, in one embodiment of the present application, the first area NA1 includes a third sub-area NA13 and a fourth sub-area NA14, and the fourth sub-area NA14 is located between the third sub-area NA13 and the second area NA2. The projection of the shift register unit 101 located in the third sub-area NA13 along the third direction is the first sub-projection. The projection of the shift register unit 101 located in the fourth sub-area NA14 along the third direction is the second sub-projection. The distance between two adjacent first sub-projections along the first direction X in the first direction X is the first distance D1. The distance between two adjacent second sub-projections along the first direction X in the first direction X is the second distance D2. The second distance D2 is less than or equal to the first distance D1.

[0139] In this embodiment, the third sub-area NA13 is located in the middle of the first area NA1, and the fourth sub-area NA14 is located at the end of the first area NA1. For example, the third sub-area NA13 is located at the periphery of the first display area AA1, and the fourth sub-area NA14 is located on one side of the second display area AA2. Among them, the first display area AA1 is the straight line portion of the display area AA. The second display area AA2 is the side close to the inner corner area of ​​the display area AA. The arrangement density of the first shift register unit 101 in the third sub-area NA13 is less than or equal to the arrangement density of the second shift register unit 101 in the fourth sub-area NA14. This design can facilitate the realization of: without affecting the display effect, all the shift register units 101 are set in the first area NA1.

[0140] In an embodiment of the present application, the first distance D1 is greater than zero, and the second distance D2 is greater than or equal to zero. The second distance D2 is smaller than the first distance D1.

[0141] In this embodiment, the arrangement density of the shift register units 101 is differentiated in the first area NA1: the arrangement density of the shift register units 101 in the middle of the first area NA1 is less than the arrangement density at both ends of the first area NA1. This differentiation can further facilitate the realization of: all the shift register units 101 are arranged in the first area NA1 without affecting the display effect.

[0142] In an embodiment of the present application, the first distance D1 is equal to the second distance D2, and both the first distance D1 and the second distance D2 are greater than zero.

[0143] In this embodiment, the shift register units 101 in the first area NA1 are evenly distributed, which can simplify the manufacturing process and reduce the manufacturing cost.

[0144] In one embodiment of the present application, the first length L1 is the sum of the second length L2 and the first distance D1.

[0145] In this embodiment, the first length L1 is the sum of the second length L2 and the first distance D1. This design can achieve: along the first direction X, the shift register unit 101 in the middle of the first area NA1 corresponds to the pixel unit in the first display area AA1 in a one-to-one correspondence. This design facilitates the wiring of the connection line between the shift register unit 101 in the middle of the first area NA1 and the corresponding signal line 102.

[0146] Figure 6 A schematic diagram of a display panel provided in an embodiment of the present application;

[0147] like Figure 6 As shown, in one embodiment of the present application, the first distance D1 and the second distance D2 are both zero.

[0148] In this embodiment, the shift register units 101 in the first area NA1 are closely arranged in the first direction X. The closely arranged arrangement can save occupied area, so as to ensure that the shift register units 101 can be located only in the first area NA1.

[0149] In one embodiment of the present application, any shift register unit 101 in the first area NA1 is electrically connected to the corresponding signal line 102. That is, all shift register units 101 in the first area NA1 are valid and can output valid signals to the corresponding signal line 102. This design can maximize the use of the space in the first area NA1.

[0150] In an embodiment of the present application, the display panel 100 further includes a dummy shift register unit 103 , which is located on a side of the shift register unit 101 close to the second area NA2 . The dummy shift register unit 103 is electrically insulated from any signal line 102 .

[0151] In the embodiment, the dummy shift register does not output a valid signal. The purpose of the dummy shift register unit 103 is to ensure the stability of the working performance of the shift register unit 101 electrically connected to the signal line 102 at the inner edge of the first area NA1.

[0152] Figure 7 A schematic diagram of a display panel provided in an embodiment of the present application.

[0153] like Figure 6 or Figure 7 As shown, in one embodiment of the present application, the display panel 100 further includes a dummy shift register unit 103. The dummy shift register unit 103 is located in the third sub-region NA13 and on a side of the shift register unit 101 close to the fourth sub-region NA14. The dummy shift register unit 103 is electrically insulated from any signal line 102.

[0154] In this embodiment, the dummy shift register unit 103 is used to compensate for the difference in total length in the first direction X between the pixel circuit in the first display area AA1 and the shift register unit 101 in the third sub-area NA13, so as to facilitate the wiring of the shift register in the fourth sub-area NA14.

[0155] In a possible implementation of the present embodiment, in the first direction X, all the shift register units 101 in the third sub-region NA13 are arranged uniformly, and a dummy shift register unit 103 is provided between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The dummy shift register unit 103 can ensure the performance of the shift register unit 101 located near the edge of the fourth sub-region NA14, and improve the stability of the shift register unit 101 when working.

[0156] like Figure 7 As shown, in one embodiment of the present application, the third sub-region NA13 includes: a first sub-region NA131 and a second sub-region NA132, the second sub-region NA132 is located between the third sub-region NA13 and the fourth sub-region NA14, and all the shift register units 101 in the third sub-region NA13 are located in the first sub-region NA131. It can be understood that the shift register unit 101 is not provided in the second sub-region NA132.

[0157] In the present embodiment, the shift register unit 101 is not provided in the second sub-region NA132. This design is conducive to the realization that within the preset length in the first direction X, the shift register unit 101 in the third sub-region NA13 corresponds to the region of the pixel circuit 104 in the first display area AA1. This design can form an isolation between the shift register unit 101 in the third sub-region NA13 and the shift register unit 101 in the fourth sub-region NA14. The arrangement pitch of the shift register unit 101 in the first sub-region NA131 is not necessarily the same as the arrangement pitch of the shift register unit 101 in the fourth sub-region NA14, and this isolation can effectively reduce the adverse effects caused by the different arrangement pitches.

[0158] like Figure 7 As shown, in one implementation of the present embodiment, a dummy shift register unit 103 is provided in the first sub-region NA131, and a dummy shift register unit 103 is provided in the second sub-region NA12. The dummy shift register unit 103 in the first sub-region NA131 is located on the side of the shift register unit 101 (valid shift register unit 101) close to the second sub-region NA132; the dummy shift register unit 103 in the fourth sub-region is located on the side of the shift register unit 101 (valid shift register unit 101) close to the second sub-region NA132. This design can ensure the electrical stability of the valid shift register unit 101 in the first sub-region NA131 and the second sub-region NA12 when they are in working state.

[0159] Fig.19 Provided in the embodiments of this application Fig.16A partial enlarged schematic diagram of the D area in the middle. Fig. 20 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the D area in the middle. Fig.21 Provided in the embodiments of this application Fig.16 A partial enlarged schematic diagram of the D area in the middle.

[0160] like Figures 8 to 10 , Figures 19 to 21 As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the first connection line 110. The first connection line 110 includes a first connection portion 111 and a second connection portion 112, the first connection portion 111 is electrically connected to the second connection portion 112, the first connection portion 111 is located in the non-display area NA, and the second connection portion 112 is located in the display area AA. The second connection portion 112 includes a first sub-portion 1121 and a second sub-portion 1122, the first sub-portion 1121 is electrically connected to the second sub-portion 1122. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X.

[0161] like Figures 8 to 10 , Figures 19 to 21 As shown, in one implementation of this embodiment, the first sub-portion 1121 is electrically connected to the second sub-portion 1122 through a via hole.

[0162] In an implementation of this embodiment, the first connection portion 111 is located in the fourth sub-region NA14.

[0163] like Figures 8 to 10 , Figures 19 to 21 As shown, in this embodiment, the first connection portion 111 is located in the non-display area NA, and the second connection portion 112 is located in the display area AA, so that the first connection line 110 bypasses the second area NA2 and is electrically connected to the corresponding signal line 102, thereby facilitating the reduction of the width of the second area NA2 at the corner position. The first direction X intersects the second direction Y. The first sub-portion 1121 extends along the second direction Y, and the second sub-portion 1122 extends along the first direction X. This design is conducive to wiring and process implementation.

[0164] like Figure 8 and Fig.19 As shown, in one embodiment of the present application, one end of the second sub-portion 1122 is connected to the first sub-portion 1121 , and the other end of the second sub-portion 1122 is connected to the corresponding signal line 102 .

[0165] In this embodiment, one end of the first sub-section 1121 is a connection point with the first sub-section 1121, and the other end of the second sub-section 1122 is a connection point with the corresponding signal line 102. One end of the second sub-section 1122 is electrically connected to the first sub-section 1121, and the other end of the second sub-section 1122 is electrically connected to the corresponding signal line 102. The second sub-section 1122 is used entirely to transmit electrical signals, that is, its effective length is equal to its actual length. Among them, the effective length refers to the length used to transmit electrical signals. The second sub-section 1122 is directly electrically connected to the signal line 102, that is, the endpoint of the second sub-section 1122 electrically connected to the signal line 102 can be located between the two endpoints of the signal line 102. Therefore, the solution provided in this embodiment makes the entire length of the second connecting portion 112 an effective length, which is convenient for saving the manufacturing materials of the second sub-section 1122 and is conducive to reducing production costs.

[0166] like Fig. 9 or Fig. 20 As shown, in one embodiment of the present application, the second sub-section 1122 includes a first node, and the first node is a connection point where the second sub-section 1122 is connected to the first sub-section 1121. The first node is located between two endpoints of the second sub-section 1122.

[0167] In this embodiment, the first node may be a through hole. The second sub-portion 1122 extends from the first node to both ends along the second direction Y, that is, the actual length of the second sub-portion 1122 is greater than the effective length of the second sub-portion 1122. This design can ensure the uniformity of the metal density in the display area AA where the plurality of second sub-portions 1122 are located. The metal density refers to the percentage of the area occupied by the metal per unit area.

[0168] like Fig.10 or Fig.21 As shown, in one embodiment of the present application, the second connection portion 112 further includes a third sub-portion 1123 , and the third sub-portion 1123 extends along the second direction Y. One end of the third sub-portion 1123 is connected to the second sub-portion 1122 , and the other end of the third sub-portion 1123 is electrically connected to the corresponding signal line 102 .

[0169] like Fig.10 or Fig.21 As shown, in one implementation of this embodiment, the third sub-portion 1123 is electrically connected to the second sub-portion 1122 through a wire via.

[0170] In this embodiment, the third sub-portion 1123 is electrically connected to the signal line 102 through a via hole, and the third sub-portion 1123 extends along the second direction Y, which can facilitate setting the position of the via hole used to electrically connect the third sub-portion 1123 and the signal line 102 at the end of the signal line 102, thereby reducing the process difficulty.

[0171] like Fig.11As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the second connection line 120. The second connection line 120 includes a third connection portion 121 and a fourth connection portion 122, and the third connection portion 121 is electrically connected to the fourth connection portion 122. The third connection portion 121 is located in the first area NA1 and is electrically connected to the shift register unit 101, and the fourth connection portion 122 is located in the second area NA2 and is electrically connected to the signal line 102.

[0172] In an implementation of this embodiment, the third connection portion 121 is located in the fourth sub-region NA14, and the fourth connection portion 122 is located in the second region NA2 and close to one side of the first boundary line.

[0173] In this embodiment, some connection lines in the non-display area NA are routed through the second area NA2 near the first boundary line. This design can ensure that the border width is within the target width and improve the utilization rate of the border position area.

[0174] Fig.12 Provided in the embodiments of this application Figure 2 or Figure 3 A partial enlarged view of area A.

[0175] like Fig.12 As shown, in one embodiment of the present application, some of the shift register units 101 in the plurality of shift register units 101 are electrically connected to the corresponding signal line 102 through the third connection line 130. The third connection line 130 includes a first sub-connection line 131 and a second sub-connection line 132. The first sub-connection line 131 is electrically connected to the second sub-connection line 132. The resistivity of the first sub-connection line 131 is different from the resistivity of the second sub-connection line 132.

[0176] In this embodiment, the lengths of the connecting lines between different shift register units 101 and the corresponding signal lines 102 are different, and the resistivity of the first sub-connecting line 131 is different from the resistivity of the second sub-connecting line 132, which can effectively compensate for the resistance difference caused by the length difference of different connecting lines, and make the resistance value difference between multiple shift register units 101 and the corresponding signal lines 102 within the allowable error range, thereby improving the stability of the driving effect of multiple shift register units 101.

[0177] In an implementation of the present embodiment, the first sub-connection line 131 and the second sub-connection line 132 are both located in the non-display area NA. For example, at least one of the first sub-connection line 131 and the second sub-connection line 132 is located in the fourth sub-area NA14.

[0178] In an implementation of the present embodiment, the resistivity of the first sub-connection line 131 is less than the resistivity of the second sub-connection line 132, and among the plurality of third connection lines 130, the longer the length of the third connection line 130 is, the longer the length of the first sub-connection line 131 is. That is, the plurality of third connection lines 130 include the third connection line 130a and the third connection line 130b, the length of the third connection line 130a is greater than the length of the third connection line 130b, and the length of the first sub-connection line 131 among the third connection lines 130a is greater than the length of the first sub-connection line 131 among the third connection lines 130b.

[0179] In the embodiment of the present application, at least two of the first connection line 110, the third connection line 130 and the common connection line 140 may be the same connection line. At least two of the second connection line 120, the third connection line 130 and the common connection line 140 may be the same connection line.

[0180] Fig. 22 A schematic diagram of a display device provided in an embodiment of the present application.

[0181] like Fig. 22 As shown, the present application further provides a display device 200 , which includes the display panel 100 of the first aspect or the second aspect.

[0182] Compared with the prior art, the shift register unit 101 is not provided in the second area NA2 of the display panel 100 in the display device 200, that is, the shift register unit 101 is not provided in the area of ​​the non-display area NA of the display panel 100 near the corner position of the display area AA. Since the shift register unit 101 is not provided in the second area NA2, the width of the second area NA2 at the corner position can be reduced, thereby reducing the width of the area at the corner position. Alternatively, in the display device 200 provided in the embodiment of the present application, the display panel 100 parallels multiple common connection lines 140 located in the second area NA2, which can reduce the total number of common connection lines 140 located in the second area NA2, and then can reduce the width of the second area NA2 at the corner position to optimize the width of the area at the corner position.

[0183] The present application also provides a device, which includes a display panel or a display device.

[0184] Compared with the prior art, in the device provided in the embodiment of the present application, the shift register unit 101 is not provided in the second area NA2 of the display panel 100, that is, the shift register unit 101 is not provided in the area of ​​the non-display area NA of the display panel 100 near the corner position of the display area AA. Since the shift register unit 101 is not provided in the second area NA2, the width of the second area NA2 at the corner position can be reduced, thereby reducing the width of the area at the corner position. Or in the device provided in the embodiment of the present application, the display panel 100 parallels a plurality of common connection lines 140 located in the second area NA2, thereby reducing the total number of common connection lines 140 located in the second area NA2, and further reducing the width of the second area NA2 at the corner position to optimize the width of the area at the corner position.

Claims

1. A display panel, characterized in that: It comprises a display area and a non-display area, wherein the display area comprises a plurality of signal lines arranged along a first direction, and the non-display area comprises a plurality of shift register units, wherein the shift register units are electrically connected to the corresponding signal lines; The display area includes a first display area and a second display area, the first display area and the second display area are arranged along a first direction; the second display area includes a chamfered area, and a boundary line between the chamfered area and the non-display area is a first boundary line; The non-display area includes a first area and a second area, the first area is adjacent to the first display area along a second direction and the second area is adjacent to the second display area along the second direction, the second direction intersects the first direction, and the first area is adjacent to the second area along the first direction; a boundary line between the second area and the display area is a second boundary line, and the first boundary line covers the second boundary line; The projection of the shift register unit along a third direction does not overlap with the second area, and the third direction is perpendicular to the first direction and the second direction; and at least some of the shift register units are arranged in the first area.

2. The display panel according to claim 1, characterized in that: A plurality of pixel circuits are arranged in the display area, the pixel circuits include a plurality of transistors, and the signal line is electrically connected to the gates of at least some of the transistors; The projection of the pixel circuit along the third direction is a first projection, and the length of the first projection along the first direction is a first length; the projection of at least part of the shift register unit along the third direction is a second projection, and the length of the second projection along the first direction is a second length; the first length is greater than the second length.

3. The display panel according to claim 2, characterized in that: The first region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the second region; The projection of the shift register unit located in the first sub-area along the third direction is a first sub-projection; the projection of the shift register unit located in the second sub-area along the third direction is a second sub-projection; the length of the first sub-projection along the first direction is a first sub-length, the length of the second sub-projection along the first direction is a second sub-length, the first sub-length is not equal to the second length, and the first sub-length is smaller than the first length, and the second sub-length is smaller than the first length.

4. The display panel according to claim 1, characterized in that: The first area includes a third sub-area and a fourth sub-area, the fourth sub-area is located between the third sub-area and the second area; the projection of the shift register unit located in the third sub-area along the third direction is a first sub-projection; the projection of the shift register unit located in the fourth sub-area along the third direction is a second sub-projection; the distance between two adjacent first sub-projections along the first direction in the first direction is a first distance; the distance between two adjacent second sub-projections along the first direction in the first direction is a second distance; the second distance is less than or equal to the first distance.

5. The display panel according to claim 4, characterized in that: The first distance is greater than zero, the second distance is greater than or equal to zero; and the second distance is smaller than the first distance.

6. The display panel according to claim 4, characterized in that: A plurality of pixel circuits are arranged in the display area, the pixel circuits include a plurality of transistors, and the signal line is electrically connected to the gates of at least some of the transistors; The projection of the pixel circuit along the third direction is a first projection, and the length of the first projection along the first direction is a first length; the first length is the sum of the second length and the first distance.

7. The display panel according to claim 4, characterized in that: The first distance and the second distance are both zero.

8. The display panel according to claim 1, characterized in that: It also includes a dummy shift register unit, which is located on a side of the shift register unit close to the second area; the dummy shift register unit is electrically insulated from any of the signal lines.

9. The display panel according to claim 1, characterized in that: Some of the shift register units among the plurality of shift register units are electrically connected to the corresponding signal lines through first connecting lines; The first connection line includes a first connection portion and a second connection portion, the first connection portion is electrically connected to the second connection portion, the first connection portion is located in the non-display area, and the second connection portion is located in the display area; The second connecting portion includes a first sub-portion and a second sub-portion, the first sub-portion is electrically connected to the second sub-portion; the first sub-portion extends along the second direction, and the second sub-portion extends along the first direction.

10. The display panel according to claim 9, characterized in that: One end of the second sub-section is connected to the first sub-section, and the other end of the second sub-section is connected to the corresponding signal line.

11. The display panel according to claim 9, characterized in that: The second sub-section includes a first node, which is a connection point between the second sub-section and the first sub-section; the first node is located between two endpoints of the second sub-section.

12. The display panel according to any one of claims 9, characterized in that: The second connecting portion further includes a third sub-portion, and the third sub-portion extends along the second direction; one end of the third sub-portion is connected to the second sub-portion, and the other end of the third sub-portion is electrically connected to the corresponding signal line.

13. The display panel according to claim 1, characterized in that: Some of the shift register units are electrically connected to the corresponding signal line through a second connecting line; the second connecting line includes a third connecting part and a fourth connecting part, and the third connecting part is electrically connected to the fourth connecting part; the third connecting part is located in the first area and is electrically connected to the shift register unit, and the fourth connecting part is located in the second area and is electrically connected to the signal line.

14. The display panel according to claim 1, characterized in that: Some of the shift register units are electrically connected to the corresponding signal line through a third connection line; the third connection line includes a first sub-connection line and a second sub-connection line; the first sub-connection line is electrically connected to the second sub-connection line; the resistivity of the first sub-connection line is different from the resistivity of the second sub-connection line.

15. The display panel according to claim 1, characterized in that: Some of the shift register units are electrically connected to the corresponding signal lines through a common connection line; one end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to the corresponding at least two signal lines.

16. A display panel, characterized in that: include: It comprises a display area and a non-display area; the display area comprises a plurality of signal lines arranged along a first direction, the non-display area comprises a plurality of shift register units, and the shift register units are electrically connected to the corresponding signal lines; The display area includes a first display area and a second display area, the first display area and the second display area are arranged along a first direction; the second display area includes a chamfered area, and a boundary line between the chamfered area and the non-display area is a first boundary line; The non-display area includes a first area and a second area, the first area is adjacent to the first display area along a second direction and the second area is adjacent to the display area along the second direction, the second direction intersects the first direction, and the first area is adjacent to the second area along the first direction; a boundary line between the second area and the display area is a second boundary line, and the second boundary line covers the first boundary line; A plurality of common connection lines are arranged in the second region, one end of the common connection line is electrically connected to at least two shift register units, and the other end of the common connection line is electrically connected to at least two corresponding signal lines.

17. The display panel according to claim 16, characterized in that: Among the plurality of common connection lines, at least some of the common connection lines include a first sub-connection line and a second sub-connection line, the first sub-connection line is electrically connected to the second sub-connection line; and the resistivity of the first sub-connection line is different from the resistivity of the second sub-connection line.

18. The display panel according to claim 16, characterized in that: The first area includes a plurality of shift register units, and the second area includes a plurality of shift register units.

19. The display panel according to claim 16, characterized in that: The signal lines include data writing control scanning signal lines; the common connection lines are electrically insulated from any data writing control scanning signal lines.

20. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1-19.

21. A device, characterized in that The device comprises the display panel according to any one of claims 1 to 19 or the display apparatus according to claim 20.

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