Display device, driving chip and electronic apparatus

Abstract

The invention discloses a display device, a driving chip and electronic equipment. A display device includes: a display panel including a plurality of data lines; the driving chip comprises a multiplexing circuit and a data signal end, the multiplexing circuit comprises an input end and a plurality of output ends, the input end is electrically connected with the data signal end, and the output ends are electrically connected with the data lines. According to the display device, the driving chip and the electronic equipment provided by the embodiment of the invention, a narrow frame of the display panel can be realized.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device, a driver chip, and an electronic device. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more common, and users have more and more requirements for display panels. Display panels are gradually developing towards thinness, high screen-to-body ratio, and narrow frame. How to achieve narrow frame is an important problem faced by technicians in this field. Summary of the invention

[0003] Embodiments of the present application provide a display device, a driving chip, and an electronic device, which can achieve a narrow frame of a display panel.

[0004] In a first aspect, an embodiment of the present application provides a display device, comprising: a display panel, comprising multiple data lines; a driving chip, comprising a multiplexing circuit and a data signal terminal, the multiplexing circuit comprising an input terminal and multiple output terminals, the input terminal is electrically connected to the data signal terminal, and the output terminal is electrically connected to the data line.

[0005] In a second aspect, an embodiment of the present application provides a driver chip for driving a display panel, the display panel includes a plurality of data lines, and the driver chip includes:

[0006] The multiplexing circuit and the data signal terminal, the multiplexing circuit comprises an input terminal and a plurality of output terminals, the input terminal is electrically connected to the data signal terminal, and the output terminal is electrically connected to the data line.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, comprising a display device as described in the embodiment of the first aspect.

[0008] Compared with setting the multiplexing circuit in the display panel, the multiplexing circuit needs to occupy the frame area of ​​the display panel, and the multiplexing circuit cannot be bent, resulting in a larger frame of the display panel. According to the display device, driver chip, and electronic device provided by the embodiments of the present application, the multiplexing circuit is set in the driver chip, so that the multiplexing circuit no longer occupies the frame area of ​​the display panel, and a narrow frame of the display panel can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0010] Figure 1 A schematic diagram showing a structure of a display device provided in an embodiment of the present application is shown;

[0011] Figure 2 Another schematic diagram showing the structure of the display device provided by the embodiment of the present application is shown;

[0012] Figure 3 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0013] Figure 4 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0014] Figure 5 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0015] Figure 6 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0016] Figure 7 Another structural schematic diagram of a display device provided in an embodiment of the present application is shown;

[0017] Figure 8 A timing diagram of a display device provided by an embodiment of the present application is shown;

[0018] Fig. 9 Another timing diagram of the display device provided by the embodiment of the present application is shown;

[0019] Fig.10 A schematic diagram showing a structure of a pixel driving circuit provided in an embodiment of the present application is shown;

[0020] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0022] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0023] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0024] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0025] In the embodiments of the present application, the term "electrically connected" may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components. The term "drive" may refer to "control" or "operate". The display panel may be a display device or a module / part of a display device.

[0026] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0027] The embodiments of the present application provide a display device, a driver chip, and an electronic device. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0028] like Figure 1As shown, the display device provided in the embodiment of the present application includes a display panel 1 and a driving chip 2. The display panel 1 is used for luminous display. The driving chip 2 is electrically connected to the display panel 1, and the driving chip 2 is used to provide a driving signal to the display panel 1 to drive the display panel 1 to emit light.

[0029] The display panel 1 includes a plurality of data lines 11, each of which extends along a first direction X, and the plurality of data lines 11 are arranged in a second direction Y. The first direction X intersects with the second direction Y. For example, the first direction X is a column direction, and the second direction Y is a row direction.

[0030] The display panel 1 further includes a sub-pixel 12, and the sub-pixel 12 is electrically connected to the data line 11. The data line 11 is used to transmit a data signal to the sub-pixel 12, and the sub-pixel 12 emits light based on the received data signal.

[0031] The driving chip 2 includes a multiplexing circuit 21 and a data signal terminal S. The multiplexing circuit 21 can be referred to as DEMUX. The multiplexing circuit 21 includes an input terminal and multiple output terminals, wherein the input terminal of the multiplexing circuit 21 is electrically connected to the data signal terminal S, and the output terminal of the multiplexing circuit 21 is electrically connected to the data line 11.

[0032] Exemplarily, the multiple output terminals of the multiplexing circuit 21 are electrically connected to the multiple data lines 11 in a one-to-one correspondence. The driving chip 2 includes a plurality of multiplexing circuits 21, and the plurality of multiplexing circuits 21 are arranged in the second direction Y in sequence.

[0033] It should be noted that the number of output terminals of the multiplexing circuit 21 in the drawings of the present application is only exemplary and is not intended to limit the present application. For example, the output terminal data of the multiplexing circuit 21 is any value greater than 1.

[0034] The data signal terminal S is used to provide a data signal, which is transmitted to the data line 11 through the multiplexing circuit 21, and the data line 11 transmits the data signal to the sub-pixel 12, thereby driving the sub-pixel 12 to emit light. Different voltages of the data signal will result in different luminances of the same sub-pixel 12.

[0035] The display panel includes multiple rows of sub-pixels, and a row of sub-pixels includes multiple sub-pixels 12 arranged in the second direction Y. During one frame of the picture, the multiple rows of sub-pixels are scanned row by row, and when a row of sub-pixels is scanned accordingly, the data signal on the data line is written into the row of sub-pixels. During the scanning time of a row of sub-pixels, multiple output terminals of the multiplexing circuit 21 and its input terminals are sequentially connected, so that the data signal terminal S provides data signals to the sub-pixels electrically connected thereto in a time-sharing manner.

[0036] Compared with setting the multiplexing circuit in the display panel, the multiplexing circuit needs to occupy the frame area of ​​the display panel, and the multiplexing circuit cannot be bent, resulting in a larger frame of the display panel. According to the display device provided by the embodiment of the present application, the multiplexing circuit is set in the driver chip, so that the multiplexing circuit no longer occupies the frame area of ​​the display panel, and a narrow frame of the display panel can be achieved.

[0037] In some embodiments, Figure 1 or Figure 2 As shown, still taking the extension of the data line 11 as the first direction X and the arrangement of the multiple data lines 11 as the second direction Y as an example, the multiple data lines 11 electrically connected to the same multiplexing circuit 21 are adjacent in the second direction Y.

[0038] As an example, Figure 1 As shown, the multiplexing circuit 21 includes two output terminals, and the two output terminals of the multiplexing circuit 21 are electrically connected to the two data lines 11 in a one-to-one correspondence. The two data lines 11 connected to the same multiplexing circuit 21 are adjacent in the second direction Y.

[0039] As another example, Figure 2 As shown, the multiplexing circuit 21 includes three output terminals, and the three output terminals of the multiplexing circuit 21 are electrically connected to the three data lines 11 one by one. The three data lines 11 electrically connected to the same multiplexing circuit 21 are adjacent in the second direction Y.

[0040] It should be noted that the m data lines 11 electrically connected to the same multiplexing circuit 21 are adjacent in the second direction Y, and m is greater than or equal to 3, which means that in the second direction Y, the m data lines are arranged in sequence, and there are no data lines electrically connected to other multiplexing circuits 21 arranged between them.

[0041] Exemplarily, the multiple output terminals of the same multiplexing circuit 21 are arranged in sequence in the second direction Y, and the arrangement order of the multiple output terminals of the multiplexing circuit 21 is the same as the arrangement order of the multiple data lines 11 electrically connected one by one. Figure 1 In the direction from left to right in FIG. 1 , for the multiplexing circuit 21 and the data line 11 electrically connected to each other, the first output end of the multiplexing circuit 21 is electrically connected to the first data line 11, and the second output end of the multiplexing circuit 21 is electrically connected to the second data line 11. For another example, in Figure 2From left to right in the figure, for the multiplexing circuit 21 and the data line 11 that are electrically connected to each other, the first output end of the multiplexing circuit 21 is electrically connected to the first data line 11, the second output end of the multiplexing circuit 21 is electrically connected to the second data line 11, and the third output end of the multiplexing circuit 21 is electrically connected to the third data line 11. In this way, the connection lines between the output end of the multiplexing circuit 21 and the data line 11 cannot cross, thereby reducing the coupling effect and improving the display effect.

[0042] In some embodiments, Figure 3 As shown, the data line 11 is electrically connected to the sub-pixel 12. The display panel includes sub-pixels of multiple luminous colors. The same multiplexing circuit 21 is electrically connected to the sub-pixels 12 of at least two luminous colors.

[0043] Exemplarily, the sub-pixel 12 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel 123 that emit different colors. For example, the first sub-pixel 121 is a red sub-pixel, the second sub-pixel 122 is a green sub-pixel, and the third sub-pixel 123 is a blue sub-pixel.

[0044] As an example, Figure 3 As shown in FIG. 4 , the luminous color pixels of the same column of sub-pixels and the first sub-pixels 121, the second sub-pixels 122 and the third sub-pixels 123 in the same row of sub-pixels are arranged alternately. Figure 3 As shown, part of the multiplexing circuit 21 is electrically connected to the first sub-pixel 121 and the second sub-pixel 122, another part of the multiplexing circuit 21 is electrically connected to the first sub-pixel 121 and the third sub-pixel 123, and another part of the multiplexing circuit 21 is electrically connected to the second sub-pixel 122 and the third sub-pixel 123. Alternatively, Figure 4 As shown, each multiplexing circuit 21 electrically connects the first sub-pixel 121 , the second sub-pixel 122 , and the third sub-pixel 123 .

[0045] As another example, Figure 5 As shown, the first sub-pixels 121 and the third sub-pixels 123 in the odd-numbered columns are arranged alternately, and the sub-pixels in the even-numbered columns are all second sub-pixels 122 . Each multiplexing circuit 21 electrically connects the first sub-pixel 121 , the second sub-pixel 122 , and the third sub-pixel 123 .

[0046] In this embodiment, the same multiplexing circuit is electrically connected to sub-pixels of at least two luminous colors, and the same data signal terminal provides data signals to sub-pixels of at least two luminous colors through the multiplexing circuit.

[0047] In some embodiments, Figure 6As shown, the input end of the multiplexing circuit 21 is electrically connected to the data signal end S through the first connection line 31, and the output end of the multiplexing circuit 21 is electrically connected to the data line 11 through the second connection line 32. The multiple output ends of the multiplexing circuit 21 are electrically connected to the multiple second connection lines 32 in a one-to-one correspondence. The first connection lines 31 electrically connected to different multiplexing circuits 21 do not cross, and the second connection lines 32 electrically connected to different multiplexing circuits 21 do not cross. In this article, "no crossing" between the routing lines means that the orthographic projections of the routing lines on the plane where the display device is located do not overlap.

[0048] It is understandable that the multiple second connection lines 32 electrically connected to the same multiplexing circuit 21 and the one first connection line 31 electrically connected between the same multiplexing circuit 21 and the data signal terminal S. Exemplarily, the multiple second connection lines 32 electrically connected to the same multiplexing circuit 21 do not cross each other.

[0049] As an example, Figure 6 As shown, the multiplexing circuit 21 includes a plurality of first transistors, the first electrodes of the first transistors are used as input terminals, the second electrodes of the first transistors are used as output terminals, and the first electrodes of the plurality of first transistors in the same multiplexing circuit 21 are electrically connected to each other. It can be understood that the first electrodes of the first transistors are electrically connected to the first connection line 31, and the second electrodes of the first transistors are electrically connected to the second connection line 32. The first connection lines 31 electrically connected to the first transistors in different multiplexing circuits 21 do not cross, and the second connection lines 32 electrically connected to the first transistors in different multiplexing circuits 21 do not cross.

[0050] The display panel includes n data lines 11, the driving chip includes n first transistors, and the n data lines 11 and the n first transistors are electrically connected in a one-to-one correspondence. For example, every two first transistors constitute a multiplexing circuit, and the driving chip includes n / 2 multiplexing circuits and n / 2 data signal terminals S. The n data lines 11 and the n first transistors are arranged in the same order. The n / 2 multiplexing circuits and the n / 2 data signal terminals S are arranged in the same order.

[0051] For example, Figure 6In the embodiment, the first first transistor T1_1 and the second first transistor T1_2 serve as the first multiplexing circuit 21_1, the third first transistor T1_3 and the fourth first transistor T1_4 serve as the second multiplexing circuit 21_2, the fifth first transistor T1_5 and the sixth first transistor T1_6 serve as the third multiplexing circuit 21_3, and so on, the n-1th first transistor T1_n-1 and the nth first transistor T1_n serve as the n / 2th multiplexing circuit 21_n / 2. The first data line 11_1 to the nth data line 11_n are arranged sequentially from left to right, and the first first transistor T1_1 to the nth first transistor T1_n are also arranged sequentially from left to right. The first multiplexing circuit 21_1 to the n / 2 th multiplexing circuit 21_n / 2 are arranged sequentially from left to right, and the first data signal terminal S_1 to the n / 2 th data signal terminal S_n are also arranged sequentially from left to right.

[0052] In this embodiment, the first connection lines electrically connecting different multiplexing circuits do not cross each other, and the second connection lines electrically connecting different multiplexing circuits do not cross each other, which can reduce the coupling effect between data signals transmitted by different multiplexing circuits, thereby improving the display effect.

[0053] In other embodiments, Figure 7 As shown, the data line 11 is electrically connected to the sub-pixel 12. The display panel includes sub-pixels of multiple luminous colors. The same multiplexing circuit electrically connects sub-pixels of the same luminous color, and at least two sub-pixels electrically connected by the multiplexing circuits have different luminous colors.

[0054] Exemplarily, the sub-pixel 12 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel 123 having different luminous colors. For example, the first sub-pixel 121 is a red sub-pixel, the second sub-pixel 122 is a green sub-pixel, and the third sub-pixel 123 is a blue sub-pixel. For example, part of the multiplexing circuit 21 is electrically connected to the first sub-pixel 121, another part of the multiplexing circuit 21 is electrically connected to the second sub-pixel 122, and another part of the multiplexing circuit 21 is electrically connected to the third sub-pixel 123.

[0055] For example, Figure 7In the embodiment, the first multiplexing circuit 21_1 is electrically connected to the first sub-pixel 121 and the first data signal terminal S_1, the second multiplexing circuit 21_2 is electrically connected to the second sub-pixel 122 and the second data signal terminal S_2, the third multiplexing circuit 21_3 is electrically connected to the third sub-pixel 123 and the third data signal terminal S_3, in addition, the fourth multiplexing circuit 21_4 is electrically connected to the first sub-pixel 121, the fifth multiplexing circuit 21_5 is electrically connected to the second sub-pixel 122, the sixth multiplexing circuit 21_6 is electrically connected to the third sub-pixel 123, and so on. Taking the first three data signal terminals as an example, the first data signal terminal S_1 only needs to provide the data signal required by the first sub-pixel 121, the second data signal terminal S_2 only needs to provide the data signal required by the second sub-pixel 122, and the third data signal terminal S_3 only needs to provide the data signal required by the third sub-pixel 123.

[0056] In the present embodiment, the same multiplexing circuit is electrically connected to sub-pixels of one luminous color, so that the data signal terminal electrically connected to the multiplexing circuit is only used to provide the data signal required for the sub-pixels of one luminous color. When displaying a pure color picture, only part of the data signal terminal needs to provide the data signal (that is, only part of the data signal terminal needs to be driven), which can greatly reduce the power consumption of the driving chip.

[0057] In some embodiments, the data lines extend along a first direction, a plurality of data lines are arranged in a second direction, and at least two data lines electrically connected to the same multiplexing circuit are separated in the second direction by at least one data line electrically connected to another multiplexing circuit.

[0058] Still Figure 7 For example, Figure 7 and Figure 6 The similarities are not repeated here, the differences include:

[0059] Figure 7 In the embodiment, the first first transistor T1_1 and the fourth first transistor T1_4 serve as the first multiplexing circuit 21_1, the second first transistor T1_2 and the fifth first transistor T1_5 serve as the second multiplexing circuit 21_2, the third first transistor T1_3 and the sixth first transistor T1_6 serve as the third multiplexing circuit 21_3, and so on, the n-3th first transistor T1_n-1 and the nth first transistor T1_n serve as the n / 2th multiplexing circuit 21_n / 2.

[0060] The first data line 11_1 to the nth data line 11_n are arranged sequentially from left to right, and the first first transistor T1_1 to the nth first transistor T1_n are also arranged sequentially from left to right. The first multiplexing circuit 21_1 electrically connects the first data line 11_1 and the fourth data line 11_4, the second multiplexing circuit 21_2 electrically connects the second data line 11_2 and the fifth data line 11_5, and the third multiplexing circuit 21_3 electrically connects the third data line 11_3 and the sixth data line 11_6. The two data lines electrically connected to the first multiplexing circuit 21_1 are separated by the data lines electrically connected to the second multiplexing circuit 21_2 and the third multiplexing circuit 21_3. Similarly, the two data lines electrically connected to the second multiplexing circuit 21_2 are separated by the data lines electrically connected to the first multiplexing circuit 21_1 and the third multiplexing circuit 21_3, and the two data lines electrically connected to the third multiplexing circuit 21_3 are separated by the data lines electrically connected to the first multiplexing circuit 21_1 and the second multiplexing circuit 21_2.

[0061] That is to say, the multiple data lines electrically connected to the same multiplexing circuit are not arranged adjacent to each other in the second direction, that is, the multiple sub-pixels of the same luminous color electrically connected to the same multiplexing circuit are not arranged adjacent to each other in the second direction. In this way, the multiple sub-pixels of the same luminous color can be dispersedly arranged in the second direction while reducing power consumption, thereby achieving a better pixel arrangement effect.

[0062] In other embodiments, the input end of the multiplexing circuit 21 is electrically connected to the data signal end S through a first connection line 31, and the output end of the multiplexing circuit 21 is electrically connected to the data line 11 through a second connection line 32. Multiple output ends of the multiplexing circuit 21 are electrically connected to multiple second connection lines 32 in a one-to-one correspondence. The first connection lines 31 electrically connected to at least two multiplexing circuits 21 cross each other, and the second connection lines 32 electrically connected to different multiplexing circuits 21 do not cross each other.

[0063] The multiple second connection lines 32 electrically connected to the same multiplexing circuit 21, and the one first connection line 31 electrically connected between the same multiplexing circuit 21 and the data signal terminal S. Exemplarily, the multiple second connection lines 32 electrically connected to the same multiplexing circuit 21 do not cross each other.

[0064] As an example, Figure 7As shown, the multiplexing circuit 21 includes a plurality of first transistors, the first electrodes of the first transistors are used as input terminals, the second electrodes of the first transistors are used as output terminals, and the first electrodes of the plurality of first transistors in the same multiplexing circuit 21 are electrically connected to each other. It is understandable that the first electrodes of the first transistors are electrically connected to the first connection line 31, and the second electrodes of the first transistors are electrically connected to the second connection line 32. The first connection lines 31 electrically connected to the first transistors in at least two multiplexing circuits 21 cross each other, and the second connection lines 32 electrically connected to the first transistors in different multiplexing circuits 21 do not cross each other.

[0065] In other words, in this embodiment, the crossed wiring is arranged on the input side of the multiplexing circuit, and there is no crossing between the wirings connected to the output side of the multiplexing circuit, thus avoiding the unpredictable coupling effect caused by the direct connection of the crossed wirings with the display panel.

[0066] In some embodiments, Figure 3 , Figure 4 , Figure 6 or Figure 7 As shown, the same data line 11 is electrically connected to the sub-pixel of the same luminous color, and the luminous colors of the sub-pixels electrically connected to at least two data lines 11 are different. For example, the sub-pixel 12 includes a first sub-pixel 121, a second sub-pixel 122, and a third sub-pixel 123 with different luminous colors. The first type of data line is electrically connected to the first sub-pixel 121, the second type of data line is electrically connected to the second sub-pixel 122, and the third type of data line is electrically connected to the third sub-pixel 123.

[0067] Exemplarily, the first sub-pixel 121 , the second sub-pixel 122 , and the third sub-pixel 123 are a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0068] Understandably, Figure 3 , Figure 4 , Figure 6 and Figure 7 The pixel arrangement shown is a real RGB pixel arrangement.

[0069] Of course, in other embodiments, the pixel arrangement may also be as follows: Figure 5 As shown, or, the pixel arrangement is other than that shown in the drawings of this application.

[0070] In some embodiments, Figure 6 or Figure 7As shown, the multiplexing circuit 21 includes a plurality of first transistors T1, the first electrodes of the first transistors T1 are used as input terminals, the first electrodes of the plurality of first transistors T1 are electrically connected to each other, and the second electrodes of the plurality of first transistors T1 are used as a plurality of output terminals. In a row scanning time, the plurality of first transistors in the same multiplexing circuit 21 are turned on in sequence.

[0071] For example, a multiplexing circuit 21 includes two first transistors. Figure 6 and Figure 8 , a row scanning time is marked as H. Taking the two first transistors in the first multiplexing circuit 21_1 as an example, the gate of the first first transistor T1_1 is connected to the first control line MUX1, and the gate of the second first transistor T1_2 is connected to the second control line MUX2. In a row scanning time H, the signals on the first control line MUX1 and the second control line MUX2 are at the on level in turn. When the signal on the first control line MUX1 is at the on level, the first first transistor T1_1 is turned on; the first data signal terminal S_1 transmits the data signal to the first data line 11_1. When the signal on the second control line MUX2 is at the on level, the second first transistor T1_2 is turned on, and the first data signal terminal S_1 transmits the data signal to the second data line 11_2.

[0072] The display panel includes multiple rows of sub-pixels. In one frame time, the multiple rows of sub-pixels are scanned row by row, and the scanning time corresponding to one row of sub-pixels is one row scanning time. In one row scanning time, multiple first transistors in the multiplexing circuit are turned on in sequence.

[0073] In this embodiment, within one row scanning time, a plurality of first transistors in the same multiplexing circuit are turned on in sequence, so that the same data signal terminal can provide data signals to different data lines in a time-sharing manner to avoid signal crosstalk on different data lines.

[0074] It should be noted that the first transistor is a P-type transistor in the drawings of the present application, and the conduction level on the first control line MUX1 and the second control line MUX2 is a low level for illustration, which is not intended to limit the present application. For example, in other examples, the first transistor is an N-type transistor, and correspondingly, the conduction level on the first control line MUX1 and the second control line MUX2 is a high level.

[0075] In some embodiments, within two adjacent row scanning times, the turn-on sequence of the plurality of first transistors of the same multiplexing circuit is the same.

[0076] For example, please refer to Figure 6 and Figure 8, in each row scanning time, the signal on the first control line MUX1 is first at the on level, and then the signal on the second control line MUX2 is at the on level. Taking the two first transistors in the first multiplexing circuit 21_1 as an example, in each row scanning time, the first first transistor T1_1 is first turned on, and then the second first transistor T1_2 is turned on. It can be understood that when the first first transistor T1_1 is turned on, the second first transistor T1_2 is turned off; when the second first transistor T1_2 is turned on, the first first transistor T1_1 is turned off.

[0077] For example, combined with reference Figure 6 The first first transistor T1_1 is electrically connected to the sub-pixels P1, P3, P5, and P7, and the second first transistor T1_2 is electrically connected to the sub-pixels P2, P4, P6, and P8. In this embodiment, the first data signal terminal S1_1 sequentially provides the data signals required by the sub-pixels P1 to P8.

[0078] In the above example, the first multiplexing circuit and the first data signal terminal electrically connected thereto are used as examples to illustrate the order in which data signals are provided. The same is true for other multiplexing circuits and the data signal terminals electrically connected thereto, which will not be described one by one here.

[0079] In some other embodiments, within two adjacent row scanning times, the turn-on order of the plurality of first transistors of the same multiplexing circuit is opposite.

[0080] For example, please refer to Figure 6 and Fig. 9 , taking the two first transistors in the first multiplexing circuit 21_1 as an example.

[0081] In the first row scanning time H_1, the signal on the first control line MUX1 is first at the on level, and then the signal on the second control line MUX2 is at the on level. In this period, the first first transistor T1_1 is first turned on, and then the second first transistor T1_2 is turned on.

[0082] In the second row scanning time H_2, the signal on the second control line MUX2 is first at the on level, and then the signal on the first control line MUX1 is at the on level. In this period, the second first transistor T1_2 is first turned on, and then the first first transistor T1_1 is turned on.

[0083] In the third row scanning time H_3, the signal on the first control line MUX1 is first at the on level, and then the signal on the second control line MUX2 is at the on level. In this period, the first first transistor T1_1 is first turned on, and then the second first transistor T1_2 is turned on.

[0084] In the fourth row scanning time H_4, the signal on the second control line MUX2 is first at the on level, and then the signal on the first control line MUX1 is at the on level. In this period, the second first transistor T1_2 is first turned on, and then the first first transistor T1_1 is turned on.

[0085] For example, the first first transistor T1_1 is electrically connected to the sub-pixels P1, P3, P5, and P7, and the second first transistor T1_2 is electrically connected to the sub-pixels P2, P4, P6, and P8. In this embodiment, the first data signal terminal S1_1 sequentially provides the data signals required by the sub-pixels P1, P2, P4, P3, P5, P6, P8, and P7.

[0086] For example, sub-pixels P1, P3, P5, and P7 are all sub-pixels of the first luminous color, and sub-pixels P2, P4, P6, and P8 are all sub-pixels of the second luminous color. When the data signal terminal S1_1 provides the data signals required by sub-pixels P2 and P4, the signal on the second control line MUX2 does not need to jump; when the data signal terminal S1_1 provides the data signals required by sub-pixels P3 and P5, the signal on the first control line MUX1 does not need to jump; when the data signal terminal S1_1 provides the data signals required by sub-pixels P6 and P8, the signal on the second control line MUX2 does not need to jump. In other words, when the data signal terminal S1_1 provides the data signals required by two sub-pixels on average, the signals on the first control line MUX1 and the second control line MUX2 jump once, so that the number of signal jumps on the first control line MUX1 and the second control line MUX2 can be reduced, thereby reducing the power consumption caused by the signal jumps on the first control line MUX1 and the second control line MUX2.

[0087] In some embodiments, Figure 6 or Figure 7 As shown, the multiplexing circuit 21 includes a plurality of first transistors T1, and the gates of the first transistors are connected to the first control signal. For example, the first transistors T1 include the first first transistor T1_1 to the nth first transistor T1_n.

[0088] The display panel includes a second transistor (not shown in the figure), and the gate of the second transistor is connected to the second control signal. Exemplarily, the display panel includes a gate drive circuit, the sub-pixel includes a pixel drive circuit and a light-emitting element, the pixel drive circuit includes a drive transistor and a switch transistor, and the second transistor is a transistor in the gate drive circuit, or the second transistor is a switch transistor in the pixel drive circuit.

[0089] The absolute value of the first on-level of the first control signal is smaller than the absolute value of the second on-level of the second control signal. For example, the first transistor and the second transistor are both turned on at a low level (negative level), the first on-level of the first control signal is a first low level, the second on-level of the second control signal is a second low level, and the absolute value of the first low level is smaller than the absolute value of the second low level.

[0090] The multiplexing circuit 21 is integrated on the driver chip 2, that is, the first transistor is integrated on the driver chip 2. The second transistor is arranged on the display panel. The driver chip has higher control accuracy than the display panel, so the absolute value of the first conduction level of the first control signal is smaller than the absolute value of the second conduction level of the second control signal, which will not affect the driving performance of the first transistor and can further reduce power consumption.

[0091] In some embodiments, the difference between the first cutoff level and the first on level of the first control signal is a first difference; the difference between the second cutoff level and the second on level of the second control signal is a second difference; the absolute value of the first difference is smaller than the absolute value of the second difference.

[0092] For example, the first cutoff level of the first control signal is VGH1, the first on-level of the first control signal is VGL1, the second cutoff level of the second control signal is VGH2, and the second on-level of the second control signal is VGL2, then |VGH1-VGL1|<|VGH2-VGL2|.

[0093] That is to say, the jump amplitude of the first control signal is smaller than the jump amplitude of the second control signal, which is more conducive to reducing the power consumption of the driving chip.

[0094] In some embodiments, the multiplexing circuit 21 includes a plurality of first transistors T1, the display panel includes a second transistor, and the second transistor includes a switch transistor of a pixel driving circuit in the display panel. The channel width-to-length ratio of the first transistor is greater than the channel width-to-length ratio of the second transistor. Here, the channel width-to-length ratio of the transistor refers to: the ratio of the channel width of the transistor to its channel length.

[0095] For example, Fig.10 As shown, the pixel driving circuit includes transistors M1 to M7, wherein transistor M3 is a driving transistor, and transistors M1, M2, M4, M5, M6, and M7 are all switch transistors. The second transistor is any one of transistors M1, M2, M4, M5, M6, and M7. It should be noted that Fig.10 The structure of the pixel driving circuit shown is merely an example and is not intended to limit the present application.

[0096] The display panel includes a plurality of sub-pixels, each of which includes a pixel driving circuit. As the resolution increases, the number of pixel driving circuits in the display panel increases, so the area occupied by the switch transistor in the pixel driving circuit is not too large.

[0097] Based on the higher control accuracy of the driver chip, in this embodiment, the first transistor integrated in the multiplexing circuit in the driver chip is arranged on the display panel relative to the multiplexing circuit, and the channel width-to-length ratio of the first transistor in the multiplexing circuit can be reduced. However, the channel width-to-length ratio of the first transistor in the multiplexing circuit integrated on the driver chip is still greater than the channel width-to-length ratio of the second transistor to ensure the driving capability of the first transistor.

[0098] In some embodiments, the multiplexing circuit 21 includes a plurality of first transistors T1, the gates of the first transistors are electrically connected to the first gate line. The display panel includes a second transistor, the gates of the second transistors are electrically connected to the second gate line, and the second transistors include switch transistors of pixel circuits in the display panel. The line width of the first gate line is greater than the line width of the second gate line.

[0099] For example, please compare reference Figure 6 and Fig.10 The first gate line includes a first control line MUX1 and / or a second control line MUX2, the second gate line includes any one of the scan lines S1, S2, S3, and Emit, the line width of the first control line MUX1 is greater than the line width of any one of the scan lines S1, S2, S3, and Emit, and the line width of the second control line MUX2 is greater than the line width of any one of the scan lines S1, S2, S3, and Emit.

[0100] The first gate line has a relatively large line width, which can reduce the impedance of the first gate line, thereby ensuring the driving capability of the first transistor.

[0101] Based on the same technical concept, the embodiment of the present application also provides a driver chip for driving a display panel, wherein the display panel includes a plurality of data lines. The driver chip includes: a multiplexing circuit and a data signal terminal, wherein the multiplexing circuit includes an input terminal and a plurality of output terminals, wherein the input terminal is electrically connected to the data signal terminal, and the output terminal is electrically connected to the data line.

[0102] Compared with setting the multiplexing circuit in the display panel, the multiplexing circuit needs to occupy the frame area of ​​the display panel, and the multiplexing circuit cannot be bent, resulting in a larger frame of the display panel. According to the driver chip provided in the embodiment of the present application, the multiplexing circuit is set in the driver chip, so that the multiplexing circuit no longer occupies the frame area of ​​the display panel, and a narrow frame of the display panel can be achieved.

[0103] Based on the same technical concept, the present application also provides an electronic device, including the display device provided by the present application. Fig.11 , Fig.11 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. Fig.11 The provided electronic device 1000 includes a display device 100, and the display device 100 includes the display device in any of the above embodiments of the present application. Fig.11 The embodiment only takes a mobile phone as an example to illustrate the electronic device 1000. It can be understood that the electronic device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other electronic devices with display functions, and the present application does not specifically limit this. The electronic device provided in the embodiment of the present application has the beneficial effects of the display device provided in the embodiment of the present application. For details, please refer to the specific description of the display device in the above embodiments, and this embodiment will not be repeated here.

[0104] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display device, characterized in that: include: A display panel including a plurality of data lines; The driving chip comprises a multiplexing circuit and a data signal terminal, wherein the multiplexing circuit comprises an input terminal and a plurality of output terminals, the input terminal is electrically connected to the data signal terminal, and the output terminal is electrically connected to the data line.

2. The display device according to claim 1, characterized in that The data lines extend along a first direction, a plurality of the data lines are arranged in a second direction, and the first direction and the second direction intersect; The plurality of data lines electrically connected to the same multiplexing circuit are adjacent to each other in the second direction.

3. The display device according to claim 2, characterized in that: The display panel includes sub-pixels of multiple luminous colors, and the data lines are electrically connected to the sub-pixels; The same multiplexing circuit electrically connects sub-pixels of at least two luminous colors.

4. The display device according to claim 2, characterized in that: The input terminal is electrically connected to the data signal terminal via a first connection line, and the output terminal is electrically connected to the data line via a second connection line; The first connection lines electrically connected to different multiplexing circuits do not cross each other, and the second connection lines electrically connected to different multiplexing circuits do not cross each other.

5. The display device according to claim 1, characterized in that The display panel includes sub-pixels of multiple luminous colors, and the data lines are electrically connected to the sub-pixels; The same multiplexing circuit is electrically connected to sub-pixels of the same luminous color, and at least two sub-pixels electrically connected to the multiplexing circuits have different luminous colors.

6. The display device according to claim 5, characterized in that: The data lines extend along a first direction, a plurality of the data lines are arranged in a second direction, and the first direction and the second direction intersect; At least two of the data lines electrically connected to the same multiplexing circuit are separated in the second direction by at least one data line electrically connected to another multiplexing circuit.

7. The display device according to claim 5, characterized in that: The input terminal is electrically connected to the data signal terminal via a first connection line, and the output terminal is electrically connected to the data line via a second connection line; The first connection lines electrically connected to at least two of the multiplexing circuits cross each other, and do not cross each other with the second connection lines.

8. The display device according to claim 1, characterized in that: The same data line is electrically connected to sub-pixels of the same luminous color, and the luminous colors of the sub-pixels electrically connected to at least two data lines are different.

9. The display device according to claim 1, characterized in that: The multiplexing circuit comprises a plurality of first transistors, the first electrodes of the first transistors serve as the input terminals, the second electrodes of the plurality of first transistors serve as the plurality of output terminals, and the first electrodes of the first transistors in the same multiplexing circuit are connected to each other; In one line scanning time, the plurality of first transistors of the same multiplexing circuit are turned on in sequence.

10. The display device according to claim 9, characterized in that: In two adjacent row scanning times, the turn-on sequence of the plurality of first transistors of the same multiplexing circuit is the same.

11. The display device according to claim 1, characterized in that: During two adjacent row scanning times, the turn-on sequence of the plurality of first transistors of the same multiplexing circuit is opposite.

12. The display device according to claim 1, characterized in that: The multiplexing circuit includes a plurality of first transistors, and gates of the first transistors are connected to a first control signal; The display panel comprises a second transistor, and a gate of the second transistor is connected to a second control signal; An absolute value of a first conduction level of the first control signal is smaller than an absolute value of a second conduction level of the second control signal.

13. The display device according to claim 12, characterized in that: The difference between the first cut-off level and the first on level of the first control signal is a first difference; The difference between the second cut-off level and the second on level of the second control signal is a second difference; An absolute value of the first difference is smaller than an absolute value of the second difference.

14. The display device according to claim 1, characterized in that The multiplexing circuit includes a plurality of first transistors, the display panel includes a second transistor, and the second transistor includes a switching transistor of a pixel circuit in the display panel; A channel width-to-length ratio of the first transistor is greater than a channel width-to-length ratio of the second transistor.

15. The display device according to claim 1, characterized in that: The multiplexing circuit includes a plurality of first transistors, the gates of the first transistors being electrically connected to the first gate line; The display panel comprises a second transistor, a gate of the second transistor is electrically connected to a second gate line, and the second transistor comprises a switch transistor of a pixel circuit in the display panel; The line width of the first gate line is greater than the line width of the second gate line.

16. A driver chip for driving a display panel, wherein the display panel comprises a plurality of data lines, characterized in that: The driver chip comprises: A multiplexing circuit and a data signal terminal, wherein the multiplexing circuit comprises an input terminal and a plurality of output terminals, wherein the input terminal is electrically connected to the data signal terminal, and the output terminal is electrically connected to the data line.

17. An electronic device, characterized in that: Comprising the display device as claimed in any one of claims 1 to 15.

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