Shift register, gate drive circuit and display panel

Abstract

The invention relates to the technical field of display, and particularly discloses a shift register, a gate drive circuit and a display panel, comprising a first pre-charging unit, a second pre-charging unit, a stability maintaining unit, a first output unit and a second output unit, the first pre-charging unit is configured to transmit a first clock signal to the control end of the first output unit according to a first pre-charging signal; the first output unit is configured to output a first level signal according to a second clock signal and a signal at the control end of the first output unit; the second pre-charging unit is configured to transmit a second clock signal to the control end of the second output unit according to a second pre-charging signal; the second output unit is configured to output a first level signal according to a first clock signal and a signal at the control end of the second output unit; the stability maintaining unit is configured to transmit the second level signal to the output end of the first output unit or the output end of the second output unit according to the trigger signal. The technical effect of a narrow frame can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] At present, most OLED products use a row scanning drive circuit to provide a gate drive signal for each row of pixel circuits, and each gate drive signal is generated by a shift register. However, with the development of display technology, the industry has increasingly demanded a narrow frame design for display panels, although the size of the display panel is getting larger and larger, requiring the display panel frame to have a compact structure and occupy a small area. Therefore, how to reduce the display panel frame has become a hot technical issue. Summary of the invention

[0003] Based on this, it is necessary to provide a shift register, a gate driving circuit and a display panel to solve the problem of how to reduce the frame of the display panel.

[0004] A shift register comprises a first pre-charge unit, a second pre-charge unit, a stabilization unit, a first output unit and a second output unit, wherein the output end of the first pre-charge unit is connected to the control end of the first output unit, and the first pre-charge unit is configured to transmit a first clock signal to the control end of the first output unit according to a first pre-charge signal; the first output unit is configured to output a first level signal according to a second clock signal and a signal at the control end of the first output unit; the output end of the second pre-charge unit is connected to the control end of the second output unit, and the second pre-charge unit is configured to transmit the second clock signal to the control end of the second output unit according to the second pre-charge signal; the second output unit is configured to output a first level signal according to the first clock signal and a signal at the control end of the second output unit; the stabilization unit is respectively connected to the output ends of the first pre-charge unit, the second pre-charge unit, the first output unit and the second output unit, and the stabilization unit is configured to transmit a second level signal to the output end of the first output unit or the output end of the second output unit according to a trigger signal.

[0005] In one embodiment, the first pre-charge unit includes a first transistor, the second pre-charge unit includes a second transistor, the stabilization unit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the first output unit includes a seventh transistor and an eighth transistor, the second output unit includes a ninth transistor and a tenth transistor, the first electrode of the first transistor is connected to the first clock terminal, the gate of the first transistor is connected to the first pre-charge terminal, and the second electrode of the first transistor is connected to the first node; the first electrode of the second transistor is connected to the second clock terminal, the gate of the second transistor is connected to the second pre-charge terminal, and the second electrode of the second transistor is connected to the second node; the gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are all connected to the trigger signal terminal; the first electrode of the third transistor is connected to the first node, and the first electrode of the fourth transistor is connected to the output of the first output unit end, the first electrode of the fifth transistor is connected to the second node, and the first electrode of the sixth transistor is connected to the output end of the second output unit; the second electrode of the third transistor, the second electrode of the fourth transistor, the second electrode of the fifth transistor and the second electrode of the sixth transistor are all connected to the second voltage end; the first electrode of the seventh transistor is connected to the first voltage end, the gate of the seventh transistor is connected to the second clock end, the second electrode of the seventh transistor is connected to the first electrode of the eighth transistor, the gate of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor serves as the output end of the first output unit; the first electrode of the ninth transistor is connected to the first voltage end, the gate of the ninth transistor is connected to the first clock end, the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor, the gate of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor serves as the output end of the second output unit.

[0006] In one embodiment, the shift register further includes a cascade unit, which is connected to the first node and the second node, and the cascade unit is configured to output a third pre-charge signal according to the voltage at the first node and to output a fourth pre-charge signal according to the voltage at the second node.

[0007] In one embodiment, the cascade unit includes an eleventh transistor and a twelfth transistor, the first electrode of the eleventh transistor is connected to the first output unit, the gate of the eleventh transistor is connected to the first node, and the second electrode of the eleventh transistor serves as the first output end of the cascade unit; the first electrode of the twelfth transistor is connected to the second output unit, the gate of the twelfth transistor is connected to the second node, and the second electrode of the twelfth transistor serves as the second output end of the cascade unit.

[0008] In one of the embodiments, the first output terminal of the cascade unit is connected to the control terminal of the second pre-charging unit.

[0009] In one embodiment, the shift register further includes an interlocking unit, which is respectively connected to the first node, the second node, the third node, the fourth node, the first output unit and the second output unit, and the interlocking unit is configured to initialize the first node and the second node according to the voltages at the third node and the fourth node.

[0010] In one embodiment, the interlocking unit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the gate of the thirteenth transistor and the gate of the fifteenth transistor are both connected to the third node, the gate of the fourteenth transistor and the gate of the sixteenth transistor are both connected to the fourth node, the first electrode of the thirteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second node, the first electrode of the fifteenth transistor is connected to the second clock terminal, the first electrode of the sixteenth transistor is connected to the first clock terminal, and the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the second electrode of the sixteenth transistor are all connected to the second voltage terminal.

[0011] In one embodiment, the shift register further includes a voltage holding unit, which is respectively connected to the first node, the second node, the first output unit and the second output unit, and is used to maintain the voltage at the first node and / or the second node.

[0012] In one embodiment, the voltage holding unit includes a first capacitor, a second capacitor and a seventeenth transistor, the first end of the first capacitor is connected to the first node, the first end of the second capacitor is connected to the second node, the second end of the first capacitor and the second end of the second capacitor are both connected to a second voltage end, the first electrode of the seventeenth transistor is connected to the output end of the first output unit, the gate of the seventeenth transistor is connected to the second voltage end, and the second electrode of the seventeenth transistor is connected to the output end of the second output unit.

[0013] A gate drive circuit comprises a plurality of cascaded shift registers as described in any one of the above embodiments, wherein the shift register comprises a first pre-charge unit, a cascade unit and an interlocking unit, wherein except for the first stage of the shift register, the cascade unit of each stage of the shift register is connected to the first pre-charge unit of the shift register of the next stage; and except for the last stage of the shift register, the interlocking unit of each stage of the shift register is connected to the first node and the second node of the shift register of the next stage.

[0014] A display panel comprises the gate driving circuit described in the above embodiment.

[0015] In the above-mentioned shift register, the first pre-charge unit transmits the first clock signal to the control end of the first output unit according to the first pre-charge signal, and the second pre-charge unit transmits the second clock signal to the control end of the second output unit according to the second pre-charge signal. The first output unit can output a first level signal according to the second clock signal and the voltage at the control end of the first output unit, and the second output unit can output a first level signal according to the first clock signal and the voltage at the control end of the second output unit. In addition, the stabilization unit can transmit the second level signal to the output end of the first output unit or the output end of the second output unit according to the trigger signal. The first output unit and the second output unit of the above-mentioned shift register can both output the first level signal or the second level signal, that is, the above-mentioned shift register can use the space occupied by a first-level shift register to output the signal waveforms required by two pixel circuits, which can greatly save the left and right borders of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the implementation methods of this specification or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0017] Figure 1 This is a schematic diagram of the structure of a shift register in one of the embodiments of the present application;

[0018] Figure 2 This is a circuit diagram of a shift register in one of the embodiments of the present application;

[0019] Figure 3 This is a schematic diagram of the structure of a shift register in another embodiment of the present application;

[0020] Figure 4 This is a circuit diagram of a shift register in another embodiment of the present application;

[0021] Figure 5 This is a schematic flow chart of a driving method of a shift register in one of the embodiments of the present application;

[0022] Figure 6 This is a timing diagram of various signals in a shift register in one embodiment of the present application;

[0023] Figure 7This is a schematic diagram of the structure of a gate driving circuit in one of the embodiments of the present application;

[0024] Figure 8 This is a connection diagram of two shift registers in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to understand the disclosure of the present invention more thoroughly and comprehensively.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] In the case of using “including”, “having” and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0028] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0029] In this application, unless otherwise clearly specified and limited, the terms "connected", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] The existing solution uses an 8T2C Scan circuit design to provide a gate drive signal for each row of pixel circuits, and each gate drive signal is generated by a shift register, that is, a first-level Scan circuit outputs a first-level gate drive signal. The shift register provided in this application can realize a first-level Scan circuit outputting two-level gate drive signals, which can greatly save left and right borders when applied to a display panel, achieving a narrow border effect.

[0031] Figure 1 This is a structural diagram of a shift register in one of the embodiments of the present application. In one of the embodiments, the shift register 10 may include a first pre-charge unit 100, a second pre-charge unit 200, a stabilization unit 300, a first output unit 400 and a second output unit 500.

[0032] The output end of the first pre-charge unit 100 can be connected to the control end of the first output unit 400, and the first pre-charge unit 100 can be configured to transmit the first clock signal SCK1 to the control end of the first output unit 400 according to the first pre-charge signal Cn-1. The first pre-charge unit 100 can also be connected to the first pre-charge end and the first clock end to obtain the first pre-charge signal Cn-1 through the first pre-charge end and obtain the first clock signal SCK1 through the first clock end, so that the first pre-charge unit 100 can transmit the first clock signal SCK1 to the control end of the first output unit 400 according to the first pre-charge signal Cn-1.

[0033] The first output unit 400 may be configured to output a first level signal VGL according to the second clock signal SCK2 and a signal at a control terminal of the first output unit 400. Figure 1 As shown, the connection point between the output terminal of the first pre-charge unit 100 and the control terminal of the first output unit 400 can be defined as a first node Qn. The first output unit 400 can also be connected to the second clock terminal and the first voltage terminal, and the first output unit 400 can obtain the second clock signal SCK2 through the second clock terminal and obtain the first level signal VGL through the first voltage terminal. In this embodiment, the first voltage terminal can be connected to a low-level signal source, and the low-level signal source can continuously provide the first level signal VGL, and the first level signal VGL can be a low-level signal.

[0034] The output end of the second pre-charge unit 200 can be connected to the control end of the second output unit 500, and the second pre-charge unit 200 can be configured to transmit the second clock signal SCK2 to the control end of the second output unit 500 according to the second pre-charge signal Cn. The second pre-charge unit 200 can also be connected to the second pre-charge end and the second clock end to obtain the second pre-charge signal Cn through the second pre-charge end and obtain the second clock signal SCK2 through the second clock end, so that the second pre-charge unit 200 can transmit the second clock signal SCK2 to the control end of the second output unit 500 according to the second pre-charge signal Cn.

[0035] The second output unit 500 may be configured to output a first level signal VGL according to the first clock signal SCK1 and the signal at the control terminal of the second output unit 500. Figure 1 As shown, the connection point between the output terminal of the second pre-charge unit 200 and the control terminal of the second output unit 500 can be defined as the second node Qn+1. The second output unit 500 can also be connected to the first clock terminal and the first voltage terminal, and the second output unit 500 can obtain the first clock signal SCK1 through the first clock terminal, and the second output unit 500 can obtain the first level signal VGL through the first voltage terminal.

[0036] The stabilization unit 300 may be connected to the output end of the first pre-charge unit 100, the second pre-charge unit 200, the first output unit 400, and the output end of the second output unit 500, respectively. The stabilization unit 300 may be configured to transmit the second level signal VGH to the output end of the first output unit 400 and / or the output end of the second output unit 500 according to the trigger signal SIN. The stabilization unit 300 may also be connected to the trigger signal end and the second voltage end, and the stabilization unit 300 may obtain the trigger signal SIN through the trigger signal end and obtain the second level signal VGH through the second voltage end, so that the stabilization unit 300 may transmit the second level signal VGH to the output end of the first output unit 400 or the output end of the second output unit 500 according to the trigger signal SIN. In this embodiment, the second voltage end may be connected to a high level signal source, and the high level signal source may continuously provide the second level signal VGH, and the second level signal VGH may be a high level signal.

[0037] The output end of the first output unit 400 can be defined as the first output end of the shift register 10, and the signal outputted from the first output end can be defined as the first output signal Sn. The output end of the second output unit 500 can be defined as the second output end of the shift register 10, and the signal outputted from the second output end can be defined as the second output signal Sn+1.

[0038] In the shift register 10 provided in the present application, the first pre-charge unit 100 transmits the first clock signal SCK1 to the control end of the first output unit 400 according to the first pre-charge signal Cn-1, and the second pre-charge unit 200 transmits the second clock signal SCK2 to the control end of the second output unit 500 according to the second pre-charge signal Cn. The first output unit 400 can output the first level signal VGL according to the second clock signal SCK2 and the voltage at the control end of the first output unit 400, and the second output unit 500 can output the first level signal VGL according to the second clock signal SCK2 and the voltage at the control end of the second output unit 500. In addition, the stabilization unit 300 can transmit the second level signal VGH to the output end of the first output unit 400 or the output end of the second output unit 500 according to the trigger signal SIN.

[0039] The first output terminal and the second output terminal of the shift register 10 can both output the first level signal VGL or the second level signal VGH, that is, the shift register 10 can use the space occupied by the first-level shift register to output the signal waveforms required by the two pixel circuits, which can greatly save the left and right borders of the display panel. In addition, by designing the stabilization unit 300, when the first output unit 400 or the second output unit 500 does not output the first level signal VGL, the stabilization unit 300 can output the second level signal VGH to the first output terminal or the second output terminal to improve the stability of the output of the shift register 10.

[0040] Figure 2 This is a circuit diagram of a shift register in one of the embodiments of the present application. The first pre-charge unit 100 may include a first transistor M1, the second pre-charge unit 200 may include a second transistor M2, the stabilization unit 300 may include a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6, the first output unit 400 may include a seventh transistor M7 and an eighth transistor M8, and the second output unit 500 may include a ninth transistor M9 and a tenth transistor M10.

[0041] In the embodiments of the present disclosure, a transistor refers to a component including at least a gate, a drain, and a source. In the present disclosure, the first electrode of the transistor may be a drain, the second electrode may be a source, or the first electrode may be a source, and the second electrode may be a drain. In the case of using transistors with opposite polarities or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In the embodiments of the present disclosure, the gate of all or part of the transistors may be used as the control electrode of the transistor, and the first electrode and the second electrode may be interchangeable as needed.

[0042] The first electrode of the first transistor M1 may be connected to the first clock terminal, the gate of the first transistor M1 may be connected to the first pre-charge terminal, and the second electrode of the first transistor M1 may be connected to the first node Qn. The first transistor M1 may be turned on or off according to the first pre-charge signal Cn-1 connected to the gate of the first transistor M1. When the first transistor M1 is turned on according to the first pre-charge signal Cn-1, the first clock signal SCK1 may be transmitted to the first node Qn through the first transistor M1.

[0043] The first electrode of the second transistor M2 can be connected to the second clock terminal, the gate of the second transistor M2 can be connected to the second pre-charge terminal, and the second electrode of the first transistor M2 can be connected to the second node Qn+1. The second transistor M2 is turned on or off according to the second pre-charge signal Cn connected to the gate of the second transistor M2. When the second transistor M2 is turned on according to the second pre-charge signal Cn, the second clock signal SCK2 outputted from the second clock terminal can be transmitted to the second node Qn+1 through the second transistor M2.

[0044] The gate of the third transistor M3, the gate of the fourth transistor M4, the gate of the fifth transistor M5, and the gate of the sixth transistor M6 may all be connected to the trigger signal terminal. The first electrode of the third transistor M3 may be connected to the first node Qn, the first electrode of the fourth transistor M4 may be connected to the output terminal of the first output unit 400, the first electrode of the fifth transistor M5 may be connected to the second node Qn+1, and the first electrode of the sixth transistor M6 may be connected to the output terminal of the second output unit 500. The second electrode of the third transistor M3, the second electrode of the fourth transistor M4, the second electrode of the fifth transistor M5, and the second electrode of the sixth transistor M6 may all be connected to the second voltage terminal.

[0045] The third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are all turned on or off according to the trigger signal SIN output by the trigger signal terminal. When the third transistor M3 is turned on according to the trigger signal SIN, the second level signal VGH output by the second voltage terminal can be transmitted to the first node Qn through the third transistor M3. When the fourth transistor M4 is turned on according to the trigger signal SIN, the second level signal VGH output by the second voltage terminal can be transmitted to the output terminal of the first output unit 400 through the fourth transistor M4. When the fifth transistor M5 is turned on according to the trigger signal SIN, the second level signal VGH output by the second voltage terminal can be transmitted to the second node Qn+1 through the fifth transistor M5. When the sixth transistor M6 is turned on according to the trigger signal SIN, the second level signal VGH output by the second voltage terminal can be transmitted to the output terminal of the second output unit 500 through the sixth transistor M6.

[0046] The first electrode of the seventh transistor M7 can be connected to the first voltage terminal, the gate of the seventh transistor M7 can be connected to the second clock terminal, the second electrode of the seventh transistor M7 can be connected to the first electrode of the eighth transistor M8, and the gate of the eighth transistor M8 can be connected to the first node Qn. Among them, the gate of the seventh transistor M7 and the gate of the eighth transistor M8 can be used as the control terminal of the first output unit 400, and the second electrode of the eighth transistor M8 can be used as the output terminal of the first output unit 400. The seventh transistor M7 is turned on or off according to the second clock signal SCK2 transmitted by the second clock terminal, and the eighth transistor M8 is turned on or off according to the voltage at the first node Qn. When the seventh transistor M7 is turned on according to the second clock signal SCK2 and the eighth transistor M8 is turned on according to the voltage at the first node Qn, the first level signal VGL transmitted by the first voltage terminal can be sequentially transmitted to the output terminal of the first output unit 400 through the seventh transistor M7 and the eighth transistor M8.

[0047] The first electrode of the ninth transistor M9 can be connected to the first voltage terminal, the gate of the ninth transistor M9 can be connected to the first clock terminal, the second electrode of the ninth transistor M9 can be connected to the first electrode of the tenth transistor M10, and the gate of the tenth transistor M10 can be connected to the second node Qn+1. Among them, the gate of the ninth transistor M9 and the gate of the tenth transistor M10 can be used as the control terminal of the second output unit 500, and the second electrode of the tenth transistor M10 can be used as the output terminal of the second output unit 500. The ninth transistor M9 is turned on or off according to the first clock signal SCK1 transmitted by the first clock terminal, and the tenth transistor M10 is turned on or off according to the voltage at the second node Qn+1. When the ninth transistor M9 is turned on according to the first clock signal SCK1 and the tenth transistor M10 is turned on according to the voltage at the second node Qn+1, the first level signal VGL transmitted by the first voltage terminal can be transmitted to the output terminal of the second output unit 500 through the ninth transistor M9 and the tenth transistor M10 in sequence.

[0048] Figure 3 This is a schematic diagram of the structure of a shift register in another embodiment of the present application. In one embodiment, the shift register 100 may further include a cascade unit 600. The cascade unit 600 may be connected to the first node Qn and the second node Qn+1, and the cascade unit 600 may be configured to output a third pre-charge signal Cn+1 according to the voltage at the first node Qn, and output a fourth pre-charge signal Cn+2 according to the voltage at the second node Qn+1.

[0049] The cascade pre-charging between the shift registers 10 of each stage can be realized by using the cascade unit 600. In some preferred embodiments, the third pre-charging signal Cn+1 output by the cascade unit 600 is the same as the signal waveform of the second pre-charging signal Cn connected to the second pre-charging unit 200. In this case, the cascade unit 600 can be connected to the second pre-charging unit 200 to output a signal waveform for controlling the second pre-charging unit 200 to enter the pre-charging state. The fourth pre-charging signal Cn+2 output by the cascade unit 600 in the shift register 10 of this stage is the same as the signal waveform of the first pre-charging signal Cn-1 connected to the first pre-charging unit 100 in the next stage of the shift register 10. In this case, the cascade unit 600 in the shift register 10 of this stage can be connected to the first pre-charging unit 100 in the next stage of the shift register 10 to output a signal waveform for controlling the first pre-charging unit 100 in the next stage of the shift register 10 to enter the pre-charging state.

[0050] For example, the third pre-charge signal Cn+1 output by the cascade unit 600 in the first-stage shift register 10 can be transmitted to the second pre-charge unit 200 of the first-stage shift register 10, that is, the first-stage shift register 10 uses the third pre-charge signal Cn+1 output by the cascade unit 600 in the first-stage shift register 10 to control the operation of the second pre-charge unit 200 in the first-stage shift register 10; the fourth pre-charge signal Cn+2 output by the cascade unit 600 in the first-stage shift register 10 can be transmitted to the first pre-charge unit 100 of the second-stage shift register 10, that is, the fourth pre-charge signal Cn+2 output by the cascade unit 600 in the first-stage shift register 10 controls the operation of the first pre-charge unit 100 in the second-stage shift register 10.

[0051] Figure 4 This is a circuit diagram of a shift register in another embodiment of the present application. In one embodiment, the cascade unit 600 may include an eleventh transistor M11 and a twelfth transistor M12, and the first electrode of the eleventh transistor M11 may be connected to the first output unit 400. Specifically, the first electrode of the eleventh transistor M11 is connected to the second electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8. The gate of the eleventh transistor M11 may be connected to the first node Qn, and the second electrode of the eleventh transistor M11 may serve as the first output terminal of the cascade unit 600. The first electrode of the twelfth transistor M12 may be connected to the second output unit 500, and specifically, the first electrode of the twelfth transistor M12 is connected to the second electrode of the ninth transistor M9 and the first electrode of the tenth transistor M10. The gate of the twelfth transistor M12 may be connected to the second node Qn+1, and the second electrode of the twelfth transistor M12 may serve as the second output terminal of the cascade unit 600.

[0052] The eleventh transistor M11 is turned on or off according to the voltage at the first node Qn, and the second electrode of the eleventh transistor M11 serves as the first output terminal of the cascade unit 600. The signal outputted from the first output terminal of the cascade unit 600 may be the third pre-charge signal Cn+1. The twelfth transistor M12 is turned on or off according to the voltage at the second node Qn+1, and the second electrode of the twelfth transistor M12 serves as the second output terminal of the cascade unit 600. The signal outputted from the second output terminal of the cascade unit 600 may be the fourth pre-charge signal Cn+2.

[0053] In this embodiment, preferably, the first output end of the cascade unit 600 in the shift register 10 at this stage can be connected to the control end of the second pre-charge unit 200 in the shift register 10 at this stage, and the control end of the second pre-charge unit 200 is the gate of the second transistor M2, that is, the second electrode of the eleventh transistor M11 can be connected to the gate of the second transistor M2. The third pre-charge signal Cn+1 output by the eleventh transistor M11 in the shift register 10 at this stage can be used as the second pre-charge signal Cn in the shift register 10 at this stage, and the second transistor M2 can be turned on or off according to the signal output by the eleventh transistor M11. When the eleventh transistor M11 is turned on according to the voltage at the first node Qn, the voltage at the connection between the second electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8 can be transmitted to the gate of the second transistor M2 through the eleventh transistor M11.

[0054] Preferably, the second output end of the cascade unit 600 in the shift register 10 of the present stage can be connected to the control end of the first pre-charge unit 100 in the shift register 10 of the next stage, that is, the second electrode of the twelfth transistor M12 in the shift register 10 of the present stage can be connected to the gate of the first transistor M1 in the shift register 10 of the next stage. The fourth pre-charge signal Cn+2 output by the twelfth transistor M12 in the shift register 10 of the present stage can be used as the first pre-charge signal Cn-1 in the shift register 10 of the next stage, that is, the first transistor M1 in the shift register 10 of the next stage is turned on or off according to the signal output by the twelfth transistor M12 in the shift register 10 of the present stage. Similarly, when the shift register 10 of the present stage is not the shift register 10 of the first stage, the first pre-charge signal Cn-1 connected to the gate of the first transistor M1 in the shift register 10 of the present stage can also be the fourth pre-charge signal Cn+2 output by the twelfth transistor M12 in the shift register 10 of the previous stage.

[0055] When the twelfth transistor M12 in the shift register 10 at this stage is turned on according to the voltage at the second node Qn+1, the voltage at the connection between the second electrode of the ninth transistor M9 and the first electrode of the tenth transistor M10 in the shift register 10 at this stage can be transmitted to the gate of the first transistor M1 of the shift register 10 at the next stage through the twelfth transistor M12 of the shift register 10 at this stage.

[0056] In some other embodiments, the first pre-charge signal Cn-1 connected to the first pre-charge unit 100 and the second pre-charge signal Cn connected to the second pre-charge unit 200 in each level of the shift register 10 can be independent input signals, and the corresponding signal waveforms are designed according to the requirements of different application scenarios in specific applications. At the same time, the third pre-charge signal Cn+1 and the fourth pre-charge signal Cn+2 outputted from the first output end of the cascade unit 600 in each level of the shift register 10 can also be connected to other circuits to provide signal waveforms required by other circuits.

[0057] In one embodiment, see Figure 3 , the shift register 10 may further include an interlocking unit 700. The interlocking unit 700 may be connected to the first node Qn, the second node Qn+1, the third node Qn+2, the fourth node Qn+3, the first output unit 400, and the second output unit 500, respectively. The interlocking unit 700 may be configured to initialize the first node Qn and the second node Qn+1 according to the voltages at the third node Qn+2 and the fourth node Qn+3. The shift register 10 provided in the present application may utilize the interlocking unit 700 to implement initialization between cascaded shift registers 10, and when the shift register 10 of the next level is output, the shift register 10 of the previous level is initialized.

[0058] In one embodiment, see Figure 4 The interlocking unit 700 may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16, the gate of the thirteenth transistor M13 and the gate of the fifteenth transistor M15 may be both connected to the third node Qn+2, the gate of the fourteenth transistor M14 and the gate of the sixteenth transistor M16 may be both connected to the fourth node Qn+3, the first electrode of the thirteenth transistor M13 may be connected to the first node Qn, the first electrode of the fourteenth transistor M14 may be connected to the second node Qn+1, the first electrode of the fifteenth transistor M15 may be connected to the second clock terminal, the first electrode of the sixteenth transistor M16 may be connected to the first clock terminal, the second electrode of the thirteenth transistor M13, the second electrode of the fourteenth transistor M14, the second electrode of the fifteenth transistor M15 and the second electrode of the sixteenth transistor M16 may be all connected to the second voltage terminal.

[0059] The thirteenth transistor M13 and the fifteenth transistor M15 can both be turned on or off according to the voltage at the third node Qn+2, and the fourteenth transistor M14 and the sixteenth transistor M16 can both be turned on or off according to the voltage at the fourth node Qn+3. In this embodiment, preferably, the potential change at the third node Qn+2 in the shift register 10 of this stage can be the same as the potential change at the first node Qn in the shift register 10 of the next stage, and the potential change at the fourth node Qn+3 in the shift register 10 of this stage can be the same as the potential change at the second node Qn+1 in the shift register 10 of the next stage.

[0060] In a specific embodiment, the gate of the thirteenth transistor M13 and the gate of the fifteenth transistor M15 in the shift register 10 at the present stage are connected to the first node Qn of the shift register 10 at the next stage, and the gate of the fourteenth transistor M14 and the gate of the sixteenth transistor M16 in the shift register 10 at the present stage are connected to the second node Qn+1 of the shift register 10 at the next stage, so as to achieve the technical effect that the potential change at the third node Qn+2 in the shift register 10 at the present stage is the same as the potential change at the first node Qn in the shift register 10 at the next stage, and the potential change at the fourth node Qn+3 in the shift register 10 at the present stage is the same as the potential change at the second node Qn+1 in the shift register 10 at the next stage.

[0061] In some other embodiments, the corresponding technical effects may also be achieved by respectively connecting the third node Qn+2 and the fourth node Qn+3 in the shift register 10 at this stage to corresponding signals.

[0062] In one embodiment, see Figure 3 , the shift register 10 may further include a voltage holding unit 800, which may be connected to the first node Qn, the second node Qn+1, the first output unit 400 and the second output unit 500, respectively, and the voltage holding unit 800 is used to hold the voltage at the first node Qn and the second node Qn+1. The shift register 10 may use the voltage holding unit 800 to achieve technical effects such as stabilization and resetting.

[0063] In one embodiment, see Figure 4 , the voltage holding unit 800 may include a first capacitor C1, a second capacitor C2 and a seventeenth transistor M17, the first end of the first capacitor C1 may be connected to the first node Qn, the first end of the second capacitor C2 may be connected to the second node Qn+1, the second end of the first capacitor C1 and the second end of the second capacitor C2 may both be connected to the second voltage terminal. The first capacitor C1 may be used to achieve the technical effect of maintaining the potential at the first node Qn, and the second capacitor C2 may be used to achieve the technical effect of maintaining the potential at the second node Qn+1.

[0064] The first electrode of the seventeenth transistor M17 may be connected to the output terminal of the first output unit 400, the gate of the seventeenth transistor M17 may be connected to the second voltage terminal, and the second electrode of the seventeenth transistor M17 may be connected to the output terminal of the second output unit 500. Specifically, the first electrode of the seventeenth transistor M17 is connected to the second electrode of the eighth transistor M8, and the second electrode of the seventeenth transistor M17 is connected to the second electrode of the tenth transistor M10.

[0065] In one embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16 and the seventeenth transistor M17 in the shift register provided by the present application can all be P-type transistors, for example, they can be polycrystalline silicon thin film transistors. Therefore, the conduction level of each transistor in the above-mentioned shift register 10 can be a low level, and the cut-off level can be a high level. In some other embodiments, the device selection of each unit in the above-mentioned shift register 10 can also select other suitable functional elements according to actual application requirements.

[0066] Since the gate of the seventeenth transistor M17 is connected to the second voltage terminal, that is, the gate of the seventeenth transistor M17 is connected to the second voltage terminal, and the second voltage terminal is connected to the high-level signal source, the seventeenth transistor M17 is in a normally closed state. The seventeenth transistor M17 can also be used as a sampling unit to detect the output signal of the first output unit 400 by sampling the waveform at the first electrode of the seventeenth transistor M17, and to detect the output signal of the second output unit 500 by sampling the waveform at the second electrode of the seventeenth transistor M17.

[0067] An embodiment of the present invention further provides a driving method for driving the shift register 10 as described in any of the above embodiments. A working cycle of the shift register 10 may include a first stage T1, a second stage T2, a third stage T3 and a fourth stage T4. Figure 5 This is a flowchart of a driving method of a shift register in one embodiment of the present application. In one embodiment, the driving method may include the following steps S100 to S400.

[0068] Step S100: In the first stage, the trigger signal is controlled to be at an on level, the first pre-charge signal is controlled to be at an off level, and the first clock signal is controlled to be at an off level.

[0069] Figure 6This is a timing diagram of various signals in a shift register in one embodiment of the present application. Figure 6 In the figure, SIN represents a trigger signal, Cn-1 represents a first precharge signal, Cn represents a second precharge signal, SCK1 represents a first clock signal, SCK2 represents a second clock signal, Sn represents a first output signal, i.e., a signal output at the first output terminal of the shift register 10, and Sn+1 represents a second output signal, i.e., a signal output at the second output terminal of the shift register 10. Figure 4 The shift register 10 shown in FIG. Figure 6 The timing diagram shown in FIG. 1 describes in detail the working process of the shift register 10 in one working cycle. Figure 4 The transistors in the shift register 10 are all P-type transistors, so in this embodiment, the on-level may refer to a low-level signal, and the off-level may refer to a high-level signal.

[0070] When the shift register 10 operates in the first stage T1, the trigger signal SIN is a low level signal, the first pre-charge signal Cn-1 is a high level signal, and the first clock signal SCK1 is a high level signal. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned on according to the trigger signal SIN, the first transistor M1 is turned off according to the first pre-charge signal Cn-1, and the ninth transistor M9 is turned off according to the first clock signal SCK1.

[0071] Since the third transistor M3 and the fifth transistor M5 are turned on, the second level signal VGH is transmitted to the first node Qn through the third transistor M3, and the second level signal VGH is transmitted to the second node Qn+1 through the fifth transistor M5. Since the voltages at the first node Qn and the second node Qn+1 are both at a high level, the eighth transistor M8, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are all turned off. Since the eighth transistor M8 is turned off, regardless of whether the seventh transistor M7 is turned on, the first level signal VGL cannot be transmitted to the second electrode of the eighth transistor M8, that is, the first level signal VGL cannot be transmitted to the first output terminal.

[0072] At the same time, since the fourth transistor M4 and the sixth transistor M6 are turned on, the second level signal VGH is transmitted to the second electrode of the eighth transistor M8 through the fourth transistor M4, that is, in the first stage T1, the first output signal Sn output by the first output terminal is a high level. At the same time, the second level signal VGH is transmitted to the second electrode of the tenth transistor M10 through the sixth transistor M6, that is, in the first stage T1, the second output signal Sn+1 output by the second output terminal is also a high level.

[0073] Step S200: In the second stage, the trigger signal is controlled to be at a cut-off level, the first pre-charge signal is controlled to be at a conduction level, the first clock signal is controlled to be at a conduction level, and the second clock signal is controlled to be at a cut-off level.

[0074] When the shift register 10 works in the second stage T2, the shift register 10 can realize the pre-charging of the first node Qn by the first pre-charging unit 100. The trigger signal SIN is a high-level signal, the first pre-charging signal Cn-1 is a low-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off according to the trigger signal SIN, the first transistor M1 is turned on according to the first pre-charging signal Cn-1, the ninth transistor M9 is turned on according to the first clock signal SCK1, and the seventh transistor M7 is turned off according to the second clock signal SCK2.

[0075] After the first transistor M1 is turned on, the first clock signal SCK1 can be transmitted to the first node Qn through the first transistor M1. Since the first clock signal SCK1 is a low-level signal, the potential at the first node Qn becomes a low level, so that the eighth transistor M8 is turned on according to the low level at the first node Qn. At this time, the seventh transistor M7 is turned off according to the second clock signal SCK2, and the first level signal VGL still cannot be transmitted to the second electrode of the eighth transistor M8, that is, the first level signal VGL cannot be transmitted to the first output terminal. In the second stage T2, the first output signal Sn output by the first output terminal is still a high level.

[0076] After the eleventh transistor M11 is turned on according to the low level at the first node Qn, the high level at the first pole of the eighth transistor M8 is output through the second pole of the eleventh transistor M11. In the present embodiment, the second pole of the eleventh transistor M11 is connected to the gate of the second transistor M2. That is, the high level at the first pole of the eighth transistor M8 is transmitted to the gate of the second transistor M2 through the eleventh transistor M11, and the second transistor M2 is turned off according to the high level at its gate. The potential at the second node Qn+1 is still at a high level, so the tenth transistor M10 is still turned off. In the second stage T2, the second output signal Sn+1 output by the second output terminal is still at a high level.

[0077] Step S300: In the third stage, the trigger signal is controlled to be at a cut-off level, the first pre-charge signal is controlled to be at a cut-off level, the first clock signal is controlled to be at a cut-off level, and the second clock signal is controlled to be at a conduction level.

[0078] When the shift register 10 operates in the third stage T3, the shift register 10 can simultaneously realize that the first output terminal outputs a low-level signal, and the second pre-charge unit 200 pre-charges the second node Qn+1. The trigger signal SIN is a high-level signal, the first pre-charge signal Cn-1 is a high-level signal, the first clock signal SCK1 is a high-level signal, and the second clock signal SCK2 is a low-level signal. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off according to the trigger signal SIN, the first transistor M1 is turned off according to the first pre-charge signal Cn-1, the ninth transistor M9 is turned off according to the first clock signal SCK1, and the seventh transistor M7 is turned on according to the second clock signal SCK2.

[0079] Due to the voltage holding effect of the first capacitor C1, the potential at the first node Qn is maintained at a low level, so the eighth transistor M8 is turned on according to the low level at the first node Qn. At the same time, the seventh transistor M7 is turned on, so that the first level signal VGL can be transmitted to the first output terminal through the seventh transistor M7 and the eighth transistor M8 in sequence. That is, in the third stage T3, the first output signal Sn output by the first output terminal is a low level.

[0080] The eleventh transistor M11 is turned on according to the low level at the first node Qn, so that the first level signal VGL can also be transmitted to the gate of the second transistor M2 according to the eleventh transistor M11, that is, the third pre-charge signal Cn+1 output by the eleventh transistor M11 is a low level signal at this time. The second transistor M2 is turned on according to the first level signal VGL. After the second transistor M2 is turned on, the second clock signal SCK2 is transmitted to the second node Qn+1 through the second transistor M2. Since the second clock signal SCK2 is a low level signal, the potential at the second node Qn+1 becomes a low level, so that the tenth transistor M10 is turned on according to the low level at the second node Qn+1. At this time, the ninth transistor M9 is turned off according to the first clock signal SCK1, and the first level signal VGL cannot be transmitted to the second pole of the tenth transistor M10, that is, the first level signal VGL cannot be transmitted to the first output terminal. That is, in the third stage T2, the second output signal Sn+1 output by the second output terminal is still a high level.

[0081] Step S400: In the fourth stage, the trigger signal is controlled to be a cut-off level, the first pre-charge signal is controlled to be a cut-off level, the first clock signal is controlled to be a conduction level, and the second clock signal is controlled to be a cut-off level.

[0082] When the shift register 10 operates in the fourth stage T4, the shift register 10 can realize that the second output terminal outputs a low-level signal. The trigger signal SIN is a high-level signal, the first pre-charge signal Cn-1 is a high-level signal, the first clock signal SCK1 is a low-level signal, and the second clock signal SCK2 is a high-level signal. The third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are all turned off according to the trigger signal SIN, the first transistor M1 is turned off according to the first pre-charge signal Cn-1, the ninth transistor M9 is turned on according to the first clock signal SCK1, and the seventh transistor M7 is turned off according to the second clock signal SCK2.

[0083] Due to the voltage holding effect of the second capacitor C2, the potential at the second node Qn+1 is maintained at a low level, so the tenth transistor M10 is turned on according to the low level at the second node Qn+1. At the same time, the ninth transistor M9 is turned on, so that the first level signal VGL can pass through the ninth transistor M9 and the tenth transistor M10 in sequence to the second output terminal. That is, in the fourth stage T4, the second output signal Sn+1 output by the second output terminal is a low level.

[0084] In addition, since the seventh transistor M7 is turned off, no matter whether the eighth transistor M8 is turned on or not, the first level signal VGL cannot be transmitted to the second electrode of the eighth transistor M8, that is, the first level signal VGL cannot be transmitted to the first output terminal. That is, in the fourth stage T4, the first output signal Sn output by the first output terminal is a high level.

[0085] After the twelfth transistor M12 is turned on according to the low level at the second node Qn+1, the first level signal VGL can also be transmitted to the first transistor M1 of the next-stage shift register 10 through the twelfth transistor M12, that is, the fourth pre-charge signal Cn+2 output by the twelfth transistor M12 in the current-stage shift register 10 is a low-level signal, so that the first transistor M1 of the next-stage shift register 10 can be turned on according to the first level signal VGL to realize the pre-charge of the first node Qn in the next-stage shift register 10.

[0086] In this embodiment, the third node Qn+2 of the shift register 10 of this stage is connected to the first node Qn of the shift register 10 of the next stage, and the fourth node Qn+3 of the shift register 10 of this stage is connected to the second node Qn+1 of the shift register 10 of the next stage. Therefore, in the above-mentioned first stage T1, second stage T2, third stage T3 and fourth stage T4, since the two pre-charge units of the shift register 10 of the next stage do not receive the pre-charge signal, and the working process is not started, the potential of the first node Qn and the potential of the second node Qn+1 of the shift register 10 of the next stage are maintained at a high level in the above-mentioned process, so the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 are all maintained in the cut-off state.

[0087] In one embodiment, the shift register 10 may further include a fifth stage in a working cycle, and the driving method may further include the following steps: in the fifth stage, controlling the potential at the third node to be a conduction level, and controlling the potential at the fourth node to be a conduction level.

[0088] In some embodiments, the driving process of the fifth stage can be implemented by connecting a low level signal to the third node Qn+2 and the fourth node Qn+3.

[0089] In this embodiment, preferably, the third node Qn+2 of the current-stage shift register 10 is connected to the first node Qn of the next-stage shift register 10, and the fourth node Qn+3 of the current-stage shift register 10 is connected to the second node Qn+1 of the next-stage shift register 10. Thus, after the current-stage shift register 10 outputs the fourth pre-charge signal Cn+2 of the low level, the next-stage shift register 10 will start to execute the work flow of the second stage T2, the third stage T3 and the fourth stage T4 as described in the above embodiment.

[0090] In the working process of the next-stage shift register 10, when the potential at the first node Qn of the next-stage shift register 10 becomes a low level, since the third node Qn+2 of the current-stage shift register 10 is connected to the first node Qn of the next-stage shift register 10, the potential at the third node Qn+2 of the current-stage shift register 10 also becomes a low level. At this time, the thirteenth transistor M13 and the fifteenth transistor M15 are turned on according to the potential at the third node Qn+2, and the second level signal VGH is transmitted to the first node Qn through the thirteenth transistor M13 to initialize the potential at the first node Qn. The second level signal VGH is also transmitted to the gate of the seventh transistor M7 through the fifteenth transistor M15 to initialize the gate of the seventh transistor M7.

[0091] When the potential at the second node Qn+1 of the next-stage shift register 10 becomes a low level, since the fourth node Qn+3 of the current-stage shift register 10 is connected to the second node Qn+1 of the next-stage shift register 10, the potential at the fourth node Qn+3 of the current-stage shift register 10 also becomes a low level. At this time, the fourteenth transistor M14 and the sixteenth transistor M16 are turned on according to the potential at the fourth node Qn+3, and the second level signal VGH is transmitted to the second node Qn+1 through the fourteenth transistor M14 to initialize the potential at the second node Qn+1. The second level signal VGH is also transmitted to the gate of the ninth transistor M9 through the sixteenth transistor M16 to initialize the gate of the ninth transistor M9. It can be seen that in the fifth stage, when the next-stage shift register 10 is output, the initialization of the previous-stage shift register 10 can be realized.

[0092] The driving method of the shift register is applied to the shift register 10 described in any one of the above embodiments, and the first pre-charge unit 100, the stabilization unit 300 and the first output unit 400 cooperate to output the first output signal Sn, and the first output signal Sn can be transmitted to the pixel circuit as a gate drive signal to drive the functional unit in the pixel circuit to work. Among them, the first pre-charge unit 100 is used to realize the pre-charging of the first node Qn, the first output unit 400 outputs the first level signal VGL according to the first node Qn and the second clock signal SCK2, and the stabilization unit 300 is used to output the second level signal VGH that remains stable when the first output unit 400 does not output the first level signal VGL.

[0093] At the same time, the second pre-charge unit 200, the stabilization unit 300 and the second output unit 500 cooperate to output the second output signal Sn+1, and the second output signal Sn+1 can also be transmitted to the pixel circuit as a gate drive signal to drive the functional unit in the pixel circuit to work. Among them, the second pre-charge unit 200 is used to realize the pre-charging of the second node Qn+1, the second output unit 500 outputs the first level signal VGL according to the second node Qn+1 and the second clock signal SCK2, and the stabilization unit 300 is used to output the second level signal VGH that remains stable when the second output unit 500 does not output the first level signal VGL.

[0094] It can be seen that when the driving method of the shift register is applied to the shift register 10 described in any of the above embodiments, a first-level Scan circuit can output a two-level gate drive signal, thereby optimizing the circuit structure and achieving a technical effect of a narrow frame. At the same time, the stabilization unit 300 can output a stable second-level signal VGH to the first output terminal and the second output terminal when the first output unit 400 and the second output unit 500 do not output the first-level signal VGL, so as to improve the stability of the output of the shift register 10.

[0095] It should be understood that, although the steps in the flowcharts of the accompanying drawings of the specification are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts of the accompanying drawings of the specification may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0096] An embodiment of the present invention further provides a gate driving circuit, which may include a plurality of cascaded shift registers as described in any one of the above embodiments. Figure 7 This is a schematic diagram of the structure of a gate driving circuit in one embodiment of the present application. In one embodiment, the gate driving circuit may include an N-stage shift register 10, where N is an integer greater than 0. Each stage of the shift register 10 may include a first pre-charge unit 100, a cascade unit 600, and an interlock unit 700.

[0097] Figure 8 This is a connection diagram of two shift registers in one embodiment of the present application. Figure 8 What is shown is the connection between two shift registers 10 in the gate drive circuit, wherein, in order to better show the connection between the shift registers 10 at each level in the gate drive circuit, some structures in the shift register 10 are omitted, but this should not be understood as limiting the scope of the invention patent.

[0098] In the above gate driving circuit, the first pre-charge signal Cn-1 connected to the control end of the first pre-charge unit 100 in the first-stage shift register 10 can be an independent input signal, or can be the fourth pre-charge signal Cn+2 output by the cascade unit 600 in the Nth-stage shift register 10. The first pre-charge signal Cn-1 connected to the control end of the first pre-charge unit 100 in the x-th shift register 10 can be the fourth pre-charge signal Cn+2 (wherein, x=2, 3, 4, ..., N) output by the cascade unit 600 in the x-1th shift register 10; the cascade unit in the x-th shift register 10 can be connected to the first pre-charge unit 100 in the x+1th shift register 10, and the fourth pre-charge signal Cn+2 output by the cascade unit 600 in the x-th shift register 10 can be used as the first pre-charge signal Cn-1 of the first pre-charge unit 100 in the x+1th shift register 10 to control the operation of the first pre-charge unit 100 in the x+1th shift register 10.

[0099] At the same time, the third node Qn+2 and the fourth node Qn+3 in the N-th stage shift register 10 can be individually connected to the corresponding signal waveform to realize the initialization of the N-th stage shift register 10. The third node Qn+2 in the N-th stage shift register 10 can also be connected to the first node Qn in the first-stage shift register 10, and the fourth node Qn+3 in the N-th stage shift register 10 can also be connected to the second node Qn+1 in the first-stage shift register 10, so that when the first-stage shift register 10 outputs, the N-th stage shift register 10 can be initialized.

[0100] The interlocking unit 700 in the y-th stage shift register 10 is connected to the first node Qn and the second node Qn+1 of the y+1-th stage shift register 10, wherein y=1, 2, 3, ..., N-1. Specifically, the third node Qn+2 in the y-th stage shift register 10 is connected to the first node Qn of the y+1-th stage shift register 10, and the fourth node Qn+4 in the y-th stage shift register 10 is connected to the second node Qn+1 of the y+1-th stage shift register 10, so that when the y+1-th stage shift register 10 outputs, the y-th stage shift register 10 can be initialized.

[0101] In the above gate drive circuit, each level of shift register 10 can output two levels of gate drive signals, which reduces the space occupied by the gate drive circuit. When the above gate drive circuit is applied to a display panel, the left and right borders can be greatly saved, achieving the technical effect of a narrow border. At the same time, the cascade shift trigger between each level of shift register 10 has high circuit stability.

[0102] An embodiment of the present invention further provides a display panel, which includes the gate drive circuit described in any one of the above embodiments. The display panel may include one or more groups of gate drive circuits. Among them, the gate drive circuit can be configured to generate a gate drive signal and use the gate drive signal to change the conduction state of the switch device in the pixel circuit. The display panel can be applied to any product or component with a display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop displays, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiments of the present invention do not specifically limit this.

[0103] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be based on the attached claims.

Claims

1. A shift register, characterized in that: It includes a first pre-charging unit, a second pre-charging unit, a stabilization unit, a first output unit and a second output unit, The output end of the first pre-charge unit is connected to the control end of the first output unit, and the first pre-charge unit is configured to transmit the first clock signal to the control end of the first output unit according to the first pre-charge signal; The first output unit is configured to output a first level signal according to a second clock signal and a signal at a control terminal of the first output unit; The output end of the second pre-charge unit is connected to the control end of the second output unit, and the second pre-charge unit is configured to transmit the second clock signal to the control end of the second output unit according to the second pre-charge signal; The second output unit is configured to output a first level signal according to the first clock signal and a signal at a control terminal of the second output unit; The stabilization maintaining unit is respectively connected to the first pre-charging unit, the second pre-charging unit, the output end of the first output unit and the output end of the second output unit, and the stabilization maintaining unit is configured to transmit the second level signal to the output end of the first output unit or the output end of the second output unit according to the trigger signal.

2. The shift register according to claim 1, characterized in that: The first pre-charge unit includes a first transistor, the second pre-charge unit includes a second transistor, the stabilization unit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, the first output unit includes a seventh transistor and an eighth transistor, the second output unit includes a ninth transistor and a tenth transistor, A first electrode of the first transistor is connected to a first clock terminal, a gate of the first transistor is connected to a first pre-charge terminal, and a second electrode of the first transistor is connected to a first node; A first electrode of the second transistor is connected to a second clock terminal, a gate of the second transistor is connected to a second pre-charge terminal, and a second electrode of the second transistor is connected to a second node; The gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are all connected to the trigger signal terminal; the first electrode of the third transistor is connected to the first node, the first electrode of the fourth transistor is connected to the output terminal of the first output unit, the first electrode of the fifth transistor is connected to the second node, and the first electrode of the sixth transistor is connected to the output terminal of the second output unit; the second electrode of the third transistor, the second electrode of the fourth transistor, the second electrode of the fifth transistor and the second electrode of the sixth transistor are all connected to the second voltage terminal; A first electrode of the seventh transistor is connected to the first voltage terminal, a gate of the seventh transistor is connected to the second clock terminal, a second electrode of the seventh transistor is connected to the first electrode of the eighth transistor, a gate of the eighth transistor is connected to the first node, and a second electrode of the eighth transistor serves as an output terminal of the first output unit; The first electrode of the ninth transistor is connected to the first voltage terminal, the gate of the ninth transistor is connected to the first clock terminal, the second electrode of the ninth transistor is connected to the first electrode of the tenth transistor, the gate of the tenth transistor is connected to the second node, and the second electrode of the tenth transistor serves as the output terminal of the second output unit.

3. The shift register according to claim 1 or 2, characterized in that: The shift register also includes a cascade unit connected to the first node and the second node, and the cascade unit is configured to output a third pre-charge signal according to the voltage at the first node and to output a fourth pre-charge signal according to the voltage at the second node.

4. The shift register according to claim 3, characterized in that: The cascade unit includes an eleventh transistor and a twelfth transistor, wherein a first electrode of the eleventh transistor is connected to the first output unit, a gate of the eleventh transistor is connected to the first node, and a second electrode of the eleventh transistor serves as a first output end of the cascade unit; a first electrode of the twelfth transistor is connected to the second output unit, a gate of the twelfth transistor is connected to the second node, and a second electrode of the twelfth transistor serves as a second output end of the cascade unit; Preferably, the first output end of the cascade unit is connected to the control end of the second pre-charging unit.

5. The shift register according to claim 1, characterized in that: The shift register also includes an interlocking unit, which is respectively connected to the first node, the second node, the third node, the fourth node, the first output unit and the second output unit, and the interlocking unit is configured to initialize the first node and the second node according to the voltage at the third node and the fourth node.

6. The shift register according to claim 5, characterized in that: The interlocking unit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the gate of the thirteenth transistor and the gate of the fifteenth transistor are both connected to the third node, the gate of the fourteenth transistor and the gate of the sixteenth transistor are both connected to the fourth node, the first electrode of the thirteenth transistor is connected to the first node, the first electrode of the fourteenth transistor is connected to the second node, the first electrode of the fifteenth transistor is connected to the second clock terminal, the first electrode of the sixteenth transistor is connected to the first clock terminal, and the second electrode of the thirteenth transistor, the second electrode of the fourteenth transistor, the second electrode of the fifteenth transistor and the second electrode of the sixteenth transistor are all connected to the second voltage terminal.

7. The shift register according to claim 1, characterized in that: The shift register further includes a voltage holding unit, which is respectively connected to the first node, the second node, the first output unit and the second output unit, and is used to hold the voltages at the first node and the second node.

8. The shift register according to claim 7, characterized in that: The voltage holding unit includes a first capacitor, a second capacitor and a seventeenth transistor, wherein a first end of the first capacitor is connected to the first node, a first end of the second capacitor is connected to the second node, and a second end of the first capacitor and a second end of the second capacitor are both connected to a second voltage end. A first electrode of the seventeenth transistor is connected to the output end of the first output unit, a gate of the seventeenth transistor is connected to the second voltage end, and a second electrode of the seventeenth transistor is connected to the output end of the second output unit.

9. A gate drive circuit, characterized in that: A plurality of cascaded shift registers as described in any one of claims 1 to 8, wherein the shift register comprises a first pre-charge unit, a cascade unit and an interlocking unit, wherein except for the first-stage shift register, the cascade unit of each stage of the shift register is connected to the first pre-charge unit of the lower-stage shift register; and except for the last stage of the shift register, the interlocking unit of each stage of the shift register is connected to the first node and the second node of the lower-stage shift register.

10. A display panel, characterized in that: Comprising the gate driving circuit as claimed in claim 9.

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