Storage device, storage system, and operating method thereof

Abstract

A storage device, a storage system, and an operating method thereof are provided. The method for operating the storage device includes storing a first page data in a cache latch, storing the first page data in a first data latch and storing an upper page data in a second data latch, programming a memory cell of a first page of a memory cell array with the first page data, storing the first page data in a second data latch and storing a second page data in the first data latch, and programming a memory cell of a second page with the second page data.

Description

Background Technology

[0001] This disclosure relates to storage devices, storage systems, and methods of operation thereof.

[0002] In non-volatile storage devices, programming data into the storage cell array takes time, and only one page of data can be programmed into the array at a time. Therefore, when writing multiple data pages to the array consecutively, it's necessary to wait for the programming of the current data page to finish before transferring and programming the next data page into the array. Consequently, the process of writing data to the storage cell array is inefficient and cannot provide continuous programming. Summary of the Invention

[0003] In one aspect, a method for operating a storage device includes: storing a first page of data in a cache latch; storing the first page of data in a first data latch and storing a previous page of data in a second data latch; programming a storage cell of a first page of a storage cell array using the first page data; storing the first page of data in the second data latch and storing a second page of data in the first data latch; and programming a storage cell of a second page using the second page data.

[0004] In some implementations, before programming the storage cells of the first page of the storage cell array using the first page data, the method further includes: determining whether the previous page data has been successfully programmed.

[0005] In some implementations, in response to determining that the previous page data has been successfully programmed, the method further includes storing the second page data in the cache latch.

[0006] In some implementations, in response to determining that the previous page data has not been successfully programmed, the method further includes: reading the previous page data from the second data latch.

[0007] In some implementations, in response to determining that the previous page data has not been successfully programmed, the method further includes: reading the first page data from the first data latch.

[0008] In some implementations, in response to determining that the previous page of data has not been successfully programmed, the method further includes: reading one or more pages of data from the storage cells of the storage cell array.

[0009] In some implementations, reading one or more pages of data from the storage cells of the storage cell array is triggered in response to a first read command. Reading the first page of data from the first data latch and the previous page of data from the second data latch is triggered in response to a second read command.

[0010] In some implementations, programming a memory cell of the first page using the first page data includes: applying a programming pulse to a word line corresponding to the memory cell of the first page based on the first page data; and verifying the memory cell of the first page.

[0011] In some implementations, programming a storage unit of the first page using the first page data includes: configuring a disable message for the storage unit applied by the programming pulse; and storing the disable message for the storage unit in a master latch.

[0012] In some implementations, verifying the storage unit of the first page includes storing verification information of the storage unit in a master latch.

[0013] In some implementations, verifying the memory cell of the first page further includes applying a verification voltage to a word line corresponding to the memory cell of the first page.

[0014] In some implementations, verifying the storage unit of the first page further includes storing the verification result in the main latch.

[0015] In some implementations, the method further includes determining whether the first page of data has been successfully programmed.

[0016] In some implementations, in response to determining that the first page data has been successfully programmed, the method further includes: storing the first page data in the second data latch, and storing the second page data in the first data latch.

[0017] In some implementations, in response to determining that the first page data has not been successfully programmed, the method further includes: determining whether the number of reprogramming loops has reached a loop threshold, and in response to determining that the number of reprogramming loops has reached the loop threshold, the method further includes: storing the first page data in a second data latch, and storing the second page data in the first data latch.

[0018] In some implementations, in response to determining that the number of reprogramming cycles has not reached the cycle threshold, the method further includes: applying the programming pulse to the word line corresponding to the memory cell of the first page based on the first page data.

[0019] In some implementations, each storage cell in the storage device is a single-level cell (SLC).

[0020] In another aspect, a storage device includes a storage cell array. The storage cell array includes storage cells; peripheral circuitry coupled to the storage cell array. The peripheral circuitry includes a page buffer coupled to the storage cell array. The page buffer includes a cache latch; a first data latch; a second data latch; and control logic coupled to the storage cell array. The peripheral circuitry is configured to: store a first page of data in the cache latch; store the previous page of data in the second data latch, and store the first page of data in the first data latch; store a second page of data in the cache latch; program the storage cells of a first page of the storage cell array using the first page data; store the first page of data in the second data latch, and store the second page of data in the first data latch; and program the storage cells of a second page of the storage cell array using the second page data.

[0021] In some implementations, after storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuitry is further configured to read the previous page data from the second data latch.

[0022] In some implementations, after storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuitry is further configured to read the first page data from the first data latch.

[0023] In some embodiments, the peripheral circuitry is further configured to read the previous page data from the second data latch after programming the memory cells of the second page of the memory cell array using the second page data.

[0024] In some implementations, the peripheral circuitry is further configured to read the previous page data from the second data latch in response to a programming failure of the memory cells of the first page.

[0025] In some implementations, the page buffer further includes a main latch, and the control logic is further configured to store the previous page data in the main latch.

[0026] In some implementations, the peripheral circuitry is configured to store the previous page data in the main latch after storing the second page data in the cache latch.

[0027] In some implementations, when the storage cells of the first page of the storage cell array are programmed using the first page data, the peripheral circuitry is further configured to disable the storage cells of the first page based on the previous page data in the master latch.

[0028] In some implementations, the page buffer further includes a bias latch. The peripheral circuitry is also configured to verify the memory cells of the first page of the memory cell array.

[0029] In some implementations, the peripheral circuitry is configured to verify that the storage cells of the first page of the storage cell array are programmed after the storage cells of the first page of the storage cell array have been programmed using the data from the first page.

[0030] In some embodiments, the peripheral device configured to program the memory cells of the first page of the memory cell array using the first page data is further configured to instruct a word line driver to apply a first programming voltage to a first word line corresponding to a memory cell of the first page of the memory cell array, based on the first page data.

[0031] In some implementations, each memory cell in the memory cell array is a single-level cell (SLC).

[0032] In another aspect, the storage device includes a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cell array includes storage cells. The peripheral circuitry includes a page buffer coupled to the storage cell array. The peripheral circuitry is configured to: store previous page data and a first page data in the page buffer; program the storage cells of a first page of the storage cell array using the first page data; store the first page data and a second page data in the page buffer; and program the storage cells of a second page of the storage cell array using the second page data.

[0033] In another aspect, a storage system includes a storage device and a memory controller coupled to the storage device. The storage device includes: a memory cell array comprising memory cells; and peripheral circuitry coupled to the memory cell array. The peripheral circuitry includes: a page buffer coupled to the memory cell array. The memory controller is configured to: send a query command to the memory cell array to confirm whether the previous page of data has been successfully programmed; and, in response to the previous page of data not being successfully programmed, send a first read command to read the first page of data and the previous page of data from the page buffer.

[0034] In some implementations, in response to the previous page of data not being successfully programmed, a second read command is sent to read one or more pages of data from the storage cells of the storage cell array.

[0035] In some implementations, after sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data in the first data latch and the previous page of data in the second data latch, the memory controller is further configured to: reallocate the new physical address of the corresponding memory cell of the memory cell array to the previous page of data and the current page of data in the page buffer, and the one or more pages of data in the memory cell array; and program the previous page of data, the current page of data, and the one or more pages of data into the memory cell array using the new physical address.

[0036] In some implementations, after sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data and the previous page of data from the page buffer, the memory controller is further configured to: erase the memory cell corresponding to the current physical address where the current programming operation is performed; and program the previous page of data, the current page of data, and the one or more pages of data into the memory cell array using the current physical address.

[0037] In some implementations, after sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data in the first data latch and the previous page of data in the second data latch, the memory controller is further configured to: reallocate a new physical address of the corresponding memory cell of the memory cell array to the previous page of data in the page buffer; and program the previous page of data into the memory cell array using the new physical address. Attached Figure Description

[0038] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate some aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0039] Figure 1 A schematic circuit diagram of an example storage device including peripheral circuitry according to some embodiments of the present disclosure is shown.

[0040] Figure 2 A block diagram of an example storage device, including a storage cell array and peripheral circuitry, is shown according to some embodiments of the present disclosure.

[0041] Figure 3A A block diagram of an example storage device including a page buffer, according to some embodiments of the present disclosure, is shown.

[0042] Figure 3B A block diagram of an example storage system including a memory controller and a storage device according to some embodiments of the present disclosure is shown.

[0043] Figure 4A A table showing corresponding data included in an example page buffer during operation of an example storage device, according to some embodiments of this disclosure, is illustrated.

[0044] Figure 4B A flowchart illustrating an example storage device for operation according to some embodiments of the present disclosure is shown.

[0045] Figure 4C A flowchart illustrating an example storage system for operation according to some embodiments of this disclosure is shown.

[0046] Figure 4D A flowchart illustrating an example storage system for operation according to some embodiments of this disclosure is shown.

[0047] Figure 4E A flowchart illustrating an example storage system for operation according to some embodiments of this disclosure is shown.

[0048] Figure 5 A flowchart illustrating an example storage device for operation according to some embodiments of the present disclosure is shown.

[0049] Figure 6 A block diagram of an example system with a storage device according to some embodiments of the present disclosure is shown.

[0050] Figure 7A A diagram of an example memory card with a storage device according to some embodiments of the present disclosure is shown.

[0051] Figure 7B A diagram of an example solid-state drive (SSD) with a storage device according to some embodiments of the present disclosure is shown.

[0052] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0053] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified in ways not specifically described in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0054] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "one," or "this" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can, at least partly depending on the context, allow for the presence of additional factors that are not necessarily explicitly described.

[0055] When multiple pages of data are written sequentially to a memory cell array, this page data can be temporarily stored in a page buffer (e.g., a cache latch or data latch within the page buffer) and then transferred and written to the memory cell array. This improves efficiency and provides continuous programming without waiting for the programming of the current data page to finish before starting the next programming process. The method of storing the page data to be written in a cache latch or data latch of the page buffer during the programming of the current page data (i.e., during NAND busy hours, or the so-called page programming time (tPROG)) and then programming this page data to the memory cell array is called cache programming. However, during the programming process, especially in a single-level cell (SLC) architecture, the data stored in the page buffer can only be retrieved after the current programming process is complete. Therefore, it is unknown whether the first page data has been successfully programmed until programming the second page data begins. Furthermore, the first page data stored in the page buffer can be erased and replaced by the next page data cached therein before the programming of the second page data is complete. Therefore, it is impossible to read the first page data stored in the page buffer to determine whether the first page data was successfully programmed. Furthermore, corruption of the page data stored in the page buffer prevents that page data from being used for data recovery if one of the page data was not successfully programmed.

[0056] To address one or more of the aforementioned problems, this disclosure proposes a solution in which the processing and use of latches in a page buffer are provided to retain page data in the page buffer without erasure. Furthermore, this disclosure also proposes a solution for using page data stored in the page buffer for data recovery in response to one of the page data being unsuccessfully programmed.

[0057] Figure 1A schematic circuit diagram of a storage device 100, including peripheral circuitry, according to some aspects of this disclosure is shown. The storage device 100 may include a storage cell array 101 and peripheral circuitry 102 coupled to the storage cell array 101. In some embodiments, the storage cell array 101 may be a NAND flash memory cell array, wherein the storage cells 106 are provided in the form of an array of three-dimensional (3D) NAND memory strings 108, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 108 includes a plurality of storage cells 106 coupled in series and stacked vertically. Each storage cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the storage cell 106. Each storage cell 106 may be a floating-gate type storage cell including a floating-gate transistor or a charge-trapping type storage cell including a charge-trapping transistor. Each array of 3D NAND memory strings 108 may include one or more 3D storage devices.

[0058] In some implementations, each memory cell 106 is a single-level cell (SLC) that can have two possible memory states and therefore can store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one unit of data in four or more memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal memory values ​​to the cell. A fourth nominal memory value can be used for the erase state.

[0059] like Figure 1As shown, each 3D NAND memory string 108 may include a source-select-gate (SSG) transistor 110 at its source end and a drain-select-gate (DSG) transistor 112 at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate the selected 3D NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the SSG transistors 110 of the 3D NAND memory strings 108 in the same block 104 are coupled via the same source line (SL) 114 (e.g., a common SL), for example, to ground. According to some embodiments, the DSG transistor 112 of each 3D NAND memory string 108 is coupled to a corresponding bit line 116 from which data can be read or programmed via an output bus (not shown). In some implementations, each 3D NAND memory string 108 is configured to be selected or deselected by applying a selection signal (e.g., a selection voltage higher than the threshold voltage of the DSG transistor 112) or a deselection voltage (e.g., a deselection voltage such as 0V) to the corresponding DSG transistor 112 via one or more DSG lines 113, and / or applying a selection voltage (e.g., a selection voltage higher than the threshold voltage of the SSG transistor 110) or a deselection voltage (e.g., 0V) to the corresponding SSG transistor 110 via one or more SSG lines 115.

[0060] like Figure 1 As shown, the 3D NAND memory string 108 can be organized into multiple blocks 104, each block potentially having a common source line 114. In some embodiments, each block 104 is the basic data unit for erase operations, meaning all memory cells 106 on the same block 104 are erased simultaneously. Memory cells 106 can be coupled via word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to a row of memory cells 106, which is the basic data unit for program and read operations. Each word line 118 can be coupled to multiple control gates (gate electrodes) at each memory cell 106 in the corresponding row and gate lines coupling the control gates.

[0061] Peripheral circuitry 102 can be coupled to memory cell array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. As described above, peripheral circuitry 102 can include any suitable circuitry for facilitating operation of memory cell array 101 by applying sensed voltage and / or current signals to each target memory cell 106 via bit line 106 and by sensing voltage and / or current signals from each target memory cell 106 via word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology. For example, Figure 2 Example peripheral circuitry 102 is shown, which includes a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, a register 214, an interface (I / F) 216, and a data bus 218. It should be understood that additional peripheral circuitry 102 may also be included in some examples.

[0062] Page buffer 204 can be configured to buffer data read from memory cell array 101 or programmed into memory cell array 702 according to control signals of control logic 212. In one example, page buffer 204 can store one or more pages of programming data (write data) to be programmed into one or more rows of memory cell array 101. In another example, page buffer 204 also performs a programming verification operation to ensure that data has been correctly programmed into memory cells 106 coupled to selected word lines 118.

[0063] The row decoder / word line driver 208 can be configured to be controlled by control logic 212 to select or deselect block 104 of memory cell array 101 and select or deselect word line 118 of the selected block 104. The row decoder / word line driver 208 can be further configured to drive memory cell array 101. For example, the row decoder / word line driver 208 can use a word line voltage generated from voltage generator 210 to drive memory cell 106 coupled to the selected word line 118. In some embodiments, the row decoder / word line driver 208 may include a decoder and a string driver (driving transistor) coupled to the local word line and word line 118.

[0064] Voltage generator 210 can be configured to be controlled by control logic 212 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.) to provide to memory cell array 101. In some embodiments, voltage generator 210 is part of a voltage source that provides voltages at various levels of different peripheral circuits 102, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages provided by voltage generator 210 to, for example, row decoder / word line driver 208 and page buffer 204 are higher than certain levels sufficient to perform memory operations. For example, the voltage provided to page buffer 204 may be between 2V and 3.3V, such as 3.3V, and the voltage provided to row decoder / word line driver 208 may be greater than 3.3V, such as between 3.3V and 30V.

[0065] The column decoder / bit line driver 206 can be configured to be controlled by control logic 212 to select one or more 3D NAND memory strings 108 by applying a bit line voltage generated from voltage generator 210. For example, the column decoder / bit line driver 206 can apply a column signal to select a set of N bits of data from page buffer 204 to be output in a read operation.

[0066] Control logic 212 can be coupled to each peripheral circuit and configured to control the operation of peripheral circuit 102. Register 214 can be coupled to control logic 212 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 102.

[0067] Interface 216 may be coupled to control logic 212 and configured to interface memory cell array 101 with a memory controller (not shown). In some embodiments, interface 216 serves as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) by control logic 212, as well as status information received from the control logic 212 by the memory controller and / or host. Interface 216 is also coupled via data bus 218 to page buffer 204 and column decoder / bit line driver 206, and serves as an input / output (I / O) interface and data buffer to buffer and relay programming data received from the memory controller and / or host from page buffer 204 and read data received from the memory controller and / or host from page buffer 204. In some embodiments, interface 216 and data bus 218 are part of the I / O circuitry of peripheral circuitry 102.

[0068] Figure 3AAn example storage device 100 is shown, which includes one or more page buffers 204, a memory cell array 101, control logic 212 coupled to the page buffers 204 and the memory cell array 101, a register 214 coupled to the control logic 212, and an interface (I / F) 216. It should be understood that additional components may also be included in some examples. The page buffer 204 may include one or more latches. In some embodiments, the page buffer 204 may include a cache latch (DC) 3331, (N-1) data latches (D1 to DN-1) (e.g., a first data latch (D1) 3333 and a second data latch (D2) 3335), a bias latch (DL) 3337, and a main latch (DS) 3339, where N is an integer greater than 1. It should be noted that the names of the latches are for illustrative purposes based on their use and / or the data stored in the page buffer, and are not limited to specific latches in the page buffer. Some or all of these latches can be replaced by other latches in the page buffer.

[0069] The latches of page buffer 204 (e.g., DC 3331, D1 3333, D2 3335, DL 3337, or DS 3339) can store one or more pages of programming data (write data) to be programmed into one or more rows of memory cell array 101. These latches in the page buffer can also store associated data for performing a programming verification operation to ensure that the data has been correctly programmed into the memory cell 106 coupled to the selected word line 118. These latches in the page buffer can also store associated data for performing a data recovery operation to retrieve the data if it has not been successfully programmed.

[0070] Figure 3B An example storage system 350 including a memory controller 300 and a storage device 100 according to some embodiments of the present disclosure is shown. The memory controller 300 includes a microprocessor 351, a controller register 353 coupled to the microprocessor 351, and a controller interface (I / F) 355 coupled between the microprocessor 351 and a host 357.

[0071] The memory controller 300 can manage data stored in the storage device 100 and communicate with the host 357. The memory controller 300 can be configured to control operations of the storage device 100, such as read, erase, program, data recovery operations, or other operations according to some embodiments of this disclosure. The memory controller 300 can be configured to control operations by sending commands (e.g., read commands) or commands with data addresses. In some embodiments, the memory controller 300 may also include a controller memory (e.g., cache memory or non-volatile memory) storing tables, verification information, failure bit count information, or other information as described in embodiments of this disclosure. The memory controller 300 can also be configured to manage various functions relating to data stored or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 300 is also configured to process error correction codes (ECC) for data read from or written to the storage device 100. The memory controller 300 can also perform any other suitable functions, such as formatting the storage device 100. For example, the memory controller 300 may communicate with an external device (e.g., a host 357) according to a specific communication protocol. The host 357 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 357 may be configured to send data to or receive data from the storage device 100 via the memory controller 300.

[0072] Figure 4A A table showing corresponding data in an example page buffer during operation of an example storage device is illustrated according to some embodiments of this disclosure.

[0073] First, during the program preamble phase (e.g., program preparation), the first programming operation begins, and the first user data is received from the host 357 via the memory controller 300 to the control logic 212 and is converted into the first page data (e.g., current programming data) into the page buffer 204. The cache latches (e.g., DC 3331) of the page buffer 204 are configured to store the current programming data (write data, or data to be programmed, also referred to herein as "page data") for this phase. It is worth noting that in the SLC architecture, only one bit of data is stored. Therefore, only one page of data is needed. Thus, each latch can store at least one page of data, and during the programming phase, the latch can directly transfer that page of data from the latch to the current page to be programmed. During this phase, the status bit of the DC for the cell in the programming state is 0, and the status bit of the DC for the cell in the erase state is 1.

[0074] Next, during the previous programming data backup phase, the previous programming data stored in the first data latch (e.g., D1 3333) of page buffer 204 during the previous programming operation is transferred to the second data latch (e.g., D2 3335) of page buffer 204. During this phase, the status bit of D2 for cells in the programming state is 0, and the status bit of D2 for cells in the erase state is 1.

[0075] Next, after the previous programming data in D1 is transferred and stored in D2, the previous programming data in D1 can be erased and overwritten by the current programming data. Thus, during the (current) data transfer phase, the current programming data stored in DC is transferred to D1. During this phase, the status bit of D1 for cells in the programming state is 0, and the status bit of D1 for cells in the erase state is 1.

[0076] Next, after the current programming data in DC is transferred and stored in D1, the current programming data in DC can be erased and overwritten by the next programming data. For example, the next user data can be received and converted into the next program data to be stored in the page buffer. Specifically, during the next page data cache entry stage, the next programming data is transferred and stored in DC. During this stage, the status bit of DC for cells in the programming state is 0, and the status bit of DC for cells in the erase state is 1.

[0077] Next, during the first programming disable process, disable information for the memory cell to which the programming pulse is applied is configured based on the current page data. The main latch (e.g., DS 3339) of the page buffer 204 is configured to store disable information (e.g., programming pulse data in D1). The disable information may correspond to a cell in the erase state at a target level. At this stage, the status bit of DS for cells in the programming state is 0, while the status bit of DC for cells in the erase state is 1. The disable information can then be used to disable programming of the memory cell using the current programming data stored in D1.

[0078] Next, after the programming statement stage, the first programming pulse stage begins. During the first programming pulse stage, the current programming data stored in the DC is transferred and programmed into the memory cell array (e.g., memory cell array 101).

[0079] Next, after the current page of the memory cell array is programmed, the first programming verification begins. During the first programming verification, a verification preset process can be executed, and verification preset information can be stored in the DS. For example, inverted data in the DS (i.e., inverted data of the program data stored in D1) is transferred and stored in the DS. The inverted data in the DS can be used to set the cell to be verified (i.e., the cell being programmed in the current page). At this stage, the DS status bit is 0 for cells in the erase state and for cells in the pass state, while the DS status bit is 1 for cells in the verification state.

[0080] Next, during the verification sensing phase of the first programming verification, verification information can be stored in the DS. For example, inverted data in the DS (i.e., inverted data of the verification preset stored in the DS) and inverted sensed (SO) node data are transferred and stored in the DS. Note that the SO node is the node that senses cell current / voltage during the read operation. It is also the sensed node during data transfer between latches. The voltage level of the SO node changes according to the programming state of the cell being programmed in the current page. For example, if the voltage level of the SO node remains logic high, the cell in the current page is programmed, and if the voltage level of the SO node remains logic low, the cell in the current page is not programmed. At this stage, the status bit of the DS is 0 for cells in the erase state and for cells in the pass state, while the status bit of the DS is 1 for cells in the failure state.

[0081] Next, during the Verification Failure Bit Count (VFC) setting phase following verification sensing in the first programming verification, the VFC may be stored in other parts of the page buffer or in the memory of the memory controller. During this phase, the bias latch of page buffer 204 (e.g., DL 3337) is configured to store verification failure information (e.g., verification result) stored in the DS. The data stored in the DL indicates whether one of the memory cells has been verified. During this phase, the status bit of the DL for cells in the erase state and for cells in the pass state is 0, while the status bit of the DS for cells in the erase state is 1.

[0082] Next, during the verification recovery phase of the first programming verification, the inverted data in the DS (i.e., the inverted data of the verification sense stored in the DS) is transmitted and stored in the DS. During this phase, the state bit of the DS for the cell in the programming state is 0, while the state bit of the DS for the cell in the erase state and the cell in the pass state is 1.

[0083] Figure 4BA flowchart illustrating an example storage device for operation according to some embodiments of this disclosure is shown. It should be noted that the latches described herein are for illustrative purposes. All or part of these latches may be replaced by or exchanged with other latches.

[0084] First, at operation 402, while the previous program is transferred and stored in the second data latch (e.g., D1 3335) of page buffer 204, the previous page data is stored in the first data latch (e.g., D2 3333) of page buffer 204.

[0085] Next, at operation 404, after retrieving the previous page data, the current page's user data is sent from the memory controller (e.g., memory controller 300) to the page buffer 204 and converted into current page data. The current page data initially stored in the cache latch (e.g., DC 3331) is transferred and stored in the first data latch (e.g., D13333).

[0086] Next, at operation 406, the memory controller (e.g., memory controller 300) can send a command to the storage device (e.g., storage device 100) and determine whether the previous page of data was successfully programmed (passed) or unsuccessfully programmed (failed). If it is determined that the previous page of data was unsuccessfully programmed (failed), the memory controller does not send the next page of data to the storage device, and the storage device continues to write the current page of data instead of the next page of data. Thus, a data recovery operation can be performed alternatively (e.g., operation 408). The data recovery operation will be discussed later. Conversely, if it is determined that the previous page of data was successfully programmed (passed), then at operation 410, the next page of data is sent from the memory controller to the cache latch DC.

[0087] Next, at operation 412, the disable information of the memory cell applied by the configuration programming pulse is determined according to the current page data. As described above, the disable information of the memory cell of the current page (e.g., the first page) is stored in the main latch (e.g., DS3339). Specifically, the disable information stored in DS corresponds to the cell in the erase state of the target level.

[0088] Next, at operation 414, a programming pulse is applied to the word line corresponding to the memory cell of the current page (e.g., the first page) to program the memory cell of the current page.

[0089] Next, at operation 416, after pulse programming, verification information is configured based on the current page data. Verification information for the memory cell to be verified is stored in DS. Specifically, since the current data stored in DS corresponds to a memory cell in an erased state, and the memory cell to be verified is at the opposite first programming level (P1) to the erased state, the data stored in DS can be inverted to represent the verification information for the memory cell to be verified.

[0090] Next, at operation 418, a verification voltage is applied to the word line corresponding to the memory cell of the current page (e.g., the first page), and the verification result is stored in DS. The verification result indicates whether the memory cell in the current page passed or failed. Verification failure information can be the inverse of verification information. Thus, the verification result (e.g., verification failure information) can be the inverse of the verification information.

[0091] Next, at operation 420, the verification failure information is transmitted from the DS to the bias latch (e.g., DL 3337). In some implementations, a Verification Failure Bit Count (VFC) can be used to count the number of memory cells that failed to be written to or had errors during the VFC setup phase following verification sensing in the first programming verification. The failure bit count can be stored in other parts of the storage device (e.g., other latches in the page buffer) or in the memory controller (e.g., memory within the memory controller, such as cache memory or non-volatile memory) to determine whether the current page data was successfully programmed (pass / fail). For example, if the failure bit count reaches a counting threshold, it can be determined that the current page data was not successfully programmed (failed). It should be noted that in some implementations, the memory controller may not actively be informed of the result (pass / fail) of whether the current page data was successfully programmed. The memory controller requires a command to retrieve the result in order to begin the data recovery process. In another example, if the failure bit count does not reach the counting threshold, it can be determined that the current page data was successfully programmed (pass). If the current page data is successfully programmed, operation 402 of the second programming process can begin, and the entire cache programming process can be executed to program the next page data. If the current page data is not successfully programmed, it means that the memory cell of the current page (e.g., the first page) should be reprogrammed using the same current page data. Thus, at operation 422, it is determined whether the number of reprogramming loops has reached a threshold. That is, to prevent the memory cell from becoming unreprogrammable (e.g., all memory cells are damaged), once the number of reprogramming loops reaches the threshold, such as 10 to 1000 times, the reprogramming process can be stopped and the next programming process can begin (i.e., operation 402, which begins the second programming process). And when it is determined that the current page data has not been successfully programmed and the number of reprogramming loops has not reached the threshold, operation 412 is executed to configure a prohibition information, and then another pulse programming operation 414 is executed to program the memory cell again using the current page data.

[0092] Figures 4C to 4E A flowchart of performing a data recovery operation 408 according to various embodiments of the present disclosure is shown.

[0093] In the first type of data recovery operation 408-1, such as Figure 4CAs shown, the operation begins at operation 451, where a first read command is sent from the memory controller to the storage device to read the previous page of data from the page buffer (e.g., in D2). It should be noted that in some embodiments, before sending the first read command, the memory controller may check whether the storage device is in an idle state (i.e., the storage device enters an idle state once the pulse programming process of the current page data is complete). If it is determined that the storage device is in an idle state, operation 451 begins and the first read command is sent. And, if it is determined that the storage device is not in an idle state, the memory controller may wait for the pulse programming of the current page data to complete and begin operation 451 until the storage device becomes idle. Next, the operation proceeds to operation 453, where a second read command is sent from the memory controller to the storage device to read one or more pages of data from the memory cell array. Next, the operation proceeds to operation 455, in which new physical addresses corresponding to the previous page data and the current page data (which are temporarily stored in the latches of the page buffer) and one or more pages of data in the memory cell array are reallocated. Next, after reallocating new physical addresses in the storage cell array for these page data, the operation proceeds to operation 457, in which the page data is written to the storage cell array with the new physical addresses. That is, the previous page data, the current page data, and the original page data are all restored to the new physical addresses in the storage cell array, and the data recovery process is complete. In this way, even if the previous page data is not successfully programmed, the data recovery process will restore the previous page data, the current page data, and the original page data. The programming of the previous page data and the current page data can be repeated (e.g., proceeding to operation 412) without continuing to program the next page data (e.g., skipping operation 410).

[0094] In the second type of data recovery operation 408-3, such as Figure 4DAs shown, the operation begins at operation 451, where a first read command is sent from the memory controller to the storage device to read the previous page of data (e.g., in D2) from the page buffer. Next, the operation proceeds to operation 453, where a second read command is sent from the memory controller to the storage device to read one or more pages of data from the memory cell array. Next, the operation proceeds to operation 461, where a new physical address corresponding to the previous page of data (which is temporarily stored in the latch of the page buffer) is reallocated in the memory cell array. Following the reallocation of the new physical address in the memory cell array for the previous page of data, the operation proceeds to operation 463, where the previous page of data is written to the memory cell array using the new physical address. That is, only the previous page of data is restored to the new physical address in the memory cell array, and the data recovery process is complete. Thus, even if the previous page of data was not successfully programmed, the data recovery process will restore the previous page of data and store it in the new physical address. You can repeat the programming of the previous page of data (e.g., proceed to operation 412) without continuing to program the next page of data (e.g., skip operation 410).

[0095] In the third type of data recovery operation 408-5, such as Figure 4E As shown, the operation begins at operation 451, where a first read command is sent from the memory controller to the storage device to read the previous page of data from the page buffer (e.g., in D2). Next, the operation proceeds to operation 453, where a second read command is sent from the memory controller to the storage device to read one or more pages of data from the memory cell array. Next, the operation proceeds to operation 471, where the memory cell corresponding to the current physical address where the current write operation is performed is erased. Next, the operation proceeds to operation 473, where the previous page data, the current page data, and one or more pages of data from the memory cell array are written to the memory cell array using the current physical address corresponding to the current write operation. That is, the previous page data, the current page data, and the original page data are all restored to the physical address being erased, and the data recovery process is complete. Since the current physical address of the current page is erased, and the previous page data, the current page data, and one or more pages of data from the memory cell array are written to the current physical address being erased, a new address is not required.

[0096] Figure 5 A flowchart illustrating an example storage device for operation according to some embodiments of the present disclosure is shown. (Refer to...) Figure 5Method 500 begins at operation 502, where a first page of data is stored in a cache latch to begin a first programming operation. Next, method 500 proceeds to operation 504, where the first page of data is stored in a first data latch and the previous page of data is stored in a second data latch. Since the first page of data in the cache latch has been transferred, method 500 proceeds to operation 506, where, in response to determining that the previous page of data has been successfully programmed, the second page of data is stored in a cache latch. Next, method 500 proceeds to operation 508, where the memory cells of the first page are programmed using the first page of data stored in the first data latch. The programming operation (e.g., pulse programming) can be any pulse programming operation in embodiments of this disclosure. Next, method 500 proceeds to operation 510, where the memory cells of the first page are verified according to any verification operation in embodiments of this disclosure. Next, method 500 proceeds to operation 512, where it is determined whether the first page of data has been successfully programmed. Furthermore, method 500 proceeds to operation 514, wherein, in response to the successful programming of the first page data, the first page data is stored in a second data latch, and the second page data is stored in the first data latch to initiate a second programming operation. Specific details of these operations can be found in embodiments of this disclosure, such as... Figures 4A-4E The implementation method.

[0097] Figure 6 A block diagram of a system 600 having a storage device according to some aspects of this disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host 608 and a storage system 602 having one or more storage devices 604 and a memory controller 606. The host 608 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 608 may be configured to send data to or receive data from storage device 604.

[0098] Storage device 604 can be any storage device disclosed herein, such as storage device 100. In some implementations, each storage device 604 includes a storage device as described in detail above.

[0099] According to some embodiments, memory controller 606 is coupled to storage device 604 and host 608 and is configured to control storage device 604. Memory controller 606 can be any memory controller disclosed herein, such as memory controller 300. In some embodiments, each memory controller 606 includes a memory controller as described in detail above. Memory controller 606 can manage data stored in storage device 604 and communicate with host 608. In some embodiments, memory controller 606 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 606 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage cell arrays. Memory controller 606 can be configured to control the operation of storage device 604, such as read, erase, and program operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the storage device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 606 is also configured to handle error correction codes (ECC) for data read from or written to the storage device 604. Any other suitable functions may also be performed by the memory controller 606, such as formatting the storage device 604. The memory controller 606 can communicate with external devices (e.g., host 608) according to specific communication protocols. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0100] The memory controller 606 and one or more storage devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 602 can be implemented and packaged into different types of end electronic products. Figure 7AIn one example shown, the memory controller 606 and a single storage device 604 can be integrated into a memory card 702. The memory card 702 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 may also include a connection between the memory card 702 and a host computer (e.g., Figure 6 The memory card connector 704 is coupled to the host 608. Figure 7B In another example shown, the memory controller 606 and multiple storage devices 604 can be integrated into the SSD 706. The SSD 706 may also include a connection between the SSD 706 and a host (e.g., Figure 6 The SSD connector 708 is coupled to the host 608 in the memory card 702. In some implementations, the SSD 706 has a larger storage capacity and / or operating speed than the memory card 702.

[0101] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance provided herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0102] The breadth and scope of this disclosure should not be limited by any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A method for operating a storage device, comprising: Store the first page of data in the cache latch; After programming the storage cell of the previous page of the storage cell array using the data from the previous page, the data from the previous page is stored in the second data latch, and the data from the first page is stored in the first data latch. The storage cells of the first page of the storage cell array are programmed using the data from the first page. The first page of data is stored in the second data latch, and the second page of data is stored in the first data latch; as well as Program the storage units of the second page using the data from the second page.

2. The method according to claim 1, wherein, Before programming the storage cells of the first page of the storage cell array using the data from the first page, the method further includes: Determine whether the data on the previous page has been successfully programmed.

3. The method according to claim 2, wherein, In response to determining that the previous page data has been successfully programmed, the method further includes: The second page of data is stored in the cache latch.

4. The method according to claim 2, wherein, In response to determining that the previous page data was not successfully programmed, the method further includes: Read the previous page data from the second data latch.

5. The method according to claim 4, wherein, In response to determining that the previous page data was not successfully programmed, the method further includes: Read the first page of data from the first data latch.

6. The method according to claim 5, wherein, In response to determining that the previous page data was not successfully programmed, the method further includes: Read one or more pages of data from the storage cells of the storage cell array.

7. The method according to claim 6, wherein, Reading one or more pages of data from the storage cells of the storage cell array is triggered in response to a first read command, and reading the first page of data from the first data latch and the previous page of data from the second data latch is triggered in response to a second read command.

8. The method according to claim 1, wherein, Programming the storage units of the first page using the data from the first page includes: Programming pulses are applied to the word lines corresponding to the memory cells of the first page based on the data from the first page; and Verify the storage unit on the first page.

9. The method according to claim 8, wherein, Programming the storage units of the first page using the data from the first page includes: Configure the prohibition information applied to the memory cell by the programming pulse; and The prohibition information of the storage unit is stored in the main latch.

10. The method according to claim 8, wherein, Verifying the storage unit of the first page includes storing the verification information of the storage unit in the main latch.

11. The method according to claim 9, wherein, Verifying the memory cell of the first page further includes applying a verification voltage to the word line corresponding to the memory cell of the first page.

12. The method according to claim 11, wherein, Verifying the storage unit of the first page further includes: The verification result is stored in the master latch.

13. The method according to claim 1, further comprising: Determine whether the data on the first page has been successfully programmed.

14. The method according to claim 13, wherein, In response to determining that the first page of data has been successfully programmed, the method further includes: The first page data is stored in the second data latch, and the second page data is stored in the first data latch.

15. The method according to claim 13, wherein, In response to determining that the first page of data has not been successfully programmed, the method further includes: Determine if the number of loop iterations in the reprogramming has reached the loop threshold, and In response to determining that the number of reprogramming loops has reached the loop threshold, the method further includes: The first page data is stored in the second data latch, and the second page data is stored in the first data latch.

16. The method according to claim 15, wherein, In response to determining that the number of loops for the reprogramming has not reached the loop threshold, the method further includes: Programming pulses are applied to the word lines corresponding to the memory cells of the first page based on the data from the first page.

17. The method according to claim 1, wherein, Each storage cell in the storage device is a single-level cell (SLC).

18. A storage device, comprising: A storage cell array, comprising storage cells; Peripheral circuitry, coupled to the memory cell array, the peripheral circuitry including: A page buffer, coupled to the memory cell array, wherein the page buffer includes: Cache latches; First data latch; and Second data latch; and The control logic is coupled to the memory cell array. The peripheral circuit is configured as follows: The first page of data is stored in the cache latch; The data of the previous page is stored in the second data latch, and the data of the first page is stored in the first data latch; The second page of data is stored in the cache latch; The storage cells of the first page of the storage cell array are programmed using the data from the first page; The first page of data is stored in the second data latch, and the second page of data is stored in the first data latch; and The storage cells of the second page of the storage cell array are programmed using the data from the second page.

19. The storage device according to claim 18, wherein, After storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuitry is further configured to: Before storing the first page data in the second data latch, the previous page data in the second data latch is read out.

20. The storage device according to claim 19, wherein, After storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuitry is further configured to: Before storing the second page data in the first data latch, read the first page data from the first data latch.

21. The storage device according to claim 19, wherein, The peripheral circuit is configured to read the first page data from the second data latch after programming the storage cells of the second page of the storage cell array using the second page data.

22. The storage device according to claim 19, wherein, The peripheral circuitry is configured to read page data from the second data latch in response to a programming failure of the memory cell of the first page.

23. The storage device according to claim 18, wherein, The page buffer also includes a main latch, and the control logic is further configured to store the previous page data in the main latch.

24. The storage device according to claim 23, wherein, The peripheral circuitry is configured to store the second page of data in the cache latch and then store the previous page of data in the main latch.

25. The storage device according to claim 23, wherein, When the storage cells of the first page of the storage cell array are programmed using the data from the first page, the peripheral circuitry is further configured to disable the storage cells of the first page based on the data from the previous page in the master latch.

26. The storage device according to claim 23, wherein, The page buffer further includes a bias latch, wherein the peripheral circuitry is further configured to: Verify the storage cells of the first page of the storage cell array.

27. The storage device according to claim 26, wherein, The peripheral circuitry is configured to verify that the storage cell of the first page of the storage cell array is after the storage cell of the first page of the storage cell array has been programmed using the data of the first page.

28. The storage device according to claim 18, wherein, The peripheral circuitry configured to program the memory cells of the first page of the memory cell array using the first page data is further configured to instruct a word line driver to apply a first programming voltage to the first word line corresponding to the memory cell of the first page of the memory cell array, based on the first page data.

29. The storage device according to claim 18, wherein, Each storage cell in the storage cell array is a single-level cell (SLC).

30. A storage device, comprising: A storage cell array, comprising storage cells; as well as Peripheral circuitry, coupled to the memory cell array, the peripheral circuitry including: Page buffers are coupled to the memory cell array. The peripheral circuit is configured as follows: Store the data from the previous page and the data from the first page in the page buffer; The storage cells of the first page of the storage cell array are programmed using the data from the first page; The first page of data and the second page of data are stored in the page buffer; and The storage cells of the second page of the storage cell array are programmed using the data from the second page.

31. A storage system, comprising: Storage device; as well as A memory controller, coupled to the memory device, wherein the memory device includes: A storage cell array, comprising storage cells; and Peripheral circuitry, coupled to the memory cell array, includes: Page buffers are coupled to the memory cell array; The memory controller is configured as follows: Send a query command to the storage array to confirm whether the previous page of data has been successfully programmed; and In response to the failure of the previous page data to be successfully programmed, a first read command is sent to read the first page data and the previous page data from the page buffer.

32. The storage system according to claim 31, wherein, The memory controller is configured to send a second read command to read one or more pages of data from the memory cells of the memory cell array in response to the previous page of data not being successfully programmed.

33. The storage system according to claim 31, wherein, After sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data from the first data latch and the previous page of data from the second data latch, the memory controller is further configured to: The new physical address of the corresponding storage cell of the storage cell array is reassigned to the previous page data and the first page data of the page buffer, as well as one or more pages of data of the storage cell array; as well as The new physical address is used to program the previous page data, the first page data, and one or more pages of data into the storage cell array.

34. The storage system according to claim 31, wherein, After sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data and the previous page of data from the page buffer, the memory controller is further configured to: Erase the memory location corresponding to the current physical address where the current programming operation is performed; and The previous page data, the first page data, and one or more pages of data are programmed into the storage cell array using the current physical address.

35. The storage system according to claim 31, wherein, After sending a first read command to read one or more pages of data from the memory cells of the memory cell array, and sending a second read command to read the first page of data from the first data latch and the previous page of data from the second data latch, wherein the memory controller is further configured to: The new physical address of the corresponding storage cell in the storage cell array is reassigned to the previous page data in the page buffer; and The data from the previous page is programmed into the storage cell array using the new physical address.

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