Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a plurality of groups of data signal lines, and each group of data signal lines comprises a first data signal line and a second data signal line; the plurality of sub-pixels are arranged in the second direction to form a plurality of sub-pixel columns; the first data signal lines and the second data signal lines in the same group are electrically connected with different sub-pixels in the same sub-pixel column respectively; a plurality of first power lines located in the display area and configured to transmit low-voltage signals; the display substrate comprises a first connecting line and a multiplexing circuit, the first connecting line comprises a plurality of wires located on different conductive layers, the multiplexing circuit is located in the first frame area, a part of the first connecting line is located between the multiplexing circuit and the display area, a part of the first connecting line is located on one side of the multiplexing circuit in the first direction, and the first direction is perpendicular to the first direction. And the orthographic projections of the first connecting lines and the multiplexing circuits on the substrate are not overlapped, so that the display quality can be improved.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as the light-emitting element and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, the electrical signals in the display substrate have the problems of high current density and excessive attenuation. Summary of the invention

[0004] The embodiments of the present disclosure provide a display substrate and a display device, which can improve the uniformity of voltage distribution and the display quality of the display device.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a plurality of frame areas;

[0007] A plurality of groups of data signal lines are located in the display area, and the plurality of groups of data signal lines are arranged at intervals along a first direction and extend along a second direction, and each group of data signal lines includes a first data signal line and a second data signal line; the first direction intersects with the second direction and the plane formed is parallel to the plane where the substrate is located;

[0008] A plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are arranged along the second direction to form a plurality of sub-pixel columns; the first data signal line and the second data signal line in the same group are electrically connected to different sub-pixels in the same sub-pixel column respectively;

[0009] a plurality of first power lines, located in the display area and configured to transmit low voltage signals;

[0010] The plurality of frame regions include a first frame region and a second frame region that are arranged opposite to each other along the second direction, and a third frame region and a fourth frame region that are arranged opposite to each other along the first direction; the display substrate further includes at least one first connecting line, the first connecting line includes a first end and a second end that are arranged opposite to each other, the first end is connected to the first power line, and the second end is located in the first frame region, and the first connecting line includes a plurality of traces located in different conductive layers;

[0011] The display substrate also includes a multiplexing circuit, which is located in the first frame area, a portion of the first connecting line is located between the multiplexing circuit and the display area, a portion of the first connecting line is located on one side of the multiplexing circuit along the first direction, and the first connecting line and the multiplexing circuit do not overlap in their orthographic projection on the plane where the substrate is located.

[0012] In some exemplary embodiments, at least part of the plurality of first power lines are arranged in pairs with at least part of the plurality of groups of data signal lines, and the first power line is located between the first data signal line and the second data signal line arranged in pairs therewith, and the first power line and the data signal lines arranged in pairs are located in different conductive layers.

[0013] In some exemplary embodiments, the plurality of routing lines include a first routing line, a second routing line, and a third routing line connected in sequence, and the third routing line is farther away from the display area than the first routing line, and the first routing line and the third routing line both extend along the second direction, and the second routing line extends along the first direction; a first end of the first connecting line is located on the first routing line, and a second end of the first connecting line is located on the third routing line; at least a portion of the second routing line is located between the multiplexing circuit and the display area, and at least a portion of the third routing line is located on one side of the multiplexing circuit along the first direction;

[0014] The display substrate further comprises a second power bus located in the first frame region, the second power bus extending along the first direction, and the second power bus configured to transmit a high voltage signal to a plurality of sub-pixels;

[0015] The orthographic projections of the first routing line and the second power bus on the plane where the substrate is located at least partially overlap, and the first routing line and the second power bus are located in different conductive layers; the orthographic projections of the second routing line and at least one data signal line on the plane where the substrate is located at least partially overlap, and the second routing line and the data signal line are located in different conductive layers.

[0016] In some exemplary embodiments, the peripheral area further includes at least one transition area, and at least one group of two adjacent frame areas are connected via one transition area; at least a portion of a boundary of the transition area close to one side of the display area is an arc-shaped boundary;

[0017] The display substrate further includes at least one connecting line, at least a portion of which is located in the transition region, the connecting line includes a first end and a second end which are arranged opposite to each other, the first end is connected to the first power line, and the second end is located in the transition region.

[0018] In some exemplary embodiments, the at least one transition region includes a first transition region, and the first transition region is located between the first border region and the third border region;

[0019] The connecting wires include a second connecting wire, and at least a portion of the second connecting wire is located in the first transition area; the second connecting wires include a fourth routing wire, a fifth routing wire, and a sixth routing wire connected in sequence, and the fourth routing wire is closer to the display area than the sixth routing wire; the first end of the second connecting wire is located on the fourth routing wire, and the second end of the second connecting wire is located on the sixth routing wire;

[0020] The display substrate further includes a second power transmission line extending along the first direction, at least a portion of the second power transmission line is located in the transition region, and the second power transmission line is configured to be connected to a second power bus and transmit a high voltage signal to a plurality of sub-pixels;

[0021] The fourth routing line at least partially overlaps with the orthographic projection of the second power transmission line on the plane where the substrate is located, and the fourth routing line and the second power transmission line are located in different conductive layers; the fifth routing line at least partially overlaps with the orthographic projection of at least one data signal line on the plane where the substrate is located, and the fifth routing line and the data signal line are located in different conductive layers.

[0022] In some exemplary embodiments, the fifth routing lines of the plurality of second connecting lines are an integrated structure connected to each other, and / or the sixth routing lines of the plurality of second connecting lines are shared.

[0023] In some exemplary embodiments, the at least one transition region includes a first transition region, and the first transition region is located between the first border region and the third border region;

[0024] The at least one connecting line includes a second connecting line, and at least a portion of the second connecting line is located in the first transition area; the display substrate also includes at least one auxiliary power line, at least a portion of the auxiliary power line is located in the first transition area, the auxiliary power line includes a first end and a second end arranged opposite to each other, the first end is connected to the second connecting line, and the second end is located in the third frame area.

[0025] In some exemplary embodiments, the display substrate also includes a plurality of horizontal lines, a plurality of vertical lines and a first power bus located in the second border area, and the horizontal lines extend along the first direction, and the vertical lines extend along the second direction, the vertical lines are connected to the first power bus, and the horizontal lines and the vertical lines are interconnected to form a mesh; the horizontal lines and the vertical lines are located on the same conductive layer, the first power bus is located on another conductive layer, and the first power bus is configured to transmit low-voltage signals.

[0026] In some exemplary embodiments, the display area includes a first area and a second area that do not overlap each other, the first area surrounds at least one side of the second area, and the plurality of first power lines are located in the first area;

[0027] The display substrate also includes a first power transmission line located in the first area, and the first power transmission line surrounds at least a portion of the second area, and the first power transmission line is connected to the plurality of first power lines; in the plane where the substrate is located, at least a portion of the first power transmission line is stepped.

[0028] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate described in any one of the aforementioned embodiments.

[0029] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0031] Figure 1 is a structural schematic diagram of a display device;

[0032] Figure 2 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0033] Figure 3A is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure;

[0034] Figure 3B is a partial cross-sectional schematic diagram of a display area of ​​a display substrate according to an embodiment of the present disclosure;

[0035] Figure 4 A schematic diagram of a partial structure of a first frame region of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 5A This is a schematic diagram of a partial structure of a first transition region of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 5B It is a schematic diagram of a partial structure of a first transition region of a display substrate according to another embodiment of the present disclosure;

[0038] Figure 6 It is a schematic diagram of a partial structure of a first transition region of a display substrate according to another embodiment of the present disclosure;

[0039] Figure 7 A schematic diagram of a partial structure of a second frame region of a display substrate according to an embodiment of the present disclosure;

[0040] Figure 8 FIG. 4 is a schematic diagram of a planar structure of a display substrate according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0042] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0043] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in the present disclosure includes a number of more than two.

[0044] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0045] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0046] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0047] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0048] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0049] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0050] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0051] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0052] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the light-emitting unit may include a light-emitting device. The circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0053] In some exemplary embodiments, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0054] In some exemplary embodiments, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel emitting white (W) light. For another example, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square shape, a diamond shape, etc., which is not limited in the present disclosure.

[0055] In some exemplary embodiments, the light emitting device may be any one of a light emitting diode, an organic light emitting diode, a quantum dot light emitting diode, a micro LED (including: mini-LED or micro-LED), etc. For example, the light emitting device may be an OLED, and the light emitting device may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel driving circuit. In some examples, the light emitting device may include: an anode, a cathode, and an organic light emitting layer located between the anode and the cathode. The anode of the light emitting device may be electrically connected to the corresponding pixel driving circuit.

[0056] The present disclosure provides a display substrate, the display substrate comprising:

[0057] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a plurality of frame areas;

[0058] A plurality of groups of data signal lines are located in the display area, and the plurality of groups of data signal lines are arranged at intervals along a first direction and extend along a second direction, and each group of data signal lines includes a first data signal line and a second data signal line; the first direction intersects with the second direction and the plane formed is parallel to the plane where the substrate is located;

[0059] A plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are arranged along the second direction to form a plurality of sub-pixel columns; the first data signal line and the second data signal line in the same group are electrically connected to different sub-pixels in the same sub-pixel column respectively;

[0060] a plurality of first power lines, located in the display area and configured to transmit low voltage signals;

[0061] The plurality of frame regions include a first frame region and a second frame region that are arranged opposite to each other along the second direction, and a third frame region and a fourth frame region that are arranged opposite to each other along the first direction; the display substrate further includes at least one first connecting line, the first connecting line includes a first end and a second end that are arranged opposite to each other, the first end is connected to the first power line, and the second end is located in the first frame region, and the first connecting line includes a plurality of traces located in different conductive layers;

[0062] The display substrate also includes a multiplexing circuit, which is located in the first frame area, a portion of the first connecting line is located between the multiplexing circuit and the display area, a portion of the first connecting line is located on one side of the multiplexing circuit along the first direction, and the first connecting line and the multiplexing circuit do not overlap in their orthographic projection on the plane where the substrate is located.

[0063] In the disclosed embodiment, by designing a display substrate with dual data signal lines, high-frequency driving can be achieved and the threshold voltage compensation capability can be improved, and the threshold voltage compensation time can be shortened. Furthermore, the display substrate adopts a SIP (VSS In Panel) design, which can reduce the overall voltage drop of the low-voltage signal and improve the uniformity of the voltage distribution. The first connecting line and the multiplexing circuit are designed so that their orthographic projections on the plane where the substrate is located do not overlap, which can avoid mutual interference between different signals, improve the display quality of the display device, and reduce display power consumption.

[0064] Figure 3A FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. Figure 3AAs shown, the display substrate may include a substrate, a display area AA located on the substrate, and a peripheral area BB located on the substrate and surrounding the display area AA. The display area AA may include a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, or folding. The shape of the display area AA may be a quadrilateral, a circle, an ellipse, or a rounded polygon, etc., which is not limited in the present disclosure.

[0065] The peripheral area BB may include multiple frame areas, and the multiple frame areas may include a first frame area B1 located on one side of the display area AA, and a second frame area B2 arranged opposite to the first frame area B1. Along the second direction Y, the first frame area B1 and the second frame area B2 are respectively located on both sides of the display area AA. The multiple frame areas may also include a third frame area B3 located on one side of the display area AA, and a fourth frame area B4 arranged opposite to the third frame area B3. Along the first direction X, the third frame area B3 and the fourth frame area B4 are respectively located on both sides of the display area AA. In the embodiment of the present disclosure, the first frame area B1 can also be referred to as the lower frame of the display substrate, the second frame area B2 can also be referred to as the upper frame of the display substrate, the third frame area B3 can also be referred to as the left frame of the display substrate, and the fourth frame area B4 can also be referred to as the right frame of the display substrate. In the embodiment of the present disclosure, the first direction X intersects with the second direction Y and the plane formed is parallel to the plane where the substrate is located. For example, the first direction X and the second direction Y can be perpendicular to each other.

[0066] The peripheral area BB may further include at least one transition area, at least one set of two adjacent frame areas are connected via a transition area, and at least a portion of a boundary of at least one transition area close to the display area AA may be an arc-shaped boundary. Figure 3AIn the figure, the peripheral area BB includes four transition areas, which are respectively the first transition area G1, the second transition area G2, the third transition area G3 and the fourth transition area G4. The first transition area G1 is located between the first frame area B1 and the third frame area B3, and the first frame area B1 and the third frame area B3 are connected via the first transition area G1. The second transition area G2 is located between the first frame area B1 and the fourth frame area B4, and the first frame area B1 and the fourth frame area B4 are connected via the second transition area G2. The third transition area G3 is located between the second frame area B2 and the fourth frame area B4, and the second frame area B2 and the fourth frame area B4 are connected via the third transition area G3. The fourth transition area G4 is located between the second frame area B2 and the third frame area B3, and the second frame area B2 and the third frame area B3 are connected via the fourth transition area G4.

[0067] In some exemplary embodiments, Figure 3A As shown, the display area AA may include at least a plurality of scan signal lines (e.g., S1, S2) and a plurality of groups of data signal lines. The plurality of scan signal lines may extend along a first direction X and be arranged at intervals along a second direction Y, and the plurality of groups of data signal lines may extend along a second direction Y and be arranged at intervals along the first direction X. The orthographic projections of the plurality of scan signal lines and the plurality of groups of data signal lines on the plane where the substrate is located intersect to form a plurality of sub-pixel regions, and a sub-pixel is arranged in each sub-pixel region. The plurality of groups of data signal lines are electrically connected to the plurality of sub-pixels, and the plurality of groups of data signal lines may be configured to provide data signals to the plurality of sub-pixels. The plurality of scan signal lines are electrically connected to the plurality of sub-pixels, and the plurality of scan signal lines may be configured to provide gate control signals to the plurality of sub-pixels. In some examples, the gate control signal may include a scan signal and a light emitting control signal.

[0068] In some exemplary embodiments, Figure 3AAs shown, each group of data signal lines includes a first data signal line DL-1 and a second data signal line DL-2, and the first data signal line DL-1 and the second data signal line DL-2 are electrically connected to different sub-pixels in the same sub-pixel column (along the second direction Y). For example, the first group of data signal lines DL1 includes a first data signal line DL-1 and a second data signal line DL-2. For example, the first data signal line DL-1 is electrically connected to the sub-pixels located in odd rows (along the first direction X) in the same sub-pixel column, and the second data signal line DL-2 is electrically connected to the sub-pixels located in even rows in the same sub-pixel column. In the embodiment of the present disclosure, by designing a display substrate with dual data signal lines, high-frequency driving can be achieved, and the threshold voltage (Vth) compensation capability can be improved, the threshold voltage compensation time can be shortened, and further, the display substrate can be integrated with a driver integrated circuit without data storage function, which can reduce the cost of the display device.

[0069] In some exemplary embodiments, Figure 3A As shown, the display substrate may further include a plurality of first power lines 10, the plurality of first power lines 10 extending along the second direction Y and arranged at intervals along the first direction X, and the plurality of first power lines 10 are located in the display area AA. The first power line 10 is also a low-level power line or a negative voltage power line. In the embodiment of the present disclosure, the display substrate adopts a SIP (VSS In Panel) design, which can reduce the overall voltage drop of the low-voltage signal, improve the uniformity of the voltage distribution, improve the display effect of the display device, and reduce the display power consumption.

[0070] In some exemplary embodiments, Figure 3A As shown, at least part of the plurality of first power lines 10 are arranged in pairs with at least part of the plurality of groups of data signal lines, and the first power line 10 is located between the first data signal line DL-1 and the second data signal line DL-2 arranged in pairs, and the first power line 10 and the paired data signal lines are located in different conductive layers. In the embodiment of the present disclosure, the first power line and the paired data signal lines are arranged in different conductive layers to avoid electrical interference between the first power line and the data signal lines.

[0071] In some exemplary embodiments, Figure 3A As shown, the display substrate may further include a first power supply line 11 , which may be located in the peripheral area BB. For example, a portion of the first power supply line 11 may surround the display area AA, and the first power supply line 11 is connected to the first power line 10 .

[0072] In some exemplary embodiments, Figure 3AAs shown, the display substrate may further include a plurality of second power lines 20, the plurality of second power lines 20 extending along the second direction Y and arranged at intervals along the first direction X. Parts of the plurality of second power lines 20 are located in the display area AA, and the plurality of second power lines 20 may extend to the first frame area B1. The second power line 20 is also a high-level power line. The second power line 20 may be electrically connected to the pixel driving circuit of the plurality of sub-pixels, and may be configured to transmit a high-voltage signal to the plurality of sub-pixels.

[0073] In some exemplary embodiments, Figure 3A As shown, the display substrate may further include a second power bus 21 , and the second power bus 21 is located in the first frame area B1 and may extend along the first direction X, and the second power bus 21 may be connected to a plurality of second power lines 20 .

[0074] In some exemplary embodiments, Figure 3A As shown, along the direction away from the display area AA, the first frame area B1 may include at least a first sub-frame area B11 and a second sub-frame area B12. The first sub-frame area B11 may be connected to the display area AA, and the second sub-frame area B12 is located on the side of the first sub-frame area B11 away from the display area AA. The first sub-frame area B11 may include at least a second power bus 21 and a multiplexing circuit 22, and the multiplexing circuit 22 may be configured to enable a signal source to provide data signals for multiple data signal lines. Towards the direction away from the first sub-frame area B11, the second sub-frame area B12 may include a bending area, a driving chip area, and a binding pin area arranged in sequence. The bending area may include a composite insulating layer provided with a groove, and the groove may be configured to bend a portion of the first frame area B1 to the back of the display area AA. The driving chip area may include at least a driving integrated circuit 23 (Integrated Circuit, IC), and the driving integrated circuit 23 may be connected to the multiplexing circuit 22 through a data transmission line. The driving integrated circuit 23 may send a data signal to the sub-pixel of the display area AA through the multiplexing circuit 22. For example, the multiplexing circuit 22 may adopt a MUX1:4 scheme. By designing a multiplexing circuit, the number of data transmission lines (connecting the driver integrated circuit and the data signal line) can be reduced, the size of the driver integrated circuit can be reduced, and the narrow frame design of the display device is beneficial. The binding pin area may include at least a plurality of binding pins, and the plurality of binding pins are configured to be bound and connected to a flexible printed circuit (FPC).

[0075] In some exemplary embodiments, the display substrate may further include a gate drive circuit and a plurality of gate drive signal lines, and the gate drive circuit may be located in the third frame area B3 and the fourth frame area B4. The gate drive circuit may include a plurality of cascaded shift registers GOA1, GOA2...GOAn, and the plurality of shift registers may be electrically connected to a plurality of scan signal lines in the display area AA. The plurality of gate drive signal lines GSTV, GCK, GCB are electrically connected to the gate drive circuit, and each shift register is electrically connected to a scan signal line.

[0076] Figure 3B FIG. 1 is a partial cross-sectional schematic diagram of a display area of ​​a display substrate according to an embodiment of the present disclosure. Figure 3B Only a partial connection structure of the connection area between the pixel driving circuit and the light emitting device is shown. Figure 3B As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least a circuit structure layer 200, a light emitting structure layer 300, and an encapsulation structure layer 400 sequentially arranged on the substrate 100. The circuit structure layer 200 may include at least a pixel driving circuit of a plurality of sub-pixels, and the pixel driving circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. For example, the transistor may be a thin film transistor. The light emitting structure layer 300 may include at least a light emitting device of a plurality of sub-pixels. In other examples, a touch structure layer 500 may be provided on the side of the encapsulation structure layer 400 away from the substrate 100 to integrate a touch function.

[0077] In some exemplary embodiments, the circuit structure layer 200 may include a semiconductor layer, a first insulating layer 101, a first gate metal layer, a second insulating layer 102, a second gate metal layer, a third insulating layer 103 (interlayer insulating layer), a first source-drain metal layer, a first planar layer 104, a second source-drain metal layer, and a second planar layer 105, which are stacked in sequence. The semiconductor layer in the display area may include: an active layer T10 of a transistor T of a pixel driving circuit. The active layer T10 of the transistor T may include: a first region, a second region, and a channel region located between the first region and the second region. The first gate metal layer in the display area may include: a gate T11 of the transistor T and a first electrode C11 of the capacitor C. The second gate metal layer may include a second electrode C22 of the capacitor C. The orthographic projections of the second electrode C22 and the first electrode C11 on the plane where the substrate 100 is located may at least partially overlap, and for example, the two may overlap. The first source-drain metal layer in the display area may include a source T12 and a drain T13 of the transistor T. The source electrode T12 of the transistor T may be electrically connected to the first region of the active layer T10, and the drain electrode T13 may be electrically connected to the second region of the active layer T10. The second source-drain metal layer of the display region may include a transfer electrode T14, and one of the source electrode T12 and the drain electrode T13 is electrically connected to the transfer electrode T14 through a via hole provided in the first flat layer 104. For example, the drain electrode T13 is electrically connected to the transfer electrode T14 through a via hole provided in the first flat layer 104. The transfer electrode T14 is configured to be electrically connected to the light emitting device to achieve electrical connection between the light emitting device and the pixel driving circuit.

[0078] The light emitting structure layer 300 may include a pixel definition layer 304 and a plurality of light emitting devices. Each light emitting device may include: a stacked first electrode 301, an organic light emitting layer 302, and a second electrode 303. The first electrode 301 of the light emitting device may be electrically connected to the transfer electrode T14 through a via hole provided in the second flat layer 105. The pixel definition layer 304 is provided on a side of the first electrode 301 away from the substrate 100, and the pixel definition layer 304 may be provided with a plurality of pixel openings, and a pixel opening may expose at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light emitting layer 302 may be provided in a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be provided on a side of the organic light emitting layer 302 away from the substrate 100, and connected to the organic light emitting layer 302. The organic light emitting layer 302 may emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303.

[0079] In some exemplary embodiments, the organic light-emitting layer 302 of the light-emitting device may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the organic light-emitting layer 302 can emit light of corresponding colors.

[0080] Figure 4 FIG. 1 is a schematic diagram of a partial structure of a first frame region of a display substrate according to an embodiment of the present disclosure. Figure 4 As shown, the display substrate may further include at least one first connection line 12, at least part of which is located in the first frame area B1. The first connection line 12 may include a first end and a second end that are arranged opposite to each other, the first end may be connected to a first power line 10, and the second end is located on a side of the first end in the opposite direction of the second direction Y. For example, the display substrate may include a plurality of first connection lines 12, and the plurality of first connection lines 12 and the plurality of first power lines 10 may be arranged in pairs one by one.

[0081] like Figure 4 As shown, the first connecting line 12 may include a plurality of lines connected in sequence, and the plurality of lines may include a first line 12-1, a second line 12-2, and a third line 12-3. The first line 12-1 and the third line 12-3 may extend along the second direction Y, the second line 12-2 may extend along the first direction X, the second line 12-2 and the third line 12-3 may be both located in the first frame area B1, a portion of the first line 12-1 is located in the first frame area B1, and the remaining portion of the first line 12-1 is located in the display area AA. Each line has a first end and a second end that are relatively arranged, the first end of the first line 12-1 is connected to the first power line 10, and the second end of the first line 12-1 is located on the side of the first end of the first line 12-1 in the opposite direction of the second direction Y. The second end of the first line 12-1 is connected to the first end of the second line 12-2, and the second end of the second line 12-2 is located on the side of the first end of the second line 12-2 in the opposite direction of the first direction X. The first end of the third routing line 12 - 3 is connected to the second end of the second routing line 12 - 2 , and the second end of the third routing line 12 - 3 is located on a side of the first end of the third routing line 12 - 3 in the opposite direction of the second direction Y.

[0082] like Figure 4 As shown, along the direction perpendicular to the plane where the substrate is located, the first frame area B1 of the display substrate may include a first conductive layer and a second conductive layer stacked, and the first conductive layer is closer to the substrate than the second conductive layer. For example, the first conductive layer may be arranged in the same layer as the first source and drain metal layer, and the second conductive layer may be arranged in the same layer as the second source and drain metal layer. The first power line 10 may be located in the first conductive layer, and the first data signal line DL-1 and the second data signal line DL-2 are both located in the second conductive layer. The first power line 10 and the first data signal line DL-1 and the second data signal line DL-2 are arranged in layers, which can avoid problems such as short circuits between signals caused by overly dense signal line layout. The first routing line 12-1 extends along the second direction Y and is located between the adjacent first data signal line DL-1 and the second data signal line DL-2. The first line 12-1 and the second power bus 21 overlap at least partially in their orthographic projections on the plane where the substrate is located. The second power bus 21 is located in the first conductive layer, and the first line 12-1 is located in the second conductive layer. By arranging the second power bus 21 and the first line 12-1 in different conductive layers, a short circuit between the second power bus 21 and the first line 12-1 can be avoided. The second line 12-2 extends along the first direction X, and the second line 12-2 overlaps partially with the orthographic projection of at least one data signal line on the plane where the substrate is located. The second line 12-2 is located in the first conductive layer, and the data signal line is located in the second conductive layer, so a short circuit between the second line 12-2 and the data signal line can be avoided.

[0083] The display substrate may also include a plurality of multiplexing control lines, and the plurality of multiplexing control lines may include at least a first multiplexing control line MUX1, a second multiplexing control line MUX2, a third multiplexing control line MUX3, and a fourth multiplexing control line MUX4. The third routing line 12-3 overlaps with the orthographic projection of at least one multiplexing control line on the plane where the substrate is located. The third routing line 12-3 is located in the second conductive layer, and the multiplexing control line is located in the first conductive layer. Such an arrangement can avoid signal coupling between the third routing line 12-3 and the multiplexing control line, and can improve the display quality of the display device. For example, the third routing line 12-3 overlaps with the orthographic projections of the first multiplexing control line MUX1, the second multiplexing control line MUX2, the third multiplexing control line MUX3, and the fourth multiplexing control line MUX4 on the plane where the substrate is located.

[0084] like Figure 4As shown, the display substrate may further include at least one second power bus branch line 21-1, the second power bus branch line 21-1 may be located in the first frame area B1, and the second power bus branch line 21-1 is located in the first conductive layer. The second power bus branch line 21-1 may extend along the second direction Y, and the second power bus branch line 21-1 may include a first end and a second end that are arranged oppositely, the first end may be connected to the second power bus 21, and the second end may be located on the side opposite to the second direction Y of the first end.

[0085] like Figure 4 As shown, at least part of the second wiring 12-2 is located between the multiplexing circuit 22 and the display area AA, and in an exemplary embodiment, the entire second wiring 12-2 is located between the multiplexing circuit 22 and the display area AA. At least part of the third wiring 12-3 is located on one side of the multiplexing circuit 22 along the first direction X, and in an exemplary embodiment, at least part of the third wiring 12-3 is located on one side of the multiplexing circuit 22 in the opposite direction of the first direction X.

[0086] The multiplexing circuit 22 may include at least a plurality of multiplexing control transistors 22-1. For example, the multiplexing circuit 22 may include four multiplexing control transistors 22-1, and the four multiplexing control transistors 22-1 may be arranged in sequence along the first direction X. The multiplexing control transistor 22-1 may include at least a gate, a source, and a drain. The gate (not shown) of the multiplexing control transistor 22-1 may be connected to the multiplexing control line, one of the source and the drain of the multiplexing control transistor 22-1 may be connected to the data signal line, and the other of the source and the drain of the multiplexing control transistor 22-1 may be connected to the data transmission line 30. For example, the four multiplexing control transistors 22-1 may be connected to the same data transmission line 30.

[0087] The orthographic projection of the third wiring 12 - 3 on the plane where the substrate is located can be located between the orthographic projection of the second power bus branch line 21 - 1 and the multiplexing circuit 22 on the plane where the substrate is located, so as to avoid crosstalk between different signals.

[0088] Figure 5A FIG. 1 is a schematic diagram of a partial structure of a first transition region of a display substrate according to an embodiment of the present disclosure. Figure 5AAs shown, the display substrate may further include at least one second connection line 13, at least part of the second connection line 13 may be located in the first transition region G1, the second connection line 13 may include a first end and a second end that are arranged opposite to each other, the first end may be connected to a first power line 10, and the second end is located on the side of the first end in the opposite direction of the second direction Y. By way of example, the display substrate may include a plurality of second connection lines 13, the number of the second connection lines 13 being less than the number of the first power lines 10. By way of example, the display substrate may include a plurality of first power lines 10, part of the plurality of first power lines 10 being connected to the second connection line 13, and the remaining part of the plurality of first power lines 10 being connected to the first connection line 12. As shown in FIG. Figure 5A As shown, the second connection line 13 may include a plurality of lines connected in sequence, and the plurality of lines may include a fourth line 13-4, a fifth line 13-5, and a sixth line 13-6. The fourth line 13-4 and the sixth line 13-6 may extend along the second direction Y, the fifth line 13-5 and the sixth line 13-6 may be located in the first transition region G1, a portion of the fourth line 13-4 may be located in the first transition region G1, and the remaining portion of the fourth line 13-4 may be located in the display region AA. Each line has a first end and a second end that are arranged opposite to each other. The first end of the fourth line 13-4 is connected to the first power line 10, and the second end of the fourth line 13-4 is located on a side of the first end of the fourth line 13-4 in the opposite direction of the second direction Y. The second end of the fourth line 13-4 is connected to the first end of the fifth line 13-5, and the second end of the fifth line 13-5 is located on a side of the first end of the fifth line 13-5 in the opposite direction of the second direction Y. The first end of the sixth line 13-6 is connected to the second end of the fifth line 13-5, and the second end of the sixth line 13-6 is located on the side opposite to the first end of the sixth line 13-6 along the second direction Y. Figure 5A As shown, the fourth routing line 13-4 and the sixth routing line 13-6 can be located in the second conductive layer, and the fifth routing line 13-5 can be located in the first conductive layer. In the embodiment of the present disclosure, by setting the second connecting line, the low voltage signals of the sub-pixels near the first transition area and the sub-pixels near the first frame area can be basically consistent, which is conducive to ensuring the uniformity of display.

[0089] In some exemplary embodiments, Figure 5AAs shown, the display substrate may further include at least one second power transmission line 21-2, at least part of the second power transmission line 21-2 may be located in the first transition region G1, one end of the second power transmission line 21-2 close to the first frame region B1 may be connected to the second power bus 21, and the second power transmission line 21-2 may be connected to a plurality of second power lines 20 located in the display region AA. The second power transmission line 21-2 is used to transmit high-voltage signals to the pixel driving circuits of the plurality of sub-pixels. The orthographic projections of the fourth line 13-4 and the second power transmission line 21-2 on the plane where the substrate is located may at least partially overlap, the fourth line 13-4 may be located in the second conductive layer, and the second power transmission line 21-2 may be located in the first conductive layer. The fourth line 13-4 and the second power transmission line 21-2 are arranged in different conductive layers, so that signal crosstalk between the fourth line 13-4 and the second power transmission line 21-2 can be avoided.

[0090] In some exemplary embodiments, Figure 5A As shown, the orthographic projection of the fifth routing line 13-5 and at least one data signal line on the plane where the substrate is located at least partially overlaps, the fifth routing line 13-5 can be set in the first conductive layer, and the data signal line is set in the second conductive layer. By setting the fifth routing line 13-5 and the data signal line in different conductive layers, signal crosstalk between the fifth routing line 13-5 and the data signal line can be avoided.

[0091] In some exemplary embodiments, Figure 5A As shown, the sixth line 13-6 overlaps with at least one multiplexing control line in the orthographic projection portion of the plane where the substrate is located, the sixth line 13-6 can be set in the second conductive layer, and the multiplexing control line can be set in the first conductive layer, which can avoid signal crosstalk between the sixth line 13-6 and the multiplexing control line. For example, the sixth line 13-6 overlaps with the orthographic projection of the first multiplexing control line MUX1, the second multiplexing control line MUX2, the third multiplexing control line MUX3, and the fourth multiplexing control line MUX4 in the plane where the substrate is located.

[0092] In some exemplary embodiments, the fifth wiring 13 - 5 of the plurality of second connection lines 13 may be an integrated structure connected to each other, which can reduce the number of wirings and is conducive to realizing a narrow frame design of the display substrate.

[0093] In some exemplary embodiments, the sixth wiring 13 - 6 of the plurality of second connection lines 13 may be shared, which may reduce the number of wirings and is conducive to realizing a narrow frame design of the display substrate.

[0094] In some exemplary embodiments, the line width of the fifth trace 13 - 5 may be approximately 10 micrometers.

[0095] In some exemplary embodiments, the display area AA may have a first center line, which may be a straight line bisecting the display area in the first direction X and extending along the second direction Y. The first transition area G1 and the second transition area G2 may be symmetrical about the first center line.

[0096] In some exemplary embodiments, the display substrate may further include at least one third connection line, at least part of which is located in the second transition region G2 , and at least part of the third connection line and at least part of the second connection line 13 may be symmetrical about the first center line.

[0097] In some exemplary embodiments, the display area AA may have a second center line, and the second center line may be a straight line that bisects the display area in the second direction Y and extends along the first direction X. The first transition area G1 and the fourth transition area G4 may be symmetrical about the second center line. The second transition area G2 and the third transition area G3 may be symmetrical about the second center line.

[0098] In some exemplary embodiments, the display substrate may further include at least one fourth connection line, at least a portion of the fourth connection line is located in the third transition region G3, and at least a portion of the fourth connection line and at least a portion of the third connection line may be symmetrical about the second center line.

[0099] In some exemplary embodiments, the display substrate may further include at least one fifth connection line, at least part of which is located in the fourth transition region G4 , and at least part of the fifth connection line and at least part of the second connection line 13 may be symmetrical about the second center line.

[0100] Figure 5B FIG. 1 is a schematic diagram of a partial structure of a first transition region of a display substrate according to another embodiment of the present disclosure. Figure 5B As shown, since the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 in the display area AA is not completely the same, for example, the number of sub-pixels included in the sub-pixel columns close to the first transition region G1 is different. Figure 5B As shown, the second connection line 13 is bent near each sub-pixel column, that is, the orthographic projection of at least part of the second connection line 13 near the display area AA on the plane where the substrate is located can be stepped, which can reduce the space occupied by the display substrate and realize a narrow frame of the display device.

[0101] In some exemplary embodiments, the step shape may be a 90-degree step, or may be a step at other angles, and the present disclosure does not limit the angle of the step shape.

[0102] Figure 6 FIG. 1 is a schematic diagram of a partial structure of a first transition region of a display substrate according to another embodiment of the present disclosure. Figure 6 As shown, the display substrate may further include at least one auxiliary power line 14 and at least one reset signal line FW, and the reset signal line FW is configured to provide a reset signal to the gate drive circuit. At least part of the auxiliary power line 14 and at least part of the reset signal line FW may be located in the first transition region G1, and the auxiliary power line 14 may include a first end and a second end that are relatively arranged, and the first end of the auxiliary power line 14 may be connected to the second connecting line 13, and the second end of the auxiliary power line 14 may be located on the side of the first end in the opposite direction of the first direction X. For example, the second end of the auxiliary power line 14 may be located in the third frame area B3. In the embodiment of the present disclosure, by providing the auxiliary power line 14, the resistance can be reduced, and the effect of shunting and reducing the current density can be achieved, so as to prevent burns caused by the large current density in the first transition region.

[0103] In some exemplary embodiments, the auxiliary power line 14 may include a plurality of connected sub-segments, and at least two of the plurality of sub-segments may be located in different conductive layers. The plurality of sub-segments may include a first sub-segment 14-1, a second sub-segment 14-2, and a third sub-segment 14-3, the first sub-segment 14-1, the second sub-segment 14-2, and the third sub-segment 14-3 may be connected in sequence, the first sub-segment 14-1 and the third sub-segment 14-3 may be located in the second conductive layer, and the second sub-segment 14-2 may be located in the first conductive layer.

[0104] In some exemplary embodiments, Figure 6 As shown, the orthographic projection of the second sub-segment 14-2 and the reset signal line FW on the plane where the substrate is located at least partially overlaps. The second sub-segment 14-2 can be set in the first conductive layer, and the reset signal line FW can be set in the second conductive layer, which can avoid signal crosstalk between the second sub-segment 14-2 and the reset signal line FW.

[0105] Figure 7 FIG. 1 is a schematic diagram of a partial structure of a second frame region of a display substrate according to an embodiment of the present disclosure. Figure 7 As shown, the display substrate may further include at least one horizontal wiring 15 and at least one vertical wiring 16, the horizontal wiring 15 extends along the first direction X, the vertical wiring 16 extends along the second direction Y, and the horizontal wiring 15 and the vertical wiring 16 are cross-connected to each other, and for example, a plurality of horizontal wirings 15 and a plurality of vertical wirings 16 are cross-connected to each other to form a mesh. For example, the horizontal wiring 15 and the vertical wiring 16 may be both located in the second frame area B2. For example, the horizontal wiring 15 and the vertical wiring 16 may be both located in the second conductive layer.

[0106] The display substrate may further include a first power bus 17, which is located in the second frame area B2 and extends along the first direction X. The horizontal wiring 15 is located on one side of the first power bus 17 along the second direction Y, and the vertical wiring 16 may include a first end and a second end that are relatively arranged, the first end is connected to the first power bus 17, and the second end is located on one side of the first end along the second direction Y. The first power bus 17 may be configured to transmit a low voltage signal. In the embodiment of the present disclosure, the low voltage resistance can be reduced by setting the horizontal wiring, the vertical wiring and the first power bus.

[0107] Figure 8 This is a schematic diagram of the planar structure of a display substrate of another embodiment of the present disclosure. The display device may have a display side and a non-display side. Among them, the display side may be the side of the display device that can display an image. When the human eye is on the display side, the image displayed by the display device can be viewed. The non-display side is opposite to the display side. The sensor can be arranged on the non-display side of the display device, and therefore, the sensor can be called an under-screen sensor. Since the sensor needs to receive light signals from the outside world that pass through the display device, the display device needs to have a higher light transmittance in the area corresponding to the sensor.

[0108] like Figure 8 As shown, the display substrate may include a substrate, a display area AA located on the substrate, and a peripheral area BB located on the substrate and surrounding the display area AA. The display area AA may include a first area AA1 and a second area AA2 that do not overlap each other. The first area AA1 may be referred to as a sensor non-corresponding area, and the second area AA2 may be referred to as a sensor corresponding area. The light transmittance of the second area AA2 is higher than the light transmittance of the first area AA1. The orthographic projection of the sensor on the display substrate may at least partially overlap with the second area AA2, so that more light can pass through the display substrate and be received by the sensor. For example, a portion of the orthographic projection of the sensor on the display substrate is located within the second area AA2. Alternatively, the entire orthographic projection of the sensor on the display substrate is located within the second area AA2. The first area AA1 may be an area in the display area AA other than the second area AA2.

[0109] In some exemplary embodiments, the first area AA1 may surround at least one side of the second area AA2. For example, the second area AA2 may be located in the top center of the display area AA, and the first area AA1 may surround the second area AA2. For example, the second area AA2 may be located in the upper left corner or upper right corner of the display area AA, etc., which is not limited in the present disclosure.

[0110] In some exemplary embodiments, the display area AA may be a rectangle, such as a rounded rectangle. The second area AA2 may be a circle, an ellipse, a rectangle, a pentagon, a hexagon, etc., which is not limited in the present disclosure.

[0111] In some exemplary embodiments, Figure 8 As shown, the display substrate may further include a first power transmission line 18, the first power transmission line 18 is configured to transmit a low voltage signal, the first power transmission line 18 is located in the first area AA1, and the first power transmission line 18 surrounds at least a portion of the second area AA2, and for example, the first power transmission line 18 may surround the entire second area AA2. The first power transmission line 18 may be connected to a plurality of first power lines 10, which may improve the uniformity of the overall display of the display area and avoid the appearance of a dark display area.

[0112] In some exemplary embodiments, Figure 8 As shown, in the plane where the substrate is located, at least a portion of the first power transmission line 18 may be in a stepped shape, and the stepped shape may be a 90-degree step, or may be a step at other angles. The present disclosure does not limit the angle of the stepped shape.

[0113] In some exemplary embodiments, the sub-pixels located in the second area AA2 and at least a portion of the sub-pixels close to the boundary of the second area AA2 are arranged in a stair-like manner.

[0114] The present disclosure also provides a display device, including a display substrate of any of the above embodiments. In some examples, the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, the present disclosure is not limited to this.

[0115] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a plurality of frame areas; A plurality of groups of data signal lines are located in the display area, and the plurality of groups of data signal lines are arranged at intervals along a first direction and extend along a second direction, and each group of data signal lines includes a first data signal line and a second data signal line; the first direction intersects with the second direction and the plane formed is parallel to the plane where the substrate is located; A plurality of sub-pixels are located in the display area, and the plurality of sub-pixels are arranged along the second direction to form a plurality of sub-pixel columns; the first data signal line and the second data signal line in the same group are electrically connected to different sub-pixels in the same sub-pixel column respectively; a plurality of first power lines, located in the display area and configured to transmit low voltage signals; The plurality of frame regions include a first frame region and a second frame region that are arranged opposite to each other along the second direction, and a third frame region and a fourth frame region that are arranged opposite to each other along the first direction; the display substrate further includes at least one first connecting line, the first connecting line includes a first end and a second end that are arranged opposite to each other, the first end is connected to the first power line, and the second end is located in the first frame region, and the first connecting line includes a plurality of traces located in different conductive layers; The display substrate also includes a multiplexing circuit, which is located in the first frame area, a portion of the first connecting line is located between the multiplexing circuit and the display area, a portion of the first connecting line is located on one side of the multiplexing circuit along the first direction, and the first connecting line and the multiplexing circuit do not overlap in their orthographic projection on the plane where the substrate is located.

2. The display substrate according to claim 1, wherein: At least part of the multiple first power lines are arranged in pairs with at least part of the multiple groups of data signal lines, and the first power line is located between the first data signal line and the second data signal line arranged in pairs, and the first power line and the data signal lines arranged in pairs are located in different conductive layers.

3. The display substrate according to claim 1 or 2, characterized in that: The plurality of routing lines include a first routing line, a second routing line, and a third routing line connected in sequence, and the third routing line is farther away from the display area than the first routing line, and the first routing line and the third routing line both extend along the second direction, and the second routing line extends along the first direction; a first end of the first connecting line is located on the first routing line, and a second end of the first connecting line is located on the third routing line; at least a portion of the second routing line is located between the multiplexing circuit and the display area, and at least a portion of the third routing line is located on one side of the multiplexing circuit along the first direction; The display substrate further comprises a second power bus located in the first frame region, the second power bus extending along the first direction, and the second power bus configured to transmit a high voltage signal to a plurality of sub-pixels; The orthographic projections of the first routing line and the second power bus on the plane where the substrate is located at least partially overlap, and the first routing line and the second power bus are located in different conductive layers; the orthographic projections of the second routing line and at least one data signal line on the plane where the substrate is located at least partially overlap, and the second routing line and the data signal line are located in different conductive layers.

4. The display substrate according to claim 1 or 2, characterized in that: The peripheral area further includes at least one transition area, and at least one group of two adjacent frame areas are connected via the transition area; at least a portion of the boundary of the transition area close to the display area is an arc-shaped boundary; The display substrate further includes at least one connecting line, at least a portion of which is located in the transition region, the connecting line includes a first end and a second end which are arranged opposite to each other, the first end is connected to the first power line, and the second end is located in the transition region.

5. The display substrate according to claim 4, wherein: The at least one transition region includes a first transition region, and the first transition region is located between the first frame region and the third frame region; The connecting wires include a second connecting wire, and at least a portion of the second connecting wire is located in the first transition area; the second connecting wires include a fourth routing wire, a fifth routing wire, and a sixth routing wire connected in sequence, and the fourth routing wire is closer to the display area than the sixth routing wire; the first end of the second connecting wire is located on the fourth routing wire, and the second end of the second connecting wire is located on the sixth routing wire; The display substrate further includes a second power transmission line extending along the first direction, at least a portion of the second power transmission line is located in the transition region, and the second power transmission line is configured to be connected to a second power bus and transmit a high voltage signal to a plurality of sub-pixels; The fourth routing line at least partially overlaps with the orthographic projection of the second power transmission line on the plane where the substrate is located, and the fourth routing line and the second power transmission line are located in different conductive layers; the fifth routing line at least partially overlaps with the orthographic projection of at least one data signal line on the plane where the substrate is located, and the fifth routing line and the data signal line are located in different conductive layers.

6. The display substrate according to claim 5, wherein: The fifth routing lines of the plurality of second connecting lines are an integrated structure connected to each other, and / or the sixth routing lines of the plurality of second connecting lines are shared.

7. The display substrate according to claim 4, wherein: The at least one transition region includes a first transition region, and the first transition region is located between the first frame region and the third frame region; The at least one connecting line includes a second connecting line, and at least a portion of the second connecting line is located in the first transition area; the display substrate also includes at least one auxiliary power line, at least a portion of the auxiliary power line is located in the first transition area, the auxiliary power line includes a first end and a second end arranged opposite to each other, the first end is connected to the second connecting line, and the second end is located in the third frame area.

8. The display substrate according to claim 1 or 2, characterized in that: The display substrate also includes a plurality of horizontal wirings, a plurality of vertical wirings and a first power bus located in the second frame area, and the horizontal wirings extend along the first direction, and the vertical wirings extend along the second direction, the vertical wirings are connected to the first power bus, and the horizontal wirings and the vertical wirings are interconnected to form a mesh; the horizontal wirings and the vertical wirings are located in the same conductive layer, the first power bus is located in another conductive layer, and the first power bus is configured to transmit low-voltage signals.

9. The display substrate according to claim 1 or 2, characterized in that: The display area includes a first area and a second area that do not overlap each other, the first area surrounds at least one side of the second area, and the plurality of first power lines are located in the first area; The display substrate also includes a first power transmission line located in the first area, and the first power transmission line surrounds at least a portion of the second area, and the first power transmission line is connected to the plurality of first power lines; in the plane where the substrate is located, at least a portion of the first power transmission line is stepped.

10. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 9.

Images