Display panels and display devices

Abstract

A display panel and a display device are disclosed. The display panel includes an array substrate (10), a color filter substrate (20), and a liquid crystal layer (LC) disposed opposite to each other between the array substrate (10) and the color filter substrate (20). The liquid crystal cell thickness of the liquid crystal layer (LC) in the light-transmitting area of ​​the display panel satisfies the following condition: when the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz, the reciprocal of the refresh rate of the display panel and the liquid crystal cell thickness conform to a quadratic polynomial relationship. The liquid crystal cell thickness of the display panel is only related to the refresh rate of the display panel, thus resulting in a simpler design complexity and higher design efficiency.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of thin-film transistor liquid crystal display (TFT-LCD) products and the increasing demands of users for display quality, the demand for high refresh rate products is growing daily. High refresh rates, in turn, require lower cell gaps.

[0003] Cell gap measurements are performed on the aperture area, but are difficult to perform on the photo spacer (PS) area due to its opacity. For LCD products, many factors influence the cell gap, including the TFT pillar (the height difference between the PS position on the TFT substrate and the light-transmitting area of ​​the pixel), the color resist level of the color filter substrate (CF), the height of the PS, and the amount of liquid crystal inside. These numerous influencing factors increase cell gap complexity and decrease design accuracy. Since high refresh rate LCD products require even lower cell gaps, reduced cell gap design accuracy significantly impacts the design efficiency of display products. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a display panel and a display device that at least partially solves the technical problem of reduced display product design efficiency caused by the complex design and low precision of liquid crystal cell thickness.

[0005] In a first aspect, this disclosure provides the following technical solution through an embodiment:

[0006] A display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed opposite to each other. The liquid crystal cell thickness in the light-transmitting area of ​​the display panel satisfies the following condition: when the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz, the reciprocal of the refresh rate of the display panel and the liquid crystal cell thickness conform to a quadratic polynomial relationship.

[0007] In some embodiments, the liquid crystal cell thickness and the refresh rate satisfy the following:

[0008] 1 / f = C2 × d 2 +C1×d+C0;

[0009] In the above formula, f is the refresh rate in Hz; d is the thickness of the liquid crystal cell in μm; the value of C2 ranges from 0.003 to 0.004, the value of C1 ranges from -0.02 to -0.01, and the value of C0 ranges from 0.01 to 0.02.

[0010] In some embodiments, when the refresh rate of the display panel is greater than 480Hz and not more than 1000Hz, the thickness of the liquid crystal cell ranges from 1.044μm to 1.6μm.

[0011] In some embodiments, the array substrate includes a first substrate and a first spacer layer, the first spacer layer being disposed on the side of the first substrate near the color filter substrate; the color filter substrate includes a second substrate and a second spacer layer, the second spacer layer being disposed on the side of the second substrate near the array substrate; the first spacer layer includes at least one first main spacer and a plurality of first secondary spacers, the first main spacers being spaced apart from the first secondary spacers; the second spacer layer includes at least one second main spacer and a plurality of second secondary spacers, the second main spacers being spaced apart from the second secondary spacers; the first main spacer abuts against the second main spacer, and the first secondary spacers and the second secondary spacers are disposed opposite to each other.

[0012] In some embodiments, the array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, wherein the organic film layer is located between the color resist layer and the first spacer layer.

[0013] In some embodiments, the organic film layer is provided with a first groove, the first secondary spacer is disposed in the first groove, and the first primary spacer is disposed on the organic film layer outside the first groove.

[0014] In some embodiments, the second primary spacer and the second secondary spacer include a black matrix layer, and the color filter substrate includes a planar protective layer covering the black matrix layer and the second substrate; in a direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the planar protective layer covering the second substrate, and the planar protective layer on the second primary spacer abuts against the first primary spacer.

[0015] In some embodiments, the sum of the thicknesses of the black matrix layer and the flat protective layer in the second primary spacer after cassette assembly deviates by no more than 20% from the height of the first primary spacer after cassette assembly.

[0016] In some embodiments, the color filter substrate includes a black matrix layer and a planarization protective layer disposed on the side of the second substrate near the array substrate, the black matrix layer being located between the second substrate and the planarization protective layer; a second groove is provided on the planarization protective layer, a second secondary spacer is disposed in the second groove, and a second primary spacer is disposed on the planarization protective layer outside the second groove.

[0017] In some embodiments, the color filter substrate includes a black matrix layer and a color resist layer disposed on the second substrate in the same layer, and a planarization protective layer covering the black matrix layer and the color resist layer; the second primary spacer and the second secondary spacer are disposed on the color resist layer, and their orthogonal projections on the second substrate are located within the orthogonal projection of the black matrix layer on the second substrate; in the direction perpendicular to the second substrate, the sum of the thicknesses of the black matrix layer and the planarization protective layer is less than the sum of the thicknesses of the color resist layer and the planarization protective layer.

[0018] In some embodiments, in the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45 μm to 0.55 μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45 μm to 0.55 μm.

[0019] In some embodiments, the product of the height of the first primary spacer before cell alignment and the compression ratio after cell alignment, and the sum of the height of the second primary spacer after cell alignment, are equal to the thickness of the liquid crystal cell, and the compression ratio ranges from 0.86 to 0.88.

[0020] In some embodiments, the deviation between the height of the first primary spacer after cassette alignment and the height of the second primary spacer after cassette alignment does not exceed 10%.

[0021] In some embodiments, the first primary septum is at the same height as the first secondary septum, and the second secondary septum is at a lower height than the second primary septum; or, the second secondary septum is at the same height as the second primary septum, and the first secondary septum is at a lower height than the first primary septum.

[0022] Secondly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0023] A display device comprising any of the display panels provided in the first aspect embodiments.

[0024] Through one or more technical solutions disclosed herein, this disclosure has the following beneficial effects or advantages:

[0025] The display panel disclosed herein has a cell gap designed such that, when the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz, the cell gap satisfies a quadratic polynomial relationship with the reciprocal of the refresh rate. By constructing a quadratic polynomial fitting relationship between the cell gap and the reciprocal of the refresh rate, compared with the conventional design of the cell gap based on TFT Pillow, color resist step difference, spacer height and liquid crystal amount, the influence factors of the cell gap are significantly reduced. This helps to reduce the design complexity of the cell gap and improve the design accuracy, thereby improving the design efficiency of liquid crystal display products.

[0026] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0027] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0028] In the attached diagram:

[0029] Figure 1 This is a schematic diagram illustrating the testing principle of liquid crystal cell thickness.

[0030] Figure 2 This is a schematic diagram of a display panel according to an embodiment of the present disclosure;

[0031] Figure 3 This is a schematic diagram showing the fitting of refresh rate and liquid crystal cell thickness according to an embodiment of the present disclosure;

[0032] Figure 4 This is a schematic diagram showing the absence of the sub-septum material Sub PS according to an embodiment of the present disclosure;

[0033] Figure 5 This is a schematic diagram of a display panel with XPS design according to an embodiment of the present disclosure;

[0034] Figure 6 This is a schematic diagram showing the arrangement of the first main spacer and the first secondary spacer according to an embodiment of the present disclosure;

[0035] Figure 7 This is a schematic diagram of the film layer structure of a display panel designed with XPS and COA according to an embodiment of this disclosure;

[0036] Figure 8AThis is a schematic diagram showing the first spacer disposed in the first groove according to an embodiment of the present disclosure;

[0037] Figure 8B This is a schematic diagram showing the arrangement of a first main spacer and a first secondary spacer in a first groove according to an embodiment of the present disclosure;

[0038] Figure 9 This is a schematic diagram of a second spacer layer formed by a black matrix layer and a planar protective layer according to an embodiment of the present disclosure;

[0039] Figure 10 This is a schematic diagram showing the second spacer disposed in the second groove according to an embodiment of the present disclosure;

[0040] Figure 11 A micrograph of the second septum according to an embodiment of the present disclosure;

[0041] Figure 12 The design of the spacer structure on the CF side of the XPS display panel according to an embodiment of the present disclosure;

[0042] Figure 13 This is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0043] Figure label:

[0044] 10. Array substrate; 11. First substrate; 12. First groove; 20. Color filter substrate; 21. Second substrate; 22. Second groove; BM, Black matrix layer; OC, Planarization protective layer; CRL, Color resist layer; ORG, Organic film layer; PS1, First spacer layer; MainPS1, First main spacer; SubPS1, First secondary spacer; PS2, Second spacer layer; MainPS2, Second main spacer; SubPS2, Second secondary spacer. Detailed Implementation

[0045] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0046] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0047] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0048] In the context of this disclosure, unless otherwise specified, the light-emitting side of the display panel is referred to as the "top side" or "upper side," and its opposite side as the "bottom side" or "lower side," to facilitate the description of relative directions. Accordingly, the direction from the bottom side to the top side is the thickness direction of the display panel, and the direction perpendicular to the thickness direction is the "planar direction" or "extension direction" of the display panel. It should be understood that these directions are relative directions rather than absolute directions.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0050] Cell gap is an important parameter in TFT-LCD design. With the development of the industry and the improvement of quality technology, LCD products with high refresh rates and extremely low cell gaps have emerged, which brings challenges to the design of cell gaps.

[0051] Cell Gap measurement principle as follows: Figure 1 As shown, after light is projected onto the liquid crystal cell, linearly polarized light is transformed into elliptical light due to the birefringence effect of the liquid crystal. This is because there is a phase difference between the x and y directions of the light. The magnitude of the phase difference is determined by the thickness d of the liquid crystal cell and the refractive index difference Δn, and the relationship is expressed as follows:

[0052] Re=Δn×d (1)

[0053] Therefore, the formula for calculating the thickness d of the liquid crystal cell is:

[0054] d=Re / Δn (2)

[0055] In the above formula, Re represents the birefringence phase difference, which refers to the phase change that occurs when linearly polarized light E is incident at a fixed angle. Before incident, the decomposed vectors Ex and Ey have the same phase, but after the light passes through the sample, the refractive indices of x and y differ, resulting in the birefringence phase difference. Δn = Ne - No, where Ne and No are characteristic parameters of the liquid crystal material.

[0056] The system procedure for measuring the thickness of the liquid crystal cell is as follows:

[0057] Spectral measurement of elliptically polarized light → Analysis of Re values ​​every 10 nm within the wavelength range of 400 nm to 800 nm → Calculation of the Re value for any wavelength using the least squares method with the Fitting formula.

[0058] The design of the liquid crystal cell thickness is related to the structural design of the postspacers (PS). Based on the postspacer structure, panels can be categorized into ordinary panels and XPS panels. In the manufacturing process of ordinary liquid crystal display panels, an array substrate (TFT) and a color filter substrate (CF) are fabricated separately. The edges of the CF and TFT substrates are then bonded together using an adhesive sealant. Liquid crystal fills the area sealed by the sealant to achieve the liquid crystal display device. Postspacers (PS) that provide support are provided in the pixel areas used for display and between the pixel areas and the sealant. These PSs are typically located on the CF substrate. For liquid crystal display panels manufactured using XPS technology, a layer of postspacers (PS) is formed on both the CF and TFT substrates and they abut against each other. In some embodiments, the two abutting PSs on the CF and TFT substrates are set to approximately equal heights. In other embodiments, the cross-sections of the two abutting PSs on the CF and TFT substrates are both strip-shaped in the direction parallel to the display panel and are made to intersect to optimize PS mura (non-uniformity) and panel strength.

[0059] The design of the cell gap for an XPS-designed LCD display product is as follows:

[0060] Cell Gap = PSH × 2 × PS compression rate - pixel segment difference + TFT Pillow (3)

[0061] In the above formula, PSH (Photo Space Height) is the free height of the columnar spacer PS on the array substrate side (TFT side) or color filter substrate (CF side) before cell assembly, and both are designed with equal height; PS compression rate is the compression rate of the columnar spacer PS after cell assembly, for example, the selectable value of the compression rate is about 87%; pixel step difference is the pixel step difference of sub-pixel RGB after OC (flattening protective layer), which is the step difference between sub-pixel RGB and black matrix; TFT Pillow is the height difference between the spacer PS setting position on the TFT substrate and the light-transmitting area of ​​the pixel.

[0062] Currently, the ultra-low PSH technology can reduce the height of the spacer on one side of XPS products to 0.9μm, that is, the PSH on one side is ≥0.9μm. According to Equation (3) and the common values ​​of pixel segment and TFT Pillow, it can be known that the thickness of the liquid crystal cell of XPS LCD panel will not be less than 1.57μm.

[0063] For ordinary LCD display products, one design for the cell gap is as follows:

[0064] Cell Gap = PSH × Compression Ratio - Pixel Segment Difference + TFT Pillow (4)

[0065] Here, PSH (Photo Space Height) is the height of the columnar spacers PS on the color filter substrate side. Similarly, if PSH is not less than 0.9μm, it can be determined that the cell thickness of a typical liquid crystal display panel will not be less than 0.78μm.

[0066] As mentioned above, many factors influence the cell gap, including TFT pillar, CF color resist step difference, and spacer height. The amount of internal liquid crystal is also an influencing factor. With the development of high refresh rate displays, smaller cell gaps are required; therefore, deviations in cell gap design precision have a more significant impact on high refresh rate displays.

[0067] To solve the above problems, firstly, please refer to [the relevant information]. Figure 2 This disclosure provides a display panel, including an array substrate 10, a color filter substrate 20 disposed opposite to each other, and a liquid crystal layer LC located between the array substrate 10 and the color filter substrate 20; the liquid crystal cell thickness of the liquid crystal layer LC in the light-transmitting area of ​​the display panel satisfies the following: when the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz, the reciprocal of the refresh rate of the display panel and the liquid crystal cell thickness conform to a quadratic polynomial relationship.

[0068] The approach to determining the relationship between liquid crystal cell thickness and refresh rate provided in this embodiment is based on the following:

[0069] A higher refresh rate for a display panel means a smaller or faster response time is required. Response time is the time it takes for a liquid crystal display to react to an input signal, that is, the time it takes for a pixel to change from dark to bright or from bright to dark. The smaller the response time, the faster the response speed when switching images, and the smoother the image switching.

[0070] The formula for response time is as follows:

[0071]

[0072]

[0073] In equations (5) and (6):

[0074] τ r Rise time represents the time interval during which the brightness decreases from 90% to 10% (normal white mode) from the power-off state to the power-on state, or the time interval during which the brightness increases from 10% to 90% (normal black mode).

[0075] τ d The delay time represents the time interval during which the brightness reaches 10% of the maximum brightness during a power outage.

[0076] γ1: Viscosity coefficient of the liquid crystal material;

[0077] d: LCD cell thickness;

[0078] V: Driving voltage;

[0079] V th Threshold voltage;

[0080] Δε: Dielectric coefficient of liquid crystal material.

[0081] Let τ on =τ r +τ d If the refresh rate is f, then:

[0082] 1 / f=kτ on

[0083]

[0084] Right now:

[0085]

[0086] It can be seen that, under the premise of the same liquid crystal material and driving voltage, the response time τ on，off The refresh rate is directly proportional to the square of the LCD cell thickness d, while the refresh rate is inversely correlated with the square of d.

[0087] Based on the above theoretical derivation, liquid crystal cell thickness design, simulation, and data verification were performed. By integrating the data, the following fitting relationship was obtained when the refresh rate is within the range of [60Hz, 480Hz]:

[0088] 1 / f = C2 × d 2 + C1×d + C0 (9)

[0089] In the above formula, f is the refresh rate in Hz; d is the liquid crystal cell thickness in μm; the value range of C2 is [0.003, 0.004], the value range of C1 is [-0.02, -0.01], and the value range of C0 is [0.01, 0.02].

[0090] Optionally, the coefficients can be set to: C2 = 0.0038, C1 = -0.0127, C2 = 0.0125, which satisfies the following conditions:

[0091] 1 / f = 0.0038d 2 – 0.0127d + 0.0125 (10)

[0092] The coefficient of determination R of the fitting relationship in equation (10) 2 =0.9999, such as Figure 3 As shown; coefficient of determination R 2 The value of R reflects the degree of fit between the estimated value of the trend line and the corresponding actual data. When the square of R is equal to or close to 1, the reliability is the highest, and vice versa.

[0093] According to Equations (9) and (10), the display panel provided in this disclosure has a cell gap designed to fit a quadratic polynomial relationship between the reciprocal of the refresh rate and the cell gap when the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz. Compared with the conventional design of the cell gap based on TFT Pillow, color resist step difference, spacer height and liquid crystal amount, this significantly reduces the influence factor of the cell gap, which is conducive to reducing the design complexity of the cell gap and improving the design accuracy, thereby improving the design efficiency of liquid crystal display products and providing a new cell gap design benchmark.

[0094] Optionally, for high refresh rate display products with a refresh rate f greater than 480Hz, such as [480Hz, 1000Hz], the range of the liquid crystal cell thickness is [1.044μm, 1.6μm], with the trend being that the higher the refresh rate, the smaller the liquid crystal cell thickness. In some embodiments, while meeting the refresh rate requirements, a higher liquid crystal cell thickness can also be selected; the higher the liquid crystal cell thickness, the higher the product transmittance. Furthermore, the liquid crystal cell thickness can also be adjusted according to the customer's gray-to-gray response time (GTG) requirements. According to the correspondence between liquid crystal cell thickness and refresh rate in the embodiments of this disclosure, the range of the liquid crystal cell thickness (Cell Gap) is 1.044μm to 3.8μm.

[0095] The correspondence between liquid crystal cell thickness and refresh rate provided in this disclosure can be used for ordinary liquid crystal display panels as well as XPS liquid crystal display panels. Taking XPS liquid crystal display products used in notebook computers as an example, the common refresh rate range is 60Hz to 360Hz, and ≥120Hz is considered a high refresh rate product. The liquid crystal cell thickness requirement for high refresh rate products is also related to the response time. When the liquid crystal material is determined, the faster the response time and the higher the refresh rate, the lower the liquid crystal cell thickness.

[0096] The cell thickness design of some XPS LCD products is as follows: 60Hz notebook products have a cell thickness of approximately 3.6μm, 90Hz notebook products have a cell thickness of approximately 3.18μm, 120Hz notebook products have a cell thickness of approximately 2.92μm, 240Hz notebook products have a cell thickness of approximately 2.4μm (GTG is 3ms), 360Hz notebook products have a cell thickness of approximately 2.0μm (GTG is 2ms), and 480Hz notebook products have a cell thickness of approximately 1.6μm (GTG is 1ms).

[0097] To ensure sufficient liquid crystal margin (LC margin) for the display, XPS LCD panels can have a main spacer (Main PS) and a sub spacer (Sub PS) in the PS layer on both the TFT and CF sides, respectively. The Sub PS is thinner or lower in height. However, if the Sub PS is too thin or too low, problems such as missing Sub PS, morphological deformation, or molding failure may occur. Figure 4 As shown. To avoid missing Sub PS (Sub-PS), its height should be controlled above 0.5μm. Therefore, the cell gap (PS) thickness cannot be reduced indefinitely; if it is too small, problems such as missing PS can easily occur during manufacturing. Currently, ultra-low PSH (Physical Sequence Height) technology can reduce the Main PS height of XPS products to 0.9μm while ensuring no missing Sub PS.

[0098] For XPS LCD panels, on the one hand, PS layers are designed on the TFT side and CF side respectively, reducing the height of the PS layer on one side. On the other hand, due to the increase in refresh rate, it is required to further reduce the thickness of the LCD cell, which requires further reduction of the height of the PS layer on one side. As mentioned above, if the height of the PS layer is too low, the process capability cannot meet the requirements, and PS defects are likely to occur, which will also limit the design of the LCD cell thickness.

[0099] To address the above issues, in some embodiments, please refer to Figure 5 The provided liquid crystal display panel with an XPS structure employs a combination of a main spacer (Main PS) and a sub spacer (Sub PS) to form a spacer layer, including:

[0100] The array substrate 10 includes a first substrate 11 and a first spacer layer PS1, the first spacer layer PS1 being disposed on the side of the first substrate 11 near the color filter substrate 20; the color filter substrate 20 includes a second substrate 21 and a second spacer layer PS2, the second spacer layer PS2 being disposed on the side of the second substrate 21 near the array substrate 10; the first spacer layer PS1 includes at least one first main spacer Main PS1 and a plurality of first sub-spacers Sub PS1, the first main spacer Main PS1 and the first sub-spacers Sub PS1 being spaced apart; the second spacer layer PS2 includes at least one second main spacer Main PS2 and a plurality of second sub-spacers Sub PS2, the second main spacer Main PS2 and the second sub-spacers Sub PS2 being spaced apart; the first main spacer Main PS1 and the second main spacer Main PS2 abut against each other, and the first sub-spacers Sub PS1 and the second sub-spacers Sub PS2 are disposed opposite to each other.

[0101] In some embodiments, the first substrate 11 is the base of the array substrate 10, also known as the substrate substrate or TFT substrate, and can be a transparent glass substrate (TFT Glass); the second substrate 21 is the base of the color filter substrate 20, also known as the CF substrate, and can also be a transparent glass substrate (CF Glass).

[0102] Optional structural designs for the primary and secondary spacers include:

[0103] ① When the PS step is formed on the color filter substrate 20 side (CF), such as Figure 5As shown, the spacers on the TFT side are of equal height, that is, the first main spacer Main PS1 and the first sub-spacer Sub PS1 are of equal height. The first main spacer Main PS1 can be designed to be thicker than the first sub-spacer Sub PS1. The spacers on the CF side are of unequal height, with the second sub-spacer Sub PS2 being lower than the second main spacer Main PS2. After the LCD panel is assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are abutted against each other, while the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are positioned opposite each other.

[0104] ② When the PS step is formed on the array substrate 10 side (TFT), the spacers on the CF side are of equal height, that is, the second main spacer Main PS2 and the second sub-spacer Sub PS2 are of equal height, and the second main spacer Main PS2 is thicker than the second sub-spacer Sub PS2; the spacers on the TFT side are of unequal height, and the height of the first sub-spacer Sub PS1 is lower than the height of the first main spacer Main PS1; after the liquid crystal panel is assembled, the first main spacer Main PS1 and the second main spacer Main PS2 are abutted against each other, and the first sub-spacer Sub PS1 and the second sub-spacer Sub PS2 are opposite to each other.

[0105] Taking the first main spacer (Main PS1) and the first secondary spacer (Sub PS1) as examples, the more robust first main spacer (Main PS1) means that, in the planar direction of the display panel, the cross-sectional area of ​​the first main spacer (Main PS1) is larger than that of the first secondary spacer (Sub PS1). Both the first main spacer (Main PS1) and the first secondary spacer (Sub PS1) can be designed as columnar structures. The cross-section of the columnar structure can be triangular, polygonal, circular, or elliptical, etc., and can be designed according to actual needs. The first main spacer (Main PS1) and the first secondary spacer (Sub PS1) are spaced apart; multiple first secondary spacers (Sub PS1) can be arranged between two first main spacers (Main PS1), such as... Figure 6 As shown; or multiple first main spacers (Main PS1) are arranged between two first secondary spacers (SubPS1). The former is preferred. The ratio of the number of first main spacers (Main PS1) to the number of first secondary spacers (Sub PS1) can be determined according to actual needs. For example, the ratio of the number of first main spacers (Main PS1) to the number of first secondary spacers (Sub PS1) can be set to 1:10 to 300. This disclosure does not limit this ratio.

[0106] When the shapes of the first main spacer Main PS1, the first secondary spacer Sub PS1, the second main spacer Main PS2, and the second secondary spacer Sub PS2 are designed according to the above scheme, the liquid crystal margin of the liquid crystal display panel can be further increased.

[0107] In some embodiments, the first main spacer Main PS1 and the first secondary spacer Sub PS1 on the TFT side, and the second main spacer Main PS2 and the second secondary spacer Sub PS2 on the CF side can all be strip-shaped, and their arrangement directions can be intersecting each other. For example, the opposing first main spacer Main PS1 and the second main spacer Main PS2 can be arranged in a cross-shaped arrangement that is perpendicular to each other or a non-cross-shaped arrangement that is not perpendicular to each other. The opposing first secondary spacer Sub PS1 and the second secondary spacer Sub PS2 can be arranged in a cross-shaped arrangement or a non-cross-shaped arrangement. This can further optimize the PS mura problem and improve the panel strength.

[0108] The above scheme provides an overall design of the spacer structure in the XPS liquid crystal display panel. The film structure on the TFT side and CF side will be further described below.

[0109] For the film structure on the TFT side, please refer to some embodiments. Figure 7 The schematic diagram of the stacked structure of the display panel shown indicates that the array substrate 10 also includes a color resist layer (CRL) and an organic film layer (ORG) stacked on the first substrate 11. The organic film layer ORG is located between the color resist layer CRL and the first spacer layer PS1. In other words, the array substrate 10 provided here is a COA substrate (Color Filter on Array), which integrates the organic film layer ORG and the color resist layer CRL on the array substrate 10. The advantage of the COA substrate is that it eliminates light leakage problems caused by cell-to-cell bonding, effectively reducing the width of the black matrix layer BM, thereby increasing the pixel aperture ratio and thus improving the transmittance of the display panel.

[0110] For COA substrates, please refer to [link / reference]. Figure 7In the thickness direction, the display panel includes a gate metal layer (Gate), a gate dielectric layer (GI), an amorphous silicon active layer (a-Si), a source / drain metal layer (SD), and a passivation layer (PVX) sequentially stacked on a first substrate 11 (TFT substrate). These film layer structures form thin-film transistors located in display regions A-A' and peripheral regions B-B'. Then, a color resist layer (CRL) and an organic film layer (ORG) are sequentially stacked on the passivation layer. Specifically, the color resist layer CRL located in the blue sub-pixel region is a blue color resist layer B-CRL, the color resist layer CRL located in the green sub-pixel region is a green color resist layer G-CRL, and the color resist layer CRL located in the red sub-pixel region is a red color resist layer R-CRL. The color resist layer CRL and the organic film layer ORG constitute a color filter layer, achieving both light filtering and planarization of the opening region. A first spacer layer PS1 on the TFT side is disposed on the side of the organic film layer ORG closest to the color filter substrate 20. Additionally, an ITO transparent electrode is also stacked on the organic film layer ORG.

[0111] Since the RGB color filter layer in the COA substrate is set on one side of the TFT substrate and is planarized by the organic film layer ORG, the position of the spacer layer and the position of the pixel opening area on the TFT side can be ignored due to pixel step difference.

[0112] It should be noted that the COA substrate integrates the color resist layer CRL onto the TFT side of the array substrate 10. Although the color filter layer is no longer provided on the color filter substrate 20 side, for the sake of convenience in describing and distinguishing the array substrate 10 on the TFT side, it will still be referred to as the CF side in the following content.

[0113] In some embodiments, please refer to Figure 8AAn organic membrane layer (ORG) has a first groove 12, a first sub-spacer (SubPS1) is disposed within the first groove 12, and a first main spacer (Main PS1) is disposed on the organic membrane layer ORG outside the first groove 12. The first groove 12 can be a blind hole formed by cutting grooves in the organic membrane layer ORG, or it can be a through-hole penetrating the organic membrane layer ORG. Spacer material is then deposited, forming the first sub-spacer (SubPS1) within the through-hole or blind hole, and the first main spacer (Main PS1) on the organic membrane layer ORG outside the through-hole or blind hole. By forming a first sub-spacer Sub PS1 within the first groove 12, on the one hand, the top surface of the first sub-spacer Sub PS1 is lower than the top surface of the first main spacer Main PS1 in the vertical direction of the array substrate 10, thereby creating a certain PS step difference between the first main spacer Main PS1 and the first sub-spacer Sub PS1, such as 0.45μm to 0.55μm, with a preferred value of 0.5μm. When this step difference is met, a normal mask can be used instead of a halftone mask to manufacture the first spacer layer PS1, thus saving mask manufacturing costs. On the other hand, while maintaining the PS step difference and further reducing the thickness of the liquid crystal cell, it ensures that the height of the first sub-spacer Sub PS1 is not too low, avoiding the problem of PS missing due to the first sub-spacer Sub PS1 being too low.

[0114] In some embodiments, please refer to Figure 8B More first grooves 12 can be formed on the organic film layer ORG, and both the first main spacer Main PS1 and the first secondary spacer Sub PS1 can be placed in the first grooves 12, forming a PS step difference between them. At this time, the second main spacer Main PS2 and the second secondary spacer Sub PS2 on the CF side can be designed with equal or nearly equal height. This also allows the use of a normal mask instead of a halftone mask to manufacture the first spacer layer PS1, further reducing the liquid crystal cell thickness.

[0115] For the membrane structure on the CF side, the following two design schemes can be adopted:

[0116] Option 1: Use the black matrix layer BM to form the second spacer layer PS2.

[0117] Please see Figure 7 and Figure 9The second main spacer Main PS2 and the second sub spacer Sub PS2 include a black matrix layer BM. The color filter substrate 20 includes a planar protective layer OC (over coat) covering the black matrix layer BM and the second substrate 21. In the direction perpendicular to the second substrate 21, the thickness of the black matrix layer BM is greater than the thickness of the planar protective layer OC covering the second substrate 21. The planar protective layer OC in the second main spacer Main PS2 abuts against the first main spacer Main PS1.

[0118] Common XPS display panel designs involve depositing a PS material layer on both the TFT and CF sides to form spacer layers. However, the display panel provided in Solution 1 only requires depositing a PS material layer on the TFT side to fabricate the first spacer layer PS1 using a patterning process. On the CF side, a thicker black matrix material is deposited on the second substrate 21 opposite to the first spacer layer PS1 to form the second spacer layer PS2. The black matrix layer BM and the planar protective layer OC, which abuts against the first main spacer Main PS1, form the second main spacer Main PS2. The black matrix layer BM and the planar protective layer OC, which is opposite to the first sub-spacer Sub PS1, form the second sub-spacer Sub PS2. The remaining black matrix layer BM can be used normally as a light-shielding structure. Therefore, Solution 1 eliminates the need to deposit PS material on the CF side to form the second spacer layer PS2, thus saving a PS mask process, reducing manufacturing costs, and increasing production efficiency.

[0119] Figure 9 The membrane structure of the second main spacer (Main PS2) and the second sub-spacer (Sub PS2) formed by the black matrix layer (BM) and the planar protective layer (OC) is shown. The height of the second spacer layer (PS2) on the CF side can be adjusted by the thickness of the black matrix layer (BM) and the thickness of the planar protective layer (OC).

[0120] In some embodiments, the second main spacer Main PS2 and the second sub spacer Sub PS2, formed using the black matrix layer BM and the planar protective layer OC, can be of equal or unequal height, depending on whether the PS step is formed on the TFT side or the CF side. Optionally, the sum of the thicknesses of the black matrix layer BM and the planar protective layer OC in the second main spacer Main PS2 after cell alignment should not deviate from the height of the first main spacer Main PS1 after cell alignment by more than 20%, i.e., the first main spacer Main PS1 and the second main spacer Main PS2 can be designed with equal or approximately equal height.

[0121] Considering that the first main spacer Main PS1, formed by PS material deposition, will be compressed after cell alignment, while the black matrix layer BM will hardly be compressed, for the XPS combined with COA liquid crystal display panel of Scheme 1, the following condition must be met: the product of the height of the first main spacer Main PS1 before cell alignment and the compression rate after cell alignment, plus the sum of the height of the second main spacer Main PS2, equals the liquid crystal cell thickness, i.e.:

[0122] d=H1×k+H t (11)

[0123] In the above formula, d is the thickness of the liquid crystal cell, H1 is the free height of the first main spacer Main PS1 in front of the cell, and H t The height of the second main spacer, Main PS2, is equal to the height of the black matrix layer BM after the cassette, or the sum of the heights of the black matrix layer BM and the flat protective layer OC after the cassette. k is the compression ratio of the first main spacer, Main PS1, after the cassette. The value of k ranges from 0.86 to 0.88, such as 0.87.

[0124] From equation (11), it can also be seen that the sum of the free height of the first main spacer Main PS1 on the TFT side before cell assembly or after disassembly, and the height of the second main spacer Main PS2, is greater than the thickness d of the liquid crystal cell, i.e., the thickness of the opening area. Additionally, as... Figure 7 As shown, the first main spacer on the TFT side, Main PS1, is positioned above the TFT device in the pixel area, which helps to reduce the thickness of the opening area.

[0125] In some embodiments, the height PSH(H1×k) of the first main spacer Main PS1 on the TFT side after being compressed by the cell alignment is equal to or approximately equal to the height Ht of the second main spacer Main PS2 on the CF side, to ensure that the height of the PS layer on one side is not too small, resulting in PS loss. "Approximately equal" means that the deviation between the height PSH1 of the first main spacer Main PS1 after cell alignment and the height Ht of the second main spacer Main PS2 after cell alignment does not exceed 10%.

[0126] It should be noted that if the height PSH of the first main spacer Main PS1 on the TFT side is ≥0.9μm, and is consistent with the height of the second main spacer Main PS2 (the sum of the thicknesses of the black matrix layer BM and the planarization protective layer OC), then the first main spacer Main PS1 and the first sub-spacer Sub PS1 can have different heights, forming a PS step difference on the TFT side. Since the COA product can planarize the array substrate 10 through the color resist layer CRL and the organic film layer ORG, the position of the first spacer layer PS1 and the pixel opening area on the TFT side can disregard the pixel step difference. In this case, the cell gap thickness can be controlled to be no less than 1.56μm.

[0127] Option 2: Deposit PS material to form a second septum layer PS2.

[0128] Please see Figure 10 The color filter substrate 20 includes a black matrix layer BM and a planarization protective layer OC disposed on the side of the second substrate 21 near the array substrate 10. The black matrix layer BM is located between the second substrate 21 and the planarization protective layer OC. A second groove 22 is provided on the planarization protective layer OC. A second sub-spacer Sub PS2 is disposed in the second groove 22, and a second main spacer Main PS2 is disposed on the planarization protective layer OC outside the second groove 22.

[0129] In some embodiments, the width or area of ​​the black matrix layer BM is greater than that of the second spacer layer PS2 on the CF side. The orthographic projection of the second groove 22 on the second substrate 21 lies within the orthographic projection of the black matrix layer BM on the second substrate 21, that is, the second groove 22 is located above the black matrix layer BM. The second groove 22 can be a blind via formed by trenching in the planar protective layer OC, or it can be a through-hole penetrating the planar protective layer OC, which can be designed according to actual needs. Spacer material is deposited in the second groove 22 to form a second sub-spacer Sub PS2. The orthographic projection of the second sub-spacer Sub PS2 on the second substrate 21 lies within the orthographic projection of the second groove 22 on the second substrate 21.

[0130] In some embodiments, in the vertical direction or thickness direction of the color filter substrate 20, the top surface of the second sub-spacer Sub PS2 located in the second groove 22 is lower than the top surface of the second main spacer Main PS2. That is, the upper surface of the second sub-spacer Sub PS2 is lower than the upper surface of the surrounding second main spacer Main PS2, and the height difference between the two is approximately 0.45 μm to 0.55 μm, thereby forming a PS step on the color filter substrate 20 side. A preferred value can be controlled at 0.5 μm. This eliminates the need for a Halftone Mask and allows the use of a Normal Mask to manufacture the spacers on the CF side, saving mask manufacturing costs. Furthermore, it allows for the design of the second main spacer Main PS2 and the second sub-spacer Sub PS2 to be lower, further reducing the liquid crystal cell thickness while avoiding PS defects caused by the excessively low height of the second sub-spacer Sub PS2. Studies have shown that PS defects are easily generated when the height of the second sub-spacer Sub PS2 is less than or equal to 0.5 μm. It should be noted that since the PS step is formed on the side of the color filter substrate 20, the top surface of the first main spacer Main PS1 and the top surface of the first sub spacer Sub PS1 are designed to be at the same height in the vertical direction or thickness direction on the side of the array substrate 10.

[0131] For a photomicrograph of the second septum Sub PS2, please refer to [the image]. Figure 11 The second sub-spacer, Sub PS2, "stands" within a blind hole or groove in the flat protective layer OC. The depth of the groove can be adjusted according to design requirements to ensure that the top surface of Sub PS2 is approximately 0.5 μm lower than the top surface of the surrounding second main spacer, Main PS2, thus creating a PS step difference. Based on this, the actual height of Sub PS2 can be designed to be equal to the actual height of Main PS2 to ensure that Sub PS2 is not missing. In this case, the minimum height between Main PS2 and Sub PS2 can be reduced to 0.6 μm, thereby significantly reducing the liquid crystal cell thickness.

[0132] When the heights of the first main spacer Main PS1 and the second main spacer Main PS2 are the same, the cell thickness CellGap satisfies:

[0133] d = H1 × 2 × PS compression ratio (12)

[0134] In equation (12), H1 is the free height of the first main spacer Main PS1 on the TFT side before the cell assembly, and is equal to the free height of the second main spacer Main PS2 before the cell assembly compression.

[0135] At this point, if the PS compression ratio is 0.87, then d = 0.6 × 2 × 0.87 = 1.044 μm. This allows the liquid crystal cell thickness d to be controlled to a minimum of 1.044 μm, i.e., d ≥ 1.044 μm.

[0136] In summary, the XPS-based liquid crystal display panel provided in the above embodiments has the following characteristics:

[0137] 1) The color resist layer CRL is fabricated on one side of the array substrate 10 and planarized by combining it with the organic film layer ORG. The influence of pixel segment difference does not need to be considered when designing the liquid crystal cell thickness, and there is no influence of TFT Pillow. Therefore, the influence factor of liquid crystal cell thickness Cell Gap is simplified, and the liquid crystal cell thickness can be controlled at ≥1.56μm.

[0138] 2) A first groove 12 is formed on the organic film layer ORG on the TFT side, and a first sub-spacer Sub PS1 is formed within the first groove 12. Alternatively, a second groove 22 is formed on the planar protective layer OC on the CF side, and a second sub-spacer Sub PS2 is formed within the second groove 22. This achieves the following: when the actual heights of the first main spacer Main PS1 and the first sub-spacer Sub PS1 on the TFT side are equal or similar, and the actual heights of the second main spacer Main PS2 and the second sub-spacer Sub PS2 on the CF side are equal or similar, a PS step is formed between the main spacer Main PS and the sub-spacer Sub PS by means of the first groove 12 or the second groove 22. On the one hand, a normal mask can be used instead of a halftone mask to prepare the PS layer, thereby saving mask manufacturing costs. On the other hand, the main spacer Main PS and the sub-spacer Sub PS can be designed to be lower, which can further reduce the thickness of the liquid crystal cell while avoiding PS loss caused by the excessively low height of the Sub PS. This achieves the goal of reducing the thickness of the liquid crystal cell. The gap was reduced from 1.5μm to 1.044μm, enabling XPS products to break through existing limitations and be designed towards higher refresh rates.

[0139] The above solution provides a structural design for the COA substrate. For ordinary display panels with the color resist layer (CRL) placed on the CF side, the following design can be adopted:

[0140] In some embodiments, please refer to Figure 12The color filter substrate 20 includes a black matrix layer BM and a color resist layer CRL disposed on the second substrate 21 in the same layer, and a planarization protective layer OC covering the black matrix layer BM and the color resist layer CRL; a second main spacer Main PS2 and a second secondary spacer Sub PS2 are disposed on the color resist layer CRL, and their orthogonal projection on the second substrate 21 is located within the orthogonal projection of the black matrix layer BM on the second substrate 21; in the direction perpendicular to the second substrate 21, the sum of the thicknesses of the black matrix layer BM and the planarization protective layer OC is less than the sum of the thicknesses of the color resist layer CRL and the planarization protective layer OC.

[0141] The black matrix layer BM is disposed in the non-transparent area of ​​the color filter substrate 20, the color resist layer CRL is disposed in the transparent area of ​​the color filter substrate 20, and the second main spacer Main PS2 and the second secondary spacer Sub PS2 are disposed on the flat protective layer OC located directly above the black matrix layer BM. The bottom area of ​​the second main spacer Main PS2 and the second secondary spacer Sub PS2 is smaller than the area of ​​the black matrix layer BM to avoid affecting light transmission.

[0142] This solution does not involve cutting grooves in the planarization protective layer OC. Instead, it thins the total thickness of the black matrix layer BM and the planarization protective layer OC at the second main spacer (Main PS2) and the second sub-spacer (Sub PS2), making it thinner than the total thickness of the color resist layer CRL and the planarization protective layer OC in the surrounding area. This reduces the overall height of the second spacer layer PS2, thereby reducing the thickness of the liquid crystal cell, and also saves one groove cutting process.

[0143] In some embodiments, the thickness of the flat protective layer OC located directly above the black matrix layer BM is greater than the thickness of the flat protective layer OC located directly above the color resist layer CRL outside the BM region. The second main spacer Main PS2 and the second sub spacer Sub PS2 are disposed on the flat protective layer OC located directly above the black matrix layer BM, which makes the structure under the spacers more stable and less prone to peeling.

[0144] Optionally, a second main spacer (Main PS2) and a second sub-spacer (Sub PS2) can be installed by creating a groove in the flat protective layer OC. This can also reduce the overall height of the second spacer layer PS2, thereby reducing the thickness of the liquid crystal cell.

[0145] It should be noted that the structure used in this case has alignment layers on both the upper and lower sides of the liquid crystal layer LC. The alignment layers and the liquid crystal layer are in direct contact. Since an alignment layer has a uniform thickness, it is not shown in the figure in this case, and its thickness is not considered. Its existence is ignored in the description of the embodiment, but this does not mean that it does not actually exist.

[0146] Secondly, please refer to Figure 13This disclosure provides a display device, including the display panel provided in the first aspect embodiment. The display device can be an electronic device with a display screen, such as a desktop computer monitor, an all-in-one computer, a laptop computer, a tablet computer, a conference all-in-one machine, or a smartphone.

[0147] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0148] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A display panel, characterized in that, The display panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate; the thickness of the liquid crystal cell in the light-transmitting area of ​​the display panel satisfies the following: When the refresh rate of the display panel is greater than or equal to 60Hz and does not exceed 480Hz, the reciprocal of the refresh rate of the display panel and the thickness of the liquid crystal cell conform to a quadratic polynomial relationship. The liquid crystal cell thickness and the refresh rate satisfy the following: 1 / f=C2×d 2 + C1×d + C0; In the above formula, f is the refresh rate in Hz; d is the thickness of the liquid crystal cell in μm; the value of C2 ranges from 0.003 to 0.004, the value of C1 ranges from -0.02 to -0.01, and the value of C0 ranges from 0.01 to 0.

02.

2. The display panel as described in claim 1, characterized in that, When the refresh rate of the display panel is greater than 480Hz and not more than 1000Hz, the thickness of the liquid crystal cell ranges from 1.044μm to 1.6μm.

3. The display panel as described in claim 1, characterized in that, The array substrate includes a first substrate and a first spacer layer, the first spacer layer being disposed on the side of the first substrate near the color filter substrate; the color filter substrate includes a second substrate and a second spacer layer, the second spacer layer being disposed on the side of the second substrate near the array substrate. The first spacer layer includes at least one first primary spacer and a plurality of first secondary spacers, with the first primary spacers and the first secondary spacers spaced apart; the second spacer layer includes at least one second primary spacer and a plurality of second secondary spacers, with the second primary spacers and the second secondary spacers spaced apart; the first primary spacer abuts against the second primary spacer, and the first secondary spacers and the second secondary spacers are disposed opposite to each other.

4. The display panel as described in claim 3, characterized in that, The array substrate further includes a color resist layer and an organic film layer stacked on the first substrate, wherein the organic film layer is located between the color resist layer and the first spacer layer.

5. The display panel as described in claim 4, characterized in that, The organic film layer has a first groove, the first secondary spacer is disposed in the first groove, and the first primary spacer is disposed on the organic film layer outside the first groove.

6. The display panel as described in claim 3, characterized in that, The second primary spacer and the second secondary spacer include a black matrix layer, and the color filter substrate includes a planar protective layer covering the black matrix layer and the second substrate; in the direction perpendicular to the second substrate, the thickness of the black matrix layer is greater than the thickness of the planar protective layer covering the second substrate, and the planar protective layer on the second primary spacer abuts against the first primary spacer.

7. The display panel as described in claim 6, characterized in that, The sum of the thicknesses of the black matrix layer and the flat protective layer in the second primary spacer after cassette assembly does not deviate by more than 20% from the height of the first primary spacer after cassette assembly.

8. The display panel as described in claim 3, characterized in that, The color filter substrate includes a black matrix layer and a planarization protective layer disposed on the side of the second substrate near the array substrate, wherein the black matrix layer is located between the second substrate and the planarization protective layer; The flat protective layer is provided with a second groove, the second secondary spacer is disposed in the second groove, and the second primary spacer is disposed on the flat protective layer outside the second groove.

9. The display panel as described in claim 3, characterized in that, The color filter substrate includes a black matrix layer and a color resist layer disposed on the same layer of the second substrate, and a planar protective layer covering the black matrix layer and the color resist layer; the second main spacer and the second secondary spacer are disposed on the color resist layer, and their orthogonal projections on the second substrate are located within the orthogonal projection of the black matrix layer on the second substrate; In the direction perpendicular to the second substrate, the sum of the thicknesses of the black matrix layer and the planar protective layer is less than the sum of the thicknesses of the color resist layer and the planar protective layer.

10. The display panel as claimed in claim 3, characterized in that, In the vertical direction of the color filter substrate, the top surface of the second sub-spacer is lower than the top surface of the second main spacer, and the height difference is 0.45μm to 0.55μm; or, in the vertical direction of the array substrate, the top surface of the first sub-spacer is lower than the top surface of the first main spacer, and the height difference is 0.45μm to 0.55μm.

11. The display panel as claimed in claim 3, characterized in that, The product of the height of the first primary spacer before cell alignment and the compression ratio after cell alignment, plus the sum of the height of the second primary spacer after cell alignment, equals the thickness of the liquid crystal cell. The compression ratio ranges from 0.86 to 0.

88.

12. The display panel as claimed in claim 3, characterized in that, The deviation between the height of the first primary spacer after alignment and the height of the second primary spacer after alignment shall not exceed 10%.

13. The display panel as claimed in claim 3, characterized in that, The first primary spacer is at the same height as the first secondary spacer, and the second secondary spacer is at a lower height than the second primary spacer; or... The second secondary septum and the second primary septum are at the same height, and the height of the first secondary septum is lower than that of the first primary septum.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

Images