Driving circuit structure, array substrate, display device, and preparation method of array substrate

Abstract

A driving circuit structure, an array substrate, a display device, and a method for fabricating the array substrate are provided. The driving circuit structure includes: a substrate; an initial signal line located on the substrate; a clock signal line located on the substrate; and a first insulating layer located on the side of the initial signal line away from the substrate and including a first via. The initial signal line is connected to the clock signal line via the first via.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving circuit structure, an array substrate, a display device, and a method for fabricating the array substrate. Background Technology

[0002] In the field of display technology, such as display panels, pixel arrays typically include multiple rows of gate lines and multiple columns of interleaved data lines. Driving the gate lines can be achieved through bonded integrated driver circuits. In recent years, with the continuous improvement of amorphous silicon thin-film transistor (TFT) or oxide thin-film transistor (OST) fabrication processes, it is also possible to directly integrate the gate line driving circuit onto the array substrate to form a GOA (Gate Driver On Array) for driving the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide scan signals to multiple rows of gate lines, thereby controlling the opening and closing of the multiple rows of gate lines. Currently, more and more display panels are adopting GOA technology to drive the gate lines. GOA technology helps to achieve narrow bezel designs in display panels and can reduce the production cost of display panels. Summary of the Invention

[0003] According to one aspect of this disclosure, a driving circuit structure is provided, comprising: a substrate; an initial signal line located on the substrate; a clock signal line located on the substrate; and a first insulating layer located on the side of the initial signal line away from the substrate and including a first via. The initial signal line is connected to the clock signal line via the first via.

[0004] In some embodiments, the drive circuit structure further includes: a second insulating layer located on the side of the first insulating layer away from the substrate and including a second via; and a protective pad that at least fills the second via. The orthographic projection of the protective pad onto the substrate at least partially overlaps with the orthographic projection of the first via onto the substrate.

[0005] In some embodiments, the clock signal line is located on the side of the initial signal line away from the substrate, and a conductive portion is provided in the first via, one end of the conductive portion being directly connected to the initial signal line, and the other end of the conductive portion being directly connected to the clock signal line.

[0006] In some embodiments, the orthographic projection of the initial signal line on the substrate partially overlaps with the orthographic projection of the clock signal line on the substrate to form an overlap region, and the orthographic projection of the first via on the substrate falls within the overlap region.

[0007] In some embodiments, the initial signal line and the clock signal line are located on the same layer, and the orthographic projection of the initial signal line on the substrate does not overlap with the orthographic projection of the clock signal line on the substrate.

[0008] In some embodiments, the driving circuit structure further includes: a first trace group including at least one initial signal line extending along a first direction; a second trace group including at least one clock signal line extending along the first direction, wherein the orthographic projection of the second trace group on the substrate does not overlap with the orthographic projection of the first trace group on the substrate; and at least one first connection line extending along a second direction intersecting the first direction and located on the side of the first insulating layer away from the substrate. At least one clock signal line in the second trace group is connected to any one of the initial signal lines in the first trace group via the first connection line.

[0009] In some embodiments, the clock signal line includes a cutout portion and a solid portion, the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projections of the first connecting line and the first via on the substrate do not overlap with the orthographic projection of the cutout portion on the substrate.

[0010] In some embodiments, the driving circuit structure further includes at least one second connection line extending along the second direction. Each clock signal line in the second trace group is connected to a corresponding second connection line, and the orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the second connection line on the substrate.

[0011] In some embodiments, the first insulating layer further includes a plurality of third vias, wherein each clock signal line in the second trace group is connected to a corresponding second connection line via one of the plurality of third vias.

[0012] In some embodiments, a clock signal line in the second trace group has two cut-out openings. One of the at least one first connecting lines is connected to the clock signal line with two cut-out openings. The orthographic projection of this first connecting line on the substrate partially overlaps with the orthographic projection of the clock signal line with two cut-out openings on the substrate. The overlapping portion is the first orthographic projection. The orthographic projection of one of the plurality of third vias on the substrate is the second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line with two cut-out openings on the substrate. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut-out openings on the substrate.

[0013] In some embodiments, the first connection line includes a first end and a second end opposite to each other, the first end of the first connection line is connected to any initial signal line in the first trace group via the first via, and the second end of the first connection line is connected to any clock signal line in the second trace group via the first via.

[0014] In some embodiments, the second trace group includes a plurality of clock signal lines arranged in parallel along the first direction, the first connecting line crosses the plurality of clock signal lines in the second trace group along the second direction, the first connecting line includes a first end and a second end opposite to each other, the first end of the first connecting line is connected to any initial signal line in the first trace group via the first via, and the orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line furthest from the initial signal line among the plurality of clock signal lines in the second trace group on the substrate.

[0015] In some embodiments, one of the at least one first connection line is fused to the clock signal line having two cutouts.

[0016] In some embodiments, the driving circuit structure further includes a first power signal line and a second power signal line extending along the first direction. The first power signal line and the second power signal line are located on the side of the second trace group away from the first trace group, and the orthographic projection of the cut opening and welded area of ​​the clock signal line on the substrate does not overlap with the orthographic projection of the first power signal line and the second power signal line on the substrate.

[0017] In some embodiments, one of the at least one first connection lines is connected to the clock signal line having two cut-out openings via the first via.

[0018] In some embodiments, the first via includes a first opening and a second opening opposite each other, the first opening and the second opening being circular or elliptical in shape, and the longitudinal section of the first via being rectangular or inverted trapezoidal, the longitudinal section being parallel to the thickness direction of the substrate.

[0019] According to another aspect of this disclosure, an array substrate is provided, which includes the driving circuit structure described in any of the preceding embodiments.

[0020] In some embodiments, the array substrate further includes: a first conductive layer located on the same layer as the initial signal line; a second conductive layer located on the side of the first insulating layer away from the substrate, the first conductive layer being connected to the second conductive layer through a conductive portion in the first via; a second insulating layer located on the side of the second conductive layer away from the substrate and including a fourth via; and a third conductive layer located on the side of the second insulating layer away from the substrate and connected to the second conductive layer via the fourth via.

[0021] In some embodiments, the second insulating layer further includes a fifth via, the third conductive layer fills the fourth via and the fifth via, and the depth of the fifth via is greater than the depth of the fourth via.

[0022] According to another aspect of this disclosure, a display device is provided, which includes an array substrate described in any of the preceding embodiments.

[0023] In some embodiments, the display device includes a display area and a peripheral area disposed around the display area, wherein the driving circuit structure is arranged in the peripheral area.

[0024] According to another aspect of this disclosure, a method for fabricating an array substrate is provided, comprising: providing a substrate; forming a plurality of initial signal lines on the substrate; forming a plurality of clock signal lines on the substrate; and forming a first insulating layer including a plurality of first vias on a side of the initial signal lines away from the substrate, wherein the initial signal lines are connected to the clock signal lines via the first vias.

[0025] In some embodiments, the initial signal line, the clock signal line, and the first insulating layer are formed using different photomasks having a first size, such that the array substrate has a second size that is different from the first size.

[0026] In some embodiments, the first dimension is larger than the second dimension, and the array substrate having the second dimension has a strip shape.

[0027] In some embodiments, the first size is 65 inches and the second size is 58.5 inches.

[0028] In some embodiments, forming a plurality of initial signal lines, a plurality of clock signal lines, and a first insulating layer on the substrate includes: depositing a first metal layer on the substrate and patterning the first metal layer by blocking a portion of a first mask having the first size to form the plurality of initial signal lines; depositing a first intermediate insulating layer on the side of the initial signal lines away from the substrate and patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form the first insulating layer including a plurality of first vias, the first vias exposing a portion of the surface of the initial signal lines; and depositing a second metal layer on the side of the first insulating layer away from the substrate and patterning the second metal layer by blocking a portion of a third mask having the first size to form the plurality of clock signal lines on the side of the first insulating layer away from the substrate, while forming a conductive portion in the first via, the initial signal lines being connected to the clock signal lines via the conductive portion.

[0029] In some embodiments, the method further includes: depositing a second intermediate insulating layer on the side of the clock signal line away from the substrate, patterning the second intermediate insulating layer by blocking a portion of the second mask to form a second insulating layer including a plurality of second vias, the second vias exposing a portion of the surface of the clock signal line; and depositing a third metal layer on the side of the second insulating layer away from the substrate, patterning the third metal layer by blocking a portion of a fourth mask having the first size to form a protective pad, the protective pad at least filling the second vias.

[0030] In some embodiments, forming a plurality of initial signal lines and a plurality of clock signal lines on the substrate includes: depositing a first metal layer on the substrate, and patterning the first metal layer by blocking a portion of a first mask having the first size to form a first trace group and a second trace group. The first trace group includes a plurality of initial signal lines arranged along a first direction, and the second trace group includes a plurality of clock signal lines arranged along the first direction. The orthographic projections of the first trace group and the second trace group on the substrate do not overlap.

[0031] In some embodiments, the method further includes: depositing a first intermediate insulating layer on the side of the initial signal line and the clock signal line away from the substrate; patterning the first intermediate insulating layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of sets of third vias, the first vias exposing portions of the surfaces of the initial signal line and the clock signal line, and the third vias exposing portions of the surface of the clock signal line; depositing a second metal layer on the side of the first insulating layer away from the substrate; patterning the second metal layer by blocking a portion of a third mask having the first size to form at least one first connecting line and at least one second connecting line arranged along a second direction, the first connecting line including opposing first and second ends, the first end of the first connecting line being via the first via... An aperture is connected to any initial signal line in the first trace group, and the second end of the first connecting line is connected to any clock signal line in the second trace group via the first via. Each clock signal line in the second trace group is connected to a corresponding second connecting line via one of the multiple sets of third vias. The second direction intersects the first direction. A second intermediate insulating layer is deposited on the side of the first connecting line and the second connecting line away from the substrate. The second intermediate insulating layer is patterned by blocking a portion of the second mask to form a second insulating layer including multiple second vias. A third metal layer is deposited on the side of the second insulating layer away from the substrate. The third metal layer is patterned by blocking a portion of the fourth mask having the first size to form a protective pad, which at least fills the second vias.

[0032] In some embodiments, the method further includes: cutting a clock signal line in the second trace group such that the clock signal line has two cut openings. The orthographic projection of a first connection line connected to the clock signal line with two cut openings on the substrate partially overlaps with the orthographic projection of the clock signal line with two cut openings on the substrate, the overlapping portion being the first orthographic projection; the orthographic projection of one group of the plurality of third vias on the substrate being the second orthographic projection, the second orthographic projection falling within the orthographic projection of the clock signal line with two cut openings on the substrate; and the first orthographic projection and the second orthographic projection being located between the orthographic projections of the two cut openings on the substrate.

[0033] In some embodiments, the method further includes: sequentially depositing a first intermediate insulating layer and a second metal layer on the side of the initial signal line and the clock signal line away from the substrate; patterning the first intermediate insulating layer and the second metal layer by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of sets of third vias, and at least one first connection line and at least one second connection line arranged along a second direction, wherein the first vias expose a portion of the surface of the initial signal line, the third vias expose a portion of the surface of the clock signal line, the first connection line crosses a plurality of clock signal lines in the second trace group along the second direction, the first connection line includes opposing first and second ends, and the first end of the first connection line is connected to any of the clock signal lines in the first trace group via the first via. An initial signal line is defined, wherein the orthographic projection of the second end of the first connection line onto the substrate falls within the orthographic projection of the clock signal line furthest from the initial signal line among the multiple clock signal lines of the second routing group onto the substrate; each clock signal line in the second routing group is connected to a corresponding second connection line via one of the multiple sets of third vias; the second direction intersects the first direction; a second intermediate insulating layer is deposited on the side of the first connection line and the second connection line away from the substrate; the second intermediate insulating layer is patterned by blocking a portion of a third mask having the first size to form a second insulating layer; and a third metal layer is deposited on the side of the second insulating layer away from the substrate; the third metal layer is patterned by blocking a portion of a fourth mask having the first size to form a pixel electrode.

[0034] In some embodiments, the method further includes: cutting a clock signal line in the second trace group to have two cut openings; and welding the clock signal line with the two cut openings to a first connecting line located between the two cut openings in a welding area. The orthographic projection of the welding area on the substrate is a first orthographic projection, and the orthographic projection of one group of the plurality of third vias on the substrate is a second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line with the two cut openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings on the substrate. Attached Figure Description

[0035] The exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings, in which:

[0036] Figure 1 A schematic diagram of the arrangement of a drive circuit is shown;

[0037] Figure 2 It shows Figure 1 A magnified view of a portion of region ①;

[0038] Figure 3 A top view and a cross-sectional view of a partial region of a drive circuit structure according to an embodiment of the present disclosure are shown;

[0039] Figure 4 A plan view of the circuit layout of a drive circuit structure according to an embodiment of the present disclosure is shown;

[0040] Figure 5 An electron microscope image of a first via according to an embodiment of the present disclosure is shown;

[0041] Figure 6 Electron microscope images of a local area of ​​the drive circuit structure according to an embodiment of the present disclosure during the fabrication stage are shown;

[0042] Figure 7 A top view of a local region of a drive circuit structure according to an embodiment of the present disclosure during the fabrication stage is shown under an electron microscope.

[0043] Figure 8 It shows along Figure 7 A cross-sectional view of the drive circuit structure taken by the cutting line;

[0044] Figure 9 A schematic diagram of the circuit layout of the drive circuit structure according to an embodiment of the present disclosure is shown;

[0045] Figure 10 It shows along Figure 9 A cross-sectional schematic diagram of a local area of ​​the drive circuit structure taken by the BB' line;

[0046] Figure 11 A cross-sectional schematic diagram of a partial region of a drive circuit structure is shown;

[0047] Figure 12 A schematic diagram of the circuit layout of the drive circuit structure according to an embodiment of the present disclosure is shown;

[0048] Figure 13 A schematic diagram of the circuit layout of the drive circuit structure according to an embodiment of the present disclosure is shown;

[0049] Figure 14 A schematic diagram of a partial region of an array substrate is shown;

[0050] Figure 15 A top view of a partial region of an array substrate according to an embodiment of the present disclosure is shown;

[0051] Figure 16 It shows along Figure 15A cross-sectional schematic diagram of a local area of ​​the array substrate taken by the CC' line;

[0052] Figure 17 Comparative data on contact resistance and current withstand value parameters of conventional array substrates and array substrates according to embodiments of the present disclosure are shown;

[0053] Figure 18 A schematic diagram of the structure of a display device according to an embodiment of the present disclosure is shown;

[0054] Figure 19 A flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure is shown;

[0055] Figure 20 A schematic diagram is shown illustrating the fabrication of a first-size product and a second-size product using a first-size photomask according to an embodiment of the present disclosure.

[0056] Figure 21 A schematic diagram is shown showing the fabrication of a first metal layer using the method provided in the embodiments of this disclosure;

[0057] Figure 22 A schematic diagram is shown showing the preparation of a first insulating layer using the method provided in the embodiments of this disclosure;

[0058] Figure 23 A schematic diagram is shown illustrating the fabrication of a second metal layer using the method provided in this disclosure embodiment;

[0059] Figure 24 A schematic diagram showing the fabrication of a second insulating layer using the method provided in this disclosure is shown; and

[0060] Figure 25 A schematic diagram is shown of the preparation of a third metal layer using the method provided in the embodiments of this disclosure.

[0061] It should be understood that the accompanying drawings are merely schematic illustrations of exemplary embodiments of the present disclosure and are not intended to limit the present disclosure, nor need they be drawn to scale. Furthermore, in the drawings, the same or similar components are indicated by the same or similar reference numerals. Detailed Implementation

[0062] The technical solutions of the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0063] Before formally describing the technical solutions of the embodiments of this disclosure, some terms used in the embodiments of this disclosure are explained and defined as follows to help those skilled in the art to more clearly understand the technical solutions of the embodiments of this disclosure.

[0064] As used herein, terms such as "A and B are in the same layer" mean that A and B are formed using the same patterning process, but this does not limit layer A and layer B to having the same height or thickness. In the case of "A and B are in the same layer," layer A and layer B are typically made of the same material. Similarly, terms such as "A and B are in different layers" mean that A and B are typically formed using different patterning processes, layer A and layer B can be made of the same or different materials, and layer A and layer B can have the same height and / or thickness, or different heights and / or thicknesses.

[0065] As used herein, the term "patterning process" or "patterning" includes, but is not limited to, processes such as depositing film layers, coating photoresist, exposure, development, etching, and photoresist stripping. After "patterning process" or "patterning," a "layer" contains at least one pattern.

[0066] GOA (Gate-of-Action) technology integrates the gate drive circuitry onto the array substrate to create a scanning drive for the gate lines. This increases the integration density of the array substrate and reduces the number of gate drive circuits required. GOA technology facilitates narrow bezel designs for display panels and can reduce their production costs.

[0067] To further reduce product development costs and to quickly respond to customer demands for products of different sizes, the inventors of this application have discovered that a mask used to fabricate products of existing sizes can be used to create products of other sizes through masking and partial exposure. Since GOA products typically place the initial signal line (or STV trace) of the GOA on the opposite side of the data line pads, when using a shared existing product mask to fabricate products of different sizes, some GOA cells and initial signal lines need to be cut off. This prevents the STV signal on the initial signal line from reaching the GOA cell, causing the product to malfunction.

[0068] Currently, one method to solve the above problem is to use cutting and welding repair techniques, borrowing the clock signal line (or CLK trace) to introduce the STV signal, thus achieving GOA drive. For example... Figure 1As shown, it displays five rows of GOA units: GOA1 to GOA4 and the Dummy GOA. GOA3 is the 1084th row of GOA units, GOA2 is the 1085th row, GOA1 is the 1086th row, and the Dummy GOA is the 1087th row. The scanning direction is from GOA1 to GOA4. As mentioned above, in order to use the existing product mask to manufacture another size product, it is necessary to cut off a portion of the structure from GOA1 to GOA3. The cutting location is... Figure 1 The locations indicated by the solid black line represent approximately 12 cuts in total. To utilize the CLK trace to introduce the STV signal, the CLK and STV traces need to be fused together. Figure 1 Five fusion points are shown, with two fusion points shown at point ① and three fusion points shown at point ②. By fusion-connecting the CLK trace to the STV trace, the STV signal at point ① can be introduced to the three lines at point ② via the CLK trace. The three lines at point ② are then connected to GOA1 to GOA3 cells, thereby introducing the STV signal to GOA1 to GOA3 cells.

[0069] Figure 2 yes Figure 1 A magnified view of a portion at point ①. (See image below.) Figure 2 As shown, VDDO and VDDE traces are arranged on both sides of the CLK trace, respectively. Both VDDO and VDDE traces partially overlap with the STV trace, and the STV, CLK, VDDO, and VDDE traces are arranged relatively closely together. During the welding process of the STV and CLK traces at repair point ①, it is highly likely that a short circuit will occur between the STV trace and the adjacent VDDO and / or VDDE traces, causing display abnormalities or even failure to display on the display panel, reducing the product's production yield.

[0070] In view of this, embodiments of the present disclosure provide some driving circuit structures. These driving circuit structures include: a substrate, an initial signal line (also referred to as an STV trace) disposed on the substrate, a clock signal line (also referred to as a CLK trace) disposed on the substrate, and a first insulating layer located on the side of the initial signal line away from the substrate, the first insulating layer including a first via, through which the initial signal line is connected to the clock signal line. The driving circuit structure may, for example, be a gate driving circuit structure, which may employ a GOA composed of multiple cascaded shift register units to provide scan signals to multiple rows of gate lines, thereby controlling the opening and closing of the multiple rows of gate lines.

[0071] It should be noted that the phrase "the initial signal line is connected to the clock signal line via the first via" means that the connection between the initial signal line and the clock signal line requires the participation of the first via, but this does not preclude the presence of other electrical components. For example, the initial signal line can be connected to the clock signal line solely through the first via (and the conductive material contained within the first via), meaning one end of the first via is directly connected to the initial signal line, and the other end is directly connected to the clock signal line. Alternatively, the initial signal line can be connected to the clock signal line via the first via and other electrical components (including but not limited to wires).

[0072] In the driving circuit structure provided in this embodiment, the initial signal line is connected to the clock signal line via a first via, thereby introducing the STV signal on the initial signal line into the GOA unit. This avoids short circuits between the initial signal line and other traces, ensuring normal display on the display panel and improving the production yield of the display panel.

[0073] The arrangement of various driving circuit structures provided in the embodiments of this disclosure will be described in more detail below with the aid of several exemplary embodiments.

[0074] Figure 3 A schematic diagram of a partial region of the drive circuit structure 100 is shown, wherein the left figure is a top view of the partial region of the drive circuit structure 100, and the right figure is a cross-sectional view taken along line AA' in the left figure. Figure 3 As shown, the driving circuit structure 100 includes: a substrate 101, an initial signal line 102 disposed on the substrate 101, a first insulating layer 104 located on the side of the initial signal line 102 away from the substrate 101, and a clock signal line 103 located on the side of the first insulating layer 104 away from the substrate 101. The first insulating layer 104 includes a first via 105, through which the initial signal line 102 is connected to the clock signal line 103. More specifically, as Figure 3 As shown, a conductive part 106 is provided in the first via 105. One end 1061 of the conductive part 106 is directly connected to the initial signal line 102, and the other end 1062 of the conductive part 106 is directly connected to the clock signal line 103, so that the initial signal line 102 is connected to the clock signal line 103 through the conductive part 106 in the first via 105.

[0075] The initial signal line 102 is connected to the clock signal line 103 through the conductive portion 106 in the first via 105, without the need for welding. This avoids short circuits between the initial signal line 102 and surrounding traces during welding, ensuring the display panel including the driving circuit structure 100 can display normally. Furthermore, since the depth of the first via 105 is typically shallow (e.g., approximately several hundred nanometers), connecting the initial signal line 102 to the clock signal line 103 via the first via 105 improves the reliability and success rate of the connection, significantly increasing the production yield of the display panel including the driving circuit structure 100. If the first via 105 has a relatively deep depth, during the etching of the first insulating layer 104 to form the first via 105, due to the metal-induced plasma effect, the etching rate of the portion of the first insulating layer 104 near the clock signal line 103 is usually higher than that of other portions. This can easily lead to the first insulating layer 104 at the bottom of the clock signal line 103 being hollowed out, thus forming an undercut. The presence of the undercut can easily cause other film layers to break at the undercut, leading to problems such as abnormal connections and electrostatic breakdown. In contrast, in Figure 3 In the driving circuit structure 100, the first via 105 has a shallow depth. During the formation of the first via 105, the first insulating layer 104 will not be chamfered, thus avoiding the negative impact of chamfering and improving product reliability. Furthermore, the presence of the first via 105 improves the visibility of repair points, helping to increase the efficiency and success rate of repairs.

[0076] The initial signal line 102 can be used to provide a start signal (STV signal) for the drive circuit structure 100, the clock signal line 103 can be used to provide a clock signal for the drive circuit structure 100, and at least one clock signal line 103 can be used to transmit the STV signal on the initial signal line 102 to the drive circuit structure 100.

[0077] The first via 105 penetrates the first insulating layer 104 and includes a first opening 1051 and a second opening 1052 opposite to each other. The shapes of the first opening 1051 and the second opening 1052 can be circular or elliptical. For example, the longitudinal section of the first via 105 can be rectangular or inverted trapezoidal. Figure 3 The cross-section shown in the right figure is parallel to the thickness direction of the substrate 101. The inverted trapezoidal first via 105 is more conducive to the connection between the clock signal line 103 and the initial signal line 102, resulting in lower via resistance.

[0078] It should be noted that the first insulating layer 104 includes a plurality of first vias 105, but not all of the first vias 105 are used to connect the initial signal line 102 and the clock signal line 103. For example, some of the first vias 105 can be used to connect the initial signal line 102 and the clock signal line 103, some of the first vias 105 can be used to connect the initial signal line 102 to other traces, or to connect the metal layer located on the same layer as the initial signal line 102 to other metal layers.

[0079] like Figure 3 As shown, the initial signal line 102 and the clock signal line 103 are located on different layers. The initial signal line 102 can be located on the same layer as, for example, the gate line, the gate electrode, etc., and the same photomask can be used to form the initial signal line 102, the gate line, the gate electrode, etc. The clock signal line 103 can be located on the same layer as, for example, the first power signal line 110, the second power signal line 111, the source / drain electrode (not shown), etc., and the same photomask can be used to form the clock signal line 103, the first power signal line 110, the second power signal line 111, the source / drain electrode, etc. The orthographic projection of the initial signal line 102 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line 103 on the substrate 101 to form an overlap region R, and the orthographic projection of the first via 105 on the substrate 101 falls within the overlap region R.

[0080] The first power signal line 110 (e.g., a VDDO trace) and the second power signal line 111 (e.g., a VDDE trace) can be used to transmit voltage signals. Figure 3 As shown, a first power signal line 110 and a second power signal line 111 are respectively arranged on both sides of the clock signal line 103, and the orthographic projections of the first power signal line 110 and the second power signal line 111 on the substrate 101 partially overlap with the orthographic projection of the initial signal line 102 on the substrate 101. Since the initial signal line 102 is connected to the clock signal line 103 through a first via 105 rather than by welding, even if the first power signal line 110 and the second power signal line 111 are arranged relatively closely with the initial signal line 102, the initial signal line 102 will not be short-circuited with the nearby first power signal line 110 and / or the second power signal line 111. This ensures normal display of the display panel and helps improve the production yield of the product.

[0081] In some embodiments, the drive circuit structure 100 may further include a second insulating layer 107 and a protective pad 109. The second insulating layer 107 is located on the side of the clock signal line 103 away from the substrate 101 and includes a second via 108. The protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 at least partially overlaps with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the clock signal line 103 exposed by the second via 108. The protective pad 109 can be used to prevent external moisture or other contaminants from corroding the conductive portion 106 in the clock signal line 103 and the first via 105, thereby protecting the conductive portion 106 in the clock signal line 103 and the first via 105.

[0082] Figure 4 A schematic diagram of the arrangement of the driving circuit structure 100 on the array substrate is shown, illustrating regions I and II, wherein... Figure 4 The magnified view of region I is Figure 3 The left image. Figure 4 Region I shows two first vias 105, and Region II shows three first vias 105. In Region I, the initial signal line 102 is connected to the clock signal line 103 via the two first vias 105. In Region II, the clock signal line 103 is connected to three horizontal connecting lines via the three first vias 105, and these three horizontal connecting lines are respectively connected to the corresponding GOA units. In this way, the STV signal on the initial signal line 102 can be introduced into the corresponding GOA unit through the clock signal line 103, realizing GOA driving.

[0083] Figure 5 This is a top view of the first via 105, which is also an electron microscope image of the first via 105. As shown in the figure, the shape of the first via 105 can be circular or elliptical, and its size can be determined according to product requirements.

[0084] Figure 6 This is a cross-sectional image after the deposition of the SD metal layer, obtained using an electron microscope. Figure 6In this diagram, the Gate layer can be the aforementioned initial signal line 102, gate line, gate, etc., and the GI layer represents the aforementioned first insulating layer 104, which can be a gate insulating layer. The SD layer can be a clock signal line 103, a first power signal line 110, a second power signal line 111, a source / drain, etc. As shown in the figure, the first via 105 in the GI layer is filled by the deposition of the SD layer. In this way, the Gate layer and the SD layer are connected through the first via 105, thereby avoiding short circuit problems caused by fusion. For example, the thickness of the Gate layer can be approximately 456.4 nm, the thickness of the GI layer can be approximately 390.3 nm, the thickness of the SD layer can be approximately 562.2 nm, the thickness of the intermediate layer between the GI layer and the SD layer can be approximately 36.38 nm, and the thickness of the intermediate layer between the Gate layer and the substrate can be approximately 39.69 nm. In some examples, the slope angle of the portion of the SD layer near the first via 105 in the GI layer is approximately 54.69°. In some examples, the first via 105 can be an inverted trapezoid with a slope angle of approximately 84.09° on the side of the first via 105.

[0085] Figure 7 The image shown is an electron microscope image of the second insulating layer 107 (also known as the PVX layer) formed on top of the SD layer. Figure 8 It is along Figure 7 The cross-sectional view is shown by the solid black line. (See image.) Figure 7 and Figure 8 As shown, the SD layer is not only located on the side of the GI layer away from the Gate layer, but also fills the first via 105 of the GI layer. The PVX layer is located on the side of the SD layer away from the GI layer, and the SD layer in the first via 105 is wrapped by the PVX layer.

[0086] The display panel including the aforementioned driving circuit structure 100 can be of various suitable types and sizes. For example, the display panel including the aforementioned driving circuit structure 100 can be a strip-shaped display panel, which can be used, for example, for installation on a subway for display purposes. In some embodiments, the display panel including the aforementioned driving circuit structure 100 is a strip screen with a size of 58.5 inches. Existing 65-inch photomasks for non-strip screens (e.g., photomasks used to fabricate 65-inch televisions) can be optimized, for example, by adding a pattern of a first via 105 and / or a pattern of a protective pad 109 to the 65-inch photomask, and then using the optimized 65-inch photomask to fabricate a 58.5-inch strip screen, thus achieving photomask sharing. Specific fabrication methods will be described later and will not be elaborated here.

[0087] Figure 9A schematic diagram of another driving circuit structure 200 is shown. Unlike driving circuit structure 100, in this driving circuit structure 200, the initial signal line 102 and the clock signal line 103 are located on the same layer.

[0088] Figure 10 It shows along Figure 9 A cross-sectional view taken from the BB' line. (See figure) Figure 9 and Figure 10 As shown, the driving circuit structure 200 includes: a substrate 101; a first trace group disposed on the substrate 101, which includes at least one initial signal line 102 extending along a first direction D1; and a second trace group disposed on the substrate 101, which includes at least one clock signal line 103 extending along the first direction D1. The initial signal line 102 and the clock signal line 103 are located on the same layer, and the orthographic projection of each initial signal line 102 on the substrate 101 does not overlap with the orthographic projection of each clock signal line 103 on the substrate 101. As an example, Figure 9 The diagram shows that the first routing group includes two initial signal lines 102, denoted as STV1 and STV2 respectively. Of course, this is just an example, and the first routing group may include more initial signal lines. Figure 9 The second routing group is shown to include 12 clock signal lines 103, denoted as CLK1 to CLK12. This is merely an example; the second routing group may include more or fewer clock signal lines. This disclosure does not impose a specific limitation on the number of initial signal lines 102 and clock signal lines 103.

[0089] The inventors of this application discovered that in products where the initial signal line 102 and the clock signal line 103 are located on different layers, during the fabrication of the clock signal line 103, the metal layer containing the clock signal line 103 needs to cross over the metal layer containing the initial signal line 102, resulting in overlap. Since the initial signal line 102 has a certain thickness, this crossing of the clock signal line 103 may cause a break in the circuit. Therefore, during the fabrication and testing stages, it is necessary to monitor for any breakage in the relevant circuits. In the drive circuit structure 200, the initial signal line 102 and the clock signal line 103 are located on the same layer, which can reduce or even avoid the problem of breakage in the clock signal line 103. Furthermore, the initial signal line 102 and the clock signal line 103 do not overlap, which helps reduce the load on the signal lines.

[0090] like Figure 9 and Figure 10As shown, the driving circuit structure 200 further includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of sets of third vias 114; at least one first connecting line 112 extending along the second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112, the first direction D1 intersecting the second direction D2. For the sake of brevity, Figure 9 Only three first connection lines 112 and two second connection lines 113 are shown schematically. In fact, the number of first connection lines 112 can be arbitrary; for example, the number of first connection lines 112 can be equal to the number of clock signal lines 103 in the second routing group. The number of second connection lines 113 can also be arbitrary; for example, the number of second connection lines 113 can be equal to the number of clock signal lines 103 in the second routing group.

[0091] The first connection line 112 includes a first end 1121 and a second end 1122. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first trace group via a first via 105, and the second end 1122 of the first connection line 112 is connected to any clock signal line 113 in the second trace group via another first via 115. For example, for... Figure 9 In one embodiment, twelve first connection lines 112 can be provided. The first end 1121 of one of the twelve first connection lines 112 can be connected to any one of the initial signal lines STV1 and STV2 via a first via 105, and the second end 1122 of this first connection line 112 can be connected to any one of the clock signal lines CLK1 to CLK12 via another first via 105. Similarly, the first end 1121 of another of the twelve first connection lines 112 can be connected to any one of the initial signal lines STV1 and STV2 via a first via 105, and the second end 1122 of this first connection line 112 can be connected to any one of the remaining eleven clock signal lines via another first via 105, and so on. Thus, the first end 1121 of each first connection line 112 is connected to the initial signal line 102 via a first via 105, and the second end 1122 of each first connection line 112 is connected to the clock signal line 103 via a first via 105. In addition, each clock signal line 103 in the second wiring group is connected to a corresponding second connection line 113 via a set of third vias 114. The other end of the second connection line 113 that is not connected to the clock signal line 103 can be connected to the GOA unit, thereby realizing a complete signal transmission path.

[0092] Any clock signal line in the second routing group has two cutouts 115 and 116. Choosing which clock signal line in the second routing group to cut determines which clock signal line will be used to transmit the STV signal on the initial signal line 102; uncut clock signal lines will not transmit the STV signal. Any one of the clock signal lines CLK1 to CLK12 can be selected to transmit the STV signal. Figure 9 Taking the transmission of STV signals via clock signal line CLK3 as an example. Figure 9 As shown, the clock signal line CLK3 has two cut openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105. The second end 1122 of the first connecting line 112 is connected to the clock signal line CLK3 via the first via 105. The orthographic projection of the first connecting line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101. The overlapping part is the first orthographic projection. The clock signal line CLK3 is connected to the second connecting line 113 via a set of third vias 114. The second orthographic projection of the set of third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first and second orthographic projections need to be located between the orthographic projections of the two cut openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. The clock signal line CLK3 is selected to transmit the STV signal. The effective transmission path of the STV signal is as follows: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connection line 112, and the clock signal line CLK3 transmits the STV signal to the GOA unit via the second connection line 113.

[0093] Each clock signal line in the second wiring group can be connected to a corresponding first connection line 112. This means that even if a clock signal line is found to be broken during production, one of the remaining unbroken clock signal lines can be cut to transmit the STV signal. This design greatly increases the selectivity of the cutting position. Furthermore, in the driver circuit structure 200, the initial signal line 102 is connected to the first connection line 112 via the first via 105, and the first connection line 112 is connected to the clock signal line 103 via the first via 105. That is, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connection line 112, avoiding fusion with the clock signal line 103. Therefore, in the driver circuit structure 200, only the clock signal line 103 needs to be cut; fusion with the clock signal line 103 is unnecessary. This allows the STV signal to be introduced into the GOA unit via the clock signal line 103, achieving GOA driving.

[0094] like Figure 9As shown, to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include both a cutout portion and a solid portion. The orthographic projection of the first connecting line 112 on the substrate 101 can partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101, but the orthographic projections of the first connecting line 112 and the first via 105 on the substrate 101 do not overlap with the orthographic projection of the cutout portion of the clock signal line 103 on the substrate 101, i.e., they avoid the cutout portion of the clock signal line 103. Since the first connecting line 112 and the clock signal line 103 are located on different layers, by making the first connecting line 112 and the first via 105 avoid the cutout portion of the clock signal line 103, the potential breakage problem when the first connecting line 112 climbs over the clock signal line 103, which has a certain thickness, can be reduced or even avoided, thereby improving the connection success rate between the clock signal line 103 and the first connecting line 112.

[0095] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby preventing a short circuit between them. For example, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0096] like Figure 9 As shown, the driving circuit structure 200 may further include a first power signal line 110 (or VDDO trace), a second power signal line 111 (or VDDE trace), a common electrode lead COM, and a third power signal line LVGL extending along the first direction D1. The second trace group is located between the first trace group and the first power signal line 110, and the display area of ​​the display panel may be located on the side of the third power signal line LVGL away from the second trace group.

[0097] like Figure 10 As shown, in some embodiments, the drive circuit structure 200 may further include a second insulating layer 107 and a protective pad 109. The second insulating layer 107 is located on the side of the first connection line 112 away from the substrate 101 and includes a second via 108. The protective pad 109 at least fills the second via 108, and the orthographic projection of the protective pad 109 on the substrate 101 at least partially overlaps with the orthographic projection of the first via 105 on the substrate 101. The protective pad 109 may cover the surface of the first connection line 112 exposed by the second via 108. The protective pad 109 can be used to prevent external moisture or other contaminants from corroding the conductive portion 106 in the first connection line 112 and the first via 105, thereby protecting the conductive portion 106 in the first connection line 112 and the first via 105. The first connection line 112 and the conductive portion 106 may be formed using the same patterning process.

[0098] The display panel including the aforementioned driving circuit structure 200 can be of various suitable types and sizes. For example, the display panel including the aforementioned driving circuit structure 200 can be a strip display panel, which can be used, for instance, to be installed on a subway for display purposes. In some embodiments, the display panel including the aforementioned driving circuit structure 200 is a strip screen with a size of 58.5 inches. An existing 65-inch photomask can be optimized, for example, by pre-adding patterns such as the first via 105, the first connecting line 112, and the protective pad 109 to the existing 65-inch photomask, and then using the optimized 65-inch photomask to fabricate a 58.5-inch strip screen, thus achieving photomask sharing. Specific fabrication methods will be described later and will not be elaborated here.

[0099] Of course, the optimized 65-inch photomask can continue to be used to fabricate 65-inch non-strip screen products (such as televisions) without adversely affecting the structure of the non-strip screen products. For example, Figure 11 A cross-sectional view of a partial area of ​​the driving circuit structure for a non-strip screen product is shown. For example... Figure 11 As shown, the driving circuit structure includes a substrate 11, an initial signal line 12, a first insulating layer 14, a second insulating layer 17, a clock signal line 18, a protective pad 19, and other structures.

[0100] Figure 12 A schematic diagram of another driving circuit structure 300 is shown. Unlike driving circuit structure 100, in this driving circuit structure 300, the initial signal line 102 and the clock signal line 103 are located on the same layer.

[0101] like Figure 12 As shown, the driving circuit structure 300 includes: a substrate 101 (not shown); a first trace group disposed on the substrate 101, which includes at least one initial signal line 102 extending along a first direction D1; and a second trace group disposed on the substrate 101, which includes at least one clock signal line 103 extending along the first direction D1. The initial signal line 102 and the clock signal line 103 are located on the same layer, and the orthographic projection of each initial signal line 102 on the substrate 101 does not overlap with the orthographic projection of each clock signal line 103 on the substrate 101. As an example, Figure 12 The diagram shows a first wiring group comprising two initial signal lines 102, denoted as STV1 and STV2. This is merely an example; the first wiring group may include more initial signal lines 102. As an example, Figure 12The second routing group is shown to include 12 clock signal lines 103, denoted as CLK1 to CLK12. This is merely an example; the second routing group may include more or fewer clock signal lines 103. This disclosure does not impose a specific limitation on the number of initial signal lines 102 and clock signal lines 103. In the drive circuit structure 300, the initial signal line 102 and the clock signal line 103 are located on the same layer. This prevents the clock signal line 103 from climbing over the initial signal line 102, which has a certain thickness, thereby reducing or even preventing the clock signal line 103 from breaking. Furthermore, the initial signal line 102 and the clock signal line 103 do not overlap, which helps reduce the load on the signal lines.

[0102] The driving circuit structure 300 further includes: a first insulating layer 104 located on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101, the first insulating layer 104 including a plurality of first vias 105 and a plurality of sets of third vias 114; at least one first connecting line 112 extending along the second direction D2 and located on the side of the first insulating layer 104 away from the substrate 101; and at least one second connecting line 113 extending along the second direction D2 and located on the same layer as the first connecting line 112. For the sake of brevity, Figure 12 Only three first connecting lines 112 and three second connecting lines 113 are shown schematically. In fact, any number of first connecting lines 112 can be arranged, as long as the first connecting lines 112 avoid the cutout areas of the third via 114 and the clock signal line 103. The number of second connecting lines 113 can be equal to the number of clock signal lines 103 in the second routing group.

[0103] The first connection line 112 includes a first end 1121 and a second end 1122. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first trace group via a first via 105. The orthographic projection of the second end 1122 of the first connection line 112 onto the substrate 101 falls within the orthographic projection of the clock signal line 103, which is furthest from the initial signal line 102 among the multiple clock signal lines in the second trace group, onto the substrate 101. That is, the first connection line 112 crosses multiple clock signal lines in the second trace group along the second direction D2. Unlike the drive circuit structure 200, the first connection line 112 is not connected to the clock signal line 103 through the first via 105, but is connected to the clock signal line 103 by welding at the fusion region 117. Since the first connecting line 112 crosses multiple clock signal lines in the second wiring group along the second direction D2, it can be fused with any clock signal line 103 in the second wiring group. This greatly increases the selectivity of the location of the fusion area 117, making the selection of the fusion area 117 more flexible. Moreover, by adopting this arrangement where the first connecting line 112 crosses multiple clock signal lines in the second wiring group along the second direction D2, even if a clock signal line 103 in the second wiring group experiences a fault such as a broken wire, other unfaulty clock signal lines 103 in the second wiring group can be selected to be fused with the first connecting line 102. This greatly improves the connection reliability between the first connecting line 112 and the clock signal line 103, and increases the production yield of the product.

[0104] Each clock signal line 103 in the second wiring group is connected to one end of a corresponding second connection line 113 via a set of third vias 114. The other end of the second connection line 113 can be connected to the GOA unit.

[0105] Any clock signal line in the second routing group has two cutouts 115 and 116. The first connecting line 112 is fused to the clock signal line 103 with two cutouts at the fusion area 117. Choosing which clock signal line in the second routing group to cut and fuse determines which clock signal line will be used to transmit the STV signal on the initial signal line 102. Clock signal lines that are not cut or fused will not transmit the STV signal. Any one of the clock signal lines CLK1 to CLK12 can be selected to transmit the STV signal. Figure 12 Taking the transmission of STV signals via clock signal line CLK3 as an example. Figure 12As shown, the clock signal line CLK3 has two cut openings 115 and 116. The first end 1121 of the first connecting line 112 is connected to the initial signal line STV2 via the first via 105. The first connecting line 112 is fused to the clock signal line CLK3 at the fusion area 117. The initial signal line STV2 is connected to the clock signal line CLK3 through the first via 105, the first connecting line 112, and the fusion area 117. The orthographic projection of the first connection line 112 on the substrate 101 partially overlaps with the orthographic projection of the clock signal line CLK3 on the substrate 101. The overlapping portion is the first orthographic projection. The clock signal line CLK3 is connected to the second connection line 113 via a set of third vias 114. The second orthographic projection of the third vias 114 on the substrate 101 falls within the orthographic projection of the clock signal line CLK3 on the substrate 101. The first and second orthographic projections need to be located between the orthographic projections of the two cut openings 115 and 116 on the substrate 101 to form an effective transmission path for the STV signal. For example, if the clock signal line CLK3 is selected to transmit the STV signal, the effective transmission path for the STV signal is as follows: the STV signal on the initial signal line STV2 is transmitted to the clock signal line CLK3 via the first connection line 112, and the clock signal line CLK3 transmits the STV signal to the GOA unit via the second connection line 113.

[0106] like Figure 12As shown, the driving circuit structure 300 may further include a first power signal line 110 (or VDDO trace), a second power signal line 111 (or VDDE trace), a common electrode lead COM, and a third power signal line LVGL extending along the first direction D1. The display area of ​​the display panel may be located on the side of the third power signal line LVGL away from the second trace group. The first power signal line 110 and the second power signal line 111 are located on the side of the second trace group away from the first trace group, and the orthogonal projections of the cutting openings 115, 116 and the fusion area 117 of the clock signal line on the substrate 101 do not overlap with the orthogonal projections of the first power signal line 110 and the second power signal line 111 on the substrate 101. As mentioned above, in related technologies, the initial signal line is very close to the first and second power signal lines. When the initial signal line is fused with the clock signal line, it is easy to cause a short circuit between the initial signal line and the nearby first and second power signal lines, which may lead to display abnormalities in the display panel. In contrast, in the drive circuit structure 300 of the embodiments of this disclosure, the first power signal line 110 and the second power signal line 111 are designed to be far from the initial signal line 102, and the cut openings 115 and 116 and the fusion area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. Thus, even if the STV signal is introduced into the GOA unit via the clock signal line 103 through cutting and fusion, a short circuit will not occur between the initial signal line 102 and the first power signal line 110 and the second power signal line 111.

[0107] like Figure 12 As shown, to reduce resistance, the initial signal line 102 and the clock signal line 103 are designed to include both a cutout portion and a solid portion. The orthographic projection of the first connecting line 112 on the substrate 101 can partially overlap with the orthographic projection of the solid portion of the clock signal line 103 on the substrate 101, but the orthographic projections of the first connecting line 112 and the first via 105 on the substrate 101 do not overlap with the orthographic projection of the cutout portion of the clock signal line 103 on the substrate 101, i.e., they avoid the cutout portion of the clock signal line 103. Since the first connecting line 112 and the clock signal line 103 are located on different layers, by making the first connecting line 112 and the first via 105 avoid the cutout portion of the clock signal line 103, the breakage problem that occurs when the first connecting line 112 crosses the clock signal line 103 which has a certain thickness can be reduced or even avoided, thereby improving the connection success rate between the clock signal line 103 and the first connecting line 112.

[0108] In some embodiments, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the second connection line 113 on the substrate 101, thereby preventing a short circuit between them. For example, the orthographic projection of the first connection line 112 on the substrate 101 does not overlap with the orthographic projection of the third via 114 on the substrate 101.

[0109] Since the first connecting line 112 is connected to the clock signal line 103 by fusion splicing, it is possible to avoid providing a first via 105 at the location corresponding to the clock signal line 103 on the first insulating layer 104. Furthermore, since no first via 105 is provided at the location corresponding to the clock signal line 103, external moisture will not corrode the clock signal line 103 and / or the first connecting line 112, thus eliminating the need to provide a protective pad at the location corresponding to the first via 105.

[0110] The display panel including the aforementioned driving circuit structure 300 can be of various suitable types and sizes. For example, the display panel including the aforementioned driving circuit structure 300 can be a strip display panel, which can be used, for instance, to be installed on a subway for display purposes. In some embodiments, the display panel including the aforementioned driving circuit structure 300 is a strip screen with a size of 58.5 inches. An existing 65-inch photomask can be optimized, for example, by adding a pattern of the first connecting line 112 to the existing 65-inch photomask, and then using the optimized 65-inch photomask to fabricate a 58.5-inch strip screen, thus achieving photomask sharing. Specific fabrication methods will be described later and will not be elaborated here.

[0111] Figure 13 A schematic diagram of another drive circuit structure 400 is provided, which is a variation of drive circuit structure 300. Figure 13 The drive circuit structure 400 shown has the same characteristics as in... Figure 12 The drive circuit structure 300 shown is essentially the same in construction, and therefore the same reference numerals are used to refer to the same components. For the sake of brevity, the similarities between drive circuit structure 400 and drive circuit structure 300 will not be described again; only the differences will be introduced below.

[0112] Unlike the driving circuit structure 300, in the driving circuit structure 400, the first connection line 112 is connected to the clock signal line 103 through the first via 105. Specifically, the first connection line 112 crosses multiple clock signal lines 103 in the second trace group along the second direction D2. The first connection line 112 includes a first end 1121 and a second end 1122. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first trace group through the first via 105. The orthographic projection of the second end 1122 of the first connection line 112 onto the substrate 101 falls within the orthographic projection of the clock signal line 103 in the second trace group that is furthest from the initial signal line 102 onto the substrate 101. Any clock signal line 103 in the second trace group has two cut-out openings 115 and 116. The first connection line 112 is connected to the clock signal line 103 with the two cut-out openings through the first via 105.

[0113] In the driving circuit structure 400, the initial signal line 102 is connected to the first connecting line 112 via the first via 105, and the first connecting line 112 is connected to the clock signal line 103 via the first via 105. That is, the initial signal line 102 is connected to the clock signal line 103 through the first via 105 and the first connecting line 112, avoiding fusion with the clock signal line 103. Therefore, in the driving circuit structure 400, only the clock signal line 103 needs to be cut, without fusion, to introduce the STV signal into the GOA unit using the clock signal line 103, thus realizing GOA driving.

[0114] For other technical effects of the drive circuit structure 400, please refer to the technical effects of the drive circuit structure 300. For the sake of brevity, they will not be elaborated here.

[0115] Figure 14 A schematic diagram of a partial region of a conventional array substrate 20 is provided. For example... Figure 14 As shown, the array substrate 20 includes: a substrate 11; a first conductive layer 21; a first insulating layer 22; a second conductive layer 23; a second insulating layer 24, which includes vias 26 and 27; and a third conductive layer 25. The second conductive layer 23 is connected to the third conductive layer 25 via via 26, and the first conductive layer 21 is connected to the third conductive layer 25 via via 27. That is, the second conductive layer 23 is connected to the first conductive layer 21 through the third conductive layer 25 (and vias 26 and 27). The first conductive layer 21 can be an initial signal line, and the second conductive layer 23 can be a clock signal line.

[0116] The array substrate 20 has two main problems: First, the second conductive layer 23 must be connected to the first conductive layer 21 via a third conductive layer 25. The material of the third conductive layer 25 is usually different from that of the first and second conductive layers 21, and the third conductive layer 25 typically has a certain area. This results in a large contact resistance for the third conductive layer 25, which is detrimental to meeting the electrical requirements of the array substrate 20. Second, the second conductive layer 23 must be connected to the first conductive layer 21 via vias 26 and 27. The vias 27 are relatively deep. During the etching of the first insulating layer 22 and the second insulating layer 24 to form the vias 27, due to the metal-induced plasma effect, the etching rate of the portions of the first insulating layer 22 and the second insulating layer 24 closest to the second conductive layer 23 is usually greater than the etching rate of other portions. This can easily lead to the first insulating layer 22 beneath the second conductive layer 23 being hollowed out, thus forming a chamfer. The presence of the chamfer can easily cause other film layers to break at the chamfer, leading to problems such as abnormal connections and electrostatic breakdown.

[0117] This disclosure provides an array substrate including the driving circuit structure described in any of the foregoing embodiments. The array substrate provided by this disclosure can at least overcome the technical problems existing in conventional array substrates 20.

[0118] Figure 15 A top view of a partial structure of the array substrate 500 is shown. Figure 16 It shows along Figure 15 A cross-sectional view taken by the CC' line. (See figure) Figure 15 and Figure 16 As shown, the array substrate 500 includes: a substrate 101; a first conductive layer 501 located on the substrate 101, the first conductive layer 501 being located on the same layer as the aforementioned initial signal line 101; a first insulating layer 104 including a first via 105; a second conductive layer 502 located on the side of the first insulating layer 104 away from the substrate 101 and connected to the first conductive layer 501 via a conductive portion 106 in the first via 105; a second insulating layer 107 located on the side of the second conductive layer 502 away from the substrate 101 and including a fourth via 504; and a third conductive layer 503 located on the side of the second insulating layer 107 away from the substrate 101 and connected to the second conductive layer 502 via the fourth via 504.

[0119] Figure 15 and 16The illustrated partial area of ​​the array substrate 500 can be the GOA region, the fan-out region, or the display area of ​​the array substrate 500. When the partial area is the GOA region of the array substrate 500, the first conductive layer 501 can refer to the initial signal line 102, and the second conductive layer 502 can refer to the clock signal line 103, i.e., this structure corresponds to the driving circuit structure 100; or, the first conductive layer 501 can refer to the initial signal line 102 and / or the clock signal line 103, and the second conductive layer 502 can refer to the first connection line 112, i.e., this structure corresponds to the driving circuit structures 200, 300, and 400. When the partial area is the display area of ​​the array substrate 500, the first conductive layer 501 can refer to the gate line and / or the gate electrode, the second conductive layer 502 can refer to the source / drain electrode, and the third conductive layer 503 can be the pixel electrode.

[0120] Unlike array substrate 20, in array substrate 500, the first conductive layer 501 is not connected to the second conductive layer 502 via the third conductive layer 503, but rather via a conductive portion 106 in the first via 105. Since the second conductive layer 502 and the conductive portion 106 in the first via 105 are formed using the same patterning process, the conductive portion 106 in the first via 105 is made of the same material as the second conductive layer 502. Therefore, the contact resistance of the conductive portion 106 in the first via 105 is negligible, i.e., zero, which helps improve the current withstand capability of array substrate 500. Furthermore, compared to the via 27 in array substrate 20, the first via 105 in array substrate 500 has a shallower depth. During the formation of the first via 105, the first insulating layer 104 is not chamfered, thus avoiding problems such as film breakage, abnormal connections, and electrostatic breakdown, which helps improve the reliability of array substrate 500.

[0121] like Figure 16As shown, in some embodiments, the second insulating layer 107 may further include a fifth via 505, and the third conductive layer 503 fills the fourth via 504 and the fifth via 505, with the depth T2 of the fifth via 505 being greater than the depth T1 of the fourth via 504. During the product design phase, the size of the fourth via 504 can be smaller than the size of the fifth via 505 because, in the actual fabrication process, a shallower fourth via 504 needs to be formed first, followed by a deeper fifth via 505. During the etching of the fifth via 505, the fourth via 504 will inevitably continue to be etched, causing its size to further increase. Therefore, during the design phase, the size of the fourth via 504 is designed to be smaller than the size of the fifth via 505 to avoid excessive size differences between them. Provided that the design rules are met, the larger the size of the fourth via 504 and the fifth via 505, the better. This is because the fourth via 504 and the fifth via 505 are connected through the third conductive layer 503. The larger the size of the fourth via 504 and the fifth via 505, the larger the contact area of ​​the third conductive layer 503, which in turn results in lower resistance of the fourth via 504 and the fifth via 505 and better current resistance of the product. This can help avoid electrostatic discharge problems caused by excessive via current.

[0122] Figure 17 Comparative data on contact resistance and current withstand parameters of a conventional array substrate 20 and an array substrate 500 according to an embodiment of this disclosure are shown. Figure 17 In the via pattern, the light-colored area represents the first conductive layer, the dark-colored area represents the second conductive layer, the squares in the light-colored area represent deep vias, and the squares in the dark-colored area represent shallow vias. In the conventional array substrate 20, the first conductive layer 21 is connected to the second conductive layer 23 via vias 26 (shallow vias) and 27 (deep vias). In the array substrate 500, the first conductive layer 501 is connected to the second conductive layer 502 via the conductive portion 106 in the first via 105. From Figure 17 The data shows that the conventional array substrate 20 has a large resistance and a small current withstand value at the vias; while the array substrate 500 has a negligible resistance (0Ω) and a large current withstand value (>10Ω) at the vias. 3 mA).

[0123] In some alternative embodiments, the second insulating layer 107 may include only the fourth via 504, omitting the fifth via 505, effectively filling the fifth via 505. This eliminates the need for etching to form a deeper fifth via 505 during fabrication, reducing etching time. The size of the fourth via 504 can be reduced, and the sizes of other vias within the display area formed using the same process as the fourth via 504 can also be reduced accordingly. This helps increase the aperture ratio of the display area, improving the transmittance of the array substrate 500 and reducing its power consumption.

[0124] Figure 18 A schematic diagram of a display device 600 is shown, which includes an array substrate 500. The array substrate 500 may include the driving circuit structures 100, 200, 300, and 400 described in any of the preceding embodiments. Examples of the display device 600 include, but are not limited to, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators.

[0125] The display device 600 includes a display area 601 and a peripheral area 602 disposed around the display area 601. Driving circuit structures 100, 200, 300, and 400 can be arranged at appropriate positions within the peripheral area 602. The driving circuit structures 100, 200, 300, and 400 can be gate driving circuit structures, which may include multiple cascaded shift register circuits. The gate driving circuit structure can generate multiple gate driving signals for output to gate lines, and can sequentially apply the multiple gate driving signals to each gate line. For example, the gate driving circuit structure can be integrated into the display device 600 as a gate driver on array (GOA) circuit.

[0126] The technical effects of the display device 600 can be referred to the technical effects of the driving circuit structure described in the previous embodiments. For the sake of simplicity, the technical effects of the display device 600 will not be described again here.

[0127] Figure 19 A flowchart of a method 700 for fabricating an array substrate is shown. The array substrate may include the driving circuit structure described in any of the preceding embodiments. Method 700 may include the following steps:

[0128] S701: Provides substrate 101.

[0129] S702: Multiple initial signal lines 102 are formed on substrate 101.

[0130] S703: Multiple clock signal lines 103 are formed on substrate 101.

[0131] S704: A first insulating layer 104 including a plurality of first vias 105 is formed on the side of the initial signal line 102 away from the substrate 101, and the initial signal line 102 is connected to the clock signal line 103 through the first vias 105.

[0132] In method 700, the initial signal line 102 is connected to the clock signal line 103 via the first via 105, thereby introducing the STV signal on the initial signal line 102 to the GOA cell via the clock signal line 103. This avoids short circuits between the initial signal line 102 and other traces, which helps to improve the production yield of the array substrate.

[0133] First, you can use Figure 14 This describes the general process of fabricating a conventional array substrate 20.

[0134] Substrate 11 is provided.

[0135] Then, a first metal layer is deposited on the substrate 11. Using a photomask, photoresist coating, exposure, development, etching, and photoresist stripping are performed on the metal layer to form a first conductive layer 21. The first conductive layer 21 can be an initial signal line, a gate line, a gate, etc.

[0136] Then, a gate insulating layer, an amorphous silicon layer, an ohmic contact layer, and a second metal layer are sequentially deposited on the side of the first conductive layer 21 away from the substrate 11. Using a second photomask, photoresist coating, exposure, development, etching, and photoresist stripping are performed on the second metal layer to form the first insulating layer 22 and the second conductive layer 23. The second conductive layer 23 includes, for example, clock signal lines, first power signal lines, second power signal lines, source and drain electrodes, etc.

[0137] Subsequently, an insulating layer is deposited on the side of the second conductive layer 23 away from the substrate 11. Using a photomask, photoresist coating, exposure, development, etching, and photoresist stripping are performed on the insulating layer to form the second insulating layer 24. The second insulating layer 24 has via patterns in the display area and the GOA area, such as vias 26 and 27.

[0138] Finally, an electrode layer is deposited on the side of the second insulating layer 24 away from the substrate 11. Using a photomask, photoresist coating, exposure, development, etching, and photoresist stripping are performed on the second insulating layer 24 to form a third conductive layer 25. The third conductive layer 25 may include pixel electrodes in the display area and connection layers in the GOA area. Figure 14 As shown, there are no vias between the first conductive layer 21 and the second conductive layer 23, and the first conductive layer 21 and the second conductive layer 23 are connected via the third conductive layer 25.

[0139] In some embodiments, the size of photomasks one, two, three, and four is 65 inches; for example, array substrate 20 can be used in a 65-inch television.

[0140] The aforementioned photomasks one, two, three, and four can be optimized and improved accordingly, and the array substrate provided in this embodiment can be prepared by using masking exposure and partial exposure to achieve photomask sharing. The size of the array substrate provided in this embodiment is different from the size of the aforementioned photomasks one, two, three, and four. The size of the aforementioned photomasks one, two, three, and four is a first size, and the size of the array substrate formed by method 700 is a second size; the first size and the second size are different. For example, the size of the aforementioned photomasks one, two, three, and four is 65 inches, and the size of the array substrate formed by method 700 is 58.5 inches, which can be formed into a bar display screen. The bar display screen can be installed on a subway, for example, for display purposes.

[0141] It should be noted that terms such as "the dimensions of mask one, two, three, and four are the first dimension" refer to the length of the diagonal of mask one, two, three, and four as the first dimension. Similarly, terms such as "the dimensions of the array substrate are the second dimension" refer to the length of the diagonal of the array substrate as the second dimension.

[0142] By optimizing and improving existing photomasks, they can be used not only to fabricate products of the first size but also products of the second size, thereby increasing photomask utilization and reducing development costs. Furthermore, since other sizes of film layers can be fabricated by optimizing existing photomasks without the need for redesigning and fabricating new photomasks, it is possible to respond more quickly to customer demands for products of different sizes.

[0143] Next, using Figure 20 This will describe in more detail how to fabricate a second-size array substrate using an existing first-size photomask.

[0144] exist Figure 20In the example, the existing photomask has a length of y inches along the first direction D1, a width of 2x inches along the second direction D2, and a diagonal length of 65 inches, which is the first size. The existing photomask can be used to fabricate one or more film layers on an array substrate, or it can be used to fabricate one or more film layers on a color filter substrate. By blocking half of the existing photomask along the second direction D2, its length along the first direction D1 remains y inches, its width along the second direction D2 becomes x inches, and its diagonal length becomes 58.5 inches, thus forming a photomask of the second size. On a substrate with a length of 2940 mm in the first direction D1 and a length of 3370 mm in the second direction D2, by exposing half of the existing photomask, ten substrates with a diagonal length of 58.5 inches can be formed, where substrate A1 can be a 58.5-inch array substrate, and substrate C1 can be a 58.5-inch color filter substrate; by performing normal exposure using the existing photomask, two substrates A2 with a diagonal length of 65 inches can be formed on the right side of the substrate. Therefore, on a substrate with a length of 2940 mm in the first direction D1 and a length of 3370 mm in the second direction D2, 10 58.5-inch strip-shaped substrates and 2 65-inch non-strip-shaped substrates can be formed.

[0145] It should be noted that using a 65-inch photomask to fabricate a 58.5-inch strip screen is just one example of using a shared photomask for strip screen fabrication. The specific size of the strip screen can be determined according to customer needs and application scenarios. When other sizes of strip screens are required, the corresponding sizes can be obtained by obscuring 1 / 3, 1 / 4, etc., of the 65-inch photomask. Alternatively, other sizes of strip screens can be obtained by partially obscuring photomasks of other sizes.

[0146] Next, using Figure 21-25 This describes a method for fabricating an array substrate including a driving circuit structure 100.

[0147] Figure 21 The left side is a top view. Figure 21 The right side is a cross-sectional view taken along line DD' in the top view. For example... Figure 21 As shown, a substrate 101 is first provided, and the material of the substrate 101 can be, for example, glass. Then, a first metal layer is deposited on the substrate 101, partially obscuring a first mask having a first size. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to pattern the first metal layer to form multiple initial signal lines 102, gate lines, gates, and other structures. The first mask can be the aforementioned mask one. The material of the first metal layer includes, but is not limited to, molybdenum-aluminum-molybdenum (Mo / Al / Mo), molybdenum-copper (Mo / Cu), molybdenum-niobium-copper (Mo / Nb / Cu), and molybdenum-niobium-copper-molybdenum-titanium (Mo / Nb / Cu / Mo / Ti).

[0148] Figure 22 The left side is a top view. Figure 22 The right side is a cross-sectional view taken along line EE' in the top view. (See image below.) Figure 22 As shown, a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer are sequentially deposited on the side of the initial signal line 102 away from the substrate 101, partially obscuring a second mask with a first dimension. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to form a first insulating layer 104 and multiple first vias 105 penetrating the first insulating layer 104. The first vias 105 expose a portion of the surface of the initial signal line 102. The position of the first vias 105 is where the initial signal line 102 overlaps with the clock signal line 103. The second mask can be obtained by adding a design pattern of first vias 105 at the overlapping position of the initial signal line 102 and the clock signal line 103 on the aforementioned third mask.

[0149] and Figure 14 Compared to the previous method, the method provided in this disclosure adds a mask process for separately preparing the first insulating layer 104. Figure 14 In this process, the first insulating layer 22 has no vias at the positions corresponding to the second conductive layer 23, and the first insulating layer 22 and the second conductive layer 23 are formed using a single photomask. Figure 22 In the process, the first insulating layer 104 includes a first via 105 at the position corresponding to the clock signal line 103. The first intermediate insulating layer needs to be patterned, therefore, a separate mask process is required to prepare the first insulating layer 104.

[0150] Figure 23 The left side is a top view. Figure 23 The right side is a cross-sectional view taken along line FF' of the top view. For example... Figure 23 As shown, a second metal layer is deposited on the side of the first insulating layer 104 away from the substrate 101, partially obscuring a third mask with a first size. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to pattern the second metal layer, forming multiple clock signal lines 103, a first power signal line 110, a second power signal line 111, and source / drain electrodes (not shown) on the side of the first insulating layer 104 away from the substrate 101. Simultaneously, a conductive portion 106 is formed in the first via 105, and the initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105. The third mask can be the aforementioned mask two. In some embodiments, the material of the second metal layer includes, but is not limited to, molybdenum-aluminum-molybdenum (Mo / Al / Mo), molybdenum-copper (Mo / Cu), molybdenum-niobium-copper (Mo / Nb / Cu), and molybdenum-niobium-copper-molybdenum-titanium (Mo / Nb / Cu / Mo / Ti).

[0151] The initial signal line 102 is connected to the clock signal line 103 through the conductive portion 106 in the first via 105, without needing to be connected to the clock signal line 103 by welding. This avoids short circuits between the initial signal line 102 and surrounding traces during welding, allowing the display panel including the drive circuit structure 100 to display normally. Furthermore, in Figure 23 In this design, the initial signal line 102 is connected to the clock signal line 103 via the conductive portion 106 in the first via 105. The depth of the first via 105 is much smaller than the depth of the via 27 in the conventional array substrate 20. Therefore, during the etching of the first intermediate insulating layer to form the first via 105, no chamfer is formed, thus avoiding problems such as film layer breakage, abnormal connection, and electrostatic breakdown. Furthermore, the presence of the first via 105 improves the identification of repair points, helping to increase the efficiency and success rate of repair personnel. The design of the first via 105 enriches product design rules and expands the utilization rate of the photomask.

[0152] Figure 24 The left side is a top view. Figure 24 The right side is a cross-sectional view taken along line GG' in the top view. For example... Figure 24 As shown, a second intermediate insulating layer is deposited on the side of the clock signal line 103 away from the substrate 101, blocking a portion of a second mask having a first size. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to form the second insulating layer 107. The second insulating layer 107 includes multiple vias in the display area and multiple second vias 108 in the GOA area. The second vias 108 expose a portion of the surface of the clock signal line 103. The first insulating layer 104 and the second insulating layer 107 share a single second mask for formation.

[0153] Figure 25 The left side is a top view. Figure 25 The right side is a cross-sectional view taken along line AA' in the top view. For example... Figure 25 As shown, a third metal layer is deposited on the side of the second insulating layer 107 away from the substrate 101, shielding a portion of the fourth mask with the first dimension. Then, photoresist coating, exposure, development, etching, and photoresist stripping processes are performed to form pixel electrodes in the display area and protective pads 109 in the GOA area. The protective pads 109 at least fill the second via 108. The protective pads 109 primarily prevent corrosion of the clock signal line 103 and conductive portion 106 by external environmental moisture. The fourth mask can be obtained by adding a pattern of protective pads 109 to the aforementioned fourth mask.

[0154] In fabricating an array substrate including a driving circuit structure 100, the structures of some of the aforementioned photomasks (first, second, third, and fourth) are optimized and improved. For example, a design pattern for a first via 105 is added to photomask three at the position corresponding to the clock signal line 103, and a design pattern for a protective pad 109 is added to photomask four, resulting in first, second, third, and fourth photomasks. By performing masking exposure and partial exposure on the first, second, third, and fourth photomasks with a first size, an array substrate of a second size can be fabricated, thereby achieving photomask sharing. In this way, the first-size photomask can be used not only to fabricate the first-size array substrate but also to fabricate the second-size array substrate, thereby improving the utilization rate of the photomasks and saving product investment costs. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By performing partial exposure by masking half of the first-size photomask, the second-size array substrate can be obtained. The second-size array substrate can be strip-shaped to form a strip display screen, which can be installed on a subway for example.

[0155] Next, using Figure 9 Here is a simple description of a method for fabricating an array substrate including a driving circuit structure 200.

[0156] A substrate 101 is provided. A first metal layer is then deposited on the substrate 101. The first metal layer is patterned by obscuring a portion of a first mask having a first size to form structures such as a first wiring group, a second wiring group, gate lines, and gate electrodes. The first wiring group includes multiple initial signal lines 102, and the second wiring group includes multiple clock signal lines 103. The initial signal lines 102 and clock signal lines 103 are arranged along a first direction and located on the same layer, and the orthogonal projections of the initial signal lines 102 and the clock signal lines 103 on the substrate 101 do not overlap. The first mask can be the aforementioned mask one.

[0157] A first intermediate insulating layer is deposited on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101. The first intermediate insulating layer is patterned by blocking a portion of a second mask having a first size to form a first insulating layer 104 including a plurality of first vias 105 and a plurality of sets of third vias 114. The first vias 105 expose portions of the surfaces of the initial signal line 102 and the clock signal line 103, and the third vias 114 expose portions of the surface of the clock signal line 103. The second mask can be obtained by adding a design pattern of first vias 105 at the positions corresponding to the clock signal line 103 on the aforementioned third mask.

[0158] A second metal layer is deposited on the side of the first insulating layer 104 away from the substrate 101. The second metal layer is patterned by shielding a portion of a third mask having a first size to form at least one first connection line 112 and at least one second connection line 113, a first power signal line 110, a second power signal line 111, and source / drain terminals (not shown) arranged along the second direction D2. The first connection line 112 includes opposing first ends 1121 and second ends 1122. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first trace group via a first via 105. The second end 1122 of the first connection line 112 is connected to any clock signal line 103 in the second trace group via a first via 105. Each clock signal line 103 in the second trace group is connected to a corresponding second connection line 113 via a set of third vias 114. The third mask can be obtained by adding the design pattern of the first connection line 112 to the aforementioned second mask.

[0159] A second intermediate insulating layer is deposited on the side of the first connection line 112 and the second connection line 113 away from the substrate 101. The second intermediate insulating layer is patterned by obscuring a portion of the second mask to form a second insulating layer 107 including a plurality of second vias 108. The first insulating layer 104 and the second insulating layer 107 can be formed using a single second mask.

[0160] A third metal layer is deposited on the side of the second insulating layer 107 away from the substrate 101. The third metal layer is patterned by shielding a portion of a fourth mask with a first dimension to form pixel electrodes in the display area and protective pads 109 in the GOA area. The protective pads 109 at least fill the second via 108. The protective pads 109 primarily prevent corrosion of the conductive materials in the first connecting line 112, the second connecting line 113, and the first via 105 by external environmental factors such as moisture. The fourth mask can be obtained by adding the design pattern of the protective pads 109 to the aforementioned fourth mask.

[0161] Any clock signal line 103 in the second trace group is cut, so that the clock signal line 103 has two cut openings 115 and 116. The orthographic projection of the clock signal line 103 with two cut openings 115 and 116 on the substrate 101 partially overlaps with the orthographic projection of the first connecting line 112 connected to the clock signal line 103 on the substrate 101. The overlapping part is the first orthographic projection. The orthographic projection of one of the multiple sets of third vias 114 on the substrate 101 is the second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line 103 with two cut openings 115 and 116 on the substrate 101. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings 115 and 116 on the substrate 101. Choosing which clock signal line 103 to cut determines which clock signal line 103 will transmit the STV signal on the initial signal line 102. Clock signal lines 103 that are not cut do not transmit the STV signal. By positioning the two cut openings 115 and 116 on the clock signal line 103 on the upper and lower sides of the first connecting line 112 and the third via 114, an effective transmission path for the STV signal can be formed. In this embodiment, the initial signal line 102 is connected to the clock signal line 103 via the first via 105 and the first connecting line 112. Only the clock signal line 103 needs to be cut; there is no need to fuse the clock signal line 103 and the first connecting line 112. This allows for the transmission of the STV signal via the clock signal line 103, which helps improve production efficiency.

[0162] In fabricating an array substrate including a driving circuit structure 200, the structures of some of the aforementioned photomasks (first, second, third, and fourth) are optimized and improved. For example, a design pattern for a first connecting line 112 is added to photomask second, a design pattern for a first via 105 is added to photomask third at the position corresponding to the clock signal line 103, and a design pattern for a protective pad 109 is added to photomask fourth, thus obtaining first, second, third, and fourth photomasks. By performing masking exposure and partial exposure on the first, second, third, and fourth photomasks with a first size, an array substrate of a second size can be fabricated, thereby achieving photomask sharing. In this way, the first-size photomask can be used not only to fabricate the first-size array substrate but also to fabricate the second-size array substrate, thereby improving the utilization rate of the photomasks and saving product investment costs. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By performing partial exposure by masking half of the first-size photomask, an array substrate of the second size can be obtained. The second-sized array substrate can be strip-shaped to form a strip display screen, which can be installed, for example, on a subway for display.

[0163] Next, using Figure 12Here is a simple description of a method for fabricating an array substrate including a driving circuit structure 300.

[0164] A substrate 101 is provided. A first metal layer is then deposited on the substrate 101. The first metal layer is patterned by obscuring a portion of a first mask having a first size to form structures such as a first wiring group, a second wiring group, gate lines, and gate electrodes. The first wiring group includes multiple initial signal lines 102, and the second wiring group includes multiple clock signal lines 103. The initial signal lines 102 and clock signal lines 103 are arranged along a first direction D1 and located on the same layer, and the orthogonal projections of the initial signal lines 102 and the clock signal lines 103 on the substrate 101 do not overlap. The first mask can be the aforementioned mask one.

[0165] A first intermediate insulating layer and a second metal layer are sequentially deposited on the side of the initial signal line 102 and the clock signal line 103 away from the substrate 101. The first intermediate insulating layer and the second conductive layer are patterned by blocking a portion of a second mask having a first size, to form a structure including a first insulating layer 104 with multiple first vias 105 and multiple sets of third vias 114, at least one first connection line 112 and at least one second connection line 113 arranged along the second direction D2, a first power signal line 110, a second power signal line 111, and source and drain terminals (not shown). Note that, unlike the driving circuit structure 200, in this embodiment, the first insulating layer 104 includes the first vias 105 only at the position corresponding to the initial signal line 102, and does not include the first vias 105 at the position corresponding to the clock signal line 103. A first connection line 112 crosses multiple clock signal lines 103 in the second trace group along the second direction D2. The first connection line 112 includes a first end 1121 and a second end 1122. The first end 1121 of the first connection line 112 is connected to any initial signal line 102 in the first trace group via a first via 105. The orthographic projection of the second end 1122 of the first connection line 112 onto the substrate 101 falls within the orthographic projection of the clock signal line 103 furthest from the initial signal line 102 among the multiple clock signal lines in the second trace group onto the substrate 101. The first connection line 112 crosses multiple clock signal lines, thus providing multiple fusion points and greatly increasing the selectivity of the fusion location. Each clock signal line 103 in the second trace group is connected to one end of a corresponding second connection line 113 via a set of third vias 114. The other end of the second connection line 113 is connected to a GOA cell.

[0166] In this embodiment, the first insulating layer 104 does not have an additional first via 105 at the position corresponding to the clock signal line 103, and the structure of the first insulating layer 104 is the same as that of the first insulating layer 22 in related technologies. Therefore, in the process of fabricating the driving circuit structure 300, the first insulating layer 104 can share a second mask with the first connecting line 112 and the second connecting line 113, without the need to add a separate mask process for the first insulating layer 104. The second mask can be obtained by adding the design pattern of the second connecting line 112 to the aforementioned second mask.

[0167] A second intermediate insulating layer is deposited on the side of the first connection line 112 and the second connection line 113 away from the substrate 101. The second intermediate insulating layer is patterned by shielding a portion of a third mask having a first size to form the second insulating layer 107. Since the first insulating layer 104 does not have an additional first via 105 at the location corresponding to the clock signal line 103, there is no need to provide a protective pad to protect the metal, and therefore no need to form a second via 108 to accommodate the protective pad at the location corresponding to the first via 105 in the second insulating layer 107. The third mask can be the aforementioned mask three.

[0168] A third metal layer is deposited on the side of the second insulating layer 107 away from the substrate 101. The third metal layer is patterned by blocking a portion of a fourth mask having a first size to form pixel electrodes in the display area. As described above, since no protective pad is required, there is no need to form a protective pad in the GOA region; only the pixel electrodes need to be formed in the display area. The fourth mask can be the aforementioned mask four.

[0169] Any clock signal line 103 in the second trace group is cut to have two cut openings 115 and 116; and the clock signal line 103 with two cut openings 115 and 116 is fused with a first connecting line 112 located between the two cut openings 115 and 116 at a fusion point 117. The orthographic projection of the clock signal line 103 with two cut openings 115 and 116 on the substrate 101 and the orthographic projection of the first connecting line 112 fused with the clock signal line 103 on the substrate 101 partially overlap, the overlapping part being the first orthographic projection. The orthographic projection of one of the multiple sets of third vias 114 on the substrate 101 is the second orthographic projection, which falls within the orthographic projection of the clock signal line 103 with two cut openings 115 and 116 on the substrate 101. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings 115 and 116 on the substrate 101.

[0170] The decision of which clock signal line 103 to cut and fuse determines which clock signal line 103 will transmit the STV signal on the initial signal line 102; clock signal lines 103 that are not cut and fused will not transmit the STV signal. An effective transmission path for the STV signal can be formed by positioning the two cut openings 115 and 116 on the clock signal line 103 above and below the first connecting line 112 and the third via 114. In this embodiment, although the clock signal line 103 needs to be cut and fused to transmit the STV signal, the first power signal line 110 and the second power signal line 111 are designed to be far from the initial signal line 102, and the cut openings 115 and 116 and the fusion area 117 of the clock signal line 103 do not overlap with the first power signal line 110 and the second power signal line 111. In this way, even if the STV signal is introduced into the GOA unit by using the clock signal line 103 through cutting and splicing, it will not cause a short circuit between the initial signal line 102 and the first power signal line 110 and the second power signal line 111.

[0171] In the fabrication process of the array substrate including the driving circuit structure 300, only the design pattern of the first connection line 112 needs to be added to the second mask. There is no need to add the design pattern of the first via 105 to the third mask or the design pattern of the protective pad 109 to the fourth mask, and no separate mask process is required for the first insulating layer 104. Therefore, compared to the array substrate 20 of the related technology, except for the need to add the design pattern of the first connection line 112 to the second mask, the fabrication process of the array substrate including the driving circuit structure 300 is basically the same as that of the array substrate 20. By sharing the aforementioned first-size masks one, three, and four, as well as the improved mask two, a second-size array substrate can be fabricated, thus achieving mask sharing. In this way, the first-size mask can be used not only to fabricate the first-size array substrate but also to fabricate the second-size array substrate, thereby improving the utilization rate of the mask and saving product investment costs. In some embodiments, the first size can be 65 inches, and the second size can be 58.5 inches. By partially exposing half of the first-size mask, the second-size array substrate can be obtained. The second-sized array substrate can be strip-shaped to form a strip display screen, which can be installed, for example, on a subway for display.

[0172] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0173] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Therefore, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0174] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, as used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine the different embodiments or examples described herein and the features of the different embodiments or examples without contradiction.

[0175] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0176] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0177] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0178] As those skilled in the art will understand, although the steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order unless the context clearly indicates otherwise. Additional or alternatively, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps. Furthermore, other method steps may be inserted between steps. Inserted steps may represent improvements to the method described herein, or may be unrelated to the method. Moreover, a given step may not be fully completed before the next step begins.

[0179] While the foregoing discussion contains several specific implementation details, these should not be construed as limiting any invention or the scope of any possible claims, but rather as descriptions of features that may be limited to specific embodiments of a particular invention. Specific features described in different embodiments of this specification may also be implemented in combination in a single embodiment. Conversely, different features described in a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A driving circuit structure, comprising: Substrate; The initial signal line is located on the substrate; Clock signal lines are located on the substrate; A first insulating layer is located on the side of the initial signal line away from the substrate and includes a first via. The first wiring group includes at least one initial signal line extending along a first direction; The second trace group includes at least one clock signal line extending along the first direction, and the orthographic projection of the second trace group on the substrate does not overlap with the orthographic projection of the first trace group on the substrate. as well as At least one first connecting line extends along a second direction intersecting the first direction and is located on the side of the first insulating layer away from the substrate. The initial signal line and the clock signal line are located on the same layer, the orthographic projection of the initial signal line on the substrate does not overlap with the orthographic projection of the clock signal line on the substrate, and at least one clock signal line in the second trace group is connected to any one of the initial signal lines in the first trace group via the first connecting line and the first via.

2. The driving circuit structure according to claim 1 further includes: A second insulating layer is located on the side of the first insulating layer away from the substrate and includes a second via. as well as Protective pad, at least filling the second through hole, Wherein, the orthographic projection of the protective pad on the substrate at least partially overlaps with the orthographic projection of the first via on the substrate.

3. The driving circuit structure according to claim 1, wherein, The clock signal line includes a cutout portion and a solid portion. The orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the solid portion on the substrate, and the orthographic projections of the first connecting line and the first via on the substrate do not overlap with the orthographic projection of the cutout portion on the substrate.

4. The driving circuit structure according to claim 1 further includes at least one second connecting line extending along the second direction, wherein, Each clock signal line in the second trace group is connected to a corresponding second connection line, and the orthographic projection of the first connection line on the substrate does not overlap with the orthographic projection of the second connection line on the substrate.

5. The driving circuit structure according to claim 4, wherein, The first insulating layer also includes multiple sets of third vias, and each clock signal line in the second trace group is connected to the corresponding second connection line via one of the multiple sets of third vias.

6. The driving circuit structure according to claim 5, wherein, One of the clock signal lines in the second routing group has two cut-outs. Wherein, one of the at least one first connecting lines is connected to the clock signal line with two cut openings, and the orthographic projection of the first connecting line on the substrate partially overlaps with the orthographic projection of the clock signal line with two cut openings on the substrate, the overlapping part being the first orthographic projection; the orthographic projection of one of the multiple sets of third vias on the substrate is the second orthographic projection, the second orthographic projection falling within the orthographic projection of the clock signal line with two cut openings on the substrate; and the first orthographic projection and the second orthographic projection being located between the orthographic projections of the two cut openings on the substrate.

7. The driving circuit structure according to claim 6, wherein, The first connection line includes a first end and a second end, the first end of the first connection line is connected to any initial signal line in the first trace group via the first via, and the second end of the first connection line is connected to any clock signal line in the second trace group via the first via.

8. The driving circuit structure according to claim 6, wherein, The second trace group includes multiple clock signal lines arranged in parallel along the first direction. The first connecting line crosses the multiple clock signal lines in the second trace group along the second direction. The first connecting line includes a first end and a second end opposite to each other. The first end of the first connecting line is connected to any initial signal line in the first trace group via the first via. The orthographic projection of the second end of the first connecting line on the substrate falls within the orthographic projection of the clock signal line furthest from the initial signal line among the multiple clock signal lines in the second trace group on the substrate.

9. The driving circuit structure according to claim 8, wherein, One of the at least one first connection lines is fused to the clock signal line having two cutouts.

10. The driving circuit structure according to claim 9, further comprising a first power signal line and a second power signal line extending along the first direction, wherein, The first power signal line and the second power signal line are located on the side of the second trace group away from the first trace group, and the orthographic projection of the cut opening and fusion area of ​​the clock signal line on the substrate does not overlap with the orthographic projection of the first power signal line and the second power signal line on the substrate.

11. The driving circuit structure according to claim 8, wherein, One of the at least one first connection lines is connected to the clock signal line with two cut-out openings through the first via.

12. The driving circuit structure according to any one of claims 1-11, wherein, The first via includes a first opening and a second opening opposite each other. The first opening and the second opening are circular or elliptical in shape. The longitudinal section of the first via is rectangular or inverted trapezoidal, and the longitudinal section is parallel to the thickness direction of the substrate.

13. An array substrate comprising a driving circuit structure according to any one of claims 1-12.

14. The array substrate according to claim 13, further comprising: The first conductive layer is located on the same layer as the initial signal line; The second conductive layer is located on the side of the first insulating layer away from the substrate, and the first conductive layer is connected to the second conductive layer through the conductive portion in the first via. A second insulating layer, located on the side of the second conductive layer away from the substrate, and including a fourth via; and The third conductive layer is located on the side of the second insulating layer away from the substrate and is connected to the second conductive layer via the fourth via.

15. The array substrate according to claim 14, wherein, The second insulating layer further includes a fifth via, the third conductive layer fills the fourth via and the fifth via, and the depth of the fifth via is greater than the depth of the fourth via.

16. A display device comprising an array substrate according to any one of claims 13-15.

17. The display device according to claim 16, wherein, The display device includes a display area and a peripheral area disposed around the display area, and the driving circuit structure is arranged in the peripheral area.

18. A method for fabricating an array substrate, comprising: Provide substrate; A first trace group is formed on the substrate, the first trace group including at least one initial signal line extending along a first direction; A second trace group is formed on the substrate, the second trace group including at least one clock signal line extending along the first direction, and the orthographic projection of the second trace group on the substrate does not overlap with the orthographic projection of the first trace group on the substrate; A first insulating layer comprising a plurality of first vias is formed on the side of the initial signal line away from the substrate; as well as At least one first connection line is formed on the side of the first insulating layer away from the substrate, and the first connection line extends along a second direction intersecting the first direction. The initial signal line and the clock signal line are located on the same layer, the orthographic projection of the initial signal line on the substrate does not overlap with the orthographic projection of the clock signal line on the substrate, and at least one clock signal line in the second trace group is connected to any one of the initial signal lines in the first trace group via the first connecting line and the first via.

19. The method according to claim 18, wherein, The initial signal line, the clock signal line, and the first insulating layer are formed using different photomasks with a first size, such that the array substrate has a second size, the first size being larger than the second size, and the array substrate with the second size having a strip shape.

20. The method according to claim 19, wherein, Multiple initial signal lines and multiple clock signal lines are formed on the substrate, including: A first metal layer is deposited on the substrate, and the first metal layer is patterned by blocking a portion of a first mask having the first size to form a first trace group and a second trace group. The first trace group includes a plurality of initial signal lines arranged along the first direction, and the second trace group includes a plurality of clock signal lines arranged along the first direction.

21. The method of claim 20, further comprising: A first intermediate insulating layer is deposited on the side of the initial signal line and the clock signal line away from the substrate. The first intermediate insulating layer is patterned by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and a plurality of sets of third vias. The first vias expose a portion of the surface of the initial signal line and the clock signal line, and the third vias expose a portion of the surface of the clock signal line. A second metal layer is deposited on the side of the first insulating layer away from the substrate. The second metal layer is patterned by blocking a portion of a third mask having the first size to form at least one first connection line and at least one second connection line arranged along a second direction. The first connection line includes opposing first and second ends. The first end of the first connection line is connected to any initial signal line in the first trace group via the first via. The second end of the first connection line is connected to any clock signal line in the second trace group via the first via. Each clock signal line in the second trace group is connected to a corresponding second connection line via one of the multiple sets of third vias. The second direction intersects the first direction. A second intermediate insulating layer is deposited on the side of the first and second connecting lines away from the substrate. The second intermediate insulating layer is patterned by blocking a portion of the second mask to form a second insulating layer including a plurality of second vias. A third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is patterned by shielding a portion of a fourth mask having the first size to form a protective pad that at least fills the second via. as well as One of the clock signal lines in the second routing group is cut, so that the clock signal line has two cut openings. The orthographic projection of the first connecting line connected to the clock signal line with two cut openings on the substrate partially overlaps with the orthographic projection of the clock signal line with two cut openings on the substrate. The overlapping part is the first orthographic projection. The orthographic projection of one of the multiple sets of third vias on the substrate is the second orthographic projection. The second orthographic projection falls within the orthographic projection of the clock signal line with two cut openings on the substrate. The first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings on the substrate.

22. The method of claim 20, further comprising: A first intermediate insulating layer and a second metal layer are sequentially deposited on the side of the initial signal line and the clock signal line away from the substrate. The first intermediate insulating layer and the second metal layer are patterned by blocking a portion of a second mask having the first size to form a first insulating layer including the plurality of first vias and the plurality of sets of third vias, as well as at least one first connection line and at least one second connection line arranged along a second direction. The first vias expose a portion of the surface of the initial signal line, and the third vias expose a portion of the surface of the clock signal line. The first connection line crosses the plurality of clock signal lines in the second trace group along the second direction. The first connection line includes opposing first and second ends. The first end of the first connection line is connected to any initial signal line in the first trace group via the first via. The orthographic projection of the second end of the first connection line on the substrate falls within the orthographic projection of the clock signal line furthest from the initial signal line among the plurality of clock signal lines in the second trace group on the substrate. Each clock signal line in the second trace group is connected to a corresponding second connection line via one set of third vias among the plurality of sets of third vias. The second direction intersects the first direction. A second intermediate insulating layer is deposited on the side of the first and second connecting lines away from the substrate, and the second intermediate insulating layer is patterned by blocking a portion of a third mask having the first size to form the second insulating layer; A third metal layer is deposited on the side of the second insulating layer away from the substrate, and the third metal layer is patterned by blocking a portion of a fourth mask having the first size to form a pixel electrode; Cut one clock signal line in the second routing group so that the clock signal line has two cut openings; and The clock signal line with the two cut openings is fused with the first connecting line located between the two cut openings in the fusion area. Wherein, the orthographic projection of the welded area on the substrate is the first orthographic projection, the orthographic projection of one of the multiple sets of third vias on the substrate is the second orthographic projection, the second orthographic projection falls within the orthographic projection of the clock signal line with two cut openings on the substrate, and the first orthographic projection and the second orthographic projection are located between the orthographic projections of the two cut openings on the substrate.

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