Shifting register, driving circuit, driving method and display device

Abstract

The invention provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: an input circuit configured to provide a first power supply voltage or a second power supply voltage to a first node and a light emitting control signal end under the control of a first input signal and a second input signal; the processing circuit is configured to provide a first power supply voltage or a second power supply voltage to a second node under the control of a first input signal and the potential of the first node, and the input circuit provides the first power supply voltage or the second power supply voltage to a light emitting control signal end under the control of the potential of the second node; and the output circuit is configured to provide the first power supply voltage or the second power supply voltage to a first output scanning signal end under the control of the first clock signal and the potential of the first node, and provide the second power supply voltage or the second power supply voltage to a second output scanning signal end under the control of the potential of the first output scanning signal end. And providing the first power supply voltage or the second power supply voltage to a second output scanning signal end.

Description

Shift register, driving circuit, driving method and display device

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method and a display device.

[0002] In the field of light-emitting diode (LED) and organic light-emitting diode (OLED) displays, the display is driven by the gate drive (GOA) circuit integrated on the array substrate and the timing design. The pixel circuit in the display usually requires multiple groups of GOA circuits to provide driving signals, which will increase the space occupied by the GOA circuit, and cannot effectively reduce the border width and cannot meet the demand for narrow borders of the display.

[0003] Summary of the invention

[0004] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit, electrically connected to a first input signal terminal, a second input signal terminal, a first power supply terminal, a second power supply terminal and a light-emitting control signal terminal, configured to provide a first power supply voltage of the first power supply terminal or a second power supply voltage of the second power supply terminal to a first node under the control of a first input signal from the first input signal terminal and a second input signal from the second input signal terminal, wherein the light-emitting control signal terminal is electrically connected to the first node; a processing circuit, electrically connected to the first input signal terminal, a first node, the first power supply terminal and the second power supply terminal, configured to provide the first power supply voltage or the second power supply voltage to a first node under the control of the first input signal and the potential of the first node A voltage is provided to a second node, wherein an input circuit is electrically connected to the second node, and under the control of the potential of the second node, the input circuit provides a first power supply voltage or a second power supply voltage to a light emitting control signal terminal; and an output circuit is electrically connected to a first clock signal terminal, a first node, a first power supply terminal, a second power supply terminal, a first output scan signal terminal and a second output scan signal terminal, and is configured to provide the first power supply voltage or the second power supply voltage to the first output scan signal terminal under the control of the first clock signal from the first clock signal terminal and the potential of the first node, and to provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal.

[0006] For example, the input circuit includes: a first input sub-circuit, electrically connected to a first input signal terminal, a second input signal terminal, a first power supply terminal and a light-emitting control signal terminal, and configured to provide a first power supply voltage to the light-emitting control signal terminal under the control of the first input signal and the second input signal; and a second input sub-circuit, electrically connected to a second input signal terminal, a second power supply terminal and a light-emitting control signal terminal, and configured to provide a second power supply voltage to the light-emitting control signal terminal under the control of the second input signal.

[0007] For example, the first input subcircuit includes a first transistor, a second transistor and a third transistor; wherein the control electrode of the first transistor is electrically connected to the first input signal terminal, the first electrode of the first transistor is electrically connected to the second input signal terminal, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the second input signal terminal, the first electrode of the second transistor is electrically connected to the first power supply terminal, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; the control electrode of the third transistor and the second electrode of the first transistor are electrically connected to the second node, and the second electrode of the third transistor and the light-emitting control signal terminal are electrically connected to the first node.

[0008] For example, the second input sub-circuit includes a fourth transistor and a fifth transistor; wherein the control electrode of the fourth transistor is electrically connected to the second input signal terminal, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor and the light-emitting control signal terminal are electrically connected to the first node; and the control electrode of the fifth transistor and the first input sub-circuit are electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifth transistor and the light-emitting control signal terminal are electrically connected to the first node.

[0009] For example, the processing circuit includes: a first processing sub-circuit, electrically connected to a first node, a second node and a second power supply terminal, configured to provide a second power supply voltage to the second node under the control of the potential of the first node; and a second processing sub-circuit, electrically connected to a first input signal terminal, a first node, a second node and a first power supply terminal, configured to provide a first power supply voltage to the second node under the control of the first input signal and the potential of the first node.

[0010] For example, the first processing subcircuit includes a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the second power supply terminal, and a second electrode of the sixth transistor is electrically connected to the second node.

[0011] For example, the second processing sub-circuit includes a seventh transistor and an eighth transistor; wherein the control electrode of the seventh transistor is electrically connected to the first input signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and the control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor and the first processing sub-circuit are electrically connected to the second node.

[0012] For example, the output circuit includes: a first output sub-circuit, electrically connected to a first clock signal terminal, a first node, a first power supply terminal, a second power supply terminal and a first output scan signal terminal, and configured to provide a first power supply voltage or a second power supply voltage to the first output scan signal terminal under the control of the potential of the first clock signal and the first node; and a second output sub-circuit, electrically connected to the first output scan signal terminal, the first power supply terminal, the second power supply terminal and the second output scan signal terminal, and configured to provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal.

[0013] For example, the first output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; wherein the control electrode of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the first output scan signal terminal; the control electrode of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is electrically connected to the first output scan signal terminal; the control electrode of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the second power supply terminal; and the control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the first output scan signal terminal.

[0014] For example, the second output sub-circuit includes a thirteenth transistor and a fourteenth transistor; wherein the control electrode of the thirteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second output scan signal terminal; and the control electrode of the fourteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the second output scan signal terminal.

[0015] For example, the shift register also includes: a first control circuit, electrically connected to a second clock signal terminal, a first output scan signal terminal, a second output scan signal terminal, a third output scan signal terminal and a fourth output scan signal terminal, and configured to provide the potential of the first output scan signal terminal to the third output scan signal terminal and to provide the potential of the second output scan signal terminal to the fourth output scan signal terminal under the control of a second clock signal from the second clock signal terminal.

[0016] For example, the first control circuit includes a fifteenth transistor and a sixteenth transistor; wherein the control electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the fifteenth transistor is electrically connected to the second output scan signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth output scan signal terminal; and the control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first output scan signal terminal, and the second electrode of the sixteenth transistor is electrically connected to the third output scan signal terminal.

[0017] For example, the shift register also includes: a second control circuit, electrically connected to a third clock signal terminal, an input circuit, a first input signal terminal and a second input signal terminal, and configured to provide the first input signal and the second input signal to the input circuit under the control of a third clock signal from the third clock signal terminal; wherein the first input signal terminal and the second input signal terminal are electrically connected to the input circuit through the second control circuit.

[0018] For example, the second control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; wherein the control electrode of the seventeenth transistor is electrically connected to the third clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the first input signal terminal, and the second electrode of the seventeenth transistor and the input circuit are electrically connected to the third node; the control electrode of the eighteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the eighteenth transistor is electrically connected to the second input signal terminal, and the second electrode of the eighteenth transistor and the input circuit are electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first input signal terminal, and the second electrode of the nineteenth transistor and the input circuit are electrically connected to the fourth node; and the control electrode of the twentieth transistor is electrically connected to the third clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the second input signal terminal, and the second electrode of the twentieth transistor and the input circuit are electrically connected to the fourth node.

[0019] According to the second aspect, the present disclosure provides a driving circuit, comprising M cascaded shift registers provided by embodiments of the present disclosure, where M is a positive integer greater than 1; the first input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the m-1-th shift register, and the second input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the m+1-th shift register, 1<m≤M-1.

[0020] For example, the first input signal terminal of the 1st stage shift register is electrically connected to the scan trigger signal terminal, and the second input signal terminal of the Mth stage shift register is electrically connected to the anti-static terminal.

[0021] According to a third aspect, the present disclosure provides a display device, including the driving circuit provided by an embodiment of the present disclosure.

[0022] According to a fourth aspect, the present disclosure provides a driving method, which is applied to a shift register provided by an embodiment of the present disclosure, including: in a first stage, the first input signal from the first input signal terminal is a first level and the second input signal from the second input signal terminal is a second level, the first power supply voltage of the first power supply terminal is provided to the light-emitting control signal terminal and the first node, and the second power supply voltage of the second power supply terminal is provided to the second node; in a second stage, the first input signal and the second input signal are both at the second level, the first power supply voltage is provided to the light-emitting control signal terminal and the first node, and the second power supply voltage is provided to the second node; in a third stage, the first input signal is the second level and the second input signal is the first level, the second power supply voltage is provided to the light-emitting control signal terminal and the first node, and the first power supply voltage is provided to the second node; and in a fourth stage, the first input signal and the second input signal are both at the second level, the second power supply voltage is provided to the light-emitting control signal terminal and the first node, and the first power supply voltage is provided to the second node.

[0023] For example, the driving method further includes: in the first stage, the first clock signal from the first clock signal terminal is at a first level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0024] For example, the second stage includes a first sub-stage, a second sub-stage and a third sub-stage, and the method also includes: in the first sub-stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal; in the second sub-stage, the first clock signal is at the first level, the second power supply voltage is provided to the first output scan signal terminal, and the first power supply voltage is provided to the second output scan signal terminal; and in the third sub-stage, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0025] For example, the driving method further includes: in the third stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0026] For example, the driving method further includes: in the fourth stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0027] For example, the driving method also includes: when it is determined that the current display data of the display area driven by the shift register is the same as the previous display data, setting the second clock signal from the second clock signal end to the second level; and when it is determined that the current display data of the designated display area driven by the shift register is different from the previous display data, setting the second clock signal to the first level; wherein the display area is the display area where the pixel row driven by the shift register is located, the current display data is the data displayed by the pixel row driven by the shift register in the current working cycle, and the previous display data is the multi-frame display data displayed in multiple consecutive working cycles before the current working cycle.

[0028] For example, the driving method further includes: in the first stage, the third clock signal from the third clock signal terminal is at the first level; in the third stage, the third clock signal is at the first level; and in the fourth stage, the third clock signal is at the second level.

[0029] For example, the driving method further includes: in the first sub-stage, the third clock signal from the third clock signal terminal is at the second level; in the second sub-stage, the third clock signal is at the first level; and in the third sub-stage, the third clock signal is at the second level.

[0030] FIG. 1A is a schematic diagram of a pixel circuit of an example;

[0031] FIG1B is a signal timing diagram of the pixel circuit in FIG1A ;

[0032] FIG. 2A is a schematic diagram of a structure of an exemplary driving circuit;

[0033] FIG2B is a schematic diagram of a light emitting control signal output by the driving circuit in FIG2A;

[0034] FIG3 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0035] FIG4 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0036] FIG5A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0037] FIG5B is a signal timing diagram of the shift register in FIG5A ;

[0038] 6A to 6F are equivalent circuit diagrams of a shift register at different stages according to an embodiment of the present disclosure;

[0039] FIG7A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0040] FIG7B is a schematic diagram of refreshing a pixel array according to an embodiment of the present disclosure;

[0041] FIG8A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0042] 8B and 8C are signal timing diagrams of the shift register in FIG. 8A ;

[0043] FIG9 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0044] FIG10A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0045] FIG10B is a signal timing diagram of the shift register in FIG10A ;

[0046] FIG11 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0047] FIG12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure; and

[0048] FIG. 13 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0049] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0050] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0051] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0052] The source and drain of the switch transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiment of the present disclosure, according to its function, the gate can be called the control electrode, one of the source and the drain can be called the first electrode, and the other of the source and the drain can be called the second electrode.

[0053] In addition, in the description of the embodiments of the present disclosure, the terms "first power supply voltage" and "second power supply voltage" are only used to distinguish that the amplitudes of the two power supply voltages are different. For example, the following description is made by taking the "first power supply voltage" as a relatively high voltage and the "second power supply voltage" as a relatively low voltage as an example. Those skilled in the art will understand that the present disclosure is not limited to this.

[0054] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vdata can represent both a data signal and a level of a data signal. Similarly, the symbol Gate can represent both a gate drive signal and a level of a gate drive signal, the symbol VINT can represent both a predetermined initial voltage terminal and a voltage of an initial signal, the symbol ELVDD can represent both a power supply and a power supply voltage provided by the power supply, INPUT can represent both an input signal terminal and an input signal provided by the input signal terminal, OUTPUT can represent both an output signal terminal and an output signal output by the output signal terminal, and VGH and VGL can represent both a power supply terminal and a power supply voltage provided by the power supply terminal. The following embodiments are the same and will not be described in detail.

[0055] The pixel unit of the pixel circuit of the LED display panel and the OLED display panel may be a 7T1C structure, that is, each pixel unit includes 7 thin film transistors TFT and 1 capacitor C, as shown in FIG. 1 .

[0056] Fig. 1A is a schematic diagram of the structure of an exemplary pixel circuit. Fig. 1B is a signal timing diagram of the pixel circuit in Fig. 1A.

[0057] In the example of FIG. 1A , the transistors T1 and T2 may be N-type transistors, and the transistors T3 to T7 may be P-type transistors.

[0058] In the example of FIG. 1B , in the initialization phase P1, the level of the gate drive signal Gate(n-1)_N is high. In the data writing phase P2, the level of the gate drive signal Gate(n)_N is high, and the level of the gate drive signal Gate(n)_P is low. In the light emitting phase P3, the level of the light emitting control signal EM is low.

[0059] In the initialization phase P1, under the high level control of the gate drive signal Gate(n-1)_N, the transistor T1 is turned on. The initialization signal VINT initializes the gate of the driving transistor T3, thereby initializing the gate voltage of the driving transistor T3 to VINT, and charging the storage capacitor CST. At this time, the voltage at point N1 is VINT.

[0060] In the data writing phase P2, under the low level control of the gate driving signal Gate(n)_P, the transistor T7 is turned on, and the initialization signal VINT is written to the anode of the light emitting element OLED along the initialization path from the predetermined initial voltage terminal to the light emitting element OLED, thereby initializing the anode voltage of the light emitting element OLED to VINT. This can release the residual charge of the anode of the light emitting element OLED, thereby eliminating the residual voltage of the anode of the light emitting element OLED.

[0061] At this time, under the high level control of the gate drive signal Gate(n)_N, transistor T2 is turned on, and under the low level control of the gate drive signal Gate(n)_P, transistor T4 is turned on. The driving transistor T3 is turned on by the voltage signal stored in the storage capacitor CST. The data signal Vdata is written to the node N1 along the data signal terminal via transistors T4, T3 and T2. At this time, the data signal Vdata can charge the storage capacitor CST, and the driving transistor T3 is gradually turned off. When Vgs=Vg-Vs=Vg-Vdata≥Vth is satisfied, the driving transistor T3 is turned off, and the charging of the storage capacitor CST is completed. At this time, the potential Vg of point N1 is Vth+Vdata.

[0062] It can be understood that Vth is the threshold voltage of the driving transistor T3, Vgs is the gate-source voltage of the driving transistor T3, Vg is the gate voltage of the driving transistor T3, and Vs is the source voltage of the driving transistor T3. The voltage difference (VINT-ELVSS) between the initial signal terminal VINT and the second power supply terminal ELVSS should be less than the threshold voltage Vth of the light-emitting element OLED, thereby ensuring that the light-emitting element OLED does not emit light during the data writing stage.

[0063] In the light-emitting stage P3, under the low level control of the light-emitting control signal EM, transistors T5 and T6 are turned on. At this time, the source potential Vs of the driving transistor T3 is Vdd, the gate potential Vg is Vth+Vdata, Vgs is Vth+Vdata-Vdd<Vth, and the driving transistor T3 is turned on under the drive of the voltage signal stored in the storage capacitor CST. Transistors T5 and T6 are turned on, the voltage of the first power supply terminal ELVDD is written into the circuit, and the driving current is applied to the light-emitting element OLED along the light-emitting path from the power supply to the light-emitting element OLED via the transistor T5, the driving transistor T3 and the transistor T6 to make the light-emitting element OLED emit light. At this time, the current Id flowing through the pixel is A(Vdd-Vdata) 2 , where A is a constant.

[0064] The display may include a pixel array and a GOA circuit, the pixel array including a plurality of pixel circuits arranged in an array, each pixel circuit may be as shown in FIG. 1A, and the pixel array is used to display a picture. The GOA circuit is used to provide a drive signal for the pixel array. For example, the GOA circuit may include a plurality of cascaded GOA units, and each level of GOA units provides a drive signal to a row of pixel units in the pixel array. For example, the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P may be gate drive signals provided by a level of GOA units corresponding to a row of pixel units, and the gate drive signal Gate(n-1)_N may be a gate drive signal provided by a previous level of GOA units.

[0065] The emission control signal EM may also be provided by an emission control signal driving (Emission On Array, EOA) circuit. The EOA circuit includes a plurality of cascaded EOA units, and each stage of EOA units provides the emission control signal EM to a row of pixel units in the pixel array.

[0066] Therefore, the pixel circuit composed of the pixel unit shown in FIG1 requires three sets of driving circuits to provide driving signals. For example, two sets of GOA circuits provide gate driving signals Gate(n)_N and gate driving signals Gate(n)_P respectively, and one set of EOA circuits provides the light emitting control signal EM. In the display, three sets of driving circuits will occupy a large space, which makes it difficult to narrow the border of the display.

[0067] In view of the above problems, the present disclosure provides a shift register, with one shift register as a GOA unit, through which a gate drive signal Gate(n)_N, a gate drive signal Gate(n)_P and a light-emitting control signal EM can be provided for a corresponding row of pixel units. A group of GOA circuits is obtained by cascading multiple shift registers provided by the present disclosure, and the group of GOA circuits can be used to provide a gate drive signal Gate(n)_N, a gate drive signal Gate(n)_P and a light-emitting control signal EM for a pixel array in a display.

[0068] Fig. 2A is a schematic diagram of the structure of an exemplary driving circuit. Fig. 2B is a schematic diagram of a light emitting control signal output by the driving circuit in Fig. 2A.

[0069] Fig. 2A shows an EOA unit 200a of an EOA circuit. Each EOA unit 200a may include 12 transistors and 3 capacitors, as shown in Fig. 2A.

[0070] In the example of FIG. 2A , transistors T1 to T12 may be P-type transistors, the output terminal EMOUTPUT outputs the light emission control signal EM, the input terminal ESTV provides a trigger signal, and the clock signal terminals ECK and ECB provide clock signals. The power supply terminal VGH may provide a power supply voltage VGH having a high level, and the power supply terminal VGL may provide a power supply voltage VGL having a low level, and the power supply voltage VGH is greater than the power supply voltage VGL.

[0071] In the EOA unit 200a, the light emission control signal EM outputted from the output terminal EMOUTPUT is controlled by the transistor T9 and the transistor T10. When the transistor T9 is turned on and the transistor T10 is turned off, the light emission control signal EM outputted from the output terminal EMOUTPUT is at a high level. When the transistor T9 is turned off and the transistor T10 is turned on, the light emission control signal EM outputted from the output terminal EMOUTPUT is at a low level.

[0072] The gate of transistor T9 is affected by the capacitance stored in capacitor C1, and the gate of transistor T10 is affected by the capacitance stored in capacitor C3. Since the capacitance stored in the capacitor is unstable, the potential of the output light emitting control signal EM will drift, as shown in FIG2B.

[0073] FIG2B shows the potential change process of the light emitting control signal EM output by the EOA unit 200a of FIG2A. In the potential change 200b of the light emitting control signal EM, in the process of dropping from a high level to a low level, the potential of the light emitting control signal EM in the region 210 is pulled down twice, which causes the light emitting control signal EM to drift and be easily disturbed by the outside world. Therefore, the design of the capacitor in the EOA unit shown in FIG2A affects the stability of the light emitting control signal EM.

[0074] In view of the above problems, the present disclosure provides a shift register, which is used as an EOA unit. The shift register includes multiple transistors and does not require a capacitor structure. A processing circuit is set in the shift register to maintain the stable output of the light emitting control signal EM so that the output light emitting control signal EM has no drift phenomenon.

[0075] FIG. 3 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0076] As shown in FIG. 3 , the shift register 300 includes an input circuit 310 , a processing circuit 320 , and an output circuit 330 .

[0077] In the embodiment of the present disclosure, the input circuit 310 is electrically connected to the first input signal terminal INPUT1, the second input signal terminal INPUT2, the first power terminal VGH, the second power terminal VGL and the emission control signal terminal EM. The input circuit 310 can output the emission control signal EM.

[0078] The input circuit 310 is configured to provide a first power supply voltage of the first power supply terminal VGH or a second power supply voltage of the second power supply terminal VGL to the first node A under the control of a first input signal from the first input signal terminal INPUT1 and a second input signal from the second input signal terminal INPUT1. The light emission control signal terminal EM is electrically connected to the first node A.

[0079] The processing circuit 320 is electrically connected to the first input signal terminal INPUT1, the first node A1, the first power terminal VGH and the second power terminal VGL. The processing circuit 320 can maintain the input circuit 310 to output a stable light emitting control signal EM.

[0080] The processing circuit 320 is configured to provide the first power supply voltage VGH or the second power supply voltage VGL to the second node B under the control of the potential of the first node A and the first input signal INPUT1. The input circuit 310 is electrically connected to the second node B. Under the control of the potential of the second node B, the input circuit 310 provides the first power supply voltage VGH or the second power supply voltage VGL to the light emitting control signal terminal EM.

[0081] For example, when the first power supply voltage VGH is provided to the first node A, the processing circuit 320 may provide the second power supply voltage VGL to the second node B under the control of the potential of the first node A and the first input signal INPUT1. Under the control of the potential of the second node B, the input circuit 310 provides the first power supply voltage VGH to the light emitting control signal terminal EM.

[0082] For example, when the second power supply voltage VGL is provided to the first node A, the processing circuit 320 may provide the first power supply voltage VGH to the second node B under the control of the potential of the first node A and the first input signal INPUT1. Under the control of the potential of the second node B, the input circuit 310 provides the second power supply voltage VGL to the light emitting control signal terminal EM.

[0083] This enables a stable feedback closed loop to be formed between the input circuit 310 and the processing circuit 320 , thereby maintaining the input circuit 310 outputting a stable light emission control signal EM.

[0084] The output circuit 330 is electrically connected to the first clock signal terminal CLK1, the first node A, the first power supply terminal VGH, the second power supply terminal VGL, the first output scan signal terminal OUTPUT1 and the second output scan signal terminal PUTPUT2. The output circuit 330 can output a scan signal, and the scan signal can be used as a gate drive signal. For example, the first output scan signal terminal OUTPUT1 outputs a gate drive signal Gate(n)_P, and the second output scan signal terminal PUTPUT2 outputs a gate drive signal Gate(n)_N.

[0085] The output circuit 330 is configured to provide the first power supply voltage VGH or the second power supply voltage VGL to the first output scan signal terminal OUTPUT1 under the control of the potential of the first node A and the first clock signal from the first clock signal terminal CLK, and to provide the first power supply voltage VGH or the second power supply voltage VGL to the second output scan signal terminal OUTPUT2 under the control of the potential of the first output scan signal terminal OUTPUT1.

[0086] In the embodiment of the present disclosure, the shift register 300 may be a driving unit in the driving circuit. The primary driving unit may output a gate driving signal Gate(n)_N, a gate driving signal Gate(n)_P and a light emitting control signal EM. For example, the driving unit may include an EOA unit and a GOA unit, the input circuit 310 and the processing circuit 320 may implement the function of the EOA unit outputting the light emitting control signal EM, and the output circuit 330 may implement the function of the GOA unit outputting the gate driving signal Gate(n).

[0087] In the embodiment of the present disclosure, the first input signal terminal INPUT1 can be the gate drive signal Gate(n-1)_N output by the previous level GOA unit in the driving circuit, and the second input signal terminal INPUT2 can be the gate drive signal Gate(n+1)_N output by the next level GOA unit in the driving circuit.

[0088] In the disclosed embodiment, the input circuit 310, the processing circuit 320 and the output circuit 330 are electrically connected to the first node A. The gate drive signal Gate(n-1)_N from the previous level GOA unit and the gate drive signal Gate(n+1)_N from the second input signal terminal INPUT2 of the next level GOA unit can be the input signal of the EOA unit, and the light-emitting control signal EM is the output signal of the EOA unit. The potential of the light-emitting control signal terminal EM is consistent with the level of the first node A. The light-emitting control signal EM output by the EOA unit can be used as the input signal of the output circuit 330, and the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P are the output signals of the GOA unit.

[0089] Through the shift register 300 provided by the present disclosure, one shift register 300 is used as a driving unit, and one driving unit can provide a gate driving signal Gate(n)_N, a gate driving signal Gate(n)_P and a light emitting control signal EM for a corresponding row of pixel units in a pixel array, thereby reducing the occupied space of the driving circuit, which is conducive to narrowing the border of the display. In addition, the processing circuit 320 in the shift register 300 is used to maintain the stable output of the light emitting control signal EM, so that the output light emitting control signal EM has no drift phenomenon.

[0090] It should be noted that the first node A and the second node B do not represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.

[0091] FIG. 4 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0092] As shown in Fig. 4, the shift register 400 includes an input circuit 410, a processing circuit 420 and an output circuit 430. The input circuit 410, the processing circuit 420 and the output circuit 430 are similar to the input circuit 310, the processing circuit 320 and the output circuit 330 mentioned above, respectively. For the sake of simplicity, the same parts are not repeated in this disclosure.

[0093] In the embodiment of the present disclosure, the input circuit 410 includes a first input sub-circuit 411 and a second input sub-circuit 412 .

[0094] In the embodiment of the present disclosure, the first end of the first input subcircuit 411 and the first end of the second input subcircuit 412 are electrically connected to the first node A, and the first node A is electrically connected to the light emitting control terminal EM. The second end of the first input subcircuit 411 and the second end of the second input subcircuit 412 are electrically connected to the second node B.

[0095] The first input subcircuit 411 is electrically connected to the first input signal terminal INPUT1, the second input signal terminal INPUT1, the first power supply terminal VGH and the emission control signal terminal EM. The first input subcircuit 411 is configured to provide the first power supply voltage VGH to the emission control signal terminal under the control of the first input signal and the second input signal.

[0096] The second input sub-circuit 412 is electrically connected to the second input signal terminal INPUT1, the second power supply terminal VGL and the emission control signal terminal EM. The second input sub-circuit 412 is configured to provide the second power supply voltage VGL to the emission control signal terminal EM under the control of the second input signal.

[0097] For example, the first input sub-circuit 411 may be used to output a light emitting control signal EM having a high potential, and the second input sub-circuit 412 may be used to output a light emitting control signal EM having a low potential.

[0098] In the embodiment of the present disclosure, the processing circuit 420 includes a first processing sub-circuit 421 and a second processing sub-circuit 422 .

[0099] In the embodiment of the present disclosure, the first end of the first processing subcircuit 421 and the first end of the second processing subcircuit 422 are electrically connected to the first node A, and the first node A is electrically connected to the light emitting control terminal EM. The second end of the first processing subcircuit 421 and the second end of the second processing subcircuit 422 are electrically connected to the second node B.

[0100] The first processing sub-circuit 421 is electrically connected to the first node A, the second node B and the second power supply terminal VGL. Under the control of the potential of the first node A, the first processing sub-circuit 421 provides the second power supply voltage VGL to the second node B.

[0101] The second processing subcircuit 422 is electrically connected to the first input signal terminal INPUT, the first node A, the second node B and the first power supply terminal VGH. Under the control of the potential of the first node A and the first input signal, the second processing subcircuit 422 provides the first power supply voltage VGH to the second node B.

[0102] In the embodiment of the present disclosure, the first end of the first input subcircuit 411 and the first end of the first processing subcircuit 421 are electrically connected to the first node A, and the second end of the first input subcircuit 411 and the second end of the first processing subcircuit 421 are electrically connected to the second node B.

[0103] When the first input sub-circuit 411 can output the light emitting control signal EM with a high potential, under the control of the potential of the first node A, the first processing sub-circuit 421 provides the second power supply voltage VGL to the second node B. At this time, under the control of the potential of the second node B, the first input sub-circuit 411 provides the first power supply voltage VGH to the light emitting control signal terminal EM. This allows a stable feedback to be formed between the first input sub-circuit 411 and the first processing sub-circuit 421, so that the first input sub-circuit 411 can output a stable light emitting control signal EM.

[0104] In the embodiment of the present disclosure, the first end of the second input subcircuit 412 and the first end of the second processing subcircuit 422 are electrically connected to the first node A, and the second end of the second input subcircuit 412 and the second end of the second processing subcircuit 422 are electrically connected to the second node B.

[0105] When the second input subcircuit 412 can output the light emitting control signal EM with a low potential, under the control of the potential of the first node A, the second processing subcircuit 422 provides the first power supply voltage VGH to the second node B. At this time, under the control of the potential of the second node B, the second input subcircuit 412 provides the second power supply voltage VGL to the light emitting control signal terminal EM. This allows a stable feedback to be formed between the second input subcircuit 412 and the second processing subcircuit 422, so that the second input subcircuit 412 can output a stable light emitting control signal EM.

[0106] In the embodiment of the present disclosure, the output circuit 430 includes a first output sub-circuit 431 and a second output sub-circuit 432 .

[0107] In the embodiment of the present disclosure, the first end of the first output subcircuit 431 is electrically connected to the first node A, and the second end of the first output subcircuit 431 and the first end of the second output subcircuit 432 are electrically connected to the first output scan signal terminal OUTPUT1. The second end of the second output subcircuit 432 is electrically connected to the second output scan signal terminal OUTPUT2.

[0108] The first output sub-circuit 431 is electrically connected to the first clock signal terminal CLK1, the first node A, the first power supply terminal VGH, the second power supply terminal VGL and the first output scan signal terminal OUTPUT1. Under the control of the potential of the first node A and the first clock signal CLK1, the first output sub-circuit 431 provides the first power supply voltage VGH or the second power supply voltage VGL to the first output scan signal terminal.

[0109] The second output sub-circuit 432 is electrically connected to the first output scan signal terminal OUTPUT1, the first power terminal VGH, the second power terminal VGL and the second output scan signal terminal OUTPUT2. Under the control of the potential of the first output scan signal terminal, the second output sub-circuit 432 provides the first power voltage VGH or the second power voltage VGL to the second output scan signal terminal.

[0110] For example, when the first output subcircuit 431 outputs a gate drive signal Gate(n)_P having a high potential, the second output subcircuit 432 outputs a gate drive signal Gate(n)_N having a low potential. When the first output subcircuit 431 outputs a gate drive signal Gate(n)_P having a low potential, the second output subcircuit 432 outputs a gate drive signal Gate(n)_N having a high potential.

[0111] FIG. 5A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0112] As shown in Fig. 5A, the shift register 500 includes an input circuit 510, a processing circuit 520, and an output circuit 530. The input circuit 510 includes a first input subcircuit 511 and a second input subcircuit 512. The processing circuit 520 includes a first processing subcircuit 521 and a second processing subcircuit 522. The output circuit 530 includes a first output subcircuit 531 and a second output subcircuit 532.

[0113] The input circuit 510, the processing circuit 520 and the output circuit 530 are similar to the input circuit 310, the processing circuit 320 and the output circuit 330 described above, respectively; the first input subcircuit 511 and the second input subcircuit 512 are similar to the first input subcircuit 411 and the second input subcircuit 412 described above, respectively; the first processing subcircuit 521 and the second processing subcircuit 522 are similar to the first processing subcircuit 421 and the second processing subcircuit 422 described above, respectively; the first output subcircuit 531 and the second output subcircuit 532 are similar to the first output subcircuit 431 and the second output subcircuit 432 described above, respectively. For the sake of simplicity, the same parts of the present disclosure will not be repeated here.

[0114] In the embodiment of the present disclosure, the first input subcircuit 511 includes a first transistor T1, a second transistor T2 and a third transistor T3. The first transistor T1, the second transistor T2 and the third transistor T3 are used as switch transistors. The first transistor T1 is an N-type transistor, and the second transistor T2 and the third transistor T3 are P-type transistors.

[0115] The gate of the first transistor T1 is electrically connected to the first input signal terminal Gate(n-1)_N, the first electrode of the first transistor T1 is electrically connected to the second input signal terminal Gate(n+1)_N, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the second transistor T2 is electrically connected to the second input signal terminal Gate(n+1)_N, the first electrode of the second transistor T2 is electrically connected to the first power supply terminal VGH, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3. The gate of the third transistor T3 and the second electrode of the first transistor T1 are electrically connected to the second node B, and the second electrode of the third transistor T3 and the light emitting control signal terminal EM(n) are electrically connected to the first node A.

[0116] The second input sub-circuit 512 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 are used as switch transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type transistors.

[0117] The gate of the fourth transistor T4 is electrically connected to the second input signal terminal Gate(n+1)_N, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 and the light emission control signal terminal EM(n) are electrically connected to the first node A. The gate of the fifth transistor T5 and the gate of the third transistor T3 in the first input sub-circuit 410 are electrically connected to the second node B, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal VGL, and the second electrode of the fifth transistor T5 and the light emission control signal terminal EM(n) are electrically connected to the first node A.

[0118] In the embodiment of the present disclosure, the first processing sub-circuit 521 includes a sixth transistor T6. The sixth transistor T6 is used as a switch transistor, and the sixth transistor T6 is an N-type transistor.

[0119] A gate electrode of the sixth transistor T6 is electrically connected to the first node A, a first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and a second electrode of the sixth transistor T6 is electrically connected to the second node B.

[0120] In the embodiment of the present disclosure, the second processing sub-circuit 522 includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 are used as switch transistors, and the seventh transistor T7 and the eighth transistor T8 are P-type transistors.

[0121] The gate of the seventh transistor T7 is electrically connected to the first input signal terminal Gate(n-1)_N, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the first node A, and the second electrode of the eighth transistor T8 and the second electrode of the sixth transistor T6 in the first processing sub-circuit 521 are electrically connected to the second node B.

[0122] In the embodiment of the present disclosure, the first output sub-circuit 531 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are used as switch transistors, the ninth transistor T9 and the twelfth transistor T12 are P-type transistors, and the tenth transistor T10 and the eleventh transistor T11 are N-type transistors.

[0123] The gate of the ninth transistor T9 is electrically connected to the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the first output scan signal terminal Gate(n)_P. The gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CLK1, the first electrode of the tenth transistor T10 is electrically connected to the second electrode of the eleventh transistor T11, and the second electrode of the tenth transistor T10 is electrically connected to the first output scan signal terminal Gate(n)_P. The gate of the eleventh transistor T11 is electrically connected to the first node A, and the first electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal VGL. The gate of the twelfth transistor T12 is electrically connected to the first node A, the first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VGH, and the second electrode of the twelfth transistor T12 is electrically connected to the first output scan signal terminal Gate(n)_P.

[0124] The second output sub-circuit 532 includes a thirteenth transistor T13 and a fourteenth transistor T14. The thirteenth transistor T13 and the fourteenth transistor T14 are used as switch transistors, the thirteenth transistor T13 is a P-type transistor, and the fourteenth transistor T14 is an N-type transistor.

[0125] The gate of the thirteenth transistor T13 is electrically connected to the first output scan signal terminal Gate(n)_P, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor T13 is electrically connected to the second output scan signal terminal Gate(n)_N. The gate of the fourteenth transistor T14 is electrically connected to the first output scan signal terminal Gate(n)_P, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourteenth transistor T14 is electrically connected to the second output scan signal terminal Gate(n)_N.

[0126] FIG. 5B is a signal timing diagram of the shift register in FIG. 5A. FIG. 5B shows the timing waveforms of each signal in each stage. The structure of the shift register shown in FIG. 5A is taken as an example below, and the working process of the shift register provided by the embodiment of the present invention is described in combination with the signal timing diagram shown in FIG. 5B. The working process of the shift register includes 6 stages.

[0127] FIG6A shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the first stage S1, FIG6B shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the second stage S2, FIG6C shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the third stage S3, FIG6D shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the fourth stage S4, and FIG6E shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the fifth stage S6. FIG6F shows an equivalent circuit diagram of a shift register according to an embodiment of the present disclosure in the sixth stage S5. The dotted lines with arrows in FIG6C to FIG6F indicate the current direction of the shift register in the corresponding stage.

[0128] Next, the operation of the shift register according to the embodiment of the present disclosure will be described in detail with reference to FIGS. 6A to 6F .

[0129] In the first stage S1 , the first input signal Gate(n−1)_N is at a high level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a low level.

[0130] Under the control of the first input signal Gate(n-1)_N, the first transistor T1 is turned on, and the seventh transistor T7 is turned off by the high level of the first input signal Gate(n-1)_N. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 through the first transistor T1. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0131] The first power supply voltage VGH is provided to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is at a high level, and the light emitting control signal EM(n) outputted by the light emitting control signal terminal EM(n) is at a high level.

[0132] The sixth transistor T6 is turned on under the control of the high level of the first node A. The eighth transistor T8 is turned off by the high level of the first node A. The second power supply voltage VGL is provided to the second node B through the sixth transistor T6, and the potential of the second node B is at a low level.

[0133] The second node B is electrically connected to the gate of the third transistor T3. Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0134] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first voltage power supply VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0135] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The second power supply voltage VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0136] In the second stage S2 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a low level.

[0137] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0138] Since the gate of the third transistor T3 does not receive an external voltage, the third transistor T3 is in a latched state, and the third transistor T3 remains in the same on state as in the first stage S1. The first power supply voltage VGH is provided to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is at a high level, and the light emitting control signal EM(n) output by the light emitting control signal terminal EM(n) is at a high level.

[0139] The sixth transistor T6 is turned on under the control of the high level of the first node A. The eighth transistor T8 is turned off by the high level of the first node A. The second power supply voltage VGL is provided to the second node B through the sixth transistor T6, and the potential of the second node B is at a low level.

[0140] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0141] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first voltage power supply VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0142] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The second power supply voltage VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0143] In the third stage S3 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a high level.

[0144] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0145] Since the gate of the third transistor T3 is in a latched state when no external voltage is received, the third transistor T3 remains in the same on state as in the second stage S2. The first power supply voltage VGH is provided to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is at a high level, and the light emitting control signal EM(n) outputted by the light emitting control signal terminal EM(n) is at a high level.

[0146] The sixth transistor T6 is turned on under the control of the high level of the first node A. The eighth transistor T8 is turned off by the high level of the first node A. The second power supply voltage VGL is provided to the second node B through the sixth transistor T6, and the potential of the second node B is at a low level.

[0147] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0148] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the tenth transistor T10 is turned on. The ninth transistor T9 is turned off by the low level of the first clock signal CLK. The second voltage power supply VGL is provided to the first output scan signal terminal Gate(n)_P through the eleventh transistor T11 and the tenth transistor T10, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a low level.

[0149] Under the control of the low level of the first output scan signal terminal Gate(n)_P, the thirteenth transistor T13 is turned on. The fourteenth transistor T14 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The first power supply voltage VGH is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a high level.

[0150] In the fourth stage S4 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a low level.

[0151] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0152] Since the gate of the third transistor T3 is in a latched state when no external voltage is received, the third transistor T3 remains in the same on state as in the third stage S3. The first power supply voltage VGH is provided to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is at a high level, and the light emitting control signal EM(n) outputted by the light emitting control signal terminal EM(n) is at a high level.

[0153] The sixth transistor T6 is turned on under the control of the high level of the first node A. The eighth transistor T8 is turned off by the high level of the first node A. The second power supply voltage VGL is provided to the second node B through the sixth transistor T6, and the potential of the second node B is at a low level.

[0154] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0155] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0156] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0157] In the fifth stage S5 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a high level, and the first clock signal CLK1 is at a low level.

[0158] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the fourth transistor T4 is turned on, and the second transistor T2 is turned off by the low level of the second input signal Gate(n+1)_N. The second power supply voltage VGL is provided to the first node A through the fourth transistor T4. At this time, the potential of the first node A is at a low level, and the light-emitting control signal EM(n) output by the light-emitting control signal terminal EM(n) is at a low level.

[0159] The eighth transistor T8 is turned on under the control of the low level of the first node A. The sixth transistor T6 is turned off by the low level of the first node A. The first power supply voltage VGH is provided to the second node B through the seventh transistor T7 and the eighth transistor T8, and the potential of the second node B is at a high level.

[0160] Under the control of the high level of the second node B, the fifth transistor T5 is turned on, and the third transistor T3 is turned off by the low level of the second node B. When the fifth transistor T5 is in the on state, the second power supply voltage VGL can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0161] Under the control of the low level of the first node A, the twelfth transistor T12 is turned on. The eleventh transistor T11 is turned off by the low level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9 and the twelfth transistor T12, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0162] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0163] In the sixth stage S6 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a low level.

[0164] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0165] Since the gate of the fifth transistor T5 does not receive an external voltage, the fifth transistor T5 is in a latched state, and the fifth transistor T5 remains in the same on state as the fifth stage S5. The second power supply voltage VGL is provided to the first node A through the fifth transistor T5. At this time, the potential of the first node A is at a low level, and the light emitting control signal EM(n) output by the light emitting control signal terminal EM(n) is at a low level.

[0166] The eighth transistor T8 is turned on under the control of the low level of the first node A. The sixth transistor T6 is turned off by the low level of the first node A. The first power supply voltage VGH is provided to the second node B through the seventh transistor T7 and the eighth transistor T8, and the potential of the second node B is at a high level.

[0167] Under the control of the high level of the second node B, the fifth transistor T5 remains in the on state, and the third transistor T3 is turned off by the low level of the second node B. When the fifth transistor T5 remains in the on state, the second power supply voltage VGL can be stably provided to the light emitting control signal terminal EM(n), forming a stable feedback, so that the light emitting control signal terminal EM(n) can output a stable light emitting control signal EM(n).

[0168] Under the control of the low level of the first node A, the twelfth transistor T12 is turned on. The eleventh transistor T11 is turned off by the low level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9 and the twelfth transistor T12, and the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0169] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0170] In the examples of FIG. 5A and FIG. 6A to FIG. 6F, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the fourteenth transistor T14 are N-type transistors, and the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12 and the thirteenth transistor T13 are P-type transistors. Those skilled in the art can understand that according to the embodiment of the present disclosure, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11 and the fourteenth transistor T14 can also be P-type transistors, and the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12 and the thirteenth transistor T13 can also be N-type transistors, and the level of the gate turn-on signal of each transistor can be changed accordingly.

[0171] In the embodiment of the present disclosure, in the cascaded multiple shift registers 500, the first clock signal terminal CLK1 of the odd-numbered shift register unit is electrically connected to the clock signal terminal CLK to receive the clock signal CLK, and the first clock signal terminal CLK1 of the even-numbered shift register unit is electrically connected to the clock signal terminal CLB to receive the clock signal CLB.

[0172] For example, the clock signal CLB and the clock signal CLK alternately appear at high levels in timing. For example, the shift register 500 may be an n-th stage shift register, where n is a positive integer, and n is an odd number greater than 1. The n-th stage shift register receives the clock signal CLK, and the n-1-th stage shift register and the n+1-th stage shift register receive the clock signal CLB.

[0173] For example, the odd-numbered shift register units write the high level of the clock signal CLK into the gate drive signal Gate(n)_N, and the even-numbered shift register units write the high level of the clock signal CLB into the gate drive signal Gate(n+1)_N and the gate drive signal Gate(n-1)_N.

[0174] In the shift register 500 provided in the present disclosure, by controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5, the light control signal EM(n) is output. By controlling the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, the stable output of the light control signal EM(n) is maintained. By controlling the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12, the gate drive signal Gate(n)_P is output. By controlling the thirteenth transistor T13 and the fourteenth transistor T14, the gate drive signal Gate(n)_N is output. By using the shift register 500 provided in the present disclosure, the gate drive signal Gate(n)_N, the gate drive signal Gate(n)_P and the light control signal EM(n) signal can be provided for the corresponding row of pixel units in the pixel array, thereby reducing the occupied space of the drive circuit and facilitating narrowing the frame of the display. In addition, the shift register 500 provided by the present disclosure does not have a capacitor structure, and maintains a stable output of the light emitting control signal EM(n) through a transistor structure, so that the output light emitting control signal EM(n) has no drift phenomenon.

[0175] FIG. 7 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0176] As shown in Fig. 7, the shift register 700 includes an input circuit 710, a processing circuit 720, an output circuit 730 and a first control circuit 740. The input circuit 710, the processing circuit 720 and the output circuit 730 are similar to the input circuit 510, the processing circuit 520 and the output circuit 530 mentioned above, respectively. For the sake of simplicity, the same parts are not repeated in this disclosure.

[0177] In the embodiment of the present disclosure, the first control circuit 740 is electrically connected to the second clock signal terminal CLK2 , the first output scan signal terminal OUTPUT1 , the second output scan signal terminal OUTPUT2 , the third output scan signal terminal OUTPUT3 , and the fourth output scan signal terminal OUTPUT4 .

[0178] Under the control of the second clock signal from the second clock signal terminal CLK2, the first control circuit 740 provides the potential of the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and the first control circuit 740 also provides the potential of the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4.

[0179] In the embodiment of the present disclosure, the first control circuit 740 is electrically connected to the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2 with the output circuit 730. The output circuit 730 outputs the gate drive signal Gate(n)_P and the gate drive signal Gate(n)_N through the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2, respectively. Under the control of the second clock signal CLK2, the first control circuit 740 can control whether to output the gate drive signal Gate(n)_P and the gate drive signal Gate(n)_N to the pixel row corresponding to the pixel array.

[0180] For example, the first control circuit 740 may output the gate driving signal Gate(n)_P outputted from the first output scanning signal terminal OUTPUT1 to the third output scanning signal terminal OUTPUT3, and the third output scanning signal terminal OUTPUT3 provides the gate driving signal Gate(n)_P to the corresponding pixel row. The first control circuit 740 may output the gate driving signal Gate(n)_N outputted from the second output scanning signal terminal OUTPUT2 to the fourth output scanning signal terminal OUTPUT4, and the fourth output scanning signal terminal OUTPUT4 provides the gate driving signal Gate(n)_N to the corresponding pixel row.

[0181] For example, the first control circuit 740 can also control the gate drive signal Gate(n)_P that is not output from the first output scan signal terminal OUTPUT1 to be output to the third output scan signal terminal OUTPUT3, and control the gate drive signal Gate(n)_N that is output from the second output scan signal terminal OUTPUT2 not to be output to the fourth output scan signal terminal OUTPUT4.

[0182] In an embodiment of the present disclosure, the shift register 700 can be used to set different refresh frequencies for different pixel rows of the pixel array. For example, the display screen may include a static screen and a dynamic screen. For example, the static screen may be the background portion of the display screen where the screen does not change, and the dynamic screen may be the portion of the display screen where the screen changes. When the display displays a screen, a static screen may appear on the display screen for a period of time. If both the static screen and the dynamic screen are refreshed at the same refresh rate (for example, a high frequency), a large power consumption will be generated. If the dynamic screen portion is set to maintain the original high-frequency refresh, and the static screen portion is set to refresh the screen at a relatively low refresh frequency, the refresh power consumption can be reduced.

[0183] For example, the frame refresh rate of the dynamic image portion can be set to 120 Hz. In 1 second, the display image refreshes 120 frames.

[0184] Accordingly, the frame refresh rate of the static image portion can also be set to 60 Hz or 30 Hz. When the frame refresh rate is 60 Hz, the display image refreshes 60 frames within 1 second. When the frame refresh rate is 30 Hz, the display image refreshes 30 frames within 1 second.

[0185] To achieve a frame refresh rate of 120 Hz for the display screen, the cascaded shift registers 700 provide the pixel array with gate drive signals Gate(n)_N and Gate(n)_P to the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2, respectively.

[0186] In this case, for the pixel rows displaying dynamic images in the pixel array, the corresponding shift register 700 can provide all the gate drive signals Gate(n)_P outputted from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and provide all the gate drive signals Gate(n)_N outputted from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4, thereby enabling the pixel rows displaying dynamic images to refresh 120 frames per second, achieving a frame refresh rate of 120 Hz.

[0187] For pixel rows displaying static images in the pixel array, the corresponding shift register 700 can provide part of the gate drive signal Gate(n)_P output by the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and provide part of the gate drive signal Gate(n)_N output by the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4, thereby reducing the refresh times of the pixel rows displaying static images.

[0188] FIG. 7B is a schematic diagram of refreshing a pixel array according to an embodiment of the present disclosure.

[0189] As shown in FIG7B , with the frame refresh rate of 120 Hz as a reference, the 120 frames displayed per second are divided into four parts according to the order of display. For example, the first part is the 1st to 30th frames, the second part is the 31st to 60th frames, the third part is the 61st to 90th frames, and the fourth part is the 91st to 120th frames.

[0190] When the frame refresh rate is set to 120Hz, it can be considered that the pixel array displays 4 parts of data per second. If the pixel array only displays the first and third parts of data per second, the frame refresh rate can be considered equivalent to 60Hz. If the pixel array only displays the first part of data per second, the frame refresh rate can be considered equivalent to 30Hz.

[0191] As shown in FIG. 7B , the solid line portion represents the displayed data, and the dotted line portion represents the data that is not displayed. Understandably, each pixel row of the pixel array is refreshed at the same speed. When the display screen refreshes a frame of the picture, multiple pixel rows can be refreshed line by line once. When the display screen refreshes 120 frames of the picture within 1 second, multiple pixel rows are refreshed line by line 120 times. For example, the pixel array may include 2000 rows of pixel rows, and after refreshing once line by line from the 1st row of pixel rows to the 2000th row of pixel rows, the display screen completes the refresh of one frame of the picture.

[0192] For pixel rows that display dynamic images in the pixel array, the pixel rows can be refreshed 120 times per second, so the refresh rate of the pixel rows can be considered to be equivalent to 120Hz. For pixel rows that display static images in the pixel array, the pixel rows can be refreshed only for the first 30 times per second, and not for the last 90 times, so the refresh rate of the pixel rows can be considered to be equivalent to 30Hz. For pixel rows that display static images in the pixel array, the pixel rows can also be refreshed only for the first 30 times and the 61st to 90th times per second, and not for the 31st to 60th times and the last 30 times, so the refresh rate of the pixel rows can be considered to be equivalent to 60Hz.

[0193] When the pixel row is set to be refreshed only for the first 30 times per second, the corresponding shift register provides the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P only in the first 30 refreshes. When the pixel row is set to be refreshed only for the first 30 times and the 61st to 90th times per second, the corresponding shift register provides the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P only in the first 30 times and the 61st to 90th refreshes.

[0194] For example, each time the shift register passes through the first stage S1 to the sixth stage S6, it can provide the gate driving signal Gate(n)_N and the gate driving signal Gate(n)_P that are refreshed once for the corresponding three rows of pixels (the n-1th row, the nth row and the n+1th row).

[0195] In the embodiment of the present disclosure, the frame refresh rate of the dynamic picture can be set to 120Hz, and the frame refresh rate of the static picture can be set to 30Hz. Accordingly, under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the dynamic picture can be set to the on state during 120 refresh processes, and the gate drive signal Gate(n)_P output by the first output scan signal terminal OUTPUT1 is all provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output by the second output scan signal terminal OUTPUT2 is all provided to the fourth output scan signal terminal OUTPUT4. Under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the static picture can be set to the on state only during the first 30 refresh processes, and set to the off state during the next 90 refresh processes. Therefore, only in the first 30 refresh processes, the gate drive signal Gate(n)_P outputted from the first output scan signal terminal OUTPUT1 is fully provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N outputted from the second output scan signal terminal OUTPUT2 is fully provided to the fourth output scan signal terminal OUTPUT4. In the 31st to 120th refresh processes, the gate drive signal Gate(n)_P outputted from the first output scan signal terminal OUTPUT1 is not provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N outputted from the second output scan signal terminal OUTPUT2 is not provided to the fourth output scan signal terminal OUTPUT4, and the pixel rows of the static picture are not refreshed, and the pictures displayed in the first 30 refreshes are kept displayed.

[0196] In the embodiment of the present disclosure, the refresh rate of the pixel row of the dynamic picture can be set to 120Hz, and the refresh rate of the pixel row of the static picture can be set to 60Hz. Accordingly, under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the dynamic picture can be set to the on state during the 120 refresh processes, and the gate drive signal Gate(n)_P output by the first output scan signal terminal OUTPUT1 is all provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output by the second output scan signal terminal OUTPUT2 is all provided to the fourth output scan signal terminal OUTPUT4. Under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the static picture can be set to the on state only in the first 30 refresh processes and the 61st to 90th refresh processes, and set to the off state in the 31st to 60th and the last 30 refresh processes. Therefore, only in the first 30 and 61st to 90th refresh processes, the gate drive signal Gate(n)_P output by the first output scan signal terminal OUTPUT1 is all provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output by the second output scan signal terminal OUTPUT2 is all provided to the fourth output scan signal terminal OUTPUT4. During the 31st to 60th refresh process, the pixel rows of the static picture are not refreshed, and the picture displayed in the first 30 refreshes is kept displayed. During the 91st to 120th refresh process, the pixel rows of the static picture are not refreshed, and the picture displayed in the 61st to 90th refreshes is kept displayed.

[0197] Through the embodiment of the present disclosure, by setting the first control circuit 740 to control the output period of the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P, the refresh rate of different areas in the pixel array can be flexibly controlled, so that different areas in the pixel array can be refreshed at different refresh rates, thereby reducing refresh power consumption.

[0198] FIG8A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0199] As shown in FIG. 8A , the shift register 800 includes an input circuit 810 , a processing circuit 820 , an output circuit 830 , and a first control circuit 840 .

[0200] The input circuit 810 includes a first input sub-circuit 811 and a second input sub-circuit 812. The processing circuit 820 includes a first processing sub-circuit 821 and a second processing sub-circuit 822. The output circuit 830 includes a first output sub-circuit 831 and a second output sub-circuit 832.

[0201] The input circuit 810, the processing circuit 820, the output circuit 830 and the first control circuit 840 are similar to the input circuit 710, the processing circuit 720, the output circuit 730 and the first control circuit 740 mentioned above, respectively; the first input subcircuit 811 and the second input subcircuit 812 are similar to the first input subcircuit 511 and the second input subcircuit 512 mentioned above, respectively; the first processing subcircuit 821 and the second processing subcircuit 822 are similar to the first processing subcircuit 521 and the second processing subcircuit 522 mentioned above, respectively; the first output subcircuit 831 and the second output subcircuit 832 are similar to the first output subcircuit 531 and the second output subcircuit 532 mentioned above, respectively. For the sake of simplicity, the same parts of the present disclosure will not be repeated here.

[0202] In the embodiment of the present disclosure, the first control circuit 840 includes a fifteenth transistor T15 and a sixteenth transistor T16. The fifteenth transistor T15 and the sixteenth transistor T16 are used as switch transistors, and the fifteenth transistor T15 and the sixteenth transistor T16 are N-type transistors.

[0203] The gate of the fifteenth transistor T15 is electrically connected to the second clock signal terminal CLK2, the first electrode of the fifteenth transistor T15 is electrically connected to the output terminal C(n)_N, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth output scan signal terminal Gate(n)_N. The fourth output scan signal terminal Gate(n)_N provides a gate drive signal Gate(n)_N to the corresponding pixel row. In the cascaded multiple shift registers, the output signal C(n)_N output by the output terminal C(n)_N is the input signal Gate(n+1)_N received by the previous stage shift register, and the output signal C(n)_N output by the output terminal C(n)_N is the input signal Gate(n-1)_N received by the next stage shift register.

[0204] The gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal CLK2, the first electrode of the sixteenth transistor T16 is electrically connected to the output terminal C(n)_P, and the second electrode of the sixteenth transistor T16 is electrically connected to the third output scan signal terminal Gate(n)_P. The third output scan signal terminal Gate(n)_P provides a gate driving signal Gate(n)_P to the corresponding pixel row.

[0205] 8B and 8C are signal timing diagrams of the shift register in FIG8A. FIG8B shows the timing waveform of the second clock signal when the third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N output signals. FIG8C shows the timing waveform of the second clock signal when the third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N do not output signals. The following describes the working process of the shift register provided by the embodiment of the present invention by taking the structure of the shift register shown in FIG8A as an example and combining the signal timing diagrams shown in FIG8B and FIG8C.

[0206] In the shift register 800 , the operation process of the input circuit 810 , the processing circuit 820 , and the output circuit 830 are the same as those shown in FIGS. 6A to 6F . For the sake of simplicity, the same parts will not be described in detail in this disclosure.

[0207] As shown in FIG. 8B , the second clock signal CLK2 is at a high level, the output signal C(n)_P output by the first output subcircuit 831 is at a low level, and the output signal C(n)_N output by the second output subcircuit 832 is at a high level.

[0208] Under the control of the second clock signal CLK2, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on. The output signal C(n)_P is provided to the third output scan signal terminal Gate(n)_P through the sixteenth transistor T16, and the output signal C(n)_N is provided to the fourth output scan signal terminal Gate(n)_N through the fifteenth transistor T15.

[0209] As shown in FIG8C , the second clock signal CLK2 is at a low level, the output signal C(n)_P output by the first output sub-circuit 831 is at a low level, and the output signal C(n)_N output by the second output sub-circuit 832 is at a high level.

[0210] Under the control of the second clock signal CLK2, the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. The third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N do not output signals.

[0211] It should be noted that the second clock signal CLK2, the output signal C(n)_P, and the output signal C(n)_N shown in FIG8B and FIG8C are only exemplary. The present disclosure does not limit the timing changes between the second clock signal CLK2, the output signal C(n)_P, and the output signal C(n)_N. Those skilled in the art can control the output signal C(n)_P and the output signal C(n)_N output by the specific shift register to be provided to a specific pixel row in the pixel array within a specific period by setting the timing of the second clock signal CLK2 accordingly in a specific period according to actual needs.

[0212] In the embodiment of the present disclosure, it can be considered that in each working cycle, the gate drive signal output by the shift register 800 can drive the corresponding pixel row to refresh once. When the shift register drives the corresponding pixel row, when it is determined that the display data of the pixel row in the current working cycle is the same as the previous display data, the second clock signal can be set to a low level. At this time, the corresponding shift register drive control output signal C(n)_P and output signal C(n)_N are not output. When it is determined that the current display data of the pixel row is different from the previous display data, the second clock signal from the second clock signal terminal is set to a high level.

[0213] For example, the display data of the pixel row in each working cycle may be determined according to the data signal provided by the data signal terminal Vdata shown in Fig. 1A. For example, the display data may be a voltage value converted from a pixel value.

[0214] For example, before displaying the display data of the current working cycle, it is possible to determine in advance that the picture displayed in the display area driven by the shift register is a static picture by comparing the display data in the current working cycle with the display data in multiple working cycles before the current working cycle. For example, the display data in the 31st working cycle is compared with the display data in the previous 30 working cycles to determine that the display data in the 31st working cycle is the same as the display data in the previous 30 working cycles. In the 31st working cycle, the second clock signal can be set to a low level. At this time, the output signal C(n)_P and the output signal C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to the shift register 800 is not refreshed.

[0215] For example, the display data in multiple working cycles of each pixel row can also be compared in advance. When it is determined that the display data in multiple working cycles are the same, the second clock signal can be set to a high level in the first part of the working cycles in the multiple working cycles. At this time, the output signal C(n)_P and the output signal C(n)_N are output to the corresponding pixel row, and the shift register 800 refreshes the corresponding pixel row. In the latter part of the working cycle, the second clock signal is set to a low level. At this time, the output signal C(n)_P and the output signal C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to the shift register 800 is not refreshed.

[0216] For example, when it is determined that the display data of 120 working cycles are all the same, the second clock signal is set to a high level in the first 30 working cycles, and is set to a low level in the last 90 working cycles.

[0217] For example, the display data that has not yet been displayed can be compared with the display data currently being displayed in advance. When it is determined that the display data in the subsequent working cycle are the same as the display data currently being displayed, the second clock signal can be set to a low level in the subsequent working cycle. At this time, the output signal C(n)_P and the output signal C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to the shift register 800 is not refreshed.

[0218] For example, the display data in the 31st to 90th working cycle is compared with the display data in the 30th working cycle, and it is determined that the display data in the 31st to 90th working cycle is the same as the display data in the 30th working cycle. In the 31st to 90th working cycle, the second clock signal can be set to a low level. At this time, the output signal C(n)_P and the output signal C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to the shift register 800 is not refreshed.

[0219] In the embodiment of the present disclosure, by setting the first control circuit 740 and designing the timing of the second clock signal CLK2, the time period for providing the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P to the pixel array is controlled, and the refresh rate of different areas in the pixel array can be flexibly controlled to achieve refresh of different areas in the pixel array at different refresh rates.

[0220] FIG. 9 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0221] As shown in Fig. 9, the shift register 900 includes an input circuit 910, a processing circuit 920, an output circuit 930, and a second control circuit 950. The input circuit 910, the processing circuit 920, and the output circuit 930 are similar to the input circuit 510, the processing circuit 520, and the output circuit 530 described above, respectively. For the sake of simplicity, the same parts are not repeated in this disclosure.

[0222] In the embodiment of the present disclosure, the second control circuit 950 is electrically connected to the third clock signal terminal CLK3, the input circuit 910, the first input signal terminal INPUT1, and the second input signal terminal INPUT2. The first input signal terminal INPUT1 and the second input signal terminal INPUT2 are electrically connected to the input circuit 910 through the second control circuit 950. For example, the first input signal of the first input signal terminal INPUT1 is provided to the input circuit 910 through the second control circuit 950, and the second input signal of the second input signal terminal INPUT2 is provided to the input circuit 910 through the second control circuit 950.

[0223] Under the control of the third clock signal from the third clock signal terminal CLK3 , the first input signal and the second input signal are provided to the input circuit 910 .

[0224] In the embodiment of the present disclosure, the second control circuit 950 includes a first output terminal and a second output terminal, and the input circuit 910 includes a first input terminal and a second input terminal. For example, the first output terminal of the second control circuit 950 is electrically connected to the first input terminal of the input circuit 910, and the second output terminal of the second control circuit 950 is electrically connected to the second input terminal of the input circuit 910. The second control circuit 950 can control one of the first input signal and the second input signal to be provided from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control one of the first input signal and the second input signal to be provided from the second output terminal to the second input terminal of the input circuit 910.

[0225] For example, under the control of the third clock signal, the second control circuit 950 can control the first input signal to be provided from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control the second input signal to be provided from the second output terminal to the second input terminal of the input circuit 910. For example, under the control of the third clock signal, the second control circuit 950 can control the second input signal to be provided from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control the first input signal to be provided from the second output terminal to the second input terminal of the input circuit 910.

[0226] In the embodiment of the present disclosure, different input signals are input to the input circuit through the control of the third clock signal, so that the pixel array is forward scanned and reverse scanned by using the cascaded multiple shift registers 900. For example, the pixel array includes 2000 rows of pixel circuits, and forward scanning can be achieved by scanning from the 1st row to the 2000th row using the cascaded multiple shift registers 900. Reverse scanning can be achieved by scanning from the 2000th row to the 1st row using the cascaded multiple shift registers 900.

[0227] FIG. 10A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0228] As shown in FIG. 10A , the shift register 1000 includes an input circuit 1010 , a processing circuit 1020 , an output circuit 1030 , and a second control circuit 1050 .

[0229] The input circuit 1010 includes a first input sub-circuit 1011 and a second input sub-circuit 1012. The processing circuit 1020 includes a first processing sub-circuit 1021 and a second processing sub-circuit 1022. The output circuit 1030 includes a first output sub-circuit 1031 and a second output sub-circuit 1032.

[0230] The input circuit 1010, the processing circuit 1020, the output circuit 1030 and the second control circuit 1050 are similar to the input circuit 910, the processing circuit 920, the output circuit 930 and the second control circuit 950 respectively, the first input subcircuit 1011 and the second input subcircuit 1012 are similar to the first input subcircuit 511 and the second input subcircuit 512 respectively, the first processing subcircuit 1021 and the second processing subcircuit 1022 are similar to the first processing subcircuit 521 and the second processing subcircuit 522 respectively, and the first output subcircuit 1031 and the second output subcircuit 1032 are similar to the first output subcircuit 531 and the second output subcircuit 532 respectively. For the sake of simplicity, the same parts of the present disclosure are not repeated here.

[0231] In the embodiment of the present disclosure, the second control circuit 1050 includes a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19 and a twentieth transistor T20. The seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19 and the twentieth transistor T20 are used as switch transistors, the seventeenth transistor T17 and the twenty-third transistor T20 are N-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are P-type transistors.

[0232] The gate of the seventeenth transistor T17 is electrically connected to the third clock signal terminal CLK3, the first electrode of the seventeenth transistor T17 is electrically connected to the first input signal terminal Gate(n-1)_N, and the second electrode of the seventeenth transistor T17 and the input circuit 1010 are electrically connected to the third node C. The gate of the eighteenth transistor T18 is electrically connected to the third clock signal terminal CLK3, the first electrode of the eighteenth transistor T18 is electrically connected to the second input signal terminal Gate(n+1)_N, and the second electrode of the eighteenth transistor T18 and the input circuit 1010 are electrically connected to the third node C. The gate of the nineteenth transistor T19 is electrically connected to the third clock signal terminal CLK3, the first electrode of the nineteenth transistor T19 is electrically connected to the first input signal terminal Gate(n-1)_N, and the second electrode of the nineteenth transistor T19 and the input circuit 1010 are electrically connected to the fourth node D. The gate of the twentieth transistor T20 is electrically connected to the third clock signal terminal CLK3 , the first electrode of the twentieth transistor T20 is electrically connected to the second input signal terminal Gate(n+1)_N, and the second electrode of the twentieth transistor T20 and the input circuit 1010 are electrically connected to the fourth node D.

[0233] In the embodiment of the present disclosure, the second electrode of the seventeenth transistor T17, the gate of the first transistor T1, and the gate of the seventh transistor T7 are electrically connected to the third node C, the second electrode of the eighteenth transistor T18, the gate of the first transistor T1, and the gate of the seventh transistor T7 are electrically connected to the third node C. The second electrode of the nineteenth transistor T19, the gate of the second transistor T2, and the gate of the fourth transistor T4 are electrically connected to the fourth node D, and the second electrode of the twentieth transistor T20, the gate of the second transistor T2, and the gate of the fourth transistor T4 are electrically connected to the fourth node D.

[0234] In the embodiment of the present disclosure, the first input signal Gate(n-1)_N or the second input signal Gate(n+1)_N is input to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the seventeenth transistor T17 and the eighteenth transistor T18. The first input signal Gate(n-1)_N or the second input signal Gate(n+1)_N is input to the gate of the second transistor T2 and the gate of the fourth transistor T4 through the nineteenth transistor T19 and the twentieth transistor T20.

[0235] FIG. 10B is a signal timing diagram of the shift register in FIG. 10A. FIG. 10B shows the timing waveforms of each signal in each stage. The structure of the shift register shown in FIG. 10A is taken as an example below, and the working process of the shift register provided by the embodiment of the present invention is described in combination with the signal timing diagram shown in FIG. 10B. The working process of the shift register includes 6 stages.

[0236] In the first stage S1 , the first input signal Gate(n−1)_N is at a high level, the second input signal Gate(n+1)_N is at a low level, the first clock signal CLK1 is at a low level, and the third clock signal CLK3 is at a high level.

[0237] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, and the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0238] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the twentieth transistor T20.

[0239] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6A , and will not be described again for the sake of brevity.

[0240] In the second stage S2 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, the first clock signal CLK1 is at a low level, and the third clock signal CLK3 is at a low level.

[0241] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0242] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0243] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6B , and will not be described again for the sake of brevity.

[0244] In the third stage S3 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, the first clock signal CLK1 is at a high level, and the third clock signal CLK3 is at a high level.

[0245] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, and the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0246] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the twentieth transistor T20.

[0247] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6C , and will not be described again for the sake of brevity.

[0248] In the fourth stage S4 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, the first clock signal CLK1 is at a low level, and the third clock signal CLK3 is at a low level.

[0249] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0250] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0251] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6D , and will not be described again for the sake of brevity.

[0252] In the fifth stage S5 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a high level, the first clock signal CLK1 is at a low level, and the third clock signal CLK3 is at a high level.

[0253] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, and the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0254] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the twentieth transistor T20.

[0255] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6E , and will not be described again for the sake of brevity.

[0256] In the sixth stage S6 , the first input signal Gate(n−1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, the first clock signal CLK1 is at a low level, and the third clock signal CLK3 is at a low level.

[0257] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, and the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0258] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0259] The operation process of transistors T1 to T14 is the same as the operation process described in FIG. 6D , and will not be described again for the sake of brevity.

[0260] In the embodiment of the present disclosure, the pixel array is scanned in the forward direction by a plurality of cascaded shift registers 1000 .

[0261] Optionally, the connection relationship between the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19 and the twentieth transistor T20 can be modified to achieve reverse scanning. For example, the connection relationship is modified as follows: the first electrode of the seventeenth transistor T17 is electrically connected to the second input signal terminal Gate(n+1)_N, the first electrode of the eighteenth transistor T18 is electrically connected to the first input signal terminal Gate(n-1)_N, the first electrode of the nineteenth transistor T19 is electrically connected to the second input signal terminal Gate(n+1)_N, and the first electrode of the twentieth transistor T20 is electrically connected to the first input signal terminal Gate(n-1)_N.

[0262] Accordingly, during reverse scanning, the timing of the third clock signal CLK3 will also change accordingly. For example, in the first stage S1, the third clock signal CLK3 is at a low level. In the second stage S2, the third clock signal CLK3 is at a high level. In the third stage S3, the third clock signal CLK3 is at a low level. In the fourth stage S4, the third clock signal CLK3 is at a high level. In the fifth stage S5, the third clock signal CLK3 is at a low level. In the sixth stage S6, the third clock signal CLK3 is at a high level.

[0263] FIG. 11 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0264] As shown in Fig. 11, the driving circuit 1100 includes M shift registers connected in cascade, where M is a positive integer greater than 1. The M shift registers include a shift register ST1, a shift register ST2, a shift register ST3, ..., and a shift register STM.

[0265] In the embodiment of the present disclosure, the shift register may be any one of the shift register 300, the shift register 400, the shift register 500, the shift register 700, the shift register 800, the shift register 900, and the shift register 1000 described above. For example, the M shift registers are all the shift register 300. For example, the M shift registers are all the shift register 500. No further details will be given here.

[0266] In the embodiment of the present disclosure, in the cascaded M shift registers, the first input signal terminal INPUT1 of the m-th shift register is electrically connected to the second scan output signal terminal OUTPUT2 of the m-1-th shift register, and the second input signal terminal INPUT2 of the m-th shift register is electrically connected to the second scan output signal terminal OUTPUT2 of the m+1-th shift register, 1<m≤M-1.

[0267] For example, the first input signal terminal INPUT1 of the second-stage shift register ST2 is electrically connected to the second scan output signal terminal OUTPUT2 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the second-stage shift register ST2 is electrically connected to the second scan output signal terminal OUTPUT2 of the third-stage shift register.

[0268] For example, the first input signal terminal INPUT1 of the second-stage shift register ST2 receives the gate drive signal Gate(1)_N from the second scan output signal terminal OUTPUT2 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the second-stage shift register ST2 receives the gate drive signal Gate(3)_N from the second scan output signal terminal OUTPUT2 of the third-stage shift register ST3. The light-emitting control signal terminal EM(n) of the second-stage shift register ST2 outputs the light-emitting control signal EM(2), the first scan output signal terminal OUTPUT1 outputs the gate drive signal Gate(2)_P, and the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(2)_N. The second-stage shift register ST2 provides the gate drive signal Gate(2)_N to the second input signal terminal INPUT2 of the first-stage shift register ST1 and the first input signal terminal INPUT1 of the third-stage shift register ST3.

[0269] For example, the second input signal terminal INPUT2 of the third-stage shift register ST3 receives the gate drive signal Gate(3)_N from the second scan output signal terminal OUTPUT2 of the next-stage shift register. The first scan output signal terminal OUTPUT1 of the third-stage shift register ST3 outputs the gate drive signal Gate(3)_P, and the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(3)_N.

[0270] In the disclosed embodiment, the first input signal terminal INPUT1 of the first stage shift register ST1 is electrically connected to the scan trigger signal terminal STV, and the second input signal terminal INPUT2 of the Mth stage shift register STM is electrically connected to the anti-static terminal ESD.

[0271] For example, the scan trigger signal terminal STV inputs the scan trigger signal STV to the first input signal terminal INPUT1 of the first-stage shift register ST1. Under the control of the scan trigger signal STV, the second input signal INPUT2 and the first clock signal CLK, the gate drive signal Gate(1)_P is output from the first scan output signal terminal OUTPUT1, the gate drive signal Gate(1)_N is output from the second scan output signal terminal OUTPUT2, and the light-emitting control signal EM(1) is output from the light-emitting control signal terminal EM(n).

[0272] For example, the first input signal terminal INPUT1 of the M-th stage shift register STM receives the gate drive signal Gate(M-1)_N output from the previous stage shift register, the first scan output signal terminal OUTPUT1 outputs the gate drive signal Gate(M)_P, the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(M)_N, and the light control signal terminal EM(n) outputs the light control signal EM(M).

[0273] In the embodiment of the present disclosure, the first power supply terminal VGH of the cascaded M shift registers is electrically connected to the power supply terminal Vgh, which provides a high potential voltage. The second power supply terminal VGL of the cascaded M shift registers is electrically connected to the power supply terminal Vgl, which provides a low potential voltage.

[0274] In the embodiment of the present disclosure, the first clock signal terminal CLK1 of the odd-numbered shift register unit is electrically connected to the clock signal terminal CLK to receive the clock signal CLK. The first clock signal terminal CLK1 of the even-numbered shift register unit is electrically connected to the clock signal terminal CLB to receive the clock signal CLB.

[0275] FIG. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0276] As shown in FIG. 12 , the display device 1200 may include a driving circuit 1210 .

[0277] In the embodiment of the present disclosure, the driving circuit 1210 may be the driving circuit 1100 described above, which will not be described in detail herein.

[0278] FIG. 13 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0279] As shown in FIG. 13 , the driving method may include operations S1310 to S1340 .

[0280] In operation S1310, in the first stage Q1, the first input signal from the first input signal terminal is at a first level and the second input signal from the second input signal terminal is at a second level, a first power supply voltage from the first power supply terminal is provided to the light emitting control signal terminal and the first node, and a second power supply voltage from the second power supply terminal is provided to the second node.

[0281] In operation S1320, in the second phase Q2, the first input signal and the second input signal are both at the second level, the first power supply voltage is provided to the light emitting control signal terminal and the first node, and the second power supply voltage is provided to the second node.

[0282] In operation S1330, in the third phase Q3, the first input signal is at the second level and the second input signal is at the first level, the second power supply voltage is supplied to the light emitting control signal terminal and the first node, and the first power supply voltage is supplied to the second node.

[0283] In operation S1340, in the fourth phase Q4, the first input signal and the second input signal are both at the second level, the second power supply voltage is provided to the light emitting control signal terminal and the first node, and the first power supply voltage is provided to the second node.

[0284] In the embodiment of the present disclosure, operations S1310 to S1340 are similar to the operations performed by the shift register 500 described above, and are not described again herein.

[0285] In the embodiment of the present disclosure, the first stage Q1 is similar to the operation of the first stage S1 shown in FIG6A , the second stage Q2 includes the operations of the second stage S2 to the fourth stage S4 shown in FIG6B to FIG6D , the third stage Q3 is similar to the operation of the fifth stage S5 shown in FIG6E , and the fourth stage Q4 is similar to the operation of the sixth stage S6 shown in FIG6F . For the sake of simplicity, the same parts of the present disclosure are not repeated here.

[0286] In the embodiment of the present disclosure, the first level is a high level and the second level is a low level. Those skilled in the art may also set the first level to a low level and the second level to a high level according to the type of transistors in the shift register.

[0287] For example, in the first phase Q1, the first clock signal from the first clock signal terminal is at the first level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0288] For example, the second phase Q2 includes a first sub-phase Q2_1 , a second sub-phase Q2_2 , and a third sub-phase Q2_3 .

[0289] In the first sub-stage Q2_1, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal. In the second sub-stage Q2_2, the first clock signal is at the first level, the second power supply voltage is provided to the first output scan signal terminal, and the first power supply voltage is provided to the second output scan signal terminal. In the third sub-stage Q2_3, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0290] The first sub-stage Q2_1 is similar to the operation of the second stage S2 shown in FIG. 6B , the second sub-stage Q2_2 is similar to the operation of the third stage S3 shown in FIG. 6C , and the third sub-stage Q2_3 is similar to the operation of the fourth stage S4 shown in FIG. 6D .

[0291] For example, in the third phase Q3, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0292] For example, in the fourth phase Q4, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0293] For example, the driving method also includes: when it is determined that the current display data of the display area driven by the shift register is the same as the previous display data, setting the second clock signal from the second clock signal end to the second level; and when it is determined that the current display data of the designated display area driven by the shift register is different from the previous display data, setting the second clock signal to the first level; wherein the display area is the display area where the pixel row driven by the shift register is located, the current display data is the data displayed by the pixel row driven by the shift register in the current working cycle, and the previous display data is the multi-frame display data displayed in multiple consecutive working cycles before the current working cycle.

[0294] For example, the driving method further includes: in the first stage Q1, the third clock signal from the third clock signal terminal is at the first level. In the third stage Q3, the third clock signal is at the first level. In the fourth stage Q4, the third clock signal is at the second level.

[0295] In the first sub-phase Q2_1 of the second phase Q2, the third clock signal from the third clock signal terminal is at the second level. In the second sub-phase Q2_2 of the second phase Q2, the third clock signal is at the first level. In the third sub-phase Q2_3 of the second phase Q2, the third clock signal is at the second level.

[0296] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0297] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0298] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

A shift register, comprising: An input circuit is electrically connected to a first input signal terminal, a second input signal terminal, a first power supply terminal, a second power supply terminal and a light-emitting control signal terminal, and is configured to provide a first power supply voltage of the first power supply terminal or a second power supply voltage of the second power supply terminal to a first node under the control of a first input signal from the first input signal terminal and a second input signal from the second input signal terminal, and the light-emitting control signal terminal is electrically connected to the first node; a processing circuit is electrically connected to the first input signal terminal, the first node, the first power supply terminal and the second power supply terminal, and is configured to provide the first power supply voltage or the second power supply voltage to a second node under the control of the potential of the first node and the first input signal, wherein the input The circuit is electrically connected to the second node, and under the control of the potential of the second node, the input circuit provides the first power supply voltage or the second power supply voltage to the light-emitting control signal terminal; and the output circuit is electrically connected to the first clock signal terminal, the first node, the first power supply terminal, the second power supply terminal, the first output scan signal terminal and the second output scan signal terminal, and is configured to provide the first power supply voltage or the second power supply voltage to the first output scan signal terminal under the control of the potential of the first node and the first clock signal from the first clock signal terminal, and to provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal. The shift register according to claim 1, wherein: The input circuit includes: a first input sub-circuit, electrically connected to the first input signal terminal, the second input signal terminal, the first power supply terminal and the light-emitting control signal terminal, and configured to provide the first power supply voltage to the light-emitting control signal terminal under the control of the first input signal and the second input signal; and a second input sub-circuit, electrically connected to the second input signal terminal, the second power supply terminal and the light-emitting control signal terminal, and configured to provide the second power supply voltage to the light-emitting control signal terminal under the control of the second input signal. The shift register according to claim 2, wherein: The first input subcircuit includes a first transistor, a second transistor and a third transistor; wherein the control electrode of the first transistor is electrically connected to the first input signal terminal, the first electrode of the first transistor is electrically connected to the second input signal terminal, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the second input signal terminal, the first electrode of the second transistor is electrically connected to the first power supply terminal, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; the control electrode of the third transistor and the second electrode of the first transistor are electrically connected to the second node, and the second electrode of the third transistor and the light-emitting control signal terminal are electrically connected to the first node. The shift register according to claim 2, wherein: The second input sub-circuit includes a fourth transistor and a fifth transistor; wherein the control electrode of the fourth transistor is electrically connected to the second input signal terminal, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor and the light-emitting control signal terminal are electrically connected to the first node; and the control electrode of the fifth transistor and the first input sub-circuit are electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifth transistor and the light-emitting control signal terminal are electrically connected to the first node. The shift register according to claim 1, wherein: The processing circuit includes: a first processing sub-circuit, electrically connected to the first node, the second node and the second power supply terminal, configured to provide the second power supply voltage to the second node under the control of the potential of the first node; and a second processing sub-circuit, electrically connected to the first input signal terminal, the first node, the second node and the first power supply terminal, configured to provide the first power supply voltage to the second node under the control of the potential of the first node and the first input signal. The shift register according to claim 5, wherein: The first processing subcircuit includes a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the second power supply terminal, and a second electrode of the sixth transistor is electrically connected to the second node. The shift register according to claim 5, wherein: The second processing sub-circuit includes a seventh transistor and an eighth transistor; wherein the control electrode of the seventh transistor is electrically connected to the first input signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and the control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor and the first processing sub-circuit are electrically connected to the second node. The shift register according to claim 1, wherein: The output circuit includes: a first output sub-circuit, electrically connected to the first clock signal terminal, the first node, the first power supply terminal, the second power supply terminal and the first output scan signal terminal, and configured to provide the first power supply voltage or the second power supply voltage to the first output scan signal terminal under the control of the potential of the first node and the first clock signal; and a second output sub-circuit, electrically connected to the first output scan signal terminal, the first power supply terminal, the second power supply terminal and the second output scan signal terminal, and configured to provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal. The shift register according to claim 8, wherein: The first output subcircuit includes a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; wherein the control electrode of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the first output scan signal terminal; the control electrode of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is electrically connected to the first output scan signal terminal; the control electrode of the eleventh transistor is electrically connected to the first node, and the first electrode of the eleventh transistor is electrically connected to the second power supply terminal; and the control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the first output scan signal terminal. The shift register according to claim 8, wherein: The second output sub-circuit includes a thirteenth transistor and a fourteenth transistor; wherein the control electrode of the thirteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second output scan signal terminal; and the control electrode of the fourteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the second output scan signal terminal. The shift register according to any one of claims 1 to 10, further comprising: A first control circuit is electrically connected to a second clock signal terminal, the first output scan signal terminal, the second output scan signal terminal, a third output scan signal terminal and a fourth output scan signal terminal, and is configured to provide the potential of the first output scan signal terminal to the third output scan signal terminal and to provide the potential of the second output scan signal terminal to the fourth output scan signal terminal under the control of a second clock signal from the second clock signal terminal. The shift register according to claim 11, wherein: The first control circuit includes a fifteenth transistor and a sixteenth transistor; wherein the control electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the fifteenth transistor is electrically connected to the second output scan signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth output scan signal terminal; and the control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first output scan signal terminal, and the second electrode of the sixteenth transistor is electrically connected to the third output scan signal terminal. The shift register according to any one of claims 1 to 12, further comprising: A second control circuit is electrically connected to a third clock signal terminal, the input circuit, the first input signal terminal and the second input signal terminal, and is configured to provide the first input signal and the second input signal to the input circuit under the control of a third clock signal from the third clock signal terminal; wherein the first input signal terminal and the second input signal terminal are electrically connected to the input circuit through the second control circuit. The shift register according to claim 13, wherein: The second control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; wherein the control electrode of the seventeenth transistor is electrically connected to the third clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the first input signal terminal, and the second electrode of the seventeenth transistor and the input circuit are electrically connected to a third node; the control electrode of the eighteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the eighteenth transistor is electrically connected to the second input signal terminal, and the second electrode of the eighteenth transistor and the input circuit are electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first input signal terminal, and the second electrode of the nineteenth transistor and the input circuit are electrically connected to a fourth node; and the control electrode of the twentieth transistor is electrically connected to the third clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the second input signal terminal, and the second electrode of the twentieth transistor and the input circuit are electrically connected to the fourth node. A driving circuit comprises M cascaded shift registers as described in any one of claims 1 to 14, where M is a positive integer greater than 1; the first input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the m-1-th shift register, and the second input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the m+1-th shift register, 1<m≤M-1. The driving circuit according to claim 15, wherein: The first input signal terminal of the first-stage shift register is electrically connected to the scan trigger signal terminal, and the second input signal terminal of the M-th-stage shift register is electrically connected to the anti-static terminal. A display device comprising the driving circuit according to claim 15 or 16. A driving method, applied to the shift register according to any one of claims 1 to 14, comprising: In the first stage, the first input signal from the first input signal terminal is at a first level and the second input signal from the second input signal terminal is at a second level, a first power supply voltage from the first power supply terminal is provided to the light emitting control signal terminal and the first node, and a second power supply voltage from the second power supply terminal is provided to the second node; In the second stage, the first input signal and the second input signal are both at the second level, the first power supply voltage is provided to the light emitting control signal terminal and the first node, and the second power supply voltage is provided to the second node; In the third stage, the first input signal is at the second level and the second input signal is at the first level, the second power supply voltage is provided to the light emitting control signal terminal and the first node, and the first power supply voltage is provided to the second node; And in the fourth stage, the first input signal and the second input signal are both at the second level, the second power supply voltage is provided to the light emitting control signal terminal and the first node, and the first power supply voltage is provided to the second node. The driving method according to claim 18, further comprising: In the first stage, the first clock signal from the first clock signal terminal is at a first level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal. The driving method according to claim 18, wherein: The second stage includes a first sub-stage, a second sub-stage and a third sub-stage, and the method also includes: in the first sub-stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal; in the second sub-stage, the first clock signal is at the first level, the second power supply voltage is provided to the first output scan signal terminal, and the first power supply voltage is provided to the second output scan signal terminal; and in the third sub-stage, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal. The driving method according to claim 18, further comprising: In the third stage, the first clock signal from the first clock signal terminal is at a second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal. The driving method according to claim 18, further comprising: In the fourth stage, the first clock signal from the first clock signal terminal is at a second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal. The driving method according to claim 18, further comprising: When it is determined that the current display data of the display area driven by the shift register is the same as the previous display data, setting the second clock signal from the second clock signal terminal to a second level; And when it is determined that the current display data of the specified display area driven by the shift register is different from the previous display data, the second clock signal is set to the first level; wherein the display area is the display area where the pixel row driven by the shift register is located, the current display data is the data displayed by the pixel row driven by the shift register in the current working cycle, and the previous display data is a plurality of frames of display data displayed in multiple consecutive working cycles before the current working cycle. The driving method according to claim 18, further comprising: In the first stage, the third clock signal from the third clock signal terminal is at a first level; In the third stage, the third clock signal is at a first level; And in the fourth stage, the third clock signal is at a second level. The driving method according to claim 20, further comprising: In the first sub-phase, the third clock signal from the third clock signal terminal is at a second level; In the second sub-phase, the third clock signal is at a first level; And in the third sub-phase, the third clock signal is at a second level.

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