Shift register, drive circuit, drive method, and display device

Abstract

The present disclosure provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises: an input circuit configured to provide a first power voltage or a second power voltage to a first node and a light-emitting control signal end under the control of a first input signal and a second input signal; a processing circuit configured to provide the first power voltage or the second power voltage to a second node under the control of the first input signal and the potential of the first node, and the input circuit provides the first power voltage or the second power voltage to the light-emitting control signal end under the control of the potential of the second node; and an output circuit configured to provide the first power voltage or the second power voltage to a first output scanning signal end under the control of a first clock signal and the potential of the first node, and provide the first power voltage or the second power voltage to a second output scanning signal end under the control of the potential of the first output scanning signal end.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a driving circuit, a driving method and a display device. BACKGROUND

[0002] In the field of light-emitting diode (LED) and organic light-emitting diode (OLED) display, the display is driven by the Gate on Array (GOA) circuit integrated on the array substrate and the timing design. The pixel circuit in the display usually needs to be provided with driving signals by multiple GOA circuits, which increases the occupied space of the GOA circuit and cannot effectively reduce the frame width, and cannot meet the needs of narrow frame of the display. SUMMARY

[0003] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit electrically connected to a first input signal terminal, a second input signal terminal, a first power supply terminal, a second power supply terminal and a light-emitting control signal terminal, configured to provide a first power supply voltage of the first power supply terminal or a second power supply voltage of the second power supply terminal to a first node under the control of a first input signal from the first input signal terminal and a second input signal from the second input signal terminal, the light-emitting control signal terminal being electrically connected to the first node; a processing circuit electrically connected to the first input signal terminal, the first node, the first power supply terminal and the second power supply terminal, configured to provide the first power supply voltage or the second power supply voltage to a second node under the control of the first input signal and the potential of the first node, wherein the input circuit is electrically connected to the second node, and the input circuit provides the first power supply voltage or the second power supply voltage to the light-emitting control signal terminal under the control of the potential of the second node; and an output circuit electrically connected to a first clock signal terminal, the first node, the first power supply terminal, the second power supply terminal, a first output scan signal terminal and a second output scan signal terminal, configured to provide the first power supply voltage or the second power supply voltage to the first output scan signal terminal under the control of a first clock signal from the first clock signal terminal and the potential of the first node, and provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal.

[0005] For example, the input circuit comprises: a first input sub-circuit electrically connected to the first input signal terminal, the second input signal terminal, the first power supply terminal and the light-emitting control signal terminal, and configured to provide the first power supply voltage to the light-emitting control signal terminal under the control of the first input signal and the second input signal; and a second input sub-circuit electrically connected to the second input signal terminal, the second power supply terminal and the light-emitting control signal terminal, and configured to provide the second power supply voltage to the light-emitting control signal terminal under the control of the second input signal.

[0006] For example, the first input sub-circuit comprises a first transistor, a second transistor and a third transistor; wherein the control electrode of the first transistor is electrically connected to the first input signal terminal, the first electrode of the first transistor is electrically connected to the second input signal terminal, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the second input signal terminal, the first electrode of the second transistor is electrically connected to the first power supply terminal, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; and the control electrode of the third transistor and the second electrode of the first transistor are electrically connected to the second node, and the second electrode of the third transistor and the light-emitting control signal terminal are electrically connected to the first node.

[0007] For example, the second input sub-circuit comprises a fourth transistor and a fifth transistor; wherein the control electrode of the fourth transistor is electrically connected to the second input signal terminal, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor and the light-emitting control signal terminal are electrically connected to the first node; and the control electrode of the fifth transistor and the first input sub-circuit are electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second power supply terminal, and the second electrode of the fifth transistor and the light-emitting control signal terminal are electrically connected to the first node.

[0008] For example, the processing circuit comprises: a first processing sub-circuit electrically connected to the first node, the second node and the second power supply terminal, and configured to provide the second power supply voltage to the second node under the control of the potential of the first node; and a second processing sub-circuit electrically connected to the first input signal terminal, the first node, the second node and the first power supply terminal, and configured to provide the first power supply voltage to the second node under the control of the first input signal and the potential of the first node.

[0009] For example, the first processing sub-circuit comprises a sixth transistor, wherein the control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second power supply terminal, and the second electrode of the sixth transistor is electrically connected to the second node.

[0010] For example, the second processing sub-circuit includes a seventh transistor and an eighth transistor; wherein the control electrode of the seventh transistor is electrically connected to the first input signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and the control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor and the first processing sub-circuit are electrically connected to the second node.

[0011] For example, the output circuit includes: a first output sub-circuit electrically connected to a first clock signal terminal, a first node, a first power supply terminal, a second power supply terminal, and a first output scan signal terminal, configured to provide a first power supply voltage or a second power supply voltage to the first output scan signal terminal under the control of the potential of the first clock signal and the first node; and a second output sub-circuit electrically connected to the first output scan signal terminal, the first power supply terminal, the second power supply terminal, and the second output scan signal terminal, configured to provide a first power supply voltage or a second power supply voltage to the second output scan signal terminal under the control of the potential of the first output scan signal terminal.

[0012] For example, the first output sub-circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein, the control electrode of the ninth transistor is electrically connected to a first clock signal terminal, the first electrode of the ninth transistor is electrically connected to a first power supply terminal, and the second electrode of the ninth transistor is electrically connected to a first output scan signal terminal; the control electrode of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is electrically connected to the first output scan signal terminal; the control electrode of the eleventh transistor is electrically connected to a first node, and the first electrode of the eleventh transistor is electrically connected to a second power supply terminal; and the control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the first output scan signal terminal.

[0013] For example, the second output sub-circuit includes a thirteenth transistor and a fourteenth transistor; wherein the control electrode of the thirteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the second output scan signal terminal; and the control electrode of the fourteenth transistor is electrically connected to the first output scan signal terminal, the first electrode of the fourteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourteenth transistor is electrically connected to the second output scan signal terminal.

[0014] For example, the shift register further includes: a first control circuit electrically connected to a second clock signal terminal, a first output scan signal terminal, a second output scan signal terminal, a third output scan signal terminal, and a fourth output scan signal terminal, configured to provide the potential of the first output scan signal terminal to the third output scan signal terminal and provide the potential of the second output scan signal terminal to the fourth output scan signal terminal under the control of a second clock signal from the second clock signal terminal.

[0015] For example, the first control circuit includes a fifteenth transistor and a sixteenth transistor; wherein the control electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the fifteenth transistor is electrically connected to the second output scan signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth output scan signal terminal; and the control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first output scan signal terminal, and the second electrode of the sixteenth transistor is electrically connected to the third output scan signal terminal.

[0016] For example, the shift register further includes: a second control circuit electrically connected to a third clock signal terminal, an input circuit, a first input signal terminal, and a second input signal terminal, configured to provide the first input signal and the second input signal to the input circuit under the control of a third clock signal from the third clock signal terminal; wherein the first input signal terminal and the second input signal terminal are electrically connected to the input circuit through the second control circuit.

[0017] For example, the second control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; wherein, the control electrode of the seventeenth transistor is electrically connected to a third clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to a first input signal terminal, and the second electrode of the seventeenth transistor is electrically connected to a third node via an input circuit; the control electrode of the eighteenth transistor is electrically connected to a third clock signal terminal, the first electrode of the eighteenth transistor is electrically connected to a second input signal terminal, and the second electrode of the eighteenth transistor is electrically connected to a third node via an input circuit; the control electrode of the nineteenth transistor is electrically connected to a third clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to a first input signal terminal, and the second electrode of the nineteenth transistor is electrically connected to a fourth node via an input circuit; and the control electrode of the twentieth transistor is electrically connected to a third clock signal terminal, the first electrode of the twentieth transistor is electrically connected to a second input signal terminal, and the second electrode of the twentieth transistor is electrically connected to a fourth node via an input circuit.

[0018] According to a second aspect, this disclosure provides a driving circuit including M cascaded shift registers provided in embodiments of this disclosure, where M is a positive integer greater than 1; the first input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the (m-1)-th shift register, and the second input signal terminal of the m-th shift register is electrically connected to the second scan output signal terminal of the (m+1)-th shift register, where 1 < m ≤ M-1.

[0019] For example, the first input signal terminal of the first-stage shift register is electrically connected to the scan trigger signal terminal, and the second input signal terminal of the M-stage shift register is electrically connected to the anti-static terminal.

[0020] According to a third aspect, this disclosure provides a display device including a driving circuit provided in an embodiment of this disclosure.

[0021] According to a fourth aspect, this disclosure provides a driving method applied to a shift register provided in an embodiment of this disclosure, comprising: in a first stage, a first input signal from a first input signal terminal is at a first level and a second input signal from a second input signal terminal is at a second level, providing a first power supply voltage from a first power supply terminal to a light-emitting control signal terminal and a first node, and providing a second power supply voltage from a second power supply terminal to a second node; in a second stage, both the first input signal and the second input signal are at the second level, providing the first power supply voltage to the light-emitting control signal terminal and the first node, and providing the second power supply voltage to the second node; in a third stage, the first input signal is at the second level and the second input signal is at the first level, providing the second power supply voltage to the light-emitting control signal terminal and the first node, and providing the first power supply voltage to the second node; and in a fourth stage, both the first input signal and the second input signal are at the second level, providing the second power supply voltage to the light-emitting control signal terminal and the first node, and providing the first power supply voltage to the second node.

[0022] For example, the driving method further includes: in a first stage, a first clock signal from a first clock signal terminal is at a first level, a first power supply voltage is provided to a first output scan signal terminal, and a second power supply voltage is provided to a second output scan signal terminal.

[0023] For example, the second stage includes a first sub-stage, a second sub-stage, and a third sub-stage, and the method further includes: in the first sub-stage, a first clock signal from a first clock signal terminal is at a second level, a first power supply voltage is provided to a first output scan signal terminal, and a second power supply voltage is provided to a second output scan signal terminal; in the second sub-stage, the first clock signal is at a first level, a second power supply voltage is provided to the first output scan signal terminal, and a first power supply voltage is provided to the second output scan signal terminal; and in the third sub-stage, a first power supply voltage is provided to the first output scan signal terminal, and a second power supply voltage is provided to the second output scan signal terminal.

[0024] For example, the driving method further includes: in the third stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0025] For example, the driving method further includes: in the fourth stage, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0026] For example, the driving method further includes: when it is determined that the current display data of the display area driven by the shift register is the same as the previous display data, setting the second clock signal from the second clock signal terminal to a second level; and when it is determined that the current display data of the specified display area driven by the shift register is different from the previous display data, setting the second clock signal to a first level; wherein, the display area is the display area where the pixel row driven by the shift register is located, the current display data is the data displayed by the pixel row driven by the shift register in the current working cycle, and the previous display data is the multi-frame display data displayed in multiple consecutive working cycles before the current working cycle.

[0027] For example, the driving method further includes: in a first stage, the third clock signal from the third clock signal terminal is at a first level; in a third stage, the third clock signal is at the first level; and in a fourth stage, the third clock signal is at a second level.

[0028] For example, the driving method further includes: in a first sub-stage, the third clock signal from the third clock signal terminal is at a second level; in a second sub-stage, the third clock signal is at a first level; and in a third sub-stage, the third clock signal is at a second level. Attached Figure Description

[0029] Figure 1A This is a schematic diagram of an example pixel circuit.

[0030] Figure 1B for Figure 1A Signal timing diagram of the mid-pixel circuit;

[0031] Figure 2A This is a schematic diagram of an example driver circuit.

[0032] Figure 2B This is a schematic diagram of the light emission control signal output by the 2A driver circuit in the figure;

[0033] Figure 3 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0034] Figure 4 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0035] Figure 5A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0036] Figure 5B yes Figure 5A Signal timing diagram of the intermediate shift register;

[0037] Figures 6A to 6F This is an equivalent circuit diagram of a shift register at different stages according to an embodiment of the present disclosure;

[0038] Figure 7A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0039] Figure 7B This is a schematic diagram of a refreshed pixel array according to an embodiment of the present disclosure;

[0040] Figure 8A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0041] Figure 8B and Figure 8C yes Figure 8A Signal timing diagram of the intermediate shift register;

[0042] Figure 9 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0043] Figure 10A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0044] Figure 10B yes Figure 10A Signal timing diagram of the intermediate shift register;

[0045] Figure 11 This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure;

[0046] Figure 12 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0047] Figure 13 This is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0049] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0050] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0051] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to their function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0052] Furthermore, in the description of the embodiments of this disclosure, the terms "first power supply voltage" and "second power supply voltage" are used only to distinguish the different amplitudes of the two power supply voltages. For example, the following description uses "first power supply voltage" as a relatively high voltage and "second power supply voltage" as a relatively low voltage. Those skilled in the art will understand that this disclosure is not limited thereto.

[0053] It should be noted that, in the description of the embodiments of this disclosure, the symbol Vdata can represent both a data signal and the level of a data signal. Similarly, the symbol Gate can represent both a gate drive signal and the level of a gate drive signal, the symbol VINT can represent both a predetermined initial voltage terminal and the voltage of an initial signal, the symbol ELVDD can represent both a power supply and the power supply voltage provided by the power supply, INPUT can represent both an input signal terminal and the input signal provided by the input signal terminal, OUTPUT can represent both an output signal terminal and the output signal output by the output signal terminal, and VGH and VGL can represent both a power supply terminal and the power supply voltage provided by the power supply terminal. The following embodiments are the same and will not be described again.

[0054] The pixel unit of the pixel circuit of LED display panel and OLED display panel can be a 7T1C structure, that is, each pixel unit consists of 7 thin film transistors (TFTs) and 1 capacitor (C), as shown in Figure 1.

[0055] Figure 1A This is a schematic diagram of an example pixel circuit. Figure 1B for Figure 1A Signal timing diagram of the mid-pixel circuit.

[0056] exist Figure 1A In the example, transistors T1 and T2 can be N-type transistors, and transistors T3 to T7 can be P-type transistors.

[0057] exist Figure 1B In the example, during the initialization phase P1, the gate drive signal Gate(n-1)_N is at a high level. During the data writing phase P2, the gate drive signal Gate(n)_N is at a high level, and the gate drive signal Gate(n)_P is at a low level. During the light emission phase P3, the light emission control signal EM is at a low level.

[0058] During the initialization phase P1, transistor T1 is turned on under the high-level control of the gate drive signal Gate(n-1)_N. The initialization signal VINT initializes the gate of the driving transistor T3, thereby initializing the gate voltage of the driving transistor T3 to VINT, and simultaneously charging the storage capacitor CST. At this time, the voltage at point N1 is VINT.

[0059] During the data writing phase P2, under the low-level control of the gate drive signal Gate(n)_P, transistor T7 is turned on, and the initialization signal VINT is written to the anode of the OLED along the initialization path from the predetermined initial voltage terminal to the OLED, thereby initializing the anode voltage of the OLED to VINT. This releases the residual charge on the anode of the OLED, thus eliminating the residual voltage on the anode.

[0060] At this time, transistor T2 is turned on under the high level control of the gate drive signal Gate(n)_N, and transistor T4 is turned on under the low level control of the gate drive signal Gate(n)_P. The driving transistor T3 is turned on under the drive of the voltage signal stored in the storage capacitor CST. The data signal Vdata is written to node N1 from the data signal terminal via transistors T4, T3, and T2. At this time, the data signal Vdata can charge the storage capacitor CST, and the driving transistor T3 gradually turns off. When Vgs = Vg - Vs = Vg - Vdata ≥ Vth, the driving transistor T3 turns off, the charging of the storage capacitor CST is completed, and the potential at point N1 is Vg = Vth + Vdata.

[0061] It can be understood that Vth is the threshold voltage of driving transistor T3, Vgs is the gate-source voltage of driving transistor T3, Vg is the gate voltage of driving transistor T3, and Vs is the source voltage of driving transistor T3. The voltage difference (VINT-ELVSS) between the initial signal terminal VINT and the second power supply terminal ELVSS should be less than the threshold voltage Vth of the OLED, thereby ensuring that the OLED does not emit light during the data writing phase.

[0062] During the light-emitting phase P3, transistors T5 and T6 are turned on under the low-level control of the light-emitting control signal EM. At this time, the source potential Vs of the driving transistor T3 is Vdd, and the gate potential Vg is Vth + Vdata. Since Vgs = Vth + Vdata - Vdd < Vth, the driving transistor T3 is turned on under the drive of the voltage signal stored in the storage capacitor CST. With transistors T5 and T6 on, the voltage at the first power supply terminal ELVDD is written into the circuit. The driving current is applied to the light-emitting element OLED along the light-emitting path from the power supply to the OLED via transistor T5, driving transistor T3, and transistor T6, causing the OLED to emit light. At this time, the current flowing through the pixel is Id = A(Vdd - Vdata). 2 , where A is a constant.

[0063] The display may include a pixel array and a GOA circuit. The pixel array includes multiple pixel circuits arranged in an array, and each pixel circuit can be as follows: Figure 1AAs shown, the pixel array is used to display the image. The GOA circuit is used to provide drive signals to the pixel array. For example, the GOA circuit may include multiple cascaded GOA units, each GOA unit providing a drive signal to a row of pixel units in the pixel array. For example, the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P can be gate drive signals provided by the first-level GOA unit corresponding to a row of pixel units, and the gate drive signal Gate(n-1)_N can be the gate drive signal provided by the previous-level GOA unit.

[0064] The emission control signal EM can also be provided by an emission control signal drive (Emission On Array, EOA) circuit. The EOA circuit consists of multiple cascaded EOA units, each of which provides the emission control signal EM to a row of pixel units in the pixel array.

[0065] Therefore, the pixel circuit composed of the pixel units shown in Figure 1 requires three sets of driving circuits to provide driving signals. For example, two sets of GOA circuits provide the gate driving signal Gate(n)_N and the gate driving signal Gate(n)_P respectively, and one set of EOA circuits provides the light emission control signal EM. In a display, three sets of driving circuits occupy a large amount of space, which makes it difficult to narrow the bezel of the display.

[0066] To address the aforementioned problems, this disclosure provides a shift register, with each shift register serving as a GOA unit. A single GOA unit can provide gate drive signals Gate(n)_N, Gate drive signals Gate(n)_P, and light emission control signals EM to a corresponding row of pixel units. By cascading multiple shift registers provided in this disclosure, a set of GOA circuits is obtained. This set of GOA circuits can then be used to provide gate drive signals Gate(n)_N, Gate drive signals Gate(n)_P, and light emission control signals EM to the pixel array in a display.

[0067] Figure 2A This is a schematic diagram of an example drive circuit. Figure 2B This is a schematic diagram of the light emission control signal output by the 2A driving circuit in the figure.

[0068] Figure 2A An EOA unit 200a of an EOA circuit is shown. Each EOA unit 200a may include 12 transistors and 3 capacitors, such as... Figure 2A As shown.

[0069] exist Figure 2AIn the example, transistors T1 to T12 can be P-type transistors. The output terminal EMOUTPUT outputs the light-emitting control signal EM, the input terminal ESTV provides the trigger signal, and the clock signal terminals ECK and ECB provide the clock signal. The power supply terminal VGH can provide a high-level power supply voltage, and the power supply terminal VGL can provide a low-level power supply voltage VGL. The power supply voltage VGH is greater than the power supply voltage VGL.

[0070] In EOA unit 200a, the light emission control signal EM output from the EMOUTPUT terminal is controlled by transistors T9 and T10. When transistor T9 is on and transistor T10 is off, the light emission control signal EM output from the EMOUTPUT terminal is at a high level. When transistor T9 is off and transistor T10 is on, the light emission control signal EM output from the EMOUTPUT terminal is at a low level.

[0071] The gate of transistor T9 is affected by the capacitance stored in capacitor C1, and the gate of transistor T10 is affected by the capacitance stored in capacitor C3. Because the stored capacitance is unstable, this causes a drift in the potential of the output light-emitting control signal EM, such as... Figure 2B As shown.

[0072] Figure 2B It shows Figure 2A The potential change process of the light emission control signal EM output by the EOA unit 200a. In the potential change 200b of the light emission control signal EM, during the process of dropping from a high level to a low level, the potential of the light emission control signal EM in region 210 experiences a secondary pull-down phenomenon. This causes the light emission control signal EM to drift, making it susceptible to external interference. Therefore, Figure 2A The design of the capacitor in the EOA unit shown will affect the stability of the light emission control signal EM.

[0073] To address the aforementioned problems, this disclosure provides a shift register that serves as the EOA unit. The shift register includes multiple transistors and eliminates the need for capacitors. A processing circuit is incorporated within the shift register to maintain a stable output of the light emission control signal EM, ensuring that the output EM is free from drift.

[0074] Figure 3 This is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0075] like Figure 3 As shown, the shift register 300 includes an input circuit 310, a processing circuit 320, and an output circuit 330.

[0076] In this embodiment, the input circuit 310 is electrically connected to the first input signal terminal INPUT1, the second input signal terminal INPUT2, the first power supply terminal VGH, the second power supply terminal VGL, and the light emission control signal terminal EM. The input circuit 310 can output the light emission control signal EM.

[0077] Input circuit 310 is configured to provide a first power supply voltage from first power supply terminal VGH or a second power supply voltage from second power supply terminal VGL to first node A under the control of a first input signal from first input signal terminal INPUT1 and a second input signal from second input signal terminal INPUT1. Light emission control signal terminal EM is electrically connected to first node A.

[0078] The processing circuit 320 is electrically connected to the first input signal terminal INPUT1, the first node A1, the first power supply terminal VGH, and the second power supply terminal VGL. The processing circuit 320 can maintain a stable light emission control signal EM output by the input circuit 310.

[0079] Processing circuit 320 is configured to provide a first power supply voltage VGH or a second power supply voltage VGL to second node B under the control of the potential of first node A and the first input signal INPUT1. Input circuit 310 is electrically connected to second node B. Under the control of the potential of second node B, input circuit 310 provides the first power supply voltage VGH or the second power supply voltage VGL to the light emission control signal terminal EM.

[0080] For example, when the first power supply voltage VGH is provided to the first node A, the processing circuit 320 can provide the second power supply voltage VGL to the second node B under the control of the potential of the first node A and the first input signal INPUT1. Under the control of the potential of the second node B, the input circuit 310 provides the first power supply voltage VGH to the light emission control signal terminal EM.

[0081] For example, when the second power supply voltage VGL is provided to the first node A, the processing circuit 320 can provide the first power supply voltage VGH to the second node B under the control of the potential of the first node A and the first input signal INPUT1. Under the control of the potential of the second node B, the input circuit 310 provides the second power supply voltage VGL to the light emission control signal terminal EM.

[0082] This creates a stable feedback loop between the input circuit 310 and the processing circuit 320, thereby maintaining a stable light-emitting control signal EM output by the input circuit 310.

[0083] Output circuit 330 is electrically connected to the first clock signal terminal CLK1, the first node A, the first power supply terminal VGH, the second power supply terminal VGL, the first output scan signal terminal OUTPUT1, and the second output scan signal terminal PUTPUT2. Output circuit 330 can output scan signals, which can be used as gate drive signals. For example, the first output scan signal terminal OUTPUT1 outputs the gate drive signal Gate(n)_P, and the second output scan signal terminal PUTPUT2 outputs the gate drive signal Gate(n)_N.

[0084] The output circuit 330 is configured to provide a first power supply voltage VGH or a second power supply voltage VGL to the first output scan signal terminal OUTPUT1 under the control of the potential of the first node A and the first clock signal from the first clock signal terminal CLK, and to provide the first power supply voltage VGH or the second power supply voltage VGL to the second output scan signal terminal OUTPUT2 under the control of the potential of the first output scan signal terminal OUTPUT1.

[0085] In this embodiment, the shift register 300 can be a driving unit in a driving circuit. The primary driving unit can output a gate driving signal Gate(n)_N, a gate driving signal Gate(n)_P, and a light emission control signal EM. For example, the driving unit may include an EOA unit and a GOA unit. The input circuit 310 and the processing circuit 320 can implement the function of the EOA unit outputting the light emission control signal EM, and the output circuit 330 can implement the function of the GOA unit outputting the gate driving signal Gate(n).

[0086] In this embodiment of the present disclosure, the first input signal terminal INPUT1 can be the gate drive signal Gate(n-1)_N output by the previous stage GOA unit in the driving circuit, and the second input signal terminal INPUT2 can be the gate drive signal Gate(n+1)_N output by the next stage GOA unit in the driving circuit.

[0087] In this embodiment, the input circuit 310, processing circuit 320, and output circuit 330 are electrically connected to the first node A. The gate drive signal Gate(n-1)_N from the previous stage GOA unit and the gate drive signal Gate(n+1)_N from the second input signal terminal INPUT2 of the next stage GOA unit can be the input signals of the EOA unit, and the light emission control signal EM is the output signal of the EOA unit. The potential of the light emission control signal terminal EM is consistent with the level of the first node A. The light emission control signal EM output by the EOA unit can be used as the input signal of the output circuit 330, and the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P are the output signals of the GOA unit.

[0088] The shift register 300 provided in this disclosure serves as a driving unit, providing gate driving signals Gate(n)_N, Gate(n)_P, and light emission control signals EM to a corresponding row of pixel units in the pixel array. This reduces the space occupied by the driving circuit and helps to narrow the bezel of the display. Furthermore, the processing circuit 320 in the shift register 300 maintains a stable output of the light emission control signal EM, ensuring that the output light emission control signal EM is free from drift.

[0089] It should be noted that the first node A and the second node B do not represent actual components, but rather the junctions of related circuit connections in the circuit diagram.

[0090] Figure 4 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0091] like Figure 4 As shown, the shift register 400 includes an input circuit 410, a processing circuit 420, and an output circuit 430. The input circuit 410, the processing circuit 420, and the output circuit 430 are similar to the input circuit 310, the processing circuit 320, and the output circuit 330 described above. For the sake of simplicity, the same parts will not be described again here.

[0092] In this embodiment of the disclosure, the input circuit 410 includes a first input sub-circuit 411 and a second input sub-circuit 412.

[0093] In this embodiment, the first terminal of the first input sub-circuit 411 and the first terminal of the second input sub-circuit 412 are electrically connected to the first node A, and the first node A is electrically connected to the light emission control terminal EM. The second terminal of the first input sub-circuit 411 and the second terminal of the second input sub-circuit 412 are electrically connected to the second node B.

[0094] The first input sub-circuit 411 is electrically connected to the first input signal terminal INPUT1, the second input signal terminal INPUT1, the first power supply terminal VGH, and the light emission control signal terminal EM. The first input sub-circuit 411 is configured to provide the first power supply voltage VGH to the light emission control signal terminal under the control of the first input signal and the second input signal.

[0095] The second input sub-circuit 412 is electrically connected to the second input signal terminal INPUT1, the second power supply terminal VGL, and the light emission control signal terminal EM. The second input sub-circuit 412 is configured to provide the second power supply voltage VGL to the light emission control signal terminal EM under the control of the second input signal.

[0096] For example, the first input sub-circuit 411 can output a high-potential light emission control signal EM, and the second input sub-circuit 412 can output a low-potential light emission control signal EM.

[0097] In this embodiment of the disclosure, the processing circuit 420 includes a first processing sub-circuit 421 and a second processing sub-circuit 422.

[0098] In this embodiment of the disclosure, a first terminal of the first processing sub-circuit 421 and a first terminal of the second processing sub-circuit 422 are electrically connected to a first node A, and the first node A is electrically connected to the light-emitting control terminal EM. A second terminal of the first processing sub-circuit 421 and a second terminal of the second processing sub-circuit 422 are electrically connected to a second node B.

[0099] The first processing sub-circuit 421 is electrically connected to the first node A, the second node B, and the second power supply terminal VGL. Under the control of the potential of the first node A, the first processing sub-circuit 421 provides the second power supply voltage VGL to the second node B.

[0100] The second processing sub-circuit 422 is electrically connected to the first input signal terminal INPUT, the first node A, the second node B, and the first power supply terminal VGH. Under the control of the potential of the first node A and the first input signal, the second processing sub-circuit 422 provides the first power supply voltage VGH to the second node B.

[0101] In this embodiment of the disclosure, the first terminal of the first input sub-circuit 411 and the first terminal of the first processing sub-circuit 421 are electrically connected to the first node A, and the second terminal of the first input sub-circuit 411 and the second terminal of the first processing sub-circuit 421 are electrically connected to the second node B.

[0102] When the first input sub-circuit 411 can output a high-potential light-emitting control signal EM, under the control of the potential of the first node A, the first processing sub-circuit 421 provides the second power supply voltage VGL to the second node B. At this time, under the control of the potential of the second node B, the first input sub-circuit 411 provides the first power supply voltage VGH to the light-emitting control signal terminal EM. This creates a stable feedback between the first input sub-circuit 411 and the first processing sub-circuit 421, enabling the first input sub-circuit 411 to output a stable light-emitting control signal EM.

[0103] In this embodiment of the disclosure, the first terminal of the second input sub-circuit 412 and the first terminal of the second processing sub-circuit 422 are electrically connected to the first node A, and the second terminal of the second input sub-circuit 412 and the second terminal of the second processing sub-circuit 422 are electrically connected to the second node B.

[0104] When the second input sub-circuit 412 can output a low-potential light-emitting control signal EM, under the control of the potential of the first node A, the second processing sub-circuit 422 provides the first power supply voltage VGH to the second node B. At this time, under the control of the potential of the second node B, the second input sub-circuit 412 provides the second power supply voltage VGL to the light-emitting control signal terminal EM. This creates a stable feedback between the second input sub-circuit 412 and the second processing sub-circuit 422, enabling the second input sub-circuit 412 to output a stable light-emitting control signal EM.

[0105] In this embodiment of the disclosure, the output circuit 430 includes a first output sub-circuit 431 and a second output sub-circuit 432.

[0106] In this embodiment of the disclosure, the first terminal of the first output sub-circuit 431 is electrically connected to the first node A, and the second terminal of the first output sub-circuit 431 and the first terminal of the second output sub-circuit 432 are electrically connected to the first output scan signal terminal OUTPUT1. The second terminal of the second output sub-circuit 432 is electrically connected to the second output scan signal terminal OUTPUT2.

[0107] The first output sub-circuit 431 is electrically connected to the first clock signal terminal CLK1, the first node A, the first power supply terminal VGH, the second power supply terminal VGL, and the first output scan signal terminal OUTPUT1. Under the control of the potential of the first node A and the first clock signal CLK1, the first output sub-circuit 431 provides the first power supply voltage VGH or the second power supply voltage VGL to the first output scan signal terminal.

[0108] The second output sub-circuit 432 is electrically connected to the first output scan signal terminal OUTPUT1, the first power supply terminal VGH, the second power supply terminal VGL, and the second output scan signal terminal OUTPUT2. Under the control of the potential of the first output scan signal terminal, the second output sub-circuit 432 provides the first power supply voltage VGH or the second power supply voltage VGL to the second output scan signal terminal.

[0109] For example, when the first output sub-circuit 431 outputs a gate drive signal Gate(n)_P with a high potential, the second output sub-circuit 432 outputs a gate drive signal Gate(n)_N with a low potential. When the first output sub-circuit 431 outputs a gate drive signal Gate(n)_P with a low potential, the second output sub-circuit 432 outputs a gate drive signal Gate(n)_N with a high potential.

[0110] Figure 5A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0111] like Figure 5AAs shown, the shift register 500 includes an input circuit 510, a processing circuit 520, and an output circuit 530.

[0112] The input circuit 510 includes a first input sub-circuit 511 and a second input sub-circuit 512. The processing circuit 520 includes a first processing sub-circuit 521 and a second processing sub-circuit 522. The output circuit 530 includes a first output sub-circuit 531 and a second output sub-circuit 532.

[0113] The input circuit 510, processing circuit 520, and output circuit 530 are similar to the input circuit 310, processing circuit 320, and output circuit 330 described above, respectively. The first input sub-circuit 511 and the second input sub-circuit 512 are similar to the first input sub-circuit 411 and the second input sub-circuit 412 described above, respectively. The first processing sub-circuit 521 and the second processing sub-circuit 522 are similar to the first processing sub-circuit 421 and the second processing sub-circuit 422 described above, respectively. The first output sub-circuit 531 and the second output sub-circuit 532 are similar to the first output sub-circuit 431 and the second output sub-circuit 432 described above, respectively. For the sake of simplicity, the same parts will not be described again here.

[0114] In this embodiment of the disclosure, the first input sub-circuit 511 includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1, the second transistor T2, and the third transistor T3 are used as switching transistors. The first transistor T1 is an N-type transistor, and the second transistor T2 and the third transistor T3 are P-type transistors.

[0115] The gate of the first transistor T1 is electrically connected to the first input signal terminal Gate(n-1)_N, the first electrode of the first transistor T1 is electrically connected to the second input signal terminal Gate(n+1)_N, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the second transistor T2 is electrically connected to the second input signal terminal Gate(n+1)_N, the first electrode of the second transistor T2 is electrically connected to the first power supply terminal VGH, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3. The gate of the third transistor T3 and the second electrode of the first transistor T1 are electrically connected to the second node B, and the second electrode of the third transistor T3 and the light emission control signal terminal EM(n) are electrically connected to the first node A.

[0116] The second input sub-circuit 512 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 are used as switching transistors, and the fourth transistor T4 and the fifth transistor T5 are N-type transistors.

[0117] The gate of the fourth transistor T4 is electrically connected to the second input signal terminal Gate(n+1)_N, the first terminal of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second terminal of the fourth transistor T4 and the light emission control signal terminal EM(n) are electrically connected to the first node A. The gate of the fifth transistor T5 and the gate of the third transistor T3 in the first input sub-circuit 410 are electrically connected to the second node B, the first terminal of the fifth transistor T5 is electrically connected to the second power supply terminal VGL, and the second terminal of the fifth transistor T5 and the light emission control signal terminal EM(n) are electrically connected to the first node A.

[0118] In this embodiment of the disclosure, the first processing sub-circuit 521 includes a sixth transistor T6. The sixth transistor T6 is used as a switching transistor, and the sixth transistor T6 is an N-type transistor.

[0119] The gate of the sixth transistor T6 is electrically connected to the first node A, the first electrode of the sixth transistor T6 is electrically connected to the second power supply terminal VGL, and the second electrode of the sixth transistor T6 is electrically connected to the second node B.

[0120] In this embodiment of the disclosure, the second processing sub-circuit 522 includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 and the eighth transistor T8 are used as switching transistors, and both the seventh transistor T7 and the eighth transistor T8 are P-type transistors.

[0121] The gate of the seventh transistor T7 is electrically connected to the first input signal terminal Gate(n-1)_N, the first terminal of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, and the second terminal of the seventh transistor T7 is electrically connected to the first terminal of the eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the first node A, and the second terminal of the eighth transistor T8 and the second terminal of the sixth transistor T6 in the first processing sub-circuit 521 are electrically connected to the second node B.

[0122] In this embodiment of the disclosure, the first output sub-circuit 531 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are used as switching transistors, the ninth transistor T9 and the twelfth transistor T12 are P-type transistors, and the tenth transistor T10 and the eleventh transistor T11 are N-type transistors.

[0123] The gate of the ninth transistor T9 is electrically connected to the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the first output scan signal terminal Gate(n)_P. The gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CLK1, the first electrode of the tenth transistor T10 is electrically connected to the second electrode of the eleventh transistor T11, and the second electrode of the tenth transistor T10 is electrically connected to the first output scan signal terminal Gate(n)_P. The gate of the eleventh transistor T11 is electrically connected to the first node A, and the first electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal VGL. The gate of the twelfth transistor T12 is electrically connected to the first node A, the first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VGH, and the second electrode of the twelfth transistor T12 is electrically connected to the first output scan signal terminal Gate(n)_P.

[0124] The second output sub-circuit 532 includes a thirteenth transistor T13 and a fourteenth transistor T14. The thirteenth transistor T13 and the fourteenth transistor T14 are used as switching transistors, with the thirteenth transistor T13 being a P-type transistor and the fourteenth transistor T14 being an N-type transistor.

[0125] The gate of the thirteenth transistor T13 is electrically connected to the first output scan signal terminal Gate(n)_P, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor T13 is electrically connected to the second output scan signal terminal Gate(n)_N. The gate of the fourteenth transistor T14 is electrically connected to the first output scan signal terminal Gate(n)_P, the first electrode of the fourteenth transistor T14 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourteenth transistor T14 is electrically connected to the second output scan signal terminal Gate(n)_N.

[0126] Figure 5B yes Figure 5A Timing diagram of the shift register. Figure 5B The timing waveforms of each signal in each stage are shown. The following example... Figure 5A Taking the structure of the shift register shown as an example, combined with... Figure 5B The signal timing diagram shown describes the operation of the shift register provided in this embodiment of the invention. The operation of the shift register includes six stages.

[0127] Figure 6A An equivalent circuit diagram of the shift register in the first stage S1 according to an embodiment of the present disclosure is shown. Figure 6B An equivalent circuit diagram of the shift register in the second stage S2 according to an embodiment of the present disclosure is shown. Figure 6C An equivalent circuit diagram of the shift register in the third stage S3 according to an embodiment of the present disclosure is shown.Figure 6D An equivalent circuit diagram of the shift register in the fourth stage S4 according to an embodiment of the present disclosure is shown. Figure 6E An equivalent circuit diagram of the shift register in the fifth stage S6 according to an embodiment of the present disclosure is shown. Figure 6F An equivalent circuit diagram of the shift register in the sixth stage S5 according to an embodiment of the present disclosure is shown. Figures 6C to 6F The dashed line with an arrow indicates the direction of current in the shift register during the corresponding stage.

[0128] Next, we will refer to Figures 6A to 6F The operation of the shift register according to embodiments of the present disclosure is described in detail.

[0129] In the first stage S1, the first input signal Gate(n-1)_N is at a high level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a low level.

[0130] Under the control of the first input signal Gate(n-1)_N, the first transistor T1 is turned on, and the seventh transistor T7 is turned off by the high level of the first input signal Gate(n-1)_N. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 through the first transistor T1. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 and the third transistor T3 are turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0131] The first power supply voltage VGH is supplied to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is high, and the light emission control signal EM(n) output by the light emission control signal terminal EM(n) is also high.

[0132] Under the control of the high level at node A, the sixth transistor T6 is turned on. The eighth transistor T8 is turned off by the high level at node A. The second power supply voltage VGL is supplied to the second node B through the sixth transistor T6, at which time the potential of the second node B is low.

[0133] The second node B is electrically connected to the gate of the third transistor T3. Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably provided to the light-emitting control signal terminal EM(n), forming stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0134] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first voltage power supply VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0135] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The second power supply voltage VGL is supplied to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0136] In the second stage S2, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, and the first clock signal CLK1 is low.

[0137] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0138] Since the gate of the third transistor T3 is not receiving an external voltage, the third transistor T3 is in a latched state and remains in the same on-state as in the first stage S1. The first power supply voltage VGH is supplied to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is high, and the light emission control signal EM(n) output by the light emission control signal terminal EM(n) is also high.

[0139] Under the control of the high level at node A, the sixth transistor T6 is turned on. The eighth transistor T8 is turned off by the high level at node A. The second power supply voltage VGL is supplied to the second node B through the sixth transistor T6, at which time the potential of the second node B is low.

[0140] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably supplied to the light-emitting control signal terminal EM(n), forming stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0141] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first voltage power supply VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0142] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The second power supply voltage VGL is supplied to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0143] In the third stage S3, the first input signal Gate(n-1)_N is at a low level, the second input signal Gate(n+1)_N is at a low level, and the first clock signal CLK1 is at a high level.

[0144] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0145] Since the gate of the third transistor T3 is not receiving an external voltage, the third transistor T3 is in a latched state and remains in the same on-state as in the second stage S2. The first power supply voltage VGH is supplied to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is high, and the light emission control signal EM(n) output by the light emission control signal terminal EM(n) is also high.

[0146] Under the control of the high level at node A, the sixth transistor T6 is turned on. The eighth transistor T8 is turned off by the high level at node A. The second power supply voltage VGL is supplied to the second node B through the sixth transistor T6, at which time the potential of the second node B is low.

[0147] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably supplied to the light-emitting control signal terminal EM(n), forming stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0148] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the tenth transistor T10 is turned on. The ninth transistor T9 is turned off by the low level of the first clock signal CLK. The second voltage power supply VGL is provided to the first output scan signal terminal Gate(n)_P through the eleventh transistor T11 and the tenth transistor T10. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a low level.

[0149] Under the control of the low level of the first output scan signal terminal Gate(n)_P, the thirteenth transistor T13 is turned on. The fourteenth transistor T14 is turned off by the high level of the first output scan signal terminal Gate(n)_P. The first power supply voltage VGH is supplied to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a high level.

[0150] In the fourth stage S4, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, and the first clock signal CLK1 is low.

[0151] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0152] Since the gate of the third transistor T3 is not receiving an external voltage, the third transistor T3 is in a latched state and remains in the same conducting state as in the third stage S3. The first power supply voltage VGH is supplied to the first node A through the second transistor T2 and the third transistor T3. At this time, the potential of the first node A is high, and the light emission control signal EM(n) output by the light emission control signal terminal EM(n) is also high.

[0153] Under the control of the high level at node A, the sixth transistor T6 is turned on. The eighth transistor T8 is turned off by the high level at node A. The second power supply voltage VGL is supplied to the second node B through the sixth transistor T6, at which time the potential of the second node B is low.

[0154] Under the control of the low level of the second node B, the third transistor T3 remains in the on state, and the fifth transistor T5 is turned off by the low level of the second node B. When the third transistor T3 remains in the on state, the first power supply voltage VGH can be stably supplied to the light-emitting control signal terminal EM(n), forming stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0155] Under the control of the high level of the first node A, the eleventh transistor T11 is turned on. The twelfth transistor T12 is turned off by the high level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0156] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0157] In the fifth stage S5, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is high, and the first clock signal CLK1 is low.

[0158] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the fourth transistor T4 is turned on, and the second transistor T2 is turned off by the low level of the second input signal Gate(n+1)_N. The second power supply voltage VGL is provided to the first node A through the fourth transistor T4. At this time, the potential of the first node A is low, and the light emission control signal EM(n) output from the light emission control signal terminal EM(n) is also low.

[0159] Under the control of the low level at the first node A, the eighth transistor T8 is turned on. The sixth transistor T6 is turned off by the low level at the first node A. The first power supply voltage VGH is supplied to the second node B through the seventh transistor T7 and the eighth transistor T8, at which time the potential of the second node B is high.

[0160] Under the control of the high level of the second node B, the fifth transistor T5 is turned on, and the third transistor T3 is turned off by the low level of the second node B. When the fifth transistor T5 is in the on state, the second power supply voltage VGL can be stably provided to the light-emitting control signal terminal EM(n), forming a stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0161] Under the control of the low level of the first node A, the twelfth transistor T12 is turned on. The eleventh transistor T11 is turned off by the low level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9 and the twelfth transistor T12. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0162] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0163] In the sixth stage S6, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, and the first clock signal CLK1 is low.

[0164] Under the control of the first input signal Gate(n-1)_N, the seventh transistor T7 is turned on, and the first transistor T1 is turned off by the low level of the first input signal Gate(n-1)_N. Under the control of the second input signal Gate(n+1)_N, the second transistor T2 is turned on, and the fourth transistor T4 is turned off by the low level of the second input signal Gate(n+1)_N.

[0165] Since the gate of the fifth transistor T5 is not receiving an external voltage, the fifth transistor T5 is in a latched state and remains in the same on-state as in the fifth stage S5. The second power supply voltage VGL is supplied to the first node A through the fifth transistor T5. At this time, the potential of the first node A is low, and the light emission control signal EM(n) output by the light emission control signal terminal EM(n) is also low.

[0166] Under the control of the low level at the first node A, the eighth transistor T8 is turned on. The sixth transistor T6 is turned off by the low level at the first node A. The first power supply voltage VGH is supplied to the second node B through the seventh transistor T7 and the eighth transistor T8, at which time the potential of the second node B is high.

[0167] Under the control of the high level of the second node B, the fifth transistor T5 remains in the on state, while the third transistor T3 is cut off by the low level of the second node B. With the fifth transistor T5 in the on state, the second power supply voltage VGL can be stably supplied to the light-emitting control signal terminal EM(n), forming stable feedback, so that the light-emitting control signal terminal EM(n) can output a stable light-emitting control signal EM(n).

[0168] Under the control of the low level of the first node A, the twelfth transistor T12 is turned on. The eleventh transistor T11 is turned off by the low level of the first node A. Under the control of the first clock signal CLK, the ninth transistor T9 is turned on. The tenth transistor T10 is turned off by the low level of the first clock signal CLK. The first power supply voltage VGH is provided to the first output scan signal terminal Gate(n)_P through the ninth transistor T9 and the twelfth transistor T12. At this time, the gate drive signal Gate(n)_P output by the first output scan signal terminal Gate(n)_P is at a high level.

[0169] Under the control of the high level of the first output scan signal terminal Gate(n)_P, the fourteenth transistor T14 is turned on. The thirteenth transistor T13 is turned off by the low level of the first output scan signal terminal Gate(n)_P. The second voltage power supply VGL is provided to the second output scan signal terminal Gate(n)_N through the fourteenth transistor T14. At this time, the gate drive signal Gate(n)_N output by the second output scan signal terminal Gate(n)_N is at a low level.

[0170] exist Figure 5A and Figures 6A to 6F In the example, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, and the fourteenth transistor T14 are N-type transistors, and the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors. Those skilled in the art will understand that, according to the embodiments of this disclosure, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, and the fourteenth transistor T14 can also be P-type transistors, and the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 can also be N-type transistors, by correspondingly changing the level of the gate conduction signal of each transistor.

[0171] In this embodiment of the disclosure, among the cascaded multiple shift registers 500, the first clock signal terminal CLK1 of the odd-numbered shift register unit is electrically connected to the clock signal terminal CLK to receive the clock signal CLK, and the first clock signal terminal CLK1 of the even-numbered shift register unit is electrically connected to the clock signal terminal CLB to receive the clock signal CLB.

[0172] For example, clock signals CLB and CLK alternately appear high in timing. For example, shift register 500 can be an nth-stage shift register, where n is a positive integer, an odd number greater than 1. The nth-stage shift register receives clock signal CLK, and the (n-1)th and (n+1)th-stage shift registers receive clock signal CLB.

[0173] For example, odd-level shift register units write the high level of clock signal CLK to gate drive signal Gate(n)_N, and even-level shift register units write the high level of clock signal CLB to gate drive signal Gate(n+1)_N and gate drive signal Gate(n-1)_N.

[0174] In the shift register 500 provided in this disclosure, the light emission control signal EM(n) is output by controlling the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5. The stable output of the light emission control signal EM(n) is maintained by controlling the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The gate drive signal Gate(n)_P is output by controlling the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12. The gate drive signal Gate(n)_N is output by controlling the thirteenth transistor T13 and the fourteenth transistor T14. The shift register 500 provided in this disclosure can provide the gate drive signal Gate(n)_N, the gate drive signal Gate(n)_P, and the light emission control signal EM(n) to a corresponding row of pixel units in the pixel array, reducing the space occupied by the driving circuit and facilitating the narrowing of the display bezel. Furthermore, the shift register 500 provided in this disclosure does not have a capacitor structure, and maintains a stable output of the light emission control signal EM(n) through a transistor structure, so that the output light emission control signal EM(n) does not drift.

[0175] Figure 7 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0176] As shown in Figure 7, the shift register 700 includes an input circuit 710, a processing circuit 720, an output circuit 730, and a first control circuit 740. The input circuit 710, processing circuit 720, and output circuit 730 are similar to the input circuit 510, processing circuit 520, and output circuit 530 described above. For the sake of simplicity, the same parts will not be described again here.

[0177] In this embodiment of the disclosure, the first control circuit 740 is electrically connected to the second clock signal terminal CLK2, the first output scan signal terminal OUTPUT1, the second output scan signal terminal OUTPUT2, the third output scan signal terminal OUTPUT3, and the fourth output scan signal terminal OUTPUT4.

[0178] Under the control of the second clock signal from the second clock signal terminal CLK2, the first control circuit 740 provides the potential of the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and the first control circuit 740 also provides the potential of the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4.

[0179] In this embodiment, the first control circuit 740 and the output circuit 730 are electrically connected to the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2. The output circuit 730 outputs gate drive signals Gate(n)_P and Gate drive signals Gate(n)_N through the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2, respectively. Under the control of the second clock signal CLK2, the first control circuit 740 can control whether to output the gate drive signals Gate(n)_P and Gate drive signals Gate(n)_N to the corresponding pixel rows of the pixel array.

[0180] For example, the first control circuit 740 can output the gate drive signal Gate(n)_P from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and the third output scan signal terminal OUTPUT3 provides the gate drive signal Gate(n)_P to the corresponding pixel row. The first control circuit 740 can also output the gate drive signal Gate(n)_N from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4, and the fourth output scan signal terminal OUTPUT4 provides the gate drive signal Gate(n)_N to the corresponding pixel row.

[0181] For example, the first control circuit 740 can also control the gate drive signal Gate(n)_P, which is not output from the first output scan signal terminal OUTPUT1, to be output to the third output scan signal terminal OUTPUT3, and control the gate drive signal Gate(n)_N, which is output from the second output scan signal terminal OUTPUT2, to be not output to the fourth output scan signal terminal OUTPUT4.

[0182] In this embodiment, the shift register 700 can be used to set different refresh rates for different pixel rows of the pixel array. For example, the displayed screen may include static and dynamic images. For example, a static image may be the background portion of the displayed screen that does not change, while a dynamic image may be the portion of the displayed screen where the image changes. When the display shows an image, a static image may appear for a period of time. If both the static and dynamic images are refreshed at the same refresh rate (e.g., a high frequency), it will result in high power consumption. If the dynamic image portion is set to maintain its original high refresh rate, and the static image portion is set to refresh at a relatively low refresh rate, the refresh power consumption can be reduced.

[0183] For example, you can set the frame refresh rate for dynamic scenes to 120Hz. The display will refresh 120 frames per second.

[0184] Accordingly, the frame refresh rate for static images can be set to 60Hz or 30Hz. At a frame refresh rate of 60Hz, the display refreshes 60 frames per second. At a frame refresh rate of 30Hz, the display refreshes 30 frames per second.

[0185] With the goal of achieving a frame refresh rate of 120Hz for the display screen, multiple cascaded shift registers 700 provide gate drive signals Gate(n)_N and Gate(n)_P to the first output scan signal terminal OUTPUT1 and the second output scan signal terminal OUTPUT2, respectively.

[0186] In this case, for the pixel row displaying dynamic images in the pixel array, the corresponding shift register 700 can provide all the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and provide all the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4, so that the pixel row displaying dynamic images refreshes 120 frames per second, achieving a frame refresh rate of 120Hz.

[0187] For a pixel row in the pixel array that displays a static image, the corresponding shift register 700 can provide part of the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and provide part of the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4, thereby reducing the number of refreshes for the pixel row that displays the static image.

[0188] Figure 7B This is a schematic diagram of a refresh pixel array according to an embodiment of the present disclosure.

[0189] like Figure 7B As shown, with a 120Hz refresh rate as a reference, the 120 frames displayed per second are divided into four parts according to the order of display. For example, part 1 consists of frames 1 to 30, part 2 consists of frames 31 to 60, part 3 consists of frames 61 to 90, and part 4 consists of frames 91 to 120.

[0190] When the frame refresh rate is set to 120Hz, the pixel array can be considered to display four parts of data per second. If only the first and third parts of the data are displayed per second, the frame refresh rate can be considered equivalent to 60Hz. If only the first part of the data is displayed per second, the frame refresh rate can be considered equivalent to 30Hz.

[0191] like Figure 7B As shown, solid lines represent displayed data, and dashed lines represent undisplayed data. Understandably, each row of pixels in the pixel array refreshes at the same rate. Multiple pixel rows can be refreshed row by row each time the display refreshes a frame. When the display refreshes 120 frames per second, the multiple pixel rows are refreshed 120 times. For example, a pixel array may include 2000 pixel rows; after refreshing each row from row 1 to row 2000 once, the display completes one frame refresh.

[0192] For a pixel row in a pixel array displaying dynamic images, setting the pixel row to refresh 120 times per second can be considered equivalent to a refresh rate of 120Hz. For a pixel row in a pixel array displaying static images, the pixel row can refresh only the first 30 times per second, and not refresh for the next 90 times; therefore, the refresh rate of the pixel row can be considered equivalent to 30Hz. For a pixel row in a pixel array displaying static images, the pixel row can also refresh only the first 30 times and from the 61st to the 90th times per second, and not refresh from the 31st to the 60th times per second, and the last 30 times per second; therefore, the refresh rate of the pixel row can be considered equivalent to 60Hz.

[0193] When the pixel row is set to refresh only the first 30 times per second, the corresponding shift register provides the gate drive signals Gate(n)_N and Gate(n)_P only during the first 30 refreshes. When the pixel row is set to refresh only the first 30 times and from the 61st to the 90th times per second, the corresponding shift register provides the gate drive signals Gate(n)_N and Gate(n)_P only during the first 30 refreshes and from the 61st to the 90th refreshes.

[0194] For example, each time the shift register passes through stages S1 to S6 mentioned above, it can provide the gate drive signal Gate(n)_N and gate drive signal Gate(n)_P for the corresponding 3 rows of pixels (row n-1, row n and row n+1) once.

[0195] In this embodiment, the frame refresh rate of the dynamic image can be set to 120Hz, and the frame refresh rate of the static image can be set to 30Hz. Correspondingly, under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the dynamic image can be set to the ON state during all 120 refresh cycles, providing all the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and providing all the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4. Under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the static image can be set to the ON state only during the first 30 refresh cycles, and to the OFF state during the subsequent 90 refresh cycles. Therefore, only during the first 30 refreshes, the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 is provided entirely to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 is provided entirely to the fourth output scan signal terminal OUTPUT4. During the 31st to 120th refreshes, the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 is not provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 is not provided to the fourth output scan signal terminal OUTPUT4. The pixel rows of the static image are not refreshed, and the image displayed during the first 30 refreshes is maintained.

[0196] In this embodiment, the refresh rate of the pixel row of the dynamic image can be set to 120Hz, and the refresh rate of the pixel row of the static image can be set to 60Hz. Correspondingly, under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the dynamic image can be set to the ON state during all 120 refresh cycles, providing all the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 to the third output scan signal terminal OUTPUT3, and providing all the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 to the fourth output scan signal terminal OUTPUT4. Under the control of the second clock signal CLK2, the first control circuit 740 in the shift register 700 corresponding to the pixel row of the static image can be set to the ON state only during the first 30 refresh cycles and the 61st to 90th refresh cycles, and set to the OFF state during the 31st to 60th refresh cycles and the last 30 refresh cycles. Therefore, only during the first 30 refreshes and the 61st to 90th refreshes, the gate drive signal Gate(n)_P output from the first output scan signal terminal OUTPUT1 is provided to the third output scan signal terminal OUTPUT3, and the gate drive signal Gate(n)_N output from the second output scan signal terminal OUTPUT2 is provided to the fourth output scan signal terminal OUTPUT4. During the 31st to 60th refreshes, the pixel rows of the static image are not refreshed, and the image displayed in the first 30 refreshes is maintained. During the 91st to 120th refreshes, the pixel rows of the static image are not refreshed, and the image displayed in the 61st to 90th refreshes is maintained.

[0197] Through the embodiments of this disclosure, by setting the first control circuit 740 to control the output time periods of the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P, the refresh rate of different regions in the pixel array can be flexibly controlled, so that different regions in the pixel array can be refreshed at different refresh rates, thereby reducing refresh power consumption.

[0198] Figure 8A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0199] like Figure 8A As shown, the shift register 800 includes an input circuit 810, a processing circuit 820, an output circuit 830, and a first control circuit 840.

[0200] The input circuit 810 includes a first input sub-circuit 811 and a second input sub-circuit 812. The processing circuit 820 includes a first processing sub-circuit 821 and a second processing sub-circuit 822. The output circuit 830 includes a first output sub-circuit 831 and a second output sub-circuit 832.

[0201] The input circuit 810, processing circuit 820, output circuit 830, and first control circuit 840 are similar to the input circuit 710, processing circuit 720, output circuit 730, and first control circuit 740 described above. The first input sub-circuit 811 and the second input sub-circuit 812 are similar to the first input sub-circuit 511 and the second input sub-circuit 512 described above. The first processing sub-circuit 821 and the second processing sub-circuit 822 are similar to the first processing sub-circuit 521 and the second processing sub-circuit 522 described above. The first output sub-circuit 831 and the second output sub-circuit 832 are similar to the first output sub-circuit 531 and the second output sub-circuit 532 described above. For simplicity, the same parts will not be described again here.

[0202] In this embodiment of the disclosure, the first control circuit 840 includes a fifteenth transistor T15 and a sixteenth transistor T16. The fifteenth transistor T15 and the sixteenth transistor T16 are used as switching transistors, and the fifteenth transistor T15 and the sixteenth transistor T16 are N-type transistors.

[0203] The gate of the fifteenth transistor T15 is electrically connected to the second clock signal terminal CLK2, the first terminal of the fifteenth transistor T15 is electrically connected to the output terminal C(n)_N, and the second terminal of the fifteenth transistor T15 is electrically connected to the fourth output scan signal terminal Gate(n)_N. The fourth output scan signal terminal Gate(n)_N provides the gate drive signal Gate(n)_N to the corresponding pixel row. In the cascaded multiple shift registers, the output signal C(n)_N output from the output terminal C(n)_N is the input signal Gate(n+1)_N received by the previous stage shift register, and the output signal C(n)_N output from the output terminal C(n)_N is the input signal Gate(n-1)_N received by the next stage shift register.

[0204] The gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal CLK2, the first terminal of the sixteenth transistor T16 is electrically connected to the output terminal C(n)_P, and the second terminal of the sixteenth transistor T16 is electrically connected to the third output scan signal terminal Gate(n)_P. The third output scan signal terminal Gate(n)_P provides the gate drive signal Gate(n)_P to the corresponding pixel row.

[0205] Figure 8B and Figure 8C yes Figure 8A Timing diagram of the shift register. Figure 8B The timing waveforms of the second clock signal are shown when the third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N output signals. Figure 8CThe timing waveforms of the second clock signal are shown when the third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N are not outputting signals. The following uses... Figure 8A Taking the structure of the shift register shown as an example, combined with... Figure 8B and Figure 8C The signal timing diagram shown describes the operation of the shift register provided in the embodiment of the present invention.

[0206] In shift register 800, the operation of input circuit 810, processing circuit 820, and output circuit 830 is similar to... Figures 6A to 6F The working process shown is the same, and for the sake of simplicity, the same parts will not be described again here.

[0207] like Figure 8B As shown, the second clock signal CLK2 is high, the output signal C(n)_P output by the first output sub-circuit 831 is low, and the output signal C(n)_N output by the second output sub-circuit 832 is high.

[0208] Under the control of the second clock signal CLK2, the fifteenth transistor T15 and the sixteenth transistor T16 are turned on. The output signal C(n)_P is provided to the third output scan signal terminal Gate(n)_P through the sixteenth transistor T16, and the output signal C(n)_N is provided to the fourth output scan signal terminal Gate(n)_N through the fifteenth transistor T15.

[0209] like Figure 8C As shown, the second clock signal CLK2 is at a low level, the output signal C(n)_P output by the first output sub-circuit 831 is at a low level, and the output signal C(n)_N output by the second output sub-circuit 832 is at a high level.

[0210] Under the control of the second clock signal CLK2, the fifteenth transistor T15 and the sixteenth transistor T16 are turned off. The third output scan signal terminal Gate(n)_P and the fourth output scan signal terminal Gate(n)_N do not output signals.

[0211] It should be noted that, Figure 8B and Figure 8C The second clock signal CLK2, output signal C(n)_P, and output signal C(n)_N shown are merely illustrative examples. This disclosure does not limit the timing variations between the second clock signal CLK2, output signal C(n)_P, and output signal C(n)_N. Those skilled in the art can, according to actual needs, control the output signals C(n)_P and C(n)_N from a specific shift register to be provided to specific pixel rows in the pixel array during specific time periods by setting the timing of the second clock signal CLK2 accordingly during specific time periods.

[0212] In this embodiment, it can be assumed that the gate drive signal output by the shift register 800 can drive the corresponding pixel row to refresh once in each working cycle. When the shift register drives the corresponding pixel row, if it is determined that the displayed data of the pixel row in the current working cycle is the same as the previously displayed data, the second clock signal can be set to a low level. At this time, the corresponding shift register drive control output signal C(n)_P and output signal C(n)_N are not output. If it is determined that the current displayed data of the pixel row is different from the previously displayed data, the second clock signal from the second clock signal terminal is set to a high level.

[0213] For example, according to Figure 1A The data signal provided by the data signal terminal Vdata, as shown, determines the display data for each row of pixels in each working cycle. For example, the display data can be a voltage value converted from the pixel value.

[0214] For example, before displaying the data for the current work cycle, the display area driven by the shift register can be pre-determined to be a static image by comparing the display data within the current work cycle with the display data from several previous work cycles. For instance, comparing the display data in the 31st work cycle with the display data from the previous 30 work cycles confirms that the display data in the 31st work cycle is the same as the display data from the previous 30 work cycles. In the 31st work cycle, the second clock signal can be set to a low level. At this time, the output signals C(n)_P and C(n)_N are not output to the corresponding pixel rows, and the pixel row corresponding to shift register 800 is not refreshed.

[0215] For example, the display data for each pixel row can be compared in advance over multiple working cycles. If the display data is determined to be identical across multiple working cycles, the second clock signal can be set to a high level in the first part of the working cycles. In this case, output signals C(n)_P and C(n)_N are output to the corresponding pixel row, and shift register 800 refreshes the corresponding pixel row. In the second part of the working cycles, the second clock signal is set to a low level. In this case, output signals C(n)_P and C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to shift register 800 is not refreshed.

[0216] For example, assuming the displayed data is identical for 120 working cycles, the second clock signal is set to a high level for the first 30 working cycles, and a low level for the remaining 90 working cycles.

[0217] For example, the display data that has not yet been displayed can be compared with the currently displayed display data in advance. If it is determined that the display data in the subsequent working cycle is the same as the currently displayed display data, the second clock signal can be set to a low level in the subsequent working cycle. At this time, the output signals C(n)_P and C(n)_N are not output to the corresponding pixel row, and the pixel row corresponding to shift register 800 is not refreshed.

[0218] For example, the display data from the 31st to the 90th working cycle is compared with the display data from the 30th working cycle to determine that the display data from the 31st to the 90th working cycle is the same as the display data from the 30th working cycle. During the 31st to the 90th working cycle, the second clock signal can be set to a low level. At this time, output signals C(n)_P and C(n)_N are not output to the corresponding pixel rows, and the pixel row corresponding to shift register 800 is not refreshed.

[0219] In this embodiment of the disclosure, by setting the timing of the first control circuit 740 and designing the timing of the second clock signal CLK2, the time period during which the gate drive signal Gate(n)_N and the gate drive signal Gate(n)_P are provided to the pixel array can be controlled. This allows for flexible control of the refresh rate of different areas in the pixel array, enabling different areas in the pixel array to be refreshed at different refresh rates.

[0220] Figure 9 This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0221] like Figure 9 As shown, the shift register 900 includes an input circuit 910, a processing circuit 920, an output circuit 930, and a second control circuit 950. The input circuit 910, processing circuit 920, and output circuit 930 are similar to the input circuit 510, processing circuit 520, and output circuit 530 described above. For the sake of simplicity, the same parts will not be described again here.

[0222] In this embodiment, the second control circuit 950 is electrically connected to the third clock signal terminal CLK3, the input circuit 910, the first input signal terminal INPUT1, and the second input signal terminal INPUT2. The first input signal terminal INPUT1 and the second input signal terminal INPUT2 are electrically connected to the input circuit 910 via the second control circuit 950. For example, the first input signal of the first input signal terminal INPUT1 is provided to the input circuit 910 via the second control circuit 950, and the second input signal of the second input signal terminal INPUT2 is also provided to the input circuit 910 via the second control circuit 950.

[0223] Under the control of the third clock signal from the third clock signal terminal CLK3, the first input signal and the second input signal are provided to the input circuit 910.

[0224] In this embodiment, the second control circuit 950 includes a first output terminal and a second output terminal, and the input circuit 910 includes a first input terminal and a second input terminal. For example, the first output terminal of the second control circuit 950 is electrically connected to the first input terminal of the input circuit 910, and the second output terminal of the second control circuit 950 is electrically connected to the second input terminal of the input circuit 910. The second control circuit 950 can control the supply of one of the first input signal and the second input signal from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control the supply of one of the first input signal and the second input signal from the second output terminal to the second input terminal of the input circuit 910.

[0225] For example, under the control of a third clock signal, the second control circuit 950 can control the first input signal to be provided from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control the second input signal to be provided from the second output terminal to the second input terminal of the input circuit 910. For example, under the control of a third clock signal, the second control circuit 950 can control the second input signal to be provided from the first output terminal to the first input terminal of the input circuit 910, and the second control circuit 950 can also control the first input signal to be provided from the second output terminal to the second input terminal of the input circuit 910.

[0226] In this embodiment, different input signals are input to the input circuit under the control of a third clock signal, thereby utilizing multiple cascaded shift registers 900 to perform forward and reverse scanning of the pixel array. For example, if the pixel array includes 2000 rows of pixel circuits, forward scanning can be achieved by scanning from row 1 to row 2000 using multiple cascaded shift registers 900. Reverse scanning can be achieved by scanning from row 2000 to row 1 using multiple cascaded shift registers 900.

[0227] Figure 10A This is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0228] like Figure 10A As shown, the shift register 1000 includes an input circuit 1010, a processing circuit 1020, an output circuit 1030, and a second control circuit 1050.

[0229] The input circuit 1010 includes a first input sub-circuit 1011 and a second input sub-circuit 1012. The processing circuit 1020 includes a first processing sub-circuit 1021 and a second processing sub-circuit 1022. The output circuit 1030 includes a first output sub-circuit 1031 and a second output sub-circuit 1032.

[0230] The input circuit 1010, processing circuit 1020, output circuit 1030, and second control circuit 1050 are similar to the input circuit 910, processing circuit 920, output circuit 930, and second control circuit 950 described above. The first input sub-circuit 1011 and the second input sub-circuit 1012 are similar to the first input sub-circuit 511 and the second input sub-circuit 512 described above. The first processing sub-circuit 1021 and the second processing sub-circuit 1022 are similar to the first processing sub-circuit 521 and the second processing sub-circuit 522 described above. The first output sub-circuit 1031 and the second output sub-circuit 1032 are similar to the first output sub-circuit 531 and the second output sub-circuit 532 described above. For simplicity, the same parts will not be described again here.

[0231] In this embodiment of the disclosure, the second control circuit 1050 includes a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. The seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 function as switching transistors. The seventeenth transistor T17 and the twentieth transistor T20 are N-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are P-type transistors.

[0232] The gate of the seventeenth transistor T17 is electrically connected to the third clock signal terminal CLK3. The first terminal of the seventeenth transistor T17 is electrically connected to the first input signal terminal Gate(n-1)_N. The second terminal of the seventeenth transistor T17 is electrically connected to the third node C via the input circuit 1010. The gate of the eighteenth transistor T18 is electrically connected to the third clock signal terminal CLK3. The first terminal of the eighteenth transistor T18 is electrically connected to the second input signal terminal Gate(n+1)_N. The second terminal of the eighteenth transistor T18 is electrically connected to the third node C via the input circuit 1010. The gate of the nineteenth transistor T19 is electrically connected to the third clock signal terminal CLK3. The first terminal of the nineteenth transistor T19 is electrically connected to the first input signal terminal Gate(n-1)_N. The second terminal of the nineteenth transistor T19 is electrically connected to the fourth node D via the input circuit 1010. The gate of the twentieth transistor T20 is electrically connected to the third clock signal terminal CLK3, the first terminal of the twentieth transistor T20 is electrically connected to the second input signal terminal Gate(n+1)_N, and the second terminal of the twentieth transistor T20 and the input circuit 1010 are electrically connected to the fourth node D.

[0233] In this embodiment of the present disclosure, the second terminal of the seventeenth transistor T17, the gate of the first transistor T1, and the gate of the seventh transistor T7 are electrically connected to the third node C; the second terminal of the eighteenth transistor T18, the gate of the first transistor T1, and the gate of the seventh transistor T7 are electrically connected to the third node C; the second terminal of the nineteenth transistor T19, the gate of the second transistor T2, and the gate of the fourth transistor T4 are electrically connected to the fourth node D; and the second terminal of the twentieth transistor T20, the gate of the second transistor T2, and the gate of the fourth transistor T4 are electrically connected to the fourth node D.

[0234] In this embodiment of the present disclosure, the first input signal Gate(n-1)_N or the second input signal Gate(n+1)_N is input to the gate of the first transistor T1 and the gate of the seventh transistor T7, controlled by the seventeenth transistor T17 and the eighteenth transistor T18. The first input signal Gate(n-1)_N or the second input signal Gate(n+1)_N is input to the gate of the second transistor T2 and the gate of the fourth transistor T4, controlled by the nineteenth transistor T19 and the twentieth transistor T20.

[0235] Figure 10B yes Figure 10A Timing diagram of the shift register. Figure 10B The timing waveforms of each signal in each stage are shown. The following example... Figure 10A Taking the structure of the shift register shown as an example, combined with... Figure 10B The signal timing diagram shown describes the operation of the shift register provided in this embodiment of the invention. The operation of the shift register includes six stages.

[0236] In the first stage S1, the first input signal Gate(n-1)_N is high, the second input signal Gate(n+1)_N is low, the first clock signal CLK1 is low, and the third clock signal CLK3 is high.

[0237] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, while the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0238] The first input signal Gate(n-1)_N is provided to the gates of the first transistor T1 and the seventh transistor T7 via the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gates of the third transistor T3 and the fourth transistor T4 via the twentieth transistor T20.

[0239] The working process of transistors T1 to T14 and Figure 6AThe described working process is the same, and for the sake of brevity, it will not be repeated here.

[0240] In the second stage S2, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, the first clock signal CLK1 is low, and the third clock signal CLK3 is low.

[0241] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, while the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0242] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0243] The working process of transistors T1 to T14 and Figure 6B The described working process is the same, and for the sake of brevity, it will not be repeated here.

[0244] In the third stage S3, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, the first clock signal CLK1 is high, and the third clock signal CLK3 is high.

[0245] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, while the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0246] The first input signal Gate(n-1)_N is provided to the gates of the first transistor T1 and the seventh transistor T7 via the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gates of the third transistor T3 and the fourth transistor T4 via the twentieth transistor T20.

[0247] The working process of transistors T1 to T14 and Figure 6C The described working process is the same, and for the sake of brevity, it will not be repeated here.

[0248] In the fourth stage S4, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, the first clock signal CLK1 is low, and the third clock signal CLK3 is low.

[0249] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, while the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0250] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0251] The working process of transistors T1 to T14 and Figure 6D The described working process is the same, and for the sake of brevity, it will not be repeated here.

[0252] In the fifth stage S5, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is high, the first clock signal CLK1 is low, and the third clock signal CLK3 is high.

[0253] Under the control of the third clock signal CLK3, the seventeenth transistor T17 and the twentieth transistor T20 are turned on, while the eighteenth transistor T18 and the nineteenth transistor T19 are turned off by the high level of the third clock signal CLK3.

[0254] The first input signal Gate(n-1)_N is provided to the gates of the first transistor T1 and the seventh transistor T7 via the seventeenth transistor T17. The second input signal Gate(n+1)_N is provided to the gates of the third transistor T3 and the fourth transistor T4 via the twentieth transistor T20.

[0255] The working process of transistors T1 to T14 and Figure 6E The described working process is the same, and for the sake of brevity, it will not be repeated here.

[0256] In the sixth stage S6, the first input signal Gate(n-1)_N is low, the second input signal Gate(n+1)_N is low, the first clock signal CLK1 is low, and the third clock signal CLK3 is low.

[0257] Under the control of the third clock signal CLK3, the eighteenth transistor T18 and the nineteenth transistor T19 are turned on, while the seventeenth transistor T17 and the twentieth transistor T20 are turned off by the low level of the third clock signal CLK3.

[0258] The first input signal Gate(n-1)_N is provided to the gate of the first transistor T1 and the gate of the seventh transistor T7 through the eighteenth transistor T18. The second input signal Gate(n+1)_N is provided to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the nineteenth transistor T19.

[0259] The working process of transistors T1 to T14 and Figure 6D The described working process is the same, and for the sake of brevity, it will not be repeated here.

[0260] In this embodiment of the disclosure, the pixel array is forward scanned by a cascaded plurality of shift registers 1000.

[0261] Optionally, the connection relationships of the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 can be modified to achieve reverse scanning. For example, the connection relationships can be modified as follows: the first electrode of the seventeenth transistor T17 is electrically connected to the second input signal terminal Gate(n+1)_N, the first electrode of the eighteenth transistor T18 is electrically connected to the first input signal terminal Gate(n-1)_N, the first electrode of the nineteenth transistor T19 is electrically connected to the second input signal terminal Gate(n+1)_N, and the first electrode of the twentieth transistor T20 is electrically connected to the first input signal terminal Gate(n-1)_N.

[0262] Accordingly, during reverse scanning, the timing of the third clock signal CLK3 will also change accordingly. For example, in the first stage S1, the third clock signal CLK3 is low. In the second stage S2, the third clock signal CLK3 is high. In the third stage S3, the third clock signal CLK3 is low. In the fourth stage S4, the third clock signal CLK3 is high. In the fifth stage S5, the third clock signal CLK3 is low. In the sixth stage S6, the third clock signal CLK3 is high.

[0263] Figure 11 This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present disclosure.

[0264] like Figure 11 As shown, the drive circuit 1100 includes M cascaded shift registers, where M is a positive integer greater than 1. The M shift registers include shift register ST1, shift register ST2, shift register ST3, ..., shift register STM.

[0265] In this embodiment of the disclosure, the shift register can be any one of shift registers 300, 400, 500, 700, 800, 900, and 1000 mentioned above. For example, all M shift registers can be shift register 300. For example, all M shift registers can be shift register 500. Further details will not be provided here.

[0266] In this embodiment of the disclosure, among the M cascaded shift registers, the first input signal terminal INPUT1 of the m-th shift register is electrically connected to the second scan output signal terminal OUTPUT2 of the (m-1)-th shift register, and the second input signal terminal INPUT2 of the m-th shift register is electrically connected to the second scan output signal terminal OUTPUT2 of the (m+1)-th shift register, where 1 < m ≤ M-1.

[0267] For example, the first input signal terminal INPUT1 of the second-stage shift register ST2 is electrically connected to the second scan output signal terminal OUTPUT2 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the second-stage shift register ST2 is electrically connected to the second scan output signal terminal OUTPUT2 of the third-stage shift register.

[0268] For example, the first input signal terminal INPUT1 of the second-stage shift register ST2 receives the gate drive signal Gate(1)_N from the second scan output signal terminal OUTPUT2 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the second-stage shift register ST2 receives the gate drive signal Gate(3)_N from the second scan output signal terminal OUTPUT2 of the third-stage shift register ST3. The light emission control signal terminal EM(n) of the second-stage shift register ST2 outputs the light emission control signal EM(2), the first scan output signal terminal OUTPUT1 outputs the gate drive signal Gate(2)_P, and the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(2)_N. The second-stage shift register ST2 provides the gate drive signal Gate(2)_N to the second input signal terminal INPUT2 of the first-stage shift register ST1 and the first input signal terminal INPUT1 of the third-stage shift register ST3.

[0269] For example, the second input signal terminal INPUT2 of the third-stage shift register ST3 receives the gate drive signal Gate(3)_N from the second scan output signal terminal OUTPUT2 of the next-stage shift register. The first scan output signal terminal OUTPUT1 of the third-stage shift register ST3 outputs the gate drive signal Gate(3)_P, and the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(3)_N.

[0270] In this embodiment of the disclosure, the first input signal terminal INPUT1 of the first-stage shift register ST1 is electrically connected to the scan trigger signal terminal STV, and the second input signal terminal INPUT2 of the M-stage shift register STM is electrically connected to the anti-static terminal ESD.

[0271] For example, the scan trigger signal STV inputs the scan trigger signal STV to the first input signal INPUT1 of the first stage shift register ST1. Under the control of the scan trigger signal STV, the second input signal INPUT2 and the first clock signal CLK, the gate drive signal Gate(1)_P is output by the first scan output signal OUTPUT1, the gate drive signal Gate(1)_N is output by the second scan output signal OUTPUT2, and the light emission control signal EM(n) is output by the light emission control signal EM(1).

[0272] For example, the first input signal terminal INPUT1 of the M-th stage shift register STM receives the gate drive signal Gate(M-1)_N output from the previous stage shift register, the first scan output signal terminal OUTPUT1 outputs the gate drive signal Gate(M)_P, the second scan output signal terminal OUTPUT2 outputs the gate drive signal Gate(M)_N, and the light emission control signal terminal EM(n) outputs the light emission control signal EM(M).

[0273] In this embodiment of the disclosure, the first power supply terminal VGH of the cascaded M shift registers is electrically connected to the power supply terminal Vgh, and the power supply terminal Vgh provides a high potential voltage. The second power supply terminal VGL of the cascaded M shift registers is electrically connected to the power supply terminal Vgl, and the power supply terminal Vgl provides a low potential voltage.

[0274] In this embodiment of the disclosure, the first clock signal terminal CLK1 of the odd-numbered shift register unit is electrically connected to the clock signal terminal CLK and receives the clock signal CLK. The first clock signal terminal CLK1 of the even-numbered shift register unit is electrically connected to the clock signal terminal CLB and receives the clock signal CLB.

[0275] Figure 12 This is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0276] like Figure 12 As shown, the display device 1200 may include a driving circuit 1210.

[0277] In this embodiment, the driving circuit 1210 may be the driving circuit 1100 described above, and will not be repeated here.

[0278] Figure 13 This is a flowchart of a driving method according to an embodiment of the present disclosure.

[0279] like Figure 13 As shown, the driving method may include operations S1310 to S1340.

[0280] In operation S1310, in the first stage Q1, the first input signal from the first input signal terminal is at a first level and the second input signal from the second input signal terminal is at a second level. The first power supply voltage from the first power supply terminal is provided to the light emission control signal terminal and the first node, and the second power supply voltage from the second power supply terminal is provided to the second node.

[0281] During operation S1320, in the second stage Q2, both the first input signal and the second input signal are at the second level, the first power supply voltage is provided to the light emission control signal terminal and the first node, and the second power supply voltage is provided to the second node.

[0282] During operation S1330, in the third stage Q3, the first input signal is at the second level and the second input signal is at the first level, the second power supply voltage is provided to the light emission control signal terminal and the first node, and the first power supply voltage is provided to the second node.

[0283] During operation S1340, in the fourth stage Q4, both the first input signal and the second input signal are at the second level, the second power supply voltage is provided to the light emission control signal terminal and the first node, and the first power supply voltage is provided to the second node.

[0284] In this embodiment of the disclosure, operations S1310 to S1340 are similar to the operations performed by the shift register 500 described above, and will not be repeated here.

[0285] In this embodiment of the disclosure, the first stage Q1 and Figure 6A The operation of the first stage S1 is similar to that shown, and the second stage Q2 includes... Figures 6B to 6D The operations shown are from the second stage S2 to the fourth stage S4, and the third stage Q3 and... Figure 6E The operation of the fifth stage S5 shown is similar to that of the fourth stage Q4. Figure 6F The operation of the sixth stage S6 shown is similar. For the sake of simplicity, the same parts will not be described again in this disclosure.

[0286] In this embodiment, the first level is high and the second level is low. Those skilled in the art can also set the first level to low and the second level to high depending on the type of transistor in the shift register.

[0287] For example, in the first stage Q1, the first clock signal from the first clock signal terminal is at the first level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0288] For example, the second stage Q2 includes the first sub-stage Q21, the second sub-stage Q22, and the third sub-stage Q23.

[0289] In the first sub-stage Q21, the first clock signal from the first clock signal terminal is at a second level, providing a first power supply voltage to the first output scan signal terminal and a second power supply voltage to the second output scan signal terminal. In the second sub-stage Q22, the first clock signal is at a first level, providing a second power supply voltage to the first output scan signal terminal and a first power supply voltage to the second output scan signal terminal. In the third sub-stage Q23, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0290] First sub-phase Q2_1 and Figure 6B The operation of the second stage S2 shown is similar, and the second sub-stage Q2_2 is similar to... Figure 6C The operation of the third stage S3 shown is similar, and the third sub-stage Q2_3 is the same as... Figure 6D The operation of the fourth stage S4 shown is similar.

[0291] For example, in the third stage Q3, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0292] For example, in the fourth stage Q4, the first clock signal from the first clock signal terminal is at the second level, the first power supply voltage is provided to the first output scan signal terminal, and the second power supply voltage is provided to the second output scan signal terminal.

[0293] For example, the driving method further includes: when it is determined that the current display data of the display area driven by the shift register is the same as the previous display data, setting the second clock signal from the second clock signal terminal to a second level; and when it is determined that the current display data of the specified display area driven by the shift register is different from the previous display data, setting the second clock signal to a first level; wherein, the display area is the display area where the pixel row driven by the shift register is located, the current display data is the data displayed by the pixel row driven by the shift register in the current working cycle, and the previous display data is the multi-frame display data displayed in multiple consecutive working cycles before the current working cycle.

[0294] For example, the driving method further includes: in the first stage Q1, the third clock signal from the third clock signal terminal is at a first level; in the third stage Q3, the third clock signal is at the first level; and in the fourth stage Q4, the third clock signal is at a second level.

[0295] In the first sub-stage Q21 of the second stage Q2, the third clock signal from the third clock signal terminal is at the second level. In the second sub-stage Q22 of the second stage Q2, the third clock signal is at the first level. In the third sub-stage Q23 of the second stage Q2, the third clock signal is at the second level.

[0296] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0297] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0298] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register, comprising: an input circuit electrically connected to a first input signal terminal, a second input signal terminal, a first power supply terminal, a second power supply terminal and a light emitting control signal terminal, configured to provide a first power supply voltage of the first power supply terminal or a second power supply voltage of the second power supply terminal to a first node under control of a first input signal from the first input signal terminal and a second input signal from the second input signal terminal, the light emitting control signal terminal being electrically connected to the first node; a processing circuit electrically connected to the first input signal terminal, the first node, the first power supply terminal and the second power supply terminal, configured to provide the first power supply voltage or the second power supply voltage to a second node under control of an electric potential of the first node and the first input signal, wherein the input circuit is electrically connected to the second node, and under control of an electric potential of the second node, the input circuit provides the first power supply voltage or the second power supply voltage to the light emitting control signal terminal; and an output circuit electrically connected to a first clock signal terminal, the first node, the first power supply terminal, the second power supply terminal, a first output scan signal terminal and a second output scan signal terminal, configured to provide the first power supply voltage or the second power supply voltage to the first output scan signal terminal under control of an electric potential of the first node and a first clock signal from the first clock signal terminal, and provide the first power supply voltage or the second power supply voltage to the second output scan signal terminal under control of an electric potential of the first output scan signal terminal.

2. The shift register of claim 1, wherein, The input circuit comprises: a first input sub-circuit electrically connected to the first input signal terminal, the second input signal terminal, the first power supply terminal and the light emitting control signal terminal, configured to provide the first power supply voltage to the light emitting control signal terminal under control of the first input signal and the second input signal; and a second input sub-circuit electrically connected to the second input signal terminal, the second power supply terminal and the light emitting control signal terminal, configured to provide the second power supply voltage to the light emitting control signal terminal under control of the second input signal.

3. The shift register of claim 2, wherein, The first input sub-circuit comprises a first transistor, a second transistor and a third transistor; wherein a control electrode of the first transistor is electrically connected to the first input signal terminal, a first electrode of the first transistor is electrically connected to the second input signal terminal, and a second electrode of the first transistor is electrically connected to a control electrode of the third transistor; a control electrode of the second transistor is electrically connected to the second input signal terminal, a first electrode of the second transistor is electrically connected to the first power supply terminal, and a second electrode of the second transistor is electrically connected to a first electrode of the third transistor; a control electrode of the third transistor and the second electrode of the first transistor are electrically connected to the second node, and a second electrode of the third transistor and the light emitting control signal terminal are electrically connected to the first node.

4. The shift register of claim 2, wherein, The second input sub-circuit comprises a fourth transistor and a fifth transistor; The control electrode of the fourth transistor is electrically connected to the second input signal end, the first electrode of the fourth transistor is electrically connected to the second power supply end, and the second electrode of the fourth transistor is electrically connected to the first node and the light-emitting control signal end. The control electrode of the fifth transistor is electrically connected to the first input sub-circuit and the second node, the first electrode of the fifth transistor is electrically connected to the second power supply end, and the second electrode of the fifth transistor is electrically connected to the first node and the light-emitting control signal end.

5. The shift register of claim 1, wherein, The processing circuit comprises: The first processing sub-circuit is electrically connected to the first node, the second node and the second power supply end, and is configured to provide the second power supply voltage to the second node under the control of the potential of the first node; and The second processing sub-circuit is electrically connected to the first input signal end, the first node, the second node and the first power supply end, and is configured to provide the first power supply voltage to the second node under the control of the potential of the first node and the first input signal.

6. The shift register of claim 5, wherein, The first processing sub-circuit comprises a sixth transistor, wherein the control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second power supply end, and the second electrode of the sixth transistor is electrically connected to the second node.

7. The shift register of claim 5, wherein, The second processing sub-circuit comprises a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the first input signal end, the first electrode of the seventh transistor is electrically connected to the first power supply end, and the second electrode of the seventh transistor is electrically connected to the first electrode of the eighth transistor; and The control electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the second node and the first processing sub-circuit.

8. The shift register of claim 1, wherein, The output circuit comprises: The first output sub-circuit is electrically connected to the first clock signal end, the first node, the first power supply end, the second power supply end and the first output scanning signal end, and is configured to provide the first power supply voltage or the second power supply voltage to the first output scanning signal end under the control of the potential of the first node and the first clock signal; and The second output sub-circuit is electrically connected to the first output scanning signal end, the first power supply end, the second power supply end and the second output scanning signal end, and is configured to provide the first power supply voltage or the second power supply voltage to the second output scanning signal end under the control of the potential of the first output scanning signal end.

9. The shift register of claim 8, wherein, The first output sub-circuit comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; The control electrode of the ninth transistor is electrically connected to the first clock signal end, the first electrode of the ninth transistor is electrically connected to the first power supply end, and the second electrode of the ninth transistor is electrically connected to the first output scanning signal end; The control electrode of the tenth transistor is electrically connected to the first clock signal end, the first electrode of the tenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is electrically connected to the first output scanning signal end; The control electrode of the eleventh transistor is electrically connected to the first node, and the first electrode of the eleventh transistor is electrically connected to the second power supply end. The control electrode of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the first power supply end, and the second electrode of the twelfth transistor is electrically connected to the first output scanning signal end.

10. The shift register of claim 8, wherein, The second output sub-circuit includes a thirteenth transistor and a fourteenth transistor; The control electrode of the thirteenth transistor is electrically connected to the first output scanning signal end, the first electrode of the thirteenth transistor is electrically connected to the first power supply end, and the second electrode of the thirteenth transistor is electrically connected to the second output scanning signal end. The control electrode of the fourteenth transistor is electrically connected to the first output scanning signal end, the first electrode of the fourteenth transistor is electrically connected to the second power supply end, and the second electrode of the fourteenth transistor is electrically connected to the second output scanning signal end.

11. The shift register according to any one of claims 1-10, further comprising: a first control circuit electrically connected to a second clock signal end, the first output scanning signal end, the second output scanning signal end, a third output scanning signal end, and a fourth output scanning signal end, and configured to provide a potential of the first output scanning signal end to the third output scanning signal end and provide a potential of the second output scanning signal end to the fourth output scanning signal end under control of a second clock signal from the second clock signal end.

12. The shift register of claim 11, wherein, The first control circuit includes a fifteenth transistor and a sixteenth transistor; The control electrode of the fifteenth transistor is electrically connected to the second clock signal end, the first electrode of the fifteenth transistor is electrically connected to the second output scanning signal end, and the second electrode of the fifteenth transistor is electrically connected to the fourth output scanning signal end. The control electrode of the sixteenth transistor is electrically connected to the second clock signal end, the first electrode of the sixteenth transistor is electrically connected to the first output scanning signal end, and the second electrode of the sixteenth transistor is electrically connected to the third output scanning signal end.

13. The shift register according to any one of claims 1-12, further comprising: a second control circuit electrically connected to a third clock signal end, the input circuit, the first input signal end, and the second input signal end, and configured to provide the first input signal and the second input signal to the input circuit under control of a third clock signal from the third clock signal end; The first input signal end and the second input signal end are electrically connected to the input circuit through the second control circuit.

14. The shift register of claim 13, wherein, The second control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; The control electrode of the seventeenth transistor is electrically connected to the third clock signal terminal, the first electrode of the seventeenth transistor is electrically connected to the first input signal terminal, and the second electrode of the seventeenth transistor is electrically connected to the input circuit and the third node; The control electrode of the eighteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the eighteenth transistor is electrically connected to the second input signal terminal, and the second electrode of the eighteenth transistor is electrically connected to the input circuit and the third node; The control electrode of the nineteenth transistor is electrically connected to the third clock signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first input signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the input circuit and the fourth node; and The control electrode of the twentieth transistor is electrically connected to the third clock signal terminal, the first electrode of the twentieth transistor is electrically connected to the second input signal terminal, and the second electrode of the twentieth transistor is electrically connected to the input circuit and the fourth node.

15. A driving circuit comprising M shift registers as claimed in any one of claims 1-14 connected in cascade, M being a positive integer greater than 1; the first input signal terminal of the mth shift register is electrically connected to the second scan output signal terminal of the (m-1)th shift register, and the second input signal terminal of the mth shift register is electrically connected to the second scan output signal terminal of the (m+1)th shift register, 1 16. The drive circuit of claim 15, wherein, the first input signal terminal of the first shift register is electrically connected to a scan trigger signal terminal, and the second input signal terminal of the Mth shift register is electrically connected to an anti-static terminal.

17. A display device comprising the driving circuit as claimed in claim 15 or 16.

18. A driving method applied to the shift register as claimed in any one of claims 1-14, comprising: in a first stage, a first input signal from a first input signal terminal is at a first level and a second input signal from a second input signal terminal is at a second level, a first power voltage of a first power terminal is provided to a light-emitting control signal terminal and a first node, and a second power voltage of a second power terminal is provided to a second node; in a second stage, the first input signal and the second input signal are both at the second level, the first power voltage is provided to the light-emitting control signal terminal and the first node, and the second power voltage is provided to the second node; in a third stage, the first input signal is at the second level and the second input signal is at the first level, the second power voltage is provided to the light-emitting control signal terminal and the first node, and the first power voltage is provided to the second node; and in a fourth stage, the first input signal and the second input signal are both at the second level, the second power voltage is provided to the light-emitting control signal terminal and the first node, and the first power voltage is provided to the second node.

19. The driving method as claimed in claim 18, further comprising: ​ In the first stage, a first clock signal from a first clock signal terminal is at a first level, the first power voltage is provided to the first output scan signal terminal, and the second power voltage is provided to the second output scan signal terminal.

20. The driving method according to claim 18, wherein The second stage includes a first sub-stage, a second sub-stage, and a third sub-stage, and the method further includes: In the first sub-stage, the first clock signal from the first clock signal terminal is at a second level, the first power voltage is provided to the first output scan signal terminal, and the second power voltage is provided to the second output scan signal terminal; In the second sub-stage, the first clock signal is at the first level, the second power voltage is provided to the first output scan signal terminal, and the first power voltage is provided to the second output scan signal terminal; and In the third sub-stage, the first power voltage is provided to the first output scan signal terminal, and the second power voltage is provided to the second output scan signal terminal.

21. The driving method of claim 18, further comprising: In the third stage, the first clock signal from the first clock signal terminal is at the second level, the first power voltage is provided to the first output scan signal terminal, and the second power voltage is provided to the second output scan signal terminal.

22. The driving method of claim 18, further comprising: In the fourth stage, the first clock signal from the first clock signal terminal is at the second level, the first power voltage is provided to the first output scan signal terminal, and the second power voltage is provided to the second output scan signal terminal.

23. The driving method of claim 18, further comprising: In a case where it is determined that current display data of a display region driven by the shift register is the same as previous display data, setting a second clock signal from a second clock signal terminal to be at a second level; and In a case where it is determined that the current display data of the display region driven by the shift register is different from the previous display data, setting the second clock signal to be at a first level; wherein the display region is a display region in which a pixel row of the shift register is located, the current display data is data displayed by the shift register for the pixel row in a current working period, and the previous display data is a plurality of frames of display data displayed in a plurality of continuous working periods before the current working period.

24. The driving method of claim 18, further comprising: In the first stage, a third clock signal from a third clock signal terminal is at a first level; In the third stage, the third clock signal is at the first level; and In the fourth stage, the third clock signal is at a second level.

25. The driving method of claim 20, further comprising: In the first sub-stage, a third clock signal from a third clock signal terminal is at a second level; In the second sub-stage, the third clock signal is at the first level; and In the third sub-stage, the third clock signal is at the second level.

Images