Shift register and driving method thereof, display substrate and display device

Abstract

The invention discloses a shift register and a driving method thereof, a display substrate and a display device. The shift register comprises a cascade output sub-circuit and a scanning output sub-circuit, the cascade output sub-circuit is configured to provide signals for a first node (N1) and a second node (N2) under the control of signals of a signal input end (IN), a first clock signal end (CK1) and a second clock signal end (CK2), and provide signals of a first power supply end or a second power supply end (V2) for a cascade output end (COUT) under the control of signals of the first node (N1) and the second node (N2); and the scanning output sub-circuit is configured to provide a signal of the first power supply end (V1) or the second power supply end (V2) to the scanning output end (NOUT) under the control of the signals of the first node (N1), the second node (N2) and the scanning control signal end (MS).

Description

Shift register and driving method thereof, display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a shift register and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003]

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a shift register, comprising: a cascade output subcircuit and a scan output subcircuit;

[0006] The cascade output subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the cascade output terminal, the first node, and the second node, respectively, and is configured to provide signals to the first node and the second node under the control of signals from the signal input terminal, the first clock signal terminal, and the second clock signal terminal, and to provide signals from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals from the first node and the second node;

[0007] The scan output sub-circuit is electrically connected to the scan control signal terminal, the first power supply terminal, the second power supply terminal, the scan output terminal, the first node and the second node, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.

[0008] In an exemplary embodiment, the scan output subcircuit includes: a first output control subcircuit and a second output control subcircuit;

[0009] The first output control subcircuit is electrically connected to the second power supply terminal, the scan output terminal and the second node respectively, and is configured to provide a signal of the second power supply terminal to the scan output terminal under the control of a signal of the second node;

[0010] The second output control subcircuit is electrically connected to the scan control signal terminal, the first power supply terminal, the scan output terminal and the first node, respectively, and is configured to provide a signal from the first power supply terminal to the scan output terminal under the control of the signal from the scan control signal terminal and the first node.

[0011] In an exemplary embodiment, the scan output subcircuit further includes: a storage subcircuit;

[0012] The storage sub-circuit is electrically connected to the scan output terminal and the first power supply terminal respectively, and is configured to store a voltage difference between the signal at the scan output terminal and the signal at the first power supply terminal.

[0013] In an exemplary embodiment, the first output control subcircuit includes: a seventeenth transistor;

[0014] The control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal.

[0015] In an exemplary embodiment, the second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor;

[0016] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;

[0017] The control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node.

[0018] In an exemplary embodiment, the second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor;

[0019] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;

[0020] The control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node.

[0021] In an exemplary embodiment, the storage subcircuit includes: a fifth capacitor;

[0022] The first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.

[0023] In an exemplary embodiment, the cascade output subcircuit includes: a first transistor to a sixteenth transistor and a first capacitor to a fourth capacitor, and any capacitor of the first capacitor to the fourth capacitor includes: a first plate and a second plate;

[0024] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0025] The control electrode of the second transistor is electrically connected to the fourth node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the fifth node;

[0026] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fifth node;

[0027] The control electrode of the fourth transistor is electrically connected to the sixth node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the seventh node;

[0028] A control electrode of the fifth transistor is electrically connected to the fifth node, a first electrode of the fifth transistor is electrically connected to the first power supply terminal, and a second electrode of the fifth transistor is electrically connected to the seventh node;

[0029] The control electrode of the sixth transistor is electrically connected to the ninth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the eighth node;

[0030] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the eighth node, and the second electrode of the seventh transistor is electrically connected to the first node;

[0031] The control electrode of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth transistor is electrically connected to the first node;

[0032] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;

[0033] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;

[0034] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the fifth node, and the second electrode of the eleventh transistor is electrically connected to the ninth node;

[0035] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0036] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node;

[0037] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the tenth node;

[0038] A control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor is electrically connected to the tenth node, and a second electrode of the fifteenth transistor is electrically connected to the sixth node;

[0039] The control electrode of the sixteenth transistor is electrically connected to the sixth node, the first electrode of the sixteenth transistor is electrically connected to the sixth node, and the second electrode of the sixteenth transistor is electrically connected to the second node;

[0040] The first plate of the first capacitor is electrically connected to the ninth node, and the second plate of the first capacitor is electrically connected to the eighth node;

[0041] A first plate of the second capacitor is electrically connected to the first node, and a second plate of the second capacitor is electrically connected to the first power supply terminal;

[0042] The first plate of the third capacitor is electrically connected to the sixth node, and the second plate of the third capacitor is electrically connected to the seventh node;

[0043] The first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal.

[0044] In an exemplary embodiment, the scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor;

[0045] The control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal;

[0046] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;

[0047] The control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;

[0048] The first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.

[0049] In an exemplary embodiment, the scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor;

[0050] The control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal;

[0051] The control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;

[0052] The control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;

[0053] The first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.

[0054] In a second aspect, the present disclosure further provides a display substrate, comprising: a gate driving circuit located in the non-display area and array-arranged sub-pixels and a plurality of gate lines located in the display area, the sub-pixels comprising a pixel driving circuit and a light-emitting device, the gate lines at least partially extending along a first direction, the gate driving circuit comprising: a plurality of cascaded shift registers, the pixel driving circuit comprising: a plurality of transistors;

[0055] The cascade output terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.

[0056] The gate line is electrically connected to the gate electrode of the at least one transistor, and any shift register is electrically connected to at least one gate line.

[0057] In an exemplary embodiment, the display area is divided into a plurality of display sub-areas, at least one display sub-area includes: at least one gate line; the display mode of any display sub-area includes: a first display mode and a second display mode, the refresh frequency of the first display mode is greater than the refresh frequency of the second display mode;

[0058] When the display mode of the display sub-area is the first display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output end is a first level signal, at least part of the time period of the signal at the scan control signal end is a valid level signal, and the signal at the scan output end is a first level signal;

[0059] When the display mode of the display sub-area is the second display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output end is a first level signal, the signal at the scan control signal end is an invalid level signal, and the signal at the scan output end is a second level signal;

[0060] Wherein, the voltage value of the first level signal is greater than the voltage value of the second level signal.

[0061] In an exemplary embodiment, the invention further comprises: at least one scan control signal line located in the non-display area, the scan control signal line at least partially extending along a second direction, the first direction and the second direction intersecting;

[0062] The scanning control signal terminals connected to all the shift registers are electrically connected to the at least one scanning control signal line.

[0063] In an exemplary embodiment, the number of the scanning control signal line is one,

[0064] The scanning control signal terminals connected to all the shift registers are electrically connected to the same scanning control signal line.

[0065] In an exemplary embodiment, the number of the scan control signal lines is at least two;

[0066] The scanning control signal end connected to any shift register from the M*(k-1)+K*M(a-1)+1th shift register to the k*M+K*M(a-1)th shift register is electrically connected to the kth scanning control signal line, 1≤k≤K, 1≤a≤N / M, M is the number of shift registers connected to a scanning control signal line, N is the total number of shift registers, and K is the number of scanning control signal lines.

[0067] In an exemplary embodiment, the screen displayed by the display substrate includes: a plurality of display frames, in any display frame, the output signal of the scan output end of the shift register is a pulse signal, and the duration H of the pulse signal satisfies the following relationship: H = L*[M*K-(M-1)]*h

[0068] Wherein, L is the number of gate lines connected to any stage of shift register, and h is the unit time, which is equal to the refresh interval time of adjacent rows of sub-pixels.

[0069] In an exemplary embodiment, the invention further comprises: a first clock signal line, a second clock signal line, a first power line, a second power line and a third power line located in the non-display area; any one of the first clock signal line, the second clock signal line, the first power line, the second power line and the third power line at least partially extending along the second direction;

[0070] The first clock signal terminal connected to any stage of the shift register is electrically connected to one of the first clock signal line and the second clock signal line, the second clock signal terminal connected to any stage of the shift register is electrically connected to the other of the first clock signal line and the second clock signal line, the clock signal lines connected to the first clock signal terminals connected to adjacent shift registers are different, the clock signal lines connected to the second clock signal terminals connected to adjacent shift registers are different, the first power supply terminals connected to all the shift registers are electrically connected to the first power supply line, the second power supply terminals connected to all the shift registers are electrically connected to the second power supply line, and the third power supply terminals connected to all the shift registers are electrically connected to the third power supply line.

[0071] In an exemplary embodiment, the scan control signal line is located on a side of any one of the first clock signal line, the second clock signal line, the first power line, the second power line, and the third power line close to the display area.

[0072] In an exemplary embodiment, the number of the second power lines is two, and the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first power line are arranged in sequence in a direction close to the display area.

[0073] In an exemplary embodiment, the shift register includes: a seventeenth transistor to a nineteenth transistor; the seventeenth transistor to the nineteenth transistor are arranged along the second direction;

[0074] At least a portion of any one of the seventeenth to nineteenth transistors is located between the first power line and the scan control signal line.

[0075] In an exemplary embodiment, any one of the transistors includes an active pattern, and an average length of the active pattern of the seventeenth transistor along the first direction is smaller than an average length of the active pattern of any one of the eighteenth transistor and the nineteenth transistor along the first direction.

[0076] In an exemplary embodiment, a line width of any one of the first power line and the second power line is greater than a line width of the scan control signal line.

[0077] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0078] In a fourth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, and the method comprises:

[0079] The cascade output subcircuit provides signals to the first node and the second node under the control of signals at the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides signals at the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals at the first node and the second node;

[0080] The scan output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.

[0081] Other aspects will be apparent upon reading and understanding the drawings and detailed description.

[0082] BRIEF DESCRIPTION OF THE DRAWINGS

[0083] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0084] FIG1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure;

[0085] FIG2 is a schematic diagram of the structure of a shift register provided by an exemplary embodiment;

[0086] FIG3 is a schematic diagram of the structure of a shift register provided by an exemplary embodiment;

[0087] FIG4 is an equivalent circuit diagram of a first output control subcircuit provided in an exemplary embodiment;

[0088] FIG5 is an equivalent circuit diagram of a second output control subcircuit provided in an exemplary embodiment;

[0089] FIG6 is an equivalent circuit diagram of a second output control subcircuit provided in another exemplary embodiment;

[0090] FIG. 7 is an equivalent circuit diagram of a storage sub-circuit provided in an exemplary embodiment;

[0091] FIG8 is an equivalent circuit diagram of a cascade output subcircuit provided in an exemplary embodiment;

[0092] FIG9 is an equivalent circuit diagram 1 of a shift register;

[0093] FIG10 is a second equivalent circuit diagram of a shift register;

[0094] FIG11 is a third equivalent circuit diagram of a shift register;

[0095] FIG12 is a fourth equivalent circuit diagram of a shift register;

[0096] FIG13 is a timing diagram of the cascade output subcircuit in the shift register provided in FIGS. 9 to 12 ;

[0097] FIG14 is a timing diagram 1 of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;

[0098] FIG15 is a second timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;

[0099] FIG16 is a third timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;

[0100] FIG17 is a fourth timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;

[0101] FIG18 is a schematic structural diagram of a display substrate;

[0102] FIG19 is a cascade schematic diagram 1 of a gate drive circuit;

[0103] FIG20 is a second cascade schematic diagram of a gate drive circuit;

[0104] FIG21 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0105] FIG22 is a schematic diagram of an equivalent circuit of another pixel driving circuit;

[0106] FIG23 is a working timing diagram of the pixel driving circuit provided in FIG21 and FIG22;

[0107] FIG24 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in FIG19;

[0108] FIG25 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in FIG20;

[0109] FIG26 is a partial schematic diagram of a non-display area of ​​a display substrate;

[0110] FIG27 is a schematic diagram of active patterns of seventeenth to nineteenth transistors;

[0111] FIG28 is a schematic diagram of FIG26 after a semiconductor layer pattern is formed;

[0112] FIG29 is a schematic diagram of a first conductive layer pattern in FIG26 ;

[0113] FIG30 is a schematic diagram of FIG26 after the first conductive layer pattern is formed;

[0114] FIG31 is a schematic diagram of a second conductive layer pattern in FIG26 ;

[0115] FIG32 is a schematic diagram of FIG26 after forming a second conductive layer pattern;

[0116] FIG33 is a schematic diagram of FIG26 after forming a third insulating layer pattern;

[0117] FIG34 is a schematic diagram of a third conductive layer pattern in FIG26;

[0118] FIG35 is a schematic diagram of FIG26 after forming a third conductive layer pattern;

[0119] FIG36 is a schematic diagram of FIG26 after forming a fourth insulating layer pattern;

[0120] FIG37 is a schematic diagram of a fourth conductive layer pattern in FIG26;

[0121] FIG. 38 is a schematic diagram of FIG. 26 after the fourth conductive layer pattern is formed.

[0122] Details

[0123] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0124] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0125] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0126] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0127] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0128] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0129] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0130] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0131] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0132] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0133] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0134] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0135] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0136] The display substrate includes: a pixel circuit, a light emitting device and a gate driving circuit, wherein the gate driving circuit is configured to provide a gate signal to the pixel circuit so that the pixel circuit can drive the light emitting device to emit light. The driving capability of the gate driving circuit is relatively weak and cannot meet the display requirements.

[0137] In the display market, most display substrates use low-temperature polysilicon (LTPS) technology, which has advantages such as high resolution, high response speed, high brightness, and high aperture ratio. Although it is popular in the market, LTPS technology also has some defects, such as high production cost and high power consumption. At this time, low-temperature polycrystalline oxide (LTPO) technology came into being. Compared with LTPS technology, LTPO technology has smaller leakage current and faster pixel response. The display substrate has an extra layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed.

[0138] The display product includes: a gate drive circuit and multiple sub-pixels. The sub-pixels include a pixel drive circuit. When the display product displays a picture, the gate drive circuit generates a drive signal, and the pixel drive circuit is initialized and data is written under the control of the drive signal to achieve display. When the display product displays, it will refresh the surface in each frame, that is, the pixel drive circuit needs to be initialized and data written in each display frame. However, for some special pictures (for example: off-screen display pictures, static pictures or pictures that are updated less frequently, etc.), the pixel drive circuit does not need to be initialized and data written in at least some display frames, and the original brightness can be maintained by a low-leakage pixel drive circuit. A gate drive circuit of a display product generates a drive signal in each frame regardless of the picture displayed, and repeatedly initializes and writes data to the pixel drive circuit, which makes the power consumption of the display product higher.

[0139] Fig. 1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure. As shown in Fig. 1, the shift register provided by an embodiment of the present disclosure may include: a cascade output subcircuit and a scan output subcircuit.

[0140] As shown in Figure 1, the cascade output sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the cascade output terminal COUT, the first node N1 and the second node N2, and is configured to provide signals to the first node N1 and the second node N2 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2, and to provide the signal of the first power supply terminal V1 or the second power supply terminal V2 to the cascade output terminal COUT under the control of the signals of the first node N1 and the second node N2; the scan output sub-circuit is electrically connected to the scan control signal terminal MS, the first power supply terminal V1, the second power supply terminal V2, the scan output terminal NOUT, the first node N1 and the second node N2, and is configured to provide the signal of the first power supply terminal V1 or the second power supply terminal V2 to the scan output terminal NOUT under the control of the signals of the first node N1, the second node N2 and the scan control signal terminal MS.

[0141] In an exemplary embodiment, the signal at the signal input terminal IN is a single pulse signal.

[0142] In an exemplary embodiment, the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a square wave signal that repeats a high voltage and a low voltage. Exemplarily, the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period and may be configured as a phase-shifted signal. Here, the signal of the second clock signal terminal CK2 may be phase-shifted by half a period compared to the signal of the first clock signal terminal CK1. The high voltage period of the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 in each period may be set to be longer than the low voltage period.

[0143] In an exemplary embodiment, the high voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the low voltage period of the signal of the second clock signal terminal CK2, and the low voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the high voltage period of the signal of the second clock signal terminal CK2.

[0144] In an exemplary embodiment, the signal of the first power terminal V1 is a constant voltage signal, and is a high level signal.

[0145] In an exemplary embodiment, the signal of the second power supply terminal V2 is a constant voltage signal, and is a low level signal.

[0146] In an exemplary embodiment, when the display product displays a normal picture, in any display frame, the signal at the scan control signal end is a valid level signal when the signal at the cascade output end is a first level signal, so that the signal at the first power supply end V1 is written to the scan output end NOUT, and when the display product displays a special picture, in some display frames, the signal at the scan control signal end is an invalid level signal when the signal at the cascade output end is a first level signal, so that the signal at the second power supply end V2 is written to the scan output end NOUT. The first level signal may be a high level signal, signal A being a valid level signal means that signal A can turn on the transistor connected to signal A, and signal A being an invalid level signal means that signal A can turn off the transistor connected to signal A.

[0147] The scan output subcircuit provided in the embodiment of the present disclosure can control the output within a display frame, and can also control the partial screen refresh of different display frames, thereby reducing the power consumption of the display product.

[0148] The shift register provided in the embodiment of the present disclosure is electrically connected to the scan control signal terminal through the scan output subcircuit, and can control whether to provide a drive signal to the scan output terminal through the scan control signal terminal. When displaying a normal picture, the drive signal can be output in each display frame, and the pixel drive circuit can be repeatedly initialized and data written to ensure normal display. When displaying a special picture, the drive signal can be not output in some display frames, thereby reducing the number of times the pixel drive circuit is initialized and data is written, thereby reducing the power consumption of the display product and realizing low-power display of the display product.

[0149] Fig. 2 is a schematic diagram of the structure of a shift register provided in an exemplary embodiment. As shown in Fig. 2, in an exemplary embodiment, the scan output subcircuit may include: a first output control subcircuit and a second output control subcircuit.

[0150] As shown in Figure 2, the first output control sub-circuit is electrically connected to the second power supply terminal V2, the scan output terminal NOUT and the second node N2, respectively, and is configured to provide a signal from the second power supply terminal V2 to the scan output terminal NOUT under the control of the signal from the second node N2; the second output control sub-circuit is electrically connected to the scan control signal terminal MS, the first power supply terminal V1, the scan output terminal NOUT and the first node N1, respectively, and is configured to provide a signal from the first power supply terminal V1 to the scan output terminal NOUT under the control of the signal from the scan control signal terminal MS and the first node N1.

[0151] FIG3 is a schematic diagram of the structure of a shift register provided in an exemplary embodiment. As shown in FIG3, in an exemplary embodiment, the scan output subcircuit may further include: a storage subcircuit. The storage subcircuit is electrically connected to the scan output terminal NOUT and the first power supply terminal V1, respectively, and is configured to store the voltage difference between the signal of the scan output terminal NOUT and the first power supply terminal V1.

[0152] Fig. 4 is an equivalent circuit diagram of a first output control subcircuit provided in an exemplary embodiment. As shown in Fig. 4, in an exemplary embodiment, the first output control subcircuit may include: a seventeenth transistor T17.

[0153] As shown in FIG4 , a control electrode of the seventeenth transistor T17 is electrically connected to the second node N2 , a first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2 , and a second electrode of the seventeenth transistor T17 is electrically connected to the scan output terminal NOUT.

[0154] FIG4 only shows an exemplary structure of the first output control subcircuit. It is easy for those skilled in the art to understand that the implementation of the first output control subcircuit is not limited thereto.

[0155] Fig. 5 is an equivalent circuit diagram of a second output control subcircuit provided in an exemplary embodiment, and Fig. 6 is an equivalent circuit diagram of a second output control subcircuit provided in another exemplary embodiment. As shown in Fig. 5 and Fig. 6, in an exemplary embodiment, the second output control subcircuit may include: an eighteenth transistor T18 and a nineteenth transistor T19.

[0156] As shown in Figure 5, the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1, and the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3; the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS, the first electrode of the nineteenth transistor T19 is electrically connected to the scan output terminal NOUT, and the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3.

[0157] As shown in Figure 6, the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the scan output terminal NOUT, and the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3; the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS, the first electrode of the nineteenth transistor T19 is electrically connected to the first power supply terminal V1, and the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3.

[0158] FIG. 5 and FIG. 6 only show two exemplary structures of the second output control subcircuit. It is easy for those skilled in the art to understand that the implementation of the second output control subcircuit is not limited thereto.

[0159] FIG. 7 is an equivalent circuit diagram of a storage sub-circuit provided in an exemplary embodiment. As shown in FIG. 7 , in an exemplary embodiment, the storage sub-circuit may include: a fifth capacitor C5 .

[0160] As shown in FIG. 7 , the first plate C51 of the fifth capacitor C5 is electrically connected to the scan output terminal NOUT, and the second plate C52 of the fifth capacitor C5 is electrically connected to the first power supply terminal V1 .

[0161] In an exemplary embodiment, the configuration of the storage sub-circuit can ensure the stability of the output signal of the scan output terminal NOUT and improve the reliability of the shift register.

[0162] FIG. 7 only shows an exemplary structure of a storage sub-circuit. Those skilled in the art will readily appreciate that the implementation of the storage sub-circuit is not limited thereto.

[0163] In an exemplary embodiment, the cascade output sub-circuit may be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C or 16T4C, which is not limited in the present disclosure.

[0164] The scan output subcircuit provided in the embodiment of the present disclosure includes only three transistors, has a simple structure, is conducive to the layout of the odor register, can also reduce the area occupied by the shift register, and can achieve a narrow frame.

[0165] FIG8 is an equivalent circuit diagram of a cascade output subcircuit provided in an exemplary embodiment. FIG8 is illustrated by taking 16T4C as an example. As shown in FIG8, in an exemplary embodiment, the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, and any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate.

[0166] As shown in FIG8 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; The sixth node N6 is electrically connected, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the seventh node N7; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the The control electrode of the eighth transistor T8 is electrically connected to the fourth node N4, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal COUT; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal COUT; the control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, and the second electrode of the twelfth transistor T12 is electrically connected to the second node N2; the control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4;The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and the second electrode of the fourteenth transistor T14 is electrically connected to the tenth node N10; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6. The second node N2 is electrically connected; the first plate C11 of the first capacitor C1 is electrically connected to the ninth node N9, and the second plate C12 of the first capacitor C1 is electrically connected to the eighth node N8; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal V1; the first plate C31 of the third capacitor C3 is electrically connected to the sixth node N6, and the second plate C32 of the third capacitor C3 is electrically connected to the seventh node N7; the first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal COUT.;

[0167] In an exemplary embodiment, when the cascade output sub-circuit is a circuit structure of 10T3C, the cascade output sub-circuit includes: first to tenth transistors T1 to T10 and first to third capacitors C1 to C3.

[0168] In an exemplary embodiment, when the cascade output sub-circuit is a circuit structure of 10T4C, the cascade output sub-circuit includes: first to tenth transistors T1 to T10 and first to fourth capacitors C1 to C4.

[0169] In an exemplary embodiment, when the cascade output sub-circuit is a 12T3C circuit structure, the cascade output sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3.

[0170] In an exemplary embodiment, when the cascade output sub-circuit is a 12T3C circuit structure, the cascade output sub-circuit includes: first to twelfth transistors T1 to T12 and first to fourth capacitors C1 to C4.

[0171] In an exemplary embodiment, when the cascade output sub-circuit is a circuit structure of 13T3C, the cascade output sub-circuit includes: first to thirteenth transistors T1 to T13 and first to third capacitors C1 to C3.

[0172] In an exemplary embodiment, when the cascade output sub-circuit is a circuit structure of 13T4C, the cascade output sub-circuit includes: first to thirteenth transistors T1 to T13 and first to fourth capacitors C1 to C4.

[0173] In an exemplary embodiment, when the cascade output sub-circuit is a 16T3C circuit structure, the cascade output sub-circuit includes: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.

[0174] FIG9 is an equivalent circuit diagram 1 of a shift register, and FIG10 is an equivalent circuit diagram 2 of a shift register. As shown in FIG9 and FIG10, in an exemplary embodiment, the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate, and the scan output subcircuit includes: a seventeenth transistor T17 to a nineteenth transistor T19, or includes: a seventeenth transistor to a nineteenth transistor T19 and a fifth capacitor C5. FIG9 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19, and FIG10 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19 and the fifth capacitor C5.

[0175] As shown in FIGS. 9 and 10 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5; The control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N9; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 ... fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7 a control electrode of the eighth transistor T8 is electrically connected to the fourth node N4, a first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1, and a second electrode of the eighth transistor T8 is electrically connected to the first node N1; a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and a second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal COUT; a control electrode of the tenth transistor T10 is electrically connected to the second node N2, a first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and a second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal COUT; The cascade output terminal COUT is electrically connected; the control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, and the second electrode of the twelfth transistor T12 is electrically connected to the second node N2; the control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4;The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and the second electrode of the fourteenth transistor T14 is electrically connected to the tenth node N10; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; the first electrode plate C11 of the first capacitor C1 is electrically connected to the ninth node N9; the control electrode of the seventeenth transistor T17 is electrically connected to the second node N2, the first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2, and the second electrode of the seventeenth transistor T17 is electrically connected to the scan output terminal NOUT; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, and the eighteenth transistor T18 is electrically connected to the first node N1. The first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1, the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3; the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS, the first electrode of the nineteenth transistor T19 is electrically connected to the scan output terminal NOUT, and the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3; the second electrode plate C12 of the first capacitor C1 is electrically connected to the eighth node N8; the first electrode plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second capacitor C2 The second plate C22 of the third capacitor C3 is electrically connected to the first power supply terminal V1; the first plate C31 of the third capacitor C3 is electrically connected to the sixth node N6, and the second plate C32 of the third capacitor C3 is electrically connected to the seventh node N7; the first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal COUT; the first plate C51 of the fifth capacitor C5 is electrically connected to the scan output terminal NOUT, and the second plate C52 of the fifth capacitor C5 is electrically connected to the first power supply terminal V1.;

[0176] FIG11 is a third equivalent circuit diagram of a shift register, and FIG12 is a fourth equivalent circuit diagram of a shift register. As shown in FIG11 and FIG12, in an exemplary embodiment, the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate, and the scan output subcircuit includes: a seventeenth transistor T17 to a nineteenth transistor T19, or includes: a seventeenth transistor T17 to a nineteenth transistor T19 and a fifth capacitor C5. FIG11 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19, and FIG12 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19 and the fifth capacitor C5.

[0177] As shown in FIGS. 11 and 12 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5; the control electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5; The control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N9; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, a control electrode of the eighth transistor T8 is electrically connected to the fourth node N4, a first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1, and a second electrode of the eighth transistor T8 is electrically connected to the first node N1; a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and a second electrode of the ninth transistor T9 is electrically connected to the cascade output terminal COUT; a control electrode of the tenth transistor T10 is electrically connected to the second node N2, a first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and a second electrode of the tenth transistor T10 is electrically connected to the cascade output terminal COUT; The cascade output terminal COUT is electrically connected; the control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, the first electrode of the eleventh transistor T11 is electrically connected to the fifth node N5, and the second electrode of the eleventh transistor T11 is electrically connected to the ninth node N9; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, and the second electrode of the twelfth transistor T12 is electrically connected to the second node N2; the control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and the second electrode of the thirteenth transistor T13 is electrically connected to the fourth node N4;The control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and the second electrode of the fourteenth transistor T14 is electrically connected to the tenth node N10; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, the first electrode of the fifteenth transistor T15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; the first electrode plate C11 of the first capacitor C1 is electrically connected to the ninth node N9; the control electrode of the seventeenth transistor T17 is electrically connected to the second node N2, the first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2, and the second electrode of the seventeenth transistor T17 is electrically connected to the scan output terminal NOUT; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, and the eighteenth transistor T18 is electrically connected to the first node N1. The first electrode of the eighteenth transistor T18 is electrically connected to the scan output terminal NOUT, the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3; the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS, the first electrode of the nineteenth transistor T19 is electrically connected to the first power supply terminal V1, and the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3; the second electrode plate C12 of the first capacitor C1 is electrically connected to the eighth node N8; the first electrode plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second capacitor C2 is electrically connected to the eighth node N8; The second plate C22 of the third capacitor C3 is electrically connected to the first power supply terminal V1; the first plate C31 of the third capacitor C3 is electrically connected to the sixth node N6, and the second plate C32 of the third capacitor C3 is electrically connected to the seventh node N7; the first plate C41 of the fourth capacitor C4 is electrically connected to the second power supply terminal V2, and the second plate C42 of the fourth capacitor C4 is electrically connected to the cascade output terminal COUT; the first plate C51 of the fifth capacitor C5 is electrically connected to the scan output terminal NOUT, and the second plate C52 of the fifth capacitor C5 is electrically connected to the first power supply terminal V1.;

[0178] In an exemplary embodiment, any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a capacitor device made by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a parasitic capacitor between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the fifth capacitor C5 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure does not limit this.

[0179] In the exemplary embodiment, FIG. 9 to FIG. 12 are described by taking the circuit structure in which the cascade output sub-circuit is 16T4C as an example.

[0180] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0181] In an exemplary embodiment, in the shift register provided in Figures 9 to 12, the first transistor T1 to the nineteenth transistor T19 may be P-type transistors. The first transistor T1 to the nineteenth transistor T19 may be P-type transistors to simplify the manufacturing process of the shift register.

[0182] In the exemplary embodiment, due to the existence of the scan control signal terminal MS, the outputs of the cascade output subcircuit and the scan output subcircuit are independent. Now, the working processes of the cascade output subcircuit and the scan output subcircuit are described separately.

[0183] In an exemplary embodiment, the first power terminal V1 continuously provides a high level signal, and the second power terminal V2 continuously provides a low level signal. Since the second power terminal V2 continuously provides a low level signal, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are continuously turned on.

[0184] In an exemplary embodiment, the third power supply terminal V3 is a low level signal in the power-on initialization stage to prevent the ninth transistor T9 and the tenth transistor T10 of the last stage control shift register from being turned on at the same time due to the delay of the output signal, or is a low level signal in the abnormal shutdown stage to prevent the ninth transistor T9 and the tenth transistor T10 from being turned on at the same time. The third power supply terminal V3 continuously provides a high level signal in the normal display stage, that is, in the normal display stage, the thirteenth transistor T13 is turned off.

[0185] FIG13 is a timing diagram of the cascade output subcircuit in the shift register provided in FIG9 to FIG12. FIG13 takes the first transistor T1 to the sixteenth transistor T16 as an example of P-type transistors. As shown in FIG13, the operation process of the cascade output subcircuit provided in an exemplary embodiment may include the following stages:

[0186] In the first stage A1, the signals of the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, and the signal of the first clock signal terminal CK1 is a low-level signal. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1, the third transistor T3 and the twelfth transistor T12 are turned on, the turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the fourth node N4, the signal of the fourth node N4 is a high-level signal, the turned-on twelfth transistor T12 transmits the high-level signal of the fourth node N4 to the second node N2, the turned-on fourteenth transistor T14 transmits the high-level signal of the signal input terminal IN to the tenth node N10, the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth transistor T15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the sixteenth transistor T16 are turned off. In addition, the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal V2 to the fifth node N5, and the signal of the fifth node N5 is a low-level signal. The turned-on eleventh transistor T11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal. The fifth transistor T5 and the sixth transistor T6 are turned on. Although the signal of the second clock signal terminal CK2 is a high-level signal, since the seventh transistor T7 is disconnected, the signal of the first node N1 will not be pulled up and remain as a low-level signal. The ninth transistor T9 is disconnected, and the signal of the cascade output terminal COUT maintains the previous low level. In the first stage A1, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the cascade output terminal COUT maintains the previous low-level signal.

[0187] In the second stage A2, the signal of the second clock signal terminal CK2 is a low level signal, and the signals of the signal input terminal IN and the first clock signal terminal CK1 are high level signals. The signal of the second clock signal terminal CK2 is a low level signal, and the seventh transistor T7 is turned on. The signal of the first clock signal terminal CK1 is a high level signal, and the first transistor T1 and the third transistor T3 are turned off. Under the action of the third capacitor C3, the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 can continue to maintain the high level signal of the previous stage. Under the action of the first capacitor C1, the fifth node N5 and the ninth node N9 can continue to maintain the low level signal of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on. The second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned off. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high-level signal of the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9. Therefore, in this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the cascade output terminal COUT is a high-level signal.

[0188] In the third stage A3, the signal at the first clock signal terminal CK1 is a low-level signal, and the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals. The signal at the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off, and under the action of the second capacitor C2, the first node N1 maintains a low-level signal in the previous stage, the ninth transistor T is continuously turned on, and the high-level signal at the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9. The signal of the first clock signal terminal CK1 is a low-level signal, the first transistor T1, the third transistor T3 and the twelfth transistor T12 are turned on, the turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the fourth node N4, and the signal of the fourth node N4 is a high-level signal, the turned-on twelfth transistor T12 transmits the high-level signal of the fourth node N4 to the second node N2, the turned-on fourteenth transistor T14 transmits the high-level signal of the signal input terminal IN to the tenth node N10, and the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth transistor T15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the sixteenth transistor T16 are disconnected. In addition, the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal V2 to the fifth node N5, and the signal of the fifth node N5 is a low-level signal. The turned-on eleventh transistor T11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal. The fifth transistor T5 and the sixth transistor T6 are turned on. In this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the cascade output terminal COUT is a high-level signal.

[0189] In the fourth stage A4, the signals of the signal input terminal IN and the second clock signal terminal CK2 are low-level signals, and the signal of the first clock signal terminal CK1 is a high-level signal. The signal of the first clock signal terminal CK1 is a high-level signal, and the first transistor T1 and the third transistor T3 are disconnected. The signal of the second clock signal terminal CK2 is a low-level signal, and the seventh transistor T7 is turned on. Due to the storage function of the third capacitor C3, the signals of the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 maintain the high-level signals of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are disconnected. Due to the storage function of the first capacitor C1, the ninth node N9 continues to maintain the low-level signal of the previous stage, and the fifth transistor T5 and the sixth transistor T6 are turned on. In addition, the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, and the high-level signal of the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9, and the signal of the cascade output terminal COUT is still a high-level signal. In this stage, the first node N1 is a high level signal, the second node N2 is a low level signal, and the cascade output terminal COUT is a high level signal.

[0190] In the fifth stage A5, the signal of the second clock signal terminal CK2 is a high level signal, and the signals of the signal input terminal IN and the first clock signal terminal CK1 are low level signals. The signal of the first clock signal terminal CK1 is a low level signal, and the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on. The signal of the second clock signal terminal CK2 is a high level signal, and the seventh transistor T7 is turned off. The turned-on first transistor T1 transmits the low level signal of the signal input terminal IN to the fourth node N4, and the signal of the fourth node N4 is a low level signal. The turned-on twelfth transistor T12 transmits the low level signal of the fourth node N4 to the first node N1, and the signal of the first node N1 becomes a low level signal. The turned-on fourteenth transistor T14 transmits the low level signal of the signal input terminal IN to the tenth node N10, and the signal of the tenth node N10 is a low level signal. The turned-on fifteenth transistor T15 transmits the low level signal of the tenth node N10 to the sixth node N6, and the signal of the sixth node N6 is a low level signal. The second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned on. The turned-on second transistor T2 transmits the low-level signal of the first clock signal terminal CK1 to the fifth node N5, so that the fifth node N5 is a low-level signal, so the fifth node N5 and the ninth node N9 continue to maintain the low-level signal of the previous stage, and the fifth transistor T5 and the sixth transistor T6 are turned on. The signal of the second clock signal terminal CK2 is a high-level signal, and the seventh transistor T7 is turned off. In addition, the high-level signal of the first power supply terminal V1 is transmitted to the first node N1 through the turned-on eighth transistor T8, and the ninth transistor T9 is turned off. The low-level signal of the second power supply terminal V2 is transmitted to the cascade output terminal COUT through the turned-on tenth transistor T10, and the signal of the cascade output terminal COUT becomes a low-level signal. In this stage, the first node N1 is a high-level signal, the second node N2 is a low-level signal, and the cascade output terminal COUT is a low-level signal.

[0191] Fig. 14 is a timing diagram 1 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12, Fig. 15 is a timing diagram 2 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12, Fig. 16 is a timing diagram 3 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12, and Fig. 17 is a timing diagram 4 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12. Fig. 14 to Fig. 17 are explained by taking the seventeenth transistor T17 to the nineteenth transistor T19 as P-type transistors as an example.

[0192] 14 and 15 are explained by taking the display product displaying a normal display screen as an example. In any display frame, when the signal at the cascade output terminal COUT is a high-level signal, at least part of the time period of the scan control signal terminal MS is a low-level signal.

[0193] As shown in FIG14 , when the output signal of the cascade output terminal COUT is a high-level signal, the first node N1 is a low-level signal, and the second node N2 is a high-level signal. The second node N2 is a high-level signal, and the seventeenth transistor T17 is disconnected. The first node N1 is a low-level signal, the eighteenth transistor T18 is turned on, at least part of the time period of the scan control signal terminal MS is a low-level signal, the nineteenth transistor T19 is turned on, and the first power supply terminal V1 is transmitted to the scan output terminal NOUT through the turned-on eighteenth transistor T18 and the nineteenth transistor T19, and the signal of the scan output terminal NOUT is a high-level signal.

[0194] As shown in FIG15 , when the output signal of the cascade output terminal COUT is a low-level signal, the first node N1 is a high-level signal, and the second node N2 is a low-level signal. The first node N1 is a high-level signal, the eighteenth transistor T18 is disconnected, and the high-level signal of the first power supply terminal V1 cannot be transmitted to the scan output terminal NOUT. The second node N2 is a low-level signal, the seventeenth transistor T17 is turned on, and the low-level signal of the second power supply terminal V2 is transmitted to the scan output terminal NOUT, and the signal of the scan output terminal NOUT is a low-level signal.

[0195] When the display product displays a normal picture, when the signal at the cascade output terminal COUT is a high level signal, the signal at the scan output terminal NOUT is a high level signal; when the signal at the cascade output terminal COUT is a low level signal, the signal at the scan output terminal NOUT is a low level signal, that is, the signal at the cascade output terminal COUT and the signal at the scan output terminal NOUT are consistent, so that normal display of the display product can be achieved.

[0196] Figures 16 and 17 are explained by taking the display product displaying a special screen as an example. In some display frames, the signal at the scanning control signal terminal MS is a high level signal when the signal at the cascade output terminal is a high level signal.

[0197] As shown in FIG16 , when the output signal of the cascade output terminal COUT is a high level signal, the first node N1 is a low level signal, and the second node N2 is a high level signal. The second node N2 is a high level signal, and the seventeenth transistor T17 is disconnected. The first node N1 is a low level signal, the eighteenth transistor T18 is turned on, the signal of the scan control signal terminal MS is a high level signal, the nineteenth transistor T19 is disconnected, the first power supply terminal V1 cannot be written to the scan output terminal NOUT, and the scan output terminal NOUT maintains a low level signal.

[0198] As shown in FIG17 , when the output signal of the cascade output terminal COUT is a low-level signal, the first node N1 is a high-level signal, and the second node N2 is a low-level signal. The first node N1 is a high-level signal, the eighteenth transistor T18 is disconnected, the signal of the scan control signal terminal MS is a high-level signal, the nineteenth transistor T19 is disconnected, and the high-level signal of the first power supply terminal V1 cannot be transmitted to the scan output terminal NOUT. The second node N2 is a low-level signal, the seventeenth transistor T17 is turned on, the low-level signal of the second power supply terminal V2 is transmitted to the scan output terminal NOUT, and the signal of the scan output terminal NOUT is a low-level signal.

[0199] As shown in Figures 16 and 17, when the display product displays a special screen, no matter whether the signal at the cascade output terminal COUT is a high-level signal or a low-level signal, the signal at the scan output terminal NOUT is a low-level signal, thereby reducing the number of initialization and data writing of the pixel driving circuit and reducing the power consumption of the display product.

[0200] The embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register. The shift register driving method may include:

[0201] Step 100, the cascade output subcircuit provides signals to the first node and the second node under the control of signals at the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides signals at the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals at the first node and the second node.

[0202] Step 200: The scan output sub-circuit provides a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.

[0203] FIG18 is a schematic diagram of the structure of a display substrate, FIG19 is a cascade schematic diagram 1 of a gate drive circuit, and FIG20 is a cascade schematic diagram 2 of a gate drive circuit. As shown in FIG18 to FIG20, the display substrate has a display area AA and a non-display area AA', and the display substrate may include: a gate drive circuit located in the non-display area AA' and array-arranged sub-pixels and a plurality of gate lines GL located in the display area AA, and the sub-pixels include: a pixel drive circuit P and a light-emitting device. Among them, the gate line GL at least partially extends along the first direction D1, the gate drive circuit includes: a plurality of cascaded shift registers, and the pixel drive circuit includes: a plurality of transistors. Among them, the cascade output terminal of at least one shift register is electrically connected to the signal input terminal of at least one shift register, the gate line is electrically connected to the gate electrode of at least one transistor, and any shift register is electrically connected to at least one gate line. NScan(i) in FIG. 19 and FIG. 20 is the cascade output subcircuit of the i-th stage shift register, NGate(i) is the scan output subcircuit of the i-th stage shift register, and NOUT(i) is the scan output terminal of the i-th stage shift register.

[0204] The shift register may be the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.

[0205] In an exemplary embodiment, as shown in FIG18, the display substrate may further include a timing controller and a data driving circuit located in the non-display area AA' and a plurality of data lines DL located in the display area AA, the data lines DL extending along the second direction D2, the first direction D1 and the second direction D2 intersecting. The pixel driving circuit is also electrically connected to the data lines DL. The timing controller is respectively connected to the data driving circuit and the gate driving circuit, the data driving circuit is respectively connected to the plurality of data lines DL, and the gate driving circuit is respectively connected to the plurality of gate lines GL. The display substrate also includes: light-emitting devices arranged in an array in the display area, the pixel driving circuit is configured to drive the light-emitting devices to emit light, and the pixel driving circuit and the light-emitting devices driven by the pixel driving circuit constitute sub-pixels.

[0206] In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driving circuit to the data driving circuit, and may provide a clock signal, a start signal, etc. suitable for the specifications of the gate driving circuit to the gate driving circuit. The data driving circuit may generate a data voltage to be provided to the data DL using the grayscale value and the control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data line DL in units of pixel rows. The gate driving circuit may generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from the timing controller. For example, the gate driving circuit may sequentially provide a scan signal with a conduction level pulse to the gate line GL.

[0207] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, and the first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the data line and the gate line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data line under the control of the gate line and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0208] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) emitting red light, the second sub-pixel may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be a rectangle, a rhombus, a pentagon, or a hexagon, which is not limited in the present disclosure.

[0209] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0210] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0211] For different display products, the cascade relationship of multiple shift registers in the gate drive circuit may be different. Regardless of the cascade relationship of multiple shift registers, each shift register drives several rows of sub-pixels, as long as a large-area device like this is changed, and after this change generates additional space, the possible simple translation and stretching of small devices are all within the scope of protection of this disclosure.

[0212] FIG. 21 is a schematic diagram of an equivalent circuit of a pixel driving circuit, and FIG. 22 is a schematic diagram of an equivalent circuit of another pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. As shown in FIG. 21 and FIG. 22, the pixel driving circuit may include 7 transistors (first transistor M1 to seventh transistor M7) and 1 capacitor C.

[0213] As shown in Figures 21 and 22, the gate electrode of the first transistor M1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1 or the third node N3; the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data The gate electrode of the fifth transistor M5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is electrically connected to the high level power line VDD, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the first scanning signal line Gate1, the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the first electrode plate of the capacitor C is electrically connected to the first node N1, and the second electrode plate of the capacitor C is electrically connected to the high level power line VDD. FIG. 21 is illustrated by taking the second electrode of the first transistor M1 being electrically connected to the first node N1 as an example, and FIG. 22 is illustrated by taking the second electrode of the first transistor M1 being electrically connected to the third node N3 as an example.

[0214] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active pattern of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active pattern of the oxide thin film transistor adopts an oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0215] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are opposite to the third transistor M3 to the seventh transistor M7 in transistor type. Exemplarily, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0216] In an exemplary embodiment, the first transistor M1 and the second transistor M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low temperature polysilicon transistors.

[0217] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0218] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0219] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0220] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0221] [Corrected 09.10.2023 according to Rule 91] FIG. 23 is a working timing diagram of the pixel driving circuit provided in FIG. 21 and FIG. 22. The following illustrates an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 21 and FIG. 22 during the display phase. FIG. 23 is illustrated by taking the first transistor M1 and the second transistor M2 as N-type transistors, and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example. The pixel driving circuit in FIG. 21 and FIG. 22 includes the first transistor M1 to the seventh transistor M7, 1 capacitor C and 8 signal lines (data signal line Data, first scanning signal line Gate1, second scanning signal line Gate2, reset signal line Reset, first initial signal line INIT1, second initial signal line INIT2, light emitting signal line EM and high-level power line VDD).

[0222] As shown in FIG. 21 , FIG. 22 and FIG. 23 , the operation process of the pixel driving circuit may include:

[0223] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 or the third node N3 through the turned-on first transistor M1, and the first node N1 or the third node N3 is initialized (reset), clearing the pre-stored voltage inside it, and completing the initialization.

[0224] The second stage P2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line Gate1 is a low level signal, the signal of the second scanning signal line Gate2 is a high level signal, and the data signal line Data outputs a data voltage. In this stage, since the first node N1 is a low level signal, the third transistor M3 is turned on. The signal of the first scanning signal line Gate1 is a low-level signal, the fourth transistor M4 is turned on and the seventh transistor M7 is turned on, the signal of the second scanning signal line Gate2 is a high-level signal, the second transistor M2 is turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, Vth is the threshold voltage of the third transistor M3, the seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor M7, the first electrode of the light-emitting device L is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.

[0225] The third stage P3 is called the light-emitting stage. The signal of the light-emitting signal line EM is a low-level signal. The fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0226] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0227] Among them, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0228] In an exemplary embodiment, the gate line may include a first gate line and a second gate line, the first gate line may include a first scan signal line and a light emitting signal line, and the second gate line may include a reset signal line and a second scan signal line.

[0229] In an exemplary embodiment, the light-emitting device may include: any one of an organic light-emitting diode OLED, a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micron-level light-emitting device, such as a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED), a sub-millimeter light-emitting diode (Mini Light-Emitting Diode, Mini LED) or a micro organic light-emitting diode (Micro OLED), etc., and the embodiments of the present disclosure are not limited to this. For example, taking the light-emitting device L as an organic light-emitting diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode).

[0230] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a gate driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0231] In an exemplary embodiment, at least one shift register provided by the embodiment of the present disclosure may be electrically connected to the second gate line.

[0232] As shown in FIGS. 19 and 20, the display substrate may further include: at least one scan control signal line located in the non-display area, the scan control signal line at least partially extending along the second direction D2. The scan control signal terminals to which all the shift registers are connected are electrically connected to at least one scan control signal line. FIG. 19 is illustrated by taking one scan control signal line MSL as an example, and FIG. 20 is illustrated by taking four scan control signal lines MSL1 to MSL4 as an example.

[0233] In an exemplary embodiment, as shown in FIG. 19 , when the number of the scan control signal line is one, the scan control signal terminals to which all the shift registers are connected are electrically connected to the same scan control signal line MSL.

[0234] In an exemplary embodiment, as shown in Figure 20, when the number of scan control signal lines is at least two, the scan control signal terminal connected to any shift register from the M*(k-1)+K*M(a-1)+1th level shift register to the k*M+K*M(a-1)th level shift register is electrically connected to the kth scan control signal line, 1≤k≤K, 1≤a≤N / M, M is the number of shift registers connected to a scan control signal line, N is the total number of shift registers, K is the number of scan control signal lines, and M≥1.

[0235] Exemplarily, taking M=7 and K=4 as an example, the scanning control signal end connected to the first-stage shift register to the seventh-stage shift register is electrically connected to the first scanning control signal line MSL1, the scanning control signal end connected to the eighth-stage shift register to the fourteenth-stage shift register is electrically connected to the second scanning control signal line MSL2, the scanning control signal end connected to the fifteenth-stage shift register to the twenty-first-stage shift register is electrically connected to the third scanning control signal line MSL3, the scanning control signal end connected to the twenty-second-stage shift register to the twenty-eighth-stage shift register is electrically connected to the fourth scanning control signal line MSL4. Then, the scanning control signal terminals connected to the twenty-ninth to thirty-fifth shift registers are electrically connected to the first scanning control signal line MSL1, the scanning control signal terminals connected to the thirty-sixth to forty-second shift registers are electrically connected to the second scanning control signal line MSL2, the scanning control signal terminals connected to the forty-third to forty-ninth shift registers are electrically connected to the third scanning control signal line MSL3, the scanning control signal terminals connected to the fiftieth to fifty-sixth shift registers are electrically connected to the fourth scanning control signal line MSL4, and so on.

[0236] In an exemplary embodiment, the screen displayed by the display substrate includes: a plurality of display frames, in any display frame, the output signal of the scan output end of the shift register is a pulse signal, and the duration H of the pulse signal satisfies the following relationship: H = L*[M*K-(M-1)]*h

[0237] Wherein, L is the number of gate lines connected to any stage of shift register, and h is the unit time, which is equal to the refresh interval time of adjacent rows of sub-pixels.

[0238] In an exemplary embodiment, the display area can be divided into a plurality of display sub-areas, at least one display sub-area includes: at least one gate line. The display mode of any display sub-area includes: a first display mode and a second display mode, and the refresh frequency of the first display mode is greater than the refresh frequency of the second display mode.

[0239] In an exemplary embodiment, when the display mode of the display sub-area is the first display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output terminal is a first level signal, at least part of the time period of the signal at the scan control signal terminal is a valid level signal, and the signal at the scan output terminal is a first level signal. When the display mode of the display sub-area is the second display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output terminal is a first level signal, the signal at the scan control signal terminal is an invalid level signal, and the signal at the scan output terminal is a second level signal. Wherein, the voltage value of the first level signal is greater than the voltage value of the second level signal, the first level signal is a high level signal, and the second level signal is a low level signal.

[0240] Fig. 24 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in Fig. 19. As shown in Fig. 24, in the time period t, since the signal of the scan control signal line MSL is a high-level signal, the signal of any output terminal from the scan output terminal NOUT(2) of the second-stage shift register to the scan output terminal NOUT(N-1) of the N-1-stage shift register is a low-level signal, that is, the pixel driving circuit connected to the gate line connected to the scan output terminal of the second-stage shift register to the scan output terminal of the N-1-stage shift register will not be initialized and data written, thereby realizing low-frequency display and low-power display of the display product.

[0241] Fig. 25 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in Fig. 20. As shown in Fig. 25, in time periods t1 and t3, the signals of the first scan control signal line MSL1 to the fourth scan control signal line MSL4 are low level signals, and at this time, the scan output terminals of all shift registers sequentially output high level signals.

[0242] As shown in Figure 25, in the time period t2, the first scanning control signal line MSL1 is a high-level signal in part of the time period, so that the scanning output ends of the first-stage shift register and the seventh-stage shift register output low-level signals. The time period in which the first scanning control signal line MSL1 is a high-level signal is from the start time when the signal at the cascade output end of the first-stage shift register is a high-level signal to the end time when the signal at the cascade output end of the seventh shift register is a high-level signal.

[0243] As shown in Figure 25, in the time period t2, the second scanning control signal line MSL2 is a high-level signal in part of the time period, so that the scanning output ends of the eighth-level shift register and the fourteenth-level shift register output low-level signals. The time period in which the second scanning control signal line MSL2 is a high-level signal is from the start time when the signal at the cascade output end of the eighth-level shift register is a high-level signal to the end time when the signal at the cascade output end of the fourteenth shift register is a high-level signal.

[0244] As shown in Figure 25, in the time period t2, the third scanning control signal line MSL3 is a high-level signal in part of the time period, so that the scanning output ends of the 43rd-level shift register and the 49th-level shift register output low-level signals, and the time period in which the third scanning control signal line MSL3 is a high-level signal is from the start time when the signal at the cascade output end of the 43rd-level shift register is a high-level signal to the end time when the signal at the cascade output end of the 49th-level shift register is a high-level signal.

[0245] As shown in Figure 25, in the time period t2, the time period when the fourth scanning control signal line MSL4 is a high-level signal is from the start time when the signal at the cascade output end of the 50th shift register is a high-level signal to the end time when the signal at the cascade output end of the 56th shift register is a high-level signal, and the time period when the fourth scanning control signal line MSL4 is a high-level signal is from the start time when the signal at the cascade output end of the 50th shift register is a high-level signal to the end time when the signal at the cascade output end of the 56th shift register is a high-level signal.

[0246] FIG26 is a partial schematic diagram of the non-display area of ​​the display substrate. As shown in FIG19, FIG20 and FIG26, the display substrate may further include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL and a third power line VCX located in the non-display area. The shift register in FIG26 is the shift register provided in FIG11, and FIG26 is described by taking one scanning control signal line as an example.

[0247] In an exemplary embodiment, any one of the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL, and the third power line VCX at least partially extends along the second direction D2;

[0248] In an exemplary embodiment, the first clock signal terminal connected to any stage of the shift register is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2, the second clock signal terminal connected to any stage of the shift register is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2, the clock signal lines connected to the first clock signal terminals connected to adjacent shift registers are different, the clock signal lines connected to the second clock signal terminals connected to adjacent shift registers are different, the first power supply terminals connected to all the shift registers are electrically connected to the first power supply line VGH, the second power supply terminals connected to all the shift registers are electrically connected to the second power supply line VGL, and the third power supply terminals connected to all the shift registers are electrically connected to the third power supply line VCX.

[0249] In an exemplary embodiment, the display substrate may further include: an initial signal line located in the non-display area, the signal input end of at least one shift register being electrically connected to the initial signal line. The initial signal line may extend along the second direction and may be located on a side of the first clock signal line away from the display area.

[0250] In an exemplary embodiment, as shown in FIGS. 19 , 20 and 25 , the scan control signal line MSL may be located on a side of any one of the first clock signal line CLK1 , the second clock signal line CLK2 , the first power line VGH, the second power line VGL and the third power line VCX close to the display area.

[0251] In an exemplary embodiment, as shown in FIG. 25 , the number of the second power lines VGL is two, and the first clock signal line CLK1, the second clock signal line CLK2, the first second power line VGL, the third power line VCX, the second second power line VGL and the first power line VGH are arranged in sequence in a direction close to the display area.

[0252] In an exemplary embodiment, as shown in FIG. 25 , the shift register may include seventeenth to nineteenth transistors T17 to T19 ; the seventeenth to nineteenth transistors T17 to T19 may be arranged along the second direction D2 .

[0253] In an exemplary embodiment, as shown in FIG. 25 , at least a portion of any one of the seventeenth to nineteenth transistors T17 to T19 is located between the first power line VGH and the scan control signal line MSL.

[0254] In an exemplary embodiment, any transistor includes an active pattern, and Figure 27 is a schematic diagram of active patterns of the seventeenth to nineteenth transistors. As shown in Figure 27, the average length of the active pattern 171 of the seventeenth transistor along the first direction D1 is less than the average length of any one of the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor along the first direction D1.

[0255] In an exemplary embodiment, as shown in FIG. 25 , the line width of any one of the first power line VGH and the second power line VGL may be greater than the line width of the scan control signal line MSL.

[0256] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. Figures 11 to 18 are explained by taking the display substrate including the shift register provided in Figure 8, that is, the shift register includes: the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 as an example.

[0257] (1) Forming a semiconductor layer pattern on a substrate. In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a semiconductor layer pattern. As shown in FIG. 28 , FIG. 28 is a schematic diagram of FIG. 26 after forming a semiconductor layer pattern.

[0258] In an exemplary embodiment, as shown in FIG. 28 , the semiconductor layer pattern of each shift register may include at least an active pattern 11 of a first transistor to an active pattern 191 of a nineteenth transistor.

[0259] In an exemplary embodiment, as shown in FIG. 28, the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor, and the active pattern 131 of the thirteenth transistor are an integrated structure, the active pattern 121 of the twelfth transistor and the active pattern 161 of the sixteenth transistor are an integrated structure, the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor, and the active pattern 191 of the nineteenth transistor are an integrated structure, and the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor, the active pattern 101 of the tenth transistor, the active pattern 111 of the eleventh transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor are separately provided.

[0260] In an exemplary embodiment, as shown in FIG. 28 , the active pattern 11 of the first transistor and the active pattern 141 of the fourteenth transistor are arranged along a first direction D1, and the active pattern 11 of the first transistor is located on a side of the active pattern 141 of the fourteenth transistor close to the display area, and the active pattern 21 of the second transistor is located on a side of the active pattern 11 of the first transistor close to the display area. The active pattern 31 of the third transistor is arranged along the second direction D2 with the active pattern 11 of the first transistor, and the active pattern 31 of the third transistor of the shift register at this stage is located on the side of the active pattern 11 of the first transistor close to the next stage shift register, the active pattern 111 of the eleventh transistor and the active pattern 151 of the fifteenth transistor are arranged along the first direction D1, the active pattern 111 of the eleventh transistor and the active pattern 111 of the first transistor are arranged along the second direction D2, the active pattern 151 of the fifteenth transistor and the active pattern 141 of the fourteenth transistor are arranged along the second direction D2, the active pattern 111 of the eleventh transistor is located on the side of the active pattern 151 of the fifteenth transistor close to the display area, the active pattern 111 of the eleventh transistor of the shift register at this stage is located on the side of the active pattern 31 of the fifteenth transistor close to the next stage shift register. The active pattern 41 of the fourth transistor of the shift register at this stage is located on the side of the active pattern 111 of the eleventh transistor close to the next stage shift register. The active pattern 61 of the sixth transistor is located on the side of the active pattern 21 of the second transistor close to the display area. The active pattern 71 of the seventh transistor is located on the side of the active pattern 61 of the sixth transistor close to the display area. The active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor are located on the side of the active pattern 21 of the second transistor close to the display area, and the active pattern 131 of the thirteenth transistor is located on the side of the active pattern 81 of the eighth transistor away from the display area. The active pattern 51 of the fifth transistor is located on the side of the active pattern 111 of the eleventh transistor close to the display area. The active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor and the active pattern 51 of the fifth transistor are arranged along the second direction D2, and the active pattern 71 of the seventh transistor of the current stage shift register is located on the side of the active pattern 81 of the eighth transistor close to the previous stage shift register, and the active pattern 51 of the fifth transistor of the current stage shift register is located on the side of the active pattern 81 of the eighth transistor close to the next stage shift register. The active pattern 161 of the sixteenth transistor is located on a side of the active pattern 41 of the fourth transistor close to the display area, the active pattern 121 of the twelfth transistor is located on a side of the active pattern 161 of the sixteenth transistor close to the display area, the active pattern 51 of the fifth transistor and the active pattern 121 of the twelfth transistor are arranged along the second direction D2, and the active pattern 121 of the twelfth transistor of the current level shift register is located on a side of the active pattern 51 of the fifth transistor close to the next level shift register.The active pattern 91 of the ninth transistor is located on the side of the active pattern 71 of the seventh transistor close to the display area, the active pattern 101 of the tenth transistor is located on the side of the active pattern 161 of the sixteenth transistor close to the display area, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are arranged along the second direction D2, and the active pattern 91 of the ninth transistor of the current level shift register can be located on the side of the active pattern 101 of the tenth transistor close to the previous level shift register. The active pattern 171 of the seventeenth transistor (also the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor) is located on the side of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor close to the display area, and the active patterns 171 of the seventeenth transistor to the active pattern 191 of the ninth transistor are arranged along the second direction D2. The active pattern 171 of the seventeenth transistor of the shift register at this level is located on the side of the active pattern 181 of the eighteenth transistor close to the next level shift register, and the active pattern 191 of the nineteenth transistor of the shift register at this level is located on the side of the active pattern 181 of the eighteenth transistor close to the previous level shift register.

[0261] In an exemplary embodiment, as shown in FIG. 28, any one of the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor, the active pattern 91 of the ninth transistor, the active pattern 111 of the eleventh transistor, the active pattern 121 of the twelfth transistor, the active pattern 141 of the fourteenth transistor, the active pattern 151 of the fifteenth transistor, the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor is strip-shaped and extends along the second direction D2.

[0262] In an exemplary embodiment, as shown in FIG. 28 , any one of the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 101 of the tenth transistor, the active pattern 131 of the thirteenth transistor, and the active pattern 161 of the sixteenth transistor has a strip shape and extends along the first direction D1.

[0263] In an exemplary embodiment, as shown in Figure 28, the integrated structure of the active pattern 121 of the twelfth transistor and the active pattern 161 of the sixteenth transistor is in an inverted "T" shape, the integrated structure of the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor can be in a "┨" shape, and the integrated structure of the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor is in a strip shape and extends along the second direction D2.

[0264] In an exemplary embodiment, as shown in FIG. 28 , an average length of the active pattern 171 of the seventeenth transistor along the first direction D1 is smaller than an average length of any of the active patterns 181 and 191 of the eighteenth and nineteenth transistors along the first direction D1.

[0265] 28, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 51-1 of the active pattern 51 of the fifth transistor may serve as the first region 81-1 of the active pattern 81 of the eighth transistor and the first region 131-1 of the active pattern 131 of the thirteenth transistor, the second region 71-2 of the active pattern 71 of the seventh transistor may serve as the second region 81-2 of the active pattern 81 of the eighth transistor, the second region 121-2 of the active pattern 121 of the twelfth transistor may serve as the second region 161-2 of the active pattern 161 of the sixteenth transistor, the second region 171-2 of the active pattern 171 of the seventeenth transistor may serve as the first region 181-1 of the active pattern 181 of the eighteenth transistor, and the second region 181-2 of the active pattern 181 of the eighteenth transistor may serve as the first region 191-2 of the active pattern 191 of the nineteenth transistor. a first region 11-1 and a second region 11-2 of an active pattern 11 of a first transistor, a first region 21-1 and a second region 21-2 of an active pattern 21 of a second transistor, a first region 31-1 and a second region 31-2 of an active pattern 31 of a third transistor, a first region 41-1 and a second region 41-2 of an active pattern 41 of a fourth transistor, a second region 51-2 of an active pattern 51 of a fifth transistor, a first region 61-1 and a second region 61-2 of an active pattern 61 of a sixth transistor, a first region 71-1 of an active pattern 71 of a seventh transistor, a first region 91-1 and a second region 91-2 of an active pattern 91 of a ninth transistor, and a first region 101 of an active pattern 101 of a tenth transistor. 1-1 and the second area 101-2, the first area 111-1 and the second area 111-2 of the active pattern 111 of the eleventh transistor, the first area 121-1 of the active pattern 121 of the twelfth transistor, the second area 131-2 of the active pattern 131 of the thirteenth transistor, the first area 141-1 and the second area 141-2 of the active pattern 141 of the fourteenth transistor, the first area 151-1 and the second area 151-2 of the active pattern 151 of the fifteenth transistor, the first area 161-1 of the active pattern 161 of the sixteenth transistor, the first area 171-1 of the active pattern 171 of the seventeenth transistor and the first area 191-1 of the active pattern 191 of the nineteenth transistor are separately set.

[0266] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 29 and 30 , where FIG. 29 is a schematic diagram of the first conductive layer pattern in FIG. 26 , and FIG. 30 is a schematic diagram of FIG. 26 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0267] In an exemplary embodiment, as shown in Figures 29 and 30, the first conductive layer pattern of each shift register may include at least: the gate electrode 12 of the first transistor to the gate electrode 192 of the nineteenth transistor, the first plate C11 of the first capacitor to the first plate C41 of the fourth capacitor, and the first connection portion L1.

[0268] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor are an integrated structure, and the integrated structure of the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor is strip-shaped and extends along the first direction D1.

[0269] In an exemplary embodiment, as shown in Figures 29 and 30, the gate electrode 22 of the second transistor and the gate electrode 82 of the eighth transistor are an integral structure. The gate electrode 22 of the second transistor may be in an "n" shape with an opening toward the display area, and the gate electrode 82 of the eighth transistor may be in a zigzag shape and at least partially extend along the first direction D1.

[0270] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 32 of the third transistor is separately provided and may have a shape of Font.

[0271] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 42 of the fourth transistor, the gate electrode 162 of the sixteenth transistor, and the C31 of the third capacitor are an integrated structure. The shape of the C31 of the third capacitor is rectangular. The gate electrode 42 of the fourth transistor of the current shift register is located on the side of the C31 of the third capacitor close to the shift register of the next stage, and the shape of the gate electrode 42 of the fourth transistor is a strip and extends along the second direction D2. The gate electrode 162 of the sixteenth transistor is located on the side of the C31 of the third capacitor close to the display area, and the shape of the gate electrode 162 of the sixteenth transistor is Font.

[0272] 29 and 30, the gate electrode 52 of the fifth transistor is provided separately. The gate electrode 52 of the fifth transistor has a zigzag shape and at least partially extends along the first direction D1.

[0273] In an exemplary embodiment, as shown in FIG. 29 and FIG. 30 , the gate electrode 62 of the sixth transistor and the first plate C11 of the first capacitor are an integrated structure. The gate electrode 62 of the sixth transistor of the current stage shift register is located on the side of the first plate C11 of the first capacitor close to the next stage shift register. The shape of the first plate C11 of the first capacitor can be The gate electrode 62 of the sixth transistor is in a zigzag shape, and at least partially extends along the second direction D2.

[0274] 29 and 30, the gate electrode 72 of the seventh transistor is provided separately. The gate electrode 72 of the seventh transistor is in a zigzag shape and at least partially extends along the first direction D1.

[0275] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 92 of the ninth transistor, the gate electrode 182 of the eighteenth transistor, and the first plate C21 of the second capacitor are an integrated structure. The gate electrode 92 of the ninth transistor and the gate electrode 182 of the eighteenth transistor are both located on the side of the first plate C21 of the second capacitor close to the display area, the gate electrode 92 of the ninth transistor is connected to the first plate C21 of the second capacitor close to the boundary of the display area, and the gate electrode 182 of the eighteenth transistor of the current shift register is connected to the first plate C21 of the second capacitor close to the boundary of the previous shift register. The shape of the first plate C21 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered. The gate electrode 92 of the ninth transistor is strip-shaped and extends along the first direction D1. The gate electrode 182 of the eighteenth transistor includes: a first connection segment 182A and at least one first branch segment 182B, the first electrode plate C21 of the second capacitor is located on the side of the first connection segment 182A away from the display area, the first branch segment 182B is located on the side of the first connection segment 182A close to the display area, and the first connection segment 182A is electrically connected to the first electrode plate C21 of the second capacitor and the at least one first branch segment 182B. The gate electrode 182 of the eighteenth transistor can be in a combing structure. The shape of the first connection segment 182A can be The first branch segment 182B may be in the shape of a strip and extend along the first direction D1, which is equivalent to a "comb tooth". At least one first branch segment 182B is arranged along the second direction D2.

[0276] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 102 of the tenth transistor and the gate electrode 172 of the seventeenth transistor are an integral structure. The gate electrode 102 of the tenth transistor may be in the shape of an "F" shape rotated to the left, and the gate electrode 172 of the seventeenth transistor may include: a second connecting segment 172A and at least one second branch segment 172B. The second branch segment 172B is located on the side of the second connecting segment 172A close to the display area. The gate electrode 172 of the seventeenth transistor is in the shape of a comb-like structure, the second connecting segment 172A extends along the second direction D2, which is equivalent to a "comb back", and the second branch segment 172B extends along the first direction D1, which is equivalent to a "comb tooth", and at least one second branch segment 172B is arranged along the second direction D2.

[0277] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor are an integrated structure, and the shape of the integrated structure of the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor is a strip and extends along the first direction D1.

[0278] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 122 of the twelfth transistor is separately provided and may be shaped as Font.

[0279] 29 and 30, the gate electrode 132 of the thirteenth transistor is separately provided. The gate electrode 132 of the thirteenth transistor is in the shape of a stripe and extends along the second direction D2.

[0280] In an exemplary embodiment, as shown in FIGS. 29 and 30 , the gate electrode 192 of the nineteenth transistor is separately provided. The gate electrode 192 of the nineteenth transistor includes: a third connection segment 192A and at least one third branch segment 192B. The third branch segment 192B is located on a side of the third connection segment 192A away from the display area. The gate electrode 192 of the nineteenth transistor may be in a comb-like structure, and the shape of the third connection segment 192A may be The third branch segment 192B is in the shape of a strip and extends along the first direction D1, which is equivalent to a "comb tooth". At least one third branch segment 192B is arranged along the second direction D2.

[0281] In an exemplary embodiment, as shown in FIGS. 29 and 30, the first plate C41 of the fourth capacitor is separately provided and is located between the gate electrode 52 of the fifth transistor and the gate electrode 182 of the eighteenth transistor. The first plate C41 of the fourth capacitor includes: a main body and a raised portion, the main body may be rectangular, and the raised portion is located on a side of the main body away from the display area. In an exemplary embodiment, as shown in FIGS. 29 and 30, the first connection portion L1 is separately provided and is block-shaped. The first connection portion L1 is located on a side of the gate electrode 42 of the fourth transistor away from the display area, and is located on a side of the first plate C31 of the third capacitor of the current shift register close to the next shift register.

[0282] In an exemplary embodiment, as shown in FIGS. 29 and 30 , a gate electrode 12 of a first transistor is arranged across an active pattern of the first transistor, a gate electrode 22 of a second transistor is arranged across an active pattern of the second transistor, a gate electrode 32 of a third transistor is arranged across an active pattern of the third transistor, a gate electrode 42 of a fourth transistor is arranged across an active pattern of the fourth transistor, a gate electrode 52 of a fifth transistor is arranged across an active pattern of the fifth transistor, a gate electrode 62 of a sixth transistor is arranged across an active pattern of the sixth transistor, a gate electrode 72 of a seventh transistor is arranged across an active pattern of the seventh transistor, a gate electrode 82 of an eighth transistor is arranged across an active pattern of the eighth transistor, a gate electrode 92 of a ninth transistor is arranged across an active pattern of the ninth transistor, a gate electrode 102 of a tenth transistor is arranged across an active pattern of the tenth transistor, and a gate electrode 112 of an eleventh transistor is arranged across an active pattern of the eleventh transistor. , the gate electrode 122 of the twelfth transistor is arranged across the active pattern of the twelfth transistor, the gate electrode 132 of the thirteenth transistor is arranged across the active pattern of the thirteenth transistor, the gate electrode 142 of the fourteenth transistor is arranged across the active pattern of the fourteenth transistor, the gate electrode 152 of the fifteenth transistor is arranged across the active pattern of the fifteenth transistor, the gate electrode 162 of the sixteenth transistor is arranged across the active pattern of the sixteenth transistor, at least one second branch segment 172B of the gate electrode 172 of the seventeenth transistor is arranged across the active pattern of the seventeenth transistor, at least one first branch segment 182B of the gate electrode 182 of the eighteenth transistor is arranged across the active pattern of the eighteenth transistor, and at least one third branch segment 192B of the gate electrode 192 of the nineteenth transistor is arranged across the active pattern of the nineteenth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0283] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductorization process on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of ​​the first transistor to the nineteenth transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor to the nineteenth transistor are both conductorized. As shown in FIG. 30 , the first connection portion L1 in the present disclosure is processed into a conductorized layer to form a conductorized first connection portion L1.

[0284] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern, patterning the second conductive film through a patterning process, and forming a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in FIGS. 31 and 32 , where FIG. 31 is a schematic diagram of the second conductive layer pattern in FIG. 26 , and FIG. 32 is a schematic diagram of FIG. 26 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0285] In an exemplary embodiment, as shown in FIGS. 31 and 32 , the second conductive layer pattern may include at least a second plate C12 of a first capacitor to a second plate C42 of a fourth capacitor located in each shift register and a second connection portion L2 .

[0286] In an exemplary embodiment, as shown in FIGS. 31 and 32 , the orthographic projection of the second electrode plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate. The area of ​​the second electrode plate C12 of the first capacitor is smaller than the area of ​​the first electrode plate of the first capacitor. The shape of the second electrode plate C12 of the first capacitor is the same as the shape of the first electrode plate of the first capacitor.

[0287] In an exemplary embodiment, as shown in FIGS. 31 and 32 , the orthographic projection of the second electrode plate C22 of the second capacitor on the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the second capacitor on the substrate. The area of ​​the second electrode plate C22 of the second capacitor is smaller than the area of ​​the first electrode plate of the second capacitor. The shape of the second electrode plate C22 of the second capacitor may be rectangular, the corners of the rectangular shape may be chamfered, and extend along the second direction D2.

[0288] In an exemplary embodiment, as shown in Figures 31 and 32, the orthographic projection of the second plate C32 of the third capacitor on the substrate overlaps at least partially with the orthographic projection of the first plate of the third capacitor on the substrate. The area of ​​the second plate C32 of the third capacitor is smaller than the area of ​​the first plate of the third capacitor. The shape of the second plate C32 of the third capacitor can be rectangular. The second plate C32 of the third capacitor is provided with a groove K near the boundary of the second plate C32 of the first capacitor, and the orthographic projection of the groove K on the substrate overlaps at least partially with the orthographic projection of the first plate of the third capacitor on the substrate, and the first plate of the third capacitor is exposed.

[0289] In an exemplary embodiment, as shown in Figures 31 and 32, the orthographic projection of the second electrode plate C42 of the fourth capacitor on the substrate is located at a position where the orthographic projection of the first electrode plate of the fourth capacitor on the substrate at least partially overlaps. The shape of the second electrode plate C42 of the fourth capacitor is the same as the shape of the first electrode plate C41 of the fourth capacitor, and the area of ​​the second electrode plate C42 of the fourth capacitor is smaller than the area of ​​the first electrode plate of the fourth capacitor.

[0290] In an exemplary embodiment, as shown in Figures 31 and 32, the second connection portion L2 is located between the second electrode plate C32 of the third capacitor and the second electrode plate C22 of the second capacitor, and is located on the side of the first capacitor C12 of the current stage shift register close to the next stage shift register. The second connection portion L2 is in a zigzag shape and at least partially extends along the first direction D1.

[0291] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIG. 33 , which is a schematic diagram of FIG. 26 after the third insulating layer pattern is formed.

[0292] In an exemplary embodiment, as shown in FIG. 33 , the third insulation layer pattern of each shift register may include at least first to fifty-first via holes V1 to V51 .

[0293] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the first transistor through the via hole.

[0294] In an exemplary embodiment, as shown in FIG. 33 , the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor, and the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor to the second area of ​​the active pattern of the first transistor through the via hole.

[0295] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the active pattern of the second transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active pattern of the second transistor through the via hole.

[0296] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of ​​the active pattern of the second transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the second transistor through the via hole.

[0297] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active pattern of the third transistor through the via hole.

[0298] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the active pattern of the third transistor, and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the third transistor through the via hole.

[0299] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0300] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0301] In an exemplary embodiment, as shown in Figure 33, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the ninth via V9 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) through the via.

[0302] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the second area of ​​the active pattern of the fifth transistor, and the tenth via hole V10 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fifth transistor through the via hole.

[0303] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first area of ​​the active pattern of the sixth transistor, and the eleventh via hole V11 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active pattern of the sixth transistor through the via hole.

[0304] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twelfth via V12 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor through the via.

[0305] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first area of ​​the active pattern of the seventh transistor, and the thirteenth via hole V13 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the first area of ​​the active pattern of the seventh transistor through the via hole.

[0306] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventh transistor (also the second area of ​​the active pattern of the eighth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the second area of ​​the active pattern of the seventh transistor (also the second area of ​​the active pattern of the eighth transistor), and the fourteenth via V14 is configured to connect the second electrode of the subsequently formed seventh transistor (also the second electrode of the eighth transistor) to the second area of ​​the active pattern of the seventh transistor (also the second area of ​​the active pattern of the eighth transistor) through the via.

[0307] In an exemplary embodiment, as shown in Figure 33, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fifteenth via V15 are etched away to expose the surface of the first area of ​​the active pattern of the ninth transistor, and the fifteenth via V15 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of ​​the active pattern of the ninth transistor through the via.

[0308] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the sixteenth via V16 are etched away to expose the surface of the second area of ​​the active pattern of the ninth transistor, and the sixteenth via V16 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the ninth transistor through the via.

[0309] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first area of ​​the active pattern of the tenth transistor, and the seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed tenth transistor to the first area of ​​the active pattern of the tenth transistor through the via hole.

[0310] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second area of ​​the active pattern of the tenth transistor, and the eighteenth via hole V18 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the tenth transistor through the via hole.

[0311] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the first area of ​​the active pattern of the eleventh transistor, and the nineteenth via hole V19 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the first area of ​​the active pattern of the eleventh transistor through the via hole.

[0312] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twentieth via V20 are etched away to expose the surface of the second area of ​​the active pattern of the eleventh transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second area of ​​the active pattern of the eleventh transistor through the via.

[0313] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twelfth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-first via V21 are etched away to expose the surface of the first area of ​​the active pattern of the twelfth transistor, and the twenty-first via V21 is configured to connect the first electrode of the subsequently formed twelfth transistor to the first area of ​​the active pattern of the twelfth transistor through the via.

[0314] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-second via V22 are etched away to expose the surface of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor), and the twenty-second via V22 is configured to connect the second electrode of the subsequently formed twelfth transistor (also the second electrode of the sixteenth transistor) to the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) through the via.

[0315] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the thirteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-third via V23 are etched away to expose the surface of the second area of ​​the active pattern of the thirteenth transistor, and the twenty-third via V23 is configured to connect the second electrode of the subsequently formed thirteenth transistor to the second area of ​​the active pattern of the thirteenth transistor through the via.

[0316] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-fourth via V24 are etched away to expose the surface of the first area of ​​the active pattern of the fourteenth transistor, and the twenty-fourth via V24 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the fourteenth transistor through the via.

[0317] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-fifth via V25 are etched away to expose the surface of the second area of ​​the active pattern of the fourteenth transistor, and the twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the second area of ​​the active pattern of the fourteenth transistor through the via.

[0318] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-sixth via V26 are etched away to expose the surface of the first area of ​​the active pattern of the fifteenth transistor, and the twenty-sixth via V26 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the first area of ​​the active pattern of the fifteenth transistor through the via.

[0319] In an exemplary embodiment, as shown in FIG33, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-seventh via V27 are etched away to expose the surface of the second area of ​​the active pattern of the fifteenth transistor, and the twenty-seventh via V27 is configured to connect the second electrode of the subsequently formed fifteenth transistor to the second area of ​​the active pattern of the fifteenth transistor through the via.

[0320] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-eighth via V28 are etched away to expose the surface of the first area of ​​the active pattern of the sixteenth transistor, and the twenty-eighth via V28 is configured to connect the first electrode of the subsequently formed sixteenth transistor to the first area of ​​the active pattern of the sixteenth transistor through the via.

[0321] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventeenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first area of ​​the active pattern of the seventeenth transistor, and the twenty-ninth via V29 is configured to connect the first electrode of the seventeenth transistor formed subsequently to the first area of ​​the active pattern of the seventeenth transistor through the via.

[0322] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventeenth transistor (also the first area of ​​the active pattern of the eighteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirtieth via V30 are etched away to expose the surface of the second area of ​​the active pattern of the seventeenth transistor (also the first area of ​​the active pattern of the eighteenth transistor), and the thirtieth via V30 is configured to connect the second electrode of the seventeenth transistor (also the first electrode of the eighteenth transistor) formed subsequently to the second area of ​​the active pattern of the seventeenth transistor (also the first area of ​​the active pattern of the eighteenth transistor) through the via.

[0323] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighteenth transistor (also the second area of ​​the active pattern of the nineteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirty-first via V31 are etched away to expose the surface of the second area of ​​the active pattern of the eighteenth transistor (also the second area of ​​the active pattern of the nineteenth transistor), and the thirty-first via V31 is configured to connect the second electrode of the subsequently formed eighteenth transistor (also the second electrode of the nineteenth transistor) to the second area of ​​the active pattern of the eighteenth transistor (also the second area of ​​the active pattern of the nineteenth transistor) through the via.

[0324] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the nineteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirty-second via V32 are etched away to expose the surface of the first area of ​​the active pattern of the nineteenth transistor, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed nineteenth transistor to the first area of ​​the active pattern of the nineteenth transistor through the via.

[0325] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) on the substrate, the second insulating layer and the third insulating layer in the thirty-third via V33 are etched away to expose the surface of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor), and the thirty-third via V33 is configured to connect the subsequently formed third connecting portion and the first electrode of the second transistor to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the via.

[0326] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor (also the gate electrode of the eighth transistor) on the substrate, the second insulating layer and the third insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the gate electrode of the second transistor (also the gate electrode of the eighth transistor), and the thirty-fourth via V34 is configured to connect the second electrode of the first transistor and the second electrode of the thirteenth transistor to be formed subsequently to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the via.

[0327] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the gate electrode of the third transistor, and the thirty-fifth via V35 is configured to connect a subsequently formed fifth connecting portion to the gate electrode of the third transistor through the via.

[0328] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) on the substrate, the second insulating layer and the third insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor), and the thirty-sixth via V36 is configured to connect the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor to be formed subsequently to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the via.

[0329] In an exemplary embodiment, as shown in Figure 33, the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the gate electrode of the fifth transistor, and the thirty-seventh via V37 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the gate electrode of the fifth transistor through the via.

[0330] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the gate electrode of the sixth transistor (the first plate of the first capacitor) on the substrate, the second insulating layer and the third insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the gate electrode of the sixth transistor (the first plate of the first capacitor), and the thirty-eighth via V38 is configured to connect the second electrode of the subsequently formed eleventh transistor to the gate electrode (the first plate of the first capacitor) of the sixth transistor through the via.

[0331] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the gate electrode of the seventh transistor, and the thirty-ninth via V39 is configured to connect the subsequently formed fourth connecting portion and the first electrode of the sixth transistor to the gate electrode of the seventh transistor through the via.

[0332] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fortieth via V40 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) on the substrate, the second insulating layer and the third insulating layer in the fortieth via V40 are etched away to expose the surface of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor), and the fortieth via V40 is configured to connect the second electrode of the seventh transistor and the second electrode of the eighth transistor to be subsequently formed to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) through the via.

[0333] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) on the substrate, the second insulating layer and the third insulating layer in the forty-first via V41 are etched away to expose the surface of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor), and the forty-first via V41 is configured to connect the second electrode of the twelfth transistor and the second electrode of the sixteenth transistor to be subsequently formed to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through the via.

[0334] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) on the substrate, the second insulating layer and the third insulating layer in the forty-second via V42 are etched away to expose the surface of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor), and the forty-second via V42 is configured to connect the first electrode of the subsequently formed third transistor to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the via.

[0335] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the gate electrode of the twelfth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-third via V43 are etched away to expose the surface of the gate electrode of the twelfth transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed tenth transistor to the gate electrode of the twelfth transistor through the via.

[0336] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the gate electrode of the thirteenth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-fourth via V44 are etched away to expose the surface of the gate electrode of the thirteenth transistor, and the forty-fourth via V44 is configured to connect the subsequently formed seventh connecting portion to the gate electrode of the thirteenth transistor through the via.

[0337] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-fifth via hole V45 on the substrate is located within the range of the orthographic projection of the gate electrode of the nineteenth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-fifth via hole V45 are etched away to expose the surface of the gate electrode of the nineteenth transistor, and the forty-fifth via hole V45 is configured to connect the subsequently formed eighth connecting portion to the gate electrode of the nineteenth transistor through the via hole.

[0338] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the first plate of the fourth capacitor on the substrate, the second insulating layer and the third insulating layer in the forty-sixth via V46 are etched away to expose the surface of the first plate of the fourth capacitor, and the forty-sixth via V46 is configured to connect the first electrode of the subsequently formed tenth transistor to the first plate of the fourth capacitor through the via.

[0339] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the first connecting portion on the substrate, the second insulating layer and the third insulating layer in the forty-seventh via V47 are etched away to expose the surface of the first connecting portion, and the forty-seventh via V47 is configured to connect the first electrode of the subsequently formed fourth transistor to the first connecting portion through the via.

[0340] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-eight via V48 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the forty-eight via V48 exposes the surface of the second plate of the first capacitor, and the forty-eight via V48 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second plate of the first capacitor through the via.

[0341] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the forty-ninth via V49 exposes the surface of the second plate of the second capacitor, and the forty-ninth via V49 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) to the second plate of the second capacitor through the via.

[0342] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the second plate of the third capacitor on the substrate, the fiftieth via V50 exposes the surface of the second plate of the third capacitor, and the fiftieth via V50 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the third capacitor through the via.

[0343] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the second electrode plate of the fourth capacitor on the substrate, the fifty-first via V51 exposes the surface of the second electrode plate of the fourth capacitor, and the fifty-first via V51 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the tenth transistor) to the second electrode plate of the fourth capacitor through the via.

[0344] In an exemplary embodiment, as shown in FIG33 , the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second connecting portion on the substrate, the fifty-second via V52 exposes the surface of the second connecting portion, and the fifty-second via V52 is configured to connect the first electrode of the subsequently formed twelfth transistor to the second connecting portion through the via.

[0345] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the third insulating layer, as shown in FIGS. 34 and 35 , where FIG. 34 is a schematic diagram of the third conductive layer pattern in FIG. 26 , and FIG. 35 is a schematic diagram of FIG. 26 after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0346] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the third conductive layer pattern may include at least first and second electrodes 13 and 14 of the first transistor to first and second electrodes 193 and 194 of the nineteenth transistor, and third to eighth connection portions L3 to L8 .

[0347] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 13 of the first transistor and the first electrode 143 of the fourteenth transistor are an integral structure. The first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is in the shape of “┘”. The first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is connected to the first region of the active pattern of the first transistor through the first via hole, and is connected to the first region of the active pattern of the fourteenth transistor through the twenty-fourth via hole.

[0348] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 14 of the first transistor is separately provided. The second electrode 14 of the first transistor is in the shape of a strip and extends along the second direction D2. The second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through the second via hole, and is connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the thirty-fourth via hole.

[0349] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 23 of the second transistor is separately provided. The first electrode 23 of the second transistor is in the shape of a strip and extends along the second direction D2. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through the third via hole, and is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the thirty-third via hole.

[0350] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor are an integrated structure. The integrated structure of the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor is in a zigzag shape and at least partially extends along the second direction D2. The second electrode 24 of the second transistor (also the second electrode 34 of the third transistor and the first electrode 113 of the eleventh transistor) is connected to the second region of the active pattern of the second transistor through the fourth via, connected to the second region of the active pattern of the third transistor through the sixth via, connected to the first region of the active pattern of the eleventh transistor through the nineteenth via, and connected to the gate electrode of the fifth transistor through the thirty-seventh via.

[0351] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 33 of the third transistor is separately provided. The first electrode 33 of the third transistor is in the shape of a strip and extends along the second direction D2. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through the fifth via hole, and is connected to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the forty-second via hole.

[0352] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 43 of the fourth transistor is separately provided. The first electrode 43 of the fourth transistor is in the shape of a strip and at least partially extends along the second direction D2. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the seventh via hole and is connected to the first connection portion through the forty-seventh via hole.

[0353] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are separately provided as an integral structure. The shape of the integral structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor is a broken line, and at least partially extends along the second direction D2. The second electrode 44 of the fourth transistor (also the second electrode 54 of the fifth transistor) is connected to the second area of ​​the active pattern of the fourth transistor through the eighth via hole, connected to the second area of ​​the active pattern of the fifth transistor through the tenth via hole, and connected to the second plate of the third capacitor through the fiftieth via hole.

[0354] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor are an integrated structure, and the integrated structure of the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor is a zigzag shape, and at least partially extends along the second direction D2. The first electrode 53 of the fifth transistor (also the first electrode 83 of the eighth transistor, the first electrode 83 of the ninth transistor, and the first electrode 133 of the thirteenth transistor) is connected to the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) through the ninth via hole, connected to the first area of ​​the active pattern of the ninth transistor through the fifteenth via hole, and connected to the second plate of the second capacitor through the forty-ninth via hole.

[0355] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 63 of the sixth transistor is separately provided. The first electrode 63 of the sixth transistor is in an “I” shape. The first electrode 63 of the sixth transistor is connected to the first region of the active pattern of the sixth transistor through the eleventh via hole, and is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.

[0356] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor are an integrated structure. The shape of the integrated structure of the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor is The second electrode 64 of the sixth transistor (also the first electrode 73 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor through the twelfth via hole, connected to the first region of the active pattern of the seventh transistor through the thirteenth via hole, and connected to the second plate of the first capacitor through the forty-eighth via hole.

[0357] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 74 of the seventh transistor and the first electrode 84 of the eighth transistor are an integrated structure. The integrated structure of the second electrode 74 of the seventh transistor and the first electrode 84 of the eighth transistor is in the shape of a strip and extends along the first direction D1. The second electrode 74 of the seventh transistor (also the first electrode 84 of the eighth transistor) is connected to the second region of the active pattern of the seventh transistor (also the second region of the active pattern of the eighth transistor) through the fourteenth via hole, and is connected to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) through the fortieth via hole.

[0358] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor are an integrated structure. The shape of the integrated structure of the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor is a “┘” shape. The second electrode 94 of the ninth transistor (also the first electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor through the sixteenth via, connected to the second region of the active pattern of the tenth transistor through the eighteenth via, and connected to the second plate of the fourth capacitor through the fifty-first via.

[0359] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 103 of the tenth transistor may be provided separately. The first electrode 103 of the tenth transistor is in a zigzag shape and at least partially extends along the second direction D2. The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through the seventeenth via hole, connected to the gate electrode of the twelfth transistor through the forty-third via hole, and connected to the first plate of the fourth capacitor through the forty-sixth via hole.

[0360] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 114 of the eleventh transistor may be provided separately. The second electrode 114 of the eleventh transistor is in the shape of a broken line and at least partially extends along the second direction D2. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the twentieth via hole, and is connected to the gate electrode (the first plate of the first capacitor) of the sixth transistor through the thirty-eighth via hole.

[0361] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 123 of the twelfth transistor may be provided separately. The first electrode 123 of the twelfth transistor is in a strip shape and extends along the first direction D1. The first electrode 123 of the twelfth transistor is connected to the first region of the active pattern of the twelfth transistor through the twenty-first via hole, and is connected to the second connection portion through the fifty-second via hole.

[0362] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor are an integrated structure. The integrated structure of the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor is in a strip shape and extends along the first direction D1. The second electrode 124 of the twelfth transistor (also the first electrode 164 of the sixteenth transistor) is connected to the second region of the active pattern of the twelfth transistor (also the second region of the active pattern of the sixteenth transistor) through the twenty-second via hole, and is connected to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through the forty-first via hole.

[0363] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 134 of the thirteenth transistor may be provided separately. The second electrode 134 of the thirteenth transistor is in the shape of a strip and extends along the first direction D1. The second electrode 134 of the thirteenth transistor is connected to the second region of the active pattern of the thirteenth transistor through the twenty-third via hole, connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the thirty-fourth via hole, and connected to the second connection portion through the fifty-second via hole.

[0364] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor are an integrated structure. The integrated structure of the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor is in the shape of a right-rotated “J”. The second electrode 144 of the fourteenth transistor (also the first electrode 153 of the fifteenth transistor) is connected to the second region of the active pattern of the fourteenth transistor through the twenty-fifth via hole, and is connected to the first region of the active pattern of the fifteenth transistor through the twenty-sixth via hole.

[0365] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 154 of the fifteenth transistor may be provided separately. The second electrode 154 of the fifteenth transistor is in the shape of a strip and extends along the second direction D2. The second electrode 154 of the fifteenth transistor is connected to the second region of the active pattern of the fifteenth transistor through the twenty-seventh via hole, and is connected to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the thirty-sixth via hole.

[0366] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 163 of the sixteenth transistor may be provided separately. The first electrode 163 of the sixteenth transistor is in the shape of a strip and extends along the first direction D1. The first electrode 163 of the sixteenth transistor is connected to the first region of the active pattern of the sixteenth transistor through the twenty-eighth via hole, and is connected to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the thirty-sixth via hole.

[0367] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 173 of the seventeenth transistor may be provided separately. The first electrode 173 of the seventeenth transistor includes: a fourth connection segment 173A and at least one fourth branch segment 173B, at least one fourth branch segment 173B is located on the side of the fourth connection segment 173A close to the display area and is connected to the fourth connection segment 173A. The first electrode 173 of the seventeenth transistor is in a comb-like structure, the shape of the fourth connection segment 173A is a "┘" shape, which is equivalent to a "comb back", the fourth branch segment 173B extends along the first direction D1, and at least one fourth branch segment 173B is arranged along the second direction D2, which is equivalent to a "comb tooth". The first electrode 173 of the seventeenth transistor is connected to the first area of ​​the active pattern of the seventeenth transistor through the twenty-ninth via.

[0368] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor are an integrated structure. The shape of the integrated structure of the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor is a comb-like structure. The integrated structure of the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor includes: a fifth connecting segment 174A and at least one fifth branch segment 174B, at least one fifth branch segment 174B is connected to the fifth connecting segment 174A, and is located on the side of the fifth connecting segment 174A away from the display area, the fifth connecting segment 174A is in the shape of a strip and extends along the second direction D2, which is equivalent to a "comb back", at least one fifth branch segment 174B is in the shape of a strip and extends along the first direction D1, and at least one fifth branch segment 174B is arranged along the second direction D2, which is equivalent to a "comb tooth". The second electrode 174 of the seventeenth transistor (also the first electrode 183 of the eighteenth transistor) is connected to the second region of the active pattern of the seventeenth transistor (also the first region of the active pattern of the eighteenth transistor) through the thirtieth via hole.

[0369] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor are an integrated structure. The shape of the integrated structure of the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor is a comb-like structure. The integrated structure of the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor includes: a sixth connecting segment 184A and at least one sixth branch segment 184B, at least one sixth branch segment 184B is connected to the sixth connecting segment 184A and is located on the side of the sixth connecting segment 184A close to the display area, the sixth connecting segment 184A is in the shape of a strip and extends along the second direction D2, which is equivalent to a "comb back", and at least one sixth branch segment 184B is in the shape of a strip and extends along the first direction D1, and at least one sixth branch segment 184B is arranged along the second direction D2, which is equivalent to a "comb tooth". The second electrode 184 of the eighteenth transistor (also the second electrode 194 of the nineteenth transistor) is connected to the second region of the active pattern of the eighteenth transistor (also the second region of the active pattern of the nineteenth transistor) through the thirty-first via hole.

[0370] In an exemplary embodiment, as shown in FIGS. 34 and 35 , the first electrode 193 of the nineteenth transistor may be provided separately. The first electrode 193 of the nineteenth transistor is shaped like an “n” rotated to the left, and its opening is away from the display area. The first electrode 193 of the nineteenth transistor is connected to the first area of ​​the active pattern of the nineteenth transistor through the thirty-second via hole.

[0371] In an exemplary embodiment, as shown in Figures 34 and 35, the third connection portion L3 is provided separately. The third connection portion L3 is in the shape of a strip and extends along the second direction D2. The third connection portion L3 is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the thirty-third via hole.

[0372] In an exemplary embodiment, as shown in Figures 34 and 35, the fourth connection portion L4 is provided separately. The fourth connection portion L4 is in a strip shape and extends along the second direction D2. The fourth connection portion L4 is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.

[0373] In an exemplary embodiment, as shown in Figures 34 and 35, the fifth connection portion L5 is provided separately. The fifth connection portion L5 is in a strip shape and extends along the second direction D2. The fifth connection portion L5 is connected to the gate electrode of the third transistor through the thirty-fifth via hole.

[0374] In an exemplary embodiment, as shown in Figures 34 and 35, the sixth connection portion L6 is provided separately. The sixth connection portion L6 is in a strip shape and extends along the second direction D2. The sixth connection portion L6 is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.

[0375] In an exemplary embodiment, as shown in Figures 34 and 35, the seventh connection portion L7 is provided separately. The seventh connection portion L7 is in a strip shape and extends along the first direction D1. The seventh connection portion L7 is connected to the gate electrode of the thirteenth transistor through the forty-fourth via hole.

[0376] In an exemplary embodiment, as shown in Figures 34 and 35, the eighth connection portion L8 is provided separately. The eighth connection portion L8 is in a strip shape and extends along the second direction D2. The eighth connection portion L8 is connected to the gate electrode of the nineteenth transistor through the forty-fifth via hole.

[0377] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include:

[0378] A fourth insulating film is deposited on the substrate formed with the aforementioned pattern, and the fourth insulating film is composed through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure. The fourth insulating layer is provided with a plurality of via patterns, as shown in FIG36 , which is a schematic diagram after the fourth insulating layer pattern is formed in FIG26 .

[0379] In an exemplary embodiment, as shown in FIG. 36 , the fourth insulation layer pattern of each shift register may include at least a fifty-second via hole V52 to a sixty-fourth via hole V64 .

[0380] In an exemplary embodiment, as shown in FIG36, the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the third connection portion on the substrate, the fifty-second via hole V52 exposes the surface of the third connection portion, and the fifty-second via hole V52 is configured to connect one of the first clock signal line and the second clock signal line formed subsequently to the third connection portion through the via hole. FIG36 is described by taking the fifty-second via hole V52 configured to connect the first clock signal line formed subsequently to the third connection portion through the via hole as an example.

[0381] In an exemplary embodiment, as shown in FIG36, the orthographic projection of the fifty-third via hole V53 on the substrate is located within the range of the orthographic projection of the fifth connecting portion on the substrate, the fifty-third via hole V53 exposes the surface of the fifth connecting portion, and the fifty-third via hole V53 is configured to connect one of the first clock signal line and the second clock signal line formed subsequently to the fifth connecting portion through the via hole. FIG36 is described by taking the fifty-third via hole V53 configured to connect the first clock signal line formed subsequently to the fifth connecting portion through the via hole as an example.

[0382] In an exemplary embodiment, as shown in FIG36, the orthographic projection of the fifty-fourth via hole V54 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fifty-fourth via hole V54 exposes the surface of the first electrode of the fourth transistor, and the fifty-fourth via hole V54 is configured to connect the other signal line of the first clock signal line and the second clock signal line formed subsequently to the first electrode of the fourth transistor through the via hole. FIG36 is described by taking the fifty-fourth via hole V54 as an example in which the second clock signal line formed subsequently is connected to the first electrode of the fourth transistor through the via hole.

[0383] In an exemplary embodiment, as shown in FIG36, the orthographic projection of the fifty-fifth via hole V55 on the substrate is located within the range of the orthographic projection of the fourth connection portion on the substrate, the fifty-fifth via hole V55 exposes the surface of the fourth connection portion, and the fifty-fifth via hole V55 is configured to connect the other signal line of the first clock signal line and the second clock signal line formed subsequently to the fourth connection portion through the via hole. FIG36 is described by taking the fifty-fifth via hole V55 as an example in which the second clock signal line formed subsequently is connected to the fourth connection portion through the via hole.

[0384] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the first electrode of the third transistor on the substrate, the fifty-sixth via V56 exposes the surface of the first electrode of the third transistor, and the fifty-sixth via V56 is configured to connect a subsequently formed first second power line to the first electrode of the third transistor through the via.

[0385] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the second pole of the fourth transistor (also the second pole of the fifth transistor) on the substrate, the fifty-seventh via V57 exposes the surface of the second pole of the fourth transistor (also the second pole of the fifth transistor), and the fifty-seventh via V57 is configured to connect the subsequently formed ninth connection portion to the second pole of the fourth transistor (also the second pole of the fifth transistor) through the via.

[0386] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the fifty-eighth via V58 on the substrate is located within the range of the orthographic projection of the sixth connecting portion on the substrate, the fifty-eighth via V58 exposes the surface of the sixth connecting portion, and the fifty-eighth via V58 is configured to connect a subsequently formed third power line to the sixth connecting portion through the via.

[0387] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the seventh connecting portion on the substrate, the fifty-ninth via V59 exposes the surface of the seventh connecting portion, and the fifty-ninth via V59 is configured to connect a subsequently formed third power line to the seventh connecting portion through the via.

[0388] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the sixtieth via hole V60 on the substrate is located within the range of the orthographic projection of the first electrode of the tenth transistor on the substrate, the sixtieth via hole V60 exposes the surface of the first electrode of the tenth transistor, and the sixtieth via hole V60 is configured to connect a second second power line formed subsequently to the first electrode of the tenth transistor through the via hole.

[0389] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the sixty-first via V61 on the substrate is located within the range of the orthographic projection of the first electrode of the seventeenth transistor on the substrate, the sixty-first via V61 exposes the surface of the first electrode of the seventeenth transistor, and the sixty-first via V61 is configured to connect a subsequently formed second second power line to the first electrode of the seventeenth transistor through the via.

[0390] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) on the substrate, the sixty-second via V62 exposes the surface of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor), and the sixty-second via V62 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the via.

[0391] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the first electrode of the nineteenth transistor on the substrate, the sixty-third via V63 exposes the surface of the first electrode of the nineteenth transistor, and the sixty-third via V63 is configured to connect a subsequently formed first power line to the first electrode of the nineteenth transistor through the via.

[0392] In an exemplary embodiment, as shown in FIG36 , the orthographic projection of the sixty-fourth via hole V64 on the substrate is located within the range of the orthographic projection of the eighth connecting portion on the substrate, the sixty-fourth via hole V64 exposes the surface of the eighth connecting portion, and the sixty-fourth via hole V64 is configured to connect a subsequently formed scanning control signal line to the eighth connecting portion through the via hole.

[0393] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 37 and 38 , where FIG. 37 is a schematic diagram of the fourth conductive layer pattern in FIG. 26 , and FIG. 38 is a schematic diagram of FIG. 26 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0394] In an exemplary embodiment, as shown in Figures 37 and 38, the fourth conductive layer pattern located in each shift register may include at least: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, two second power lines VGL, a third power line VCX, a scan control signal line MSL and a ninth connection portion L9.

[0395] In an exemplary embodiment, as shown in Figures 37 and 38, the first clock signal line CLK1, the second clock signal line CLK2, the first second power line VGL, the third power line VCX, the second second power line VGL, the first power line VGH and the scan control signal line MSL are sequentially arranged in a direction close to the display area. The ninth connection portion L9 is located between the first second power line VGL and the third power line VCX.

[0396] 37 and 38, the first clock signal line CLK1 may be in a line shape with a main portion extending along the second direction D2. The first clock signal line CLK1 is connected to the third connection portion through the fifty-second via hole and to the fifth connection portion through the fifty-third via hole.

[0397] 37 and 38, the second clock signal line CLK2 may be in the shape of a line whose main portion extends along the second direction D2. The second clock signal line CLK2 is connected to the first electrode of the fourth transistor through the fifty-fourth via hole and to the fourth connection portion through the fifty-fifth via hole.

[0398] 37 and 38, the shape of the first second power line VGL may be a line shape in which the main body portion extends along the second direction D2. The first second power line VGL is connected to the first electrode of the fourth transistor through the fifty-sixth via hole and is connected to the first electrode of the third transistor through the fifty-fifth via hole.

[0399] 37 and 38, the third power line VCX may be in a line shape with a main portion extending along the second direction D2. The third power line VCX is connected to the sixth connection portion through the fifty-eighth via hole and to the seventh connection portion through the fifty-ninth via hole.

[0400] 37 and 38, the second second power line VGL may be in the shape of a line whose main body portion extends along the second direction D2. The second second power line VGL is connected to the first electrode of the tenth transistor through the sixtieth via hole and to the first electrode of the seventeenth transistor through the sixty-first via hole.

[0401] In an exemplary embodiment, as shown in Figures 37 and 38, the shape of the first power line VGH may be a line shape in which the main body portion extends along the second direction D2. The first power line VGH is connected to the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the sixty-second via hole, and is connected to the first electrode of the nineteenth transistor through the sixty-third via hole.

[0402] 37 and 38, the shape of the scan control signal line MSL may be a line shape in which a main portion extends along the second direction D2. The scan control signal line MSL is connected to the eighth connection portion through the sixty-fourth via hole.

[0403] In an exemplary embodiment, the line width of the scan control signal line MSL is smaller than the line width of any one of the first power line VGH and the second power line VGL.

[0404] In an exemplary embodiment, the line width of the third power line VCX is smaller than the line width of any one signal line of the first power line VGH and the second power line VGL.

[0405] In an exemplary embodiment, the line width of the first clock signal line CLK1 and the second clock signal line CLK2 is smaller than the line width of any one of the first power line VGH and the second power line VGL.

[0406] (8) Forming a planar layer. In an exemplary embodiment, forming a planar layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern, coating a planar film, and patterning the fifth insulating film and the planar film by a patterning process to form a fifth insulating layer pattern covering the aforementioned structure and a planar layer pattern covering the fifth insulating layer pattern.

[0407] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include a plurality of shift registers, and the shift registers are electrically connected to the first clock signal line, the second clock signal line, the first power line, the second power line, the third power line and the scan control signal line. In a plane perpendicular to the display substrate, the drive circuit layer may be arranged on the substrate, and the substrate may include a first flexible layer, a barrier layer, a substrate conductive layer and a second flexible layer stacked. The drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer and a flat layer sequentially arranged on the substrate. The semiconductor layer may include at least active patterns of the first transistor to the nineteenth transistor, the first conductive layer may include at least gate electrodes of the first transistor to the nineteenth transistor and the first plate of the first capacitor to the first plate of the fourth capacitor, the second conductive layer may include at least the second plate of the first capacitor to the second plate of the fourth capacitor, the third conductive layer may include at least the first electrode and the second electrode of any transistor among the first transistor to the nineteenth transistor, and the fourth conductive layer may include at least: a first clock signal line, a second clock signal line, a first power line, a second power line, a third power line and a scan control signal line.

[0408] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0409] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0410] In an exemplary embodiment, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0411] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0412] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer, the third insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fourth insulating layer may be referred to as a passivation (PVX) layer.

[0413] In an exemplary embodiment, the planar layer and the planar layer may employ an organic material such as a resin or the like.

[0414] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0415] On the substrate forming the aforementioned pattern, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the second flat layer; on the substrate forming the aforementioned pattern, a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern; on the substrate formed with the pixel definition layer pattern, an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern; on the substrate forming the organic material layer pattern, a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.

[0416] At this point, the light-emitting structure layer is prepared on the substrate.

[0417] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns, wherein the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light emitting device, wherein the anode of the first light emitting device is located at a red sub-pixel emitting red light, the anode of the second light emitting device may be located at a blue sub-pixel emitting blue light, the anode of the third light emitting device may be located at a first green sub-pixel emitting green light, and the anode of the fourth light emitting device may be located at a second green sub-pixel emitting green light.

[0418] In an exemplary embodiment, the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the first direction D1, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the first direction D1. Alternatively, the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the second direction D2, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the second direction D2.

[0419] In an exemplary embodiment, the shapes and areas of anode electrodes of four sub-pixels in one pixel unit may be the same, or may be different.

[0420] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0421] In an exemplary embodiment, the organic structure layer may include at least: an organic light emitting layer of a light emitting device.

[0422] In an exemplary embodiment, the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.

[0423] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.

[0424] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0425] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0426] The embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0427] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0428] In an exemplary embodiment, the display device may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0429] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0430] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0431] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

A shift register, comprising: Cascade output subcircuit and scan output subcircuit; The cascade output subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the cascade output terminal, the first node and the second node, respectively, and is configured to provide signals to the first node and the second node under the control of the signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal, and to provide signals of the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals of the first node and the second node; the scan output subcircuit is electrically connected to the scan control signal terminal, the first power supply terminal, the second power supply terminal, the scan output terminal, the first node and the second node, respectively, and is configured to provide signals of the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals of the first node, the second node and the scan control signal terminal. The shift register according to claim 1, wherein: The scan output subcircuit includes: a first output control subcircuit and a second output control subcircuit; the first output control subcircuit is electrically connected to the second power supply terminal, the scan output terminal and the second node, respectively, and is configured to provide the signal of the second power supply terminal to the scan output terminal under the control of the signal of the second node; the second output control subcircuit is electrically connected to the scan control signal terminal, the first power supply terminal, the scan output terminal and the first node, respectively, and is configured to provide the signal of the first power supply terminal to the scan output terminal under the control of the scan control signal terminal and the signal of the first node. The shift register according to claim 2, wherein: The scan output subcircuit further includes: a storage subcircuit; the storage subcircuit is electrically connected to the scan output terminal and the first power supply terminal respectively, and is configured to store a voltage difference between the signal at the scan output terminal and the signal at the first power supply terminal. The shift register according to claim 2, wherein: The first output control subcircuit includes: a seventeenth transistor; the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal. The shift register according to claim 2, wherein: The second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor; the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node. The shift register according to claim 2, wherein: The second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor; the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node. The shift register according to claim 3, wherein: The storage subcircuit includes: a fifth capacitor; a first plate of the fifth capacitor is electrically connected to the scan output terminal, and a second plate of the fifth capacitor is electrically connected to the first power supply terminal. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor to a sixteenth transistor and a first capacitor to a fourth capacitor, any capacitor of the first capacitor to the fourth capacitor includes: a first plate and a second plate; a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode of the first transistor is electrically connected to the signal input terminal, and a second electrode of the first transistor is electrically connected to the fourth node; a control electrode of the second transistor is electrically connected to the fourth node, a first electrode of the second transistor is electrically connected to the first clock signal terminal, and a second electrode of the second transistor is electrically connected to the fifth node; a control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fifth node; a control electrode of the fourth transistor is electrically connected to the fourth node, a first electrode of the second transistor is electrically connected to the first clock signal terminal, and a second electrode of the third transistor is electrically connected to the fifth node; The control electrode of the fifth transistor is electrically connected to the fifth node, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the seventh node; the control electrode of the sixth transistor is electrically connected to the ninth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the eighth node; the control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the eighth node, and the second electrode of the seventh transistor is electrically connected to the first node; the control electrode of the eighth transistor is electrically connected to the fourth node, and the first electrode of the eighth transistor is electrically connected to the eighth node. The first power supply terminal is electrically connected to the first power supply terminal, and the second pole of the eighth transistor is electrically connected to the first node; the control pole of the ninth transistor is electrically connected to the first node, the first pole of the ninth transistor is electrically connected to the first power supply terminal, and the second pole of the ninth transistor is electrically connected to the cascade output terminal; the control pole of the tenth transistor is electrically connected to the second node, the first pole of the tenth transistor is electrically connected to the second power supply terminal, and the second pole of the tenth transistor is electrically connected to the cascade output terminal; the control pole of the eleventh transistor is electrically connected to the second power supply terminal, the first pole of the eleventh transistor is electrically connected to the fifth node, and the second pole of the eleventh transistor is electrically connected to the ninth node; the control pole of the twelfth transistor is electrically connected to the second power supply terminal, the first pole of the twelfth transistor is electrically connected to the fourth node, and the control pole of the twelfth transistor is electrically connected to the the second electrode is electrically connected to the second node; the control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node; the control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the tenth node; the control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the tenth node, and the second electrode of the fifteenth transistor is electrically connected to the sixth node; the control electrode of the sixteenth transistor is electrically connected to the sixth node, the first electrode of the sixteenth transistor is electrically connected to the sixth node, and the second electrode of the sixteenth transistor is electrically connected to the second node;The first plate of the first capacitor is electrically connected to the ninth node, and the second plate of the first capacitor is electrically connected to the eighth node; the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the first power supply terminal; the first plate of the third capacitor is electrically connected to the sixth node, and the second plate of the third capacitor is electrically connected to the seventh node; the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal.; The shift register according to claim 1 or 8, wherein: The scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor; the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal; the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node; the first plate of the fifth capacitor is electrically connected to the scan output terminal, and the second plate of the fifth capacitor is electrically connected to the first power supply terminal. The shift register according to claim 1 or 8, wherein: The scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor; the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal; the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node; the first plate of the fifth capacitor is electrically connected to the scan output terminal, and the second plate of the fifth capacitor is electrically connected to the first power supply terminal. A display substrate comprises a display area and a non-display area, wherein: include: A gate driving circuit located in the non-display area and array-arranged sub-pixels and multiple gate lines located in the display area, the sub-pixels include a pixel driving circuit and a light-emitting device, the gate line at least partially extends along a first direction, the gate driving circuit includes: a plurality of cascaded shift registers as described in any one of claims 1 to 10, the pixel driving circuit includes: a plurality of transistors; the cascade output end of at least one shift register is electrically connected to the signal input end of at least one shift register; the gate line is electrically connected to the gate electrode of the at least one transistor, and any shift register is electrically connected to at least one gate line. The display substrate according to claim 11, wherein The display area is divided into a plurality of display sub-areas, at least one display sub-area includes: at least one gate line; the display mode of any display sub-area includes: a first display mode and a second display mode, and the refresh frequency of the first display mode is greater than the refresh frequency of the second display mode; when the display mode of the display sub-area is the first display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output end is a first level signal, at least part of the time period of the signal at the scan control signal end is a valid level signal, and the signal at the scan output end is a first level signal; when the display mode of the display sub-area is the second display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output end is a first level signal, the signal at the scan control signal end is an invalid level signal, and the signal at the scan output end is a second level signal; wherein the voltage value of the first level signal is greater than the voltage value of the second level signal. The display substrate according to claim 11 or 12, further comprising: at least one scan control signal line located in the non-display area, the scan control signal line at least partially extending along a second direction, the first direction and the second direction intersecting; The scanning control signal terminals connected to all the shift registers are electrically connected to the at least one scanning control signal line. The display substrate according to claim 13, wherein: The number of the scanning control signal line is one, and the scanning control signal terminals connected to all the shift registers are electrically connected to the same scanning control signal line. The display substrate according to claim 13, wherein: The number of the scanning control signal lines is at least two; the scanning control signal end connected to any shift register from the M*(k-1)+K*M(a-1)+1th level shift register to the k*M+K*M(a-1)th level shift register is electrically connected to the kth scanning control signal line, 1≤k≤K, 1≤a≤N / M, M is the number of shift registers connected to a scanning control signal line, N is the total number of shift registers, and K is the number of scanning control signal lines. The display substrate according to claim 15, wherein The picture displayed by the display substrate includes: multiple display frames. In any display frame, the output signal of the scan output end of the shift register is a pulse signal, and the duration H of the pulse signal satisfies the following relationship; H=L*[M*K-(M-1)]*h, wherein L is the number of gate lines connected to any level of shift register, and h is the unit time, which is equal to the refresh interval time of adjacent rows of sub-pixels. The display substrate according to claim 13, further comprising: A first clock signal line, a second clock signal line, a first power line, a second power line and a third power line located in the non-display area; Any one of the first clock signal line, the second clock signal line, the first power line, the second power line and the third power line at least partially extends along the second direction; the first clock signal end connected to any level of shift register is electrically connected to one of the first clock signal line and the second clock signal line, the second clock signal end connected to any level of shift register is electrically connected to the other of the first clock signal line and the second clock signal line, the clock signal lines connected to the first clock signal ends connected to adjacent shift registers are different, the clock signal lines connected to the second clock signal ends connected to adjacent shift registers are different, the first power ends connected to all shift registers are electrically connected to the first power line, the second power ends connected to all shift registers are electrically connected to the second power line, and the third power ends connected to all shift registers are electrically connected to the third power line. The display substrate according to claim 17, wherein: The scan control signal line is located at a side of any one of the first clock signal line, the second clock signal line, the first power line, the second power line and the third power line close to the display area. The display substrate according to claim 17 or 18, wherein: The number of the second power lines is two, and the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first power line are arranged in sequence along a direction close to the display area. The display substrate according to claim 19, wherein: The shift register includes: a seventeenth transistor to a nineteenth transistor; the seventeenth transistor to the nineteenth transistor are arranged along the second direction; at least a portion of any one of the seventeenth transistor to the nineteenth transistor is located between the first power line and the scan control signal line. The display substrate according to claim 20, wherein: Any transistor includes an active pattern, and an average length of the active pattern of the seventeenth transistor along the first direction is smaller than an average length of the active pattern of any transistor of the eighteenth transistor and the nineteenth transistor along the first direction. The display substrate according to claim 17, wherein: A line width of any one of the first power line and the second power line is greater than a line width of the scan control signal line. A display device, comprising: A display substrate as claimed in any one of claims 11 to 22. A shift register driving method, configured to drive the shift register according to any one of claims 1 to 10, the method comprising: The cascade output subcircuit provides signals to the first node and the second node under the control of the signals at the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides signals from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of the signals at the first node and the second node; the scan output subcircuit provides signals from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals at the first node, the second node and the scan control signal terminal.

Images