Improved energy saving Ethernet (EEE) operation

Abstract

A network interface device operates in a normal transmit mode of operation in which the network interface device continuously receives transmission symbols from a link partner via a communication link. The network interface device determines that receiving circuitry of the network interface device transitions to a low power mode in response to receiving a sleep signal from a link partner. The network interface device then operates according to a silence / refresh cycle of the low power mode to conserve power. The silence / refresh cycle corresponds to a schedule that includes a refresh time window within which receive circuitry of the network interface device is to be energized to receive a refresh signal from the link partner. Upon transmitting the sleep signal, the network interface device transitions to a silent time window of the timeschedule within which the network interface device ignores transmissions from the link partner.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 344,730, filed on May 23, 2022, entitled “Energy Efficient Ethernet (EEE) Low Power Idle (LPI) Signaling.” In addition, this application is a continuation-in-part of U.S. Patent Application No. 18 / 142,491, filed on May 2, 2023, entitled “Energy Efficient Ethernet (EEE) Low Power Idle (LPI) Signaling,” which claims the benefit of U.S. Provisional Patent Application No. 63 / 337,235, filed on May 2, 2022, entitled “RevisitAlert Signaling,” and U.S. Provisional Patent Application No. 63 / 337,240, filed on May 2, 2022, entitled “Energy Efficient Ethernet (EEE) Quiet Signaling Clarification.” All of the above applications are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to communication techniques, and more particularly to power saving techniques for communications. Background Art

[0004] IEEE 802.3ch TM Standards, Institute of Electrical and Electronics Engineers (IEEE), pages 1-207, June 30, 2020 (“IEEE Std 802.3ch TM-2020”) describes a feature called Energy Efficient Ethernet (EEE) that reduces power consumption during periods when a transmitter does not need to send data. For example, when a transmitter does not need to send data via a communication link, the transmitter transitions the communication link from a normal operating mode to a low power idle (LPI) operating mode. During LPI mode, the transmitter and link partner receiver operate in a repeating silent refresh cycle, where the transmitter does not send anything during periodic time periods (referred to as “silent time periods”) and sends refresh symbols during other periodic time periods (referred to as “refresh time periods”). Since nothing is sent during the silent time periods, power consumption at the transmitter is reduced. Similarly, the link partner receiver may also perform refresh during the silent time periods. The LPI includes a plurality of repeated quiet / refresh cycles, wherein each quiet / refresh cycle includes a quiet period and a refresh period. During the quiet period, the leader device does not transmit (according to an embodiment), and during the refresh period, the leader device sends a refresh signal including a refresh symbol. The follower device receives the refresh signal during the refresh period and uses the refresh symbol to synchronize with the timing of the leader device and adjust the adaptive filter of the follower device. The quiet period is significantly longer than the refresh period, and therefore the power consumption during the quiet / refresh period is significantly reduced compared to normal operation.

[0005] The quiet / refresh cycle includes a designated window (referred to herein as an "alert time window") during which the leader device may send a signal (referred to herein as an "alert signal") that warns the follower device that the leader device will soon send a wake-up signal, wherein the wake-up signal is a request to exit the LPI mode. When in the LPI mode, the follower device is configured to power on (at least some receiver circuitry) to prepare to receive the alert signal in any alert time window. In response to receiving the alert signal in the alert time window, the follower device keeps at least some receiver circuitry powered on in anticipation of receiving the wake-up signal. In response to receiving the wake-up signal, the follower device receiver exits the LPI mode. When in the LPI mode, the follower device is configured to power off (at least some) receiving circuitry when outside the alert time window. Similarly, when in the LPI mode, the leader device is configured to power off (at least some) sending circuitry during the quiet time period, unless the leader device determines to exit the LPI mode, in which case the leader device powers on the sending circuitry to send the alert signal during one of the alert time windows.

[0006] The LPI mode described above can also be independently performed in the opposite direction from the follower device to the leader device. In other words, the forward link from the leader device to the follower device can be operated in LPI mode independently of the reverse link from the follower device to the leader device, and vice versa. Summary of the invention

[0007] In one embodiment, a network interface device includes: a physical layer (PHY) circuit device including a transceiver, the PHY processor configured to perform PHY functions associated with a communication link. The network interface also includes a controller. The controller is configured to: operate the PHY circuit device in a normal receive operation mode, wherein the PHY circuit device continuously receives transmission symbols from a link partner via a communication link; determine that a receive circuit device of the PHY circuit device is to transition to a low power mode in response to receiving a sleep signal from the link partner; and in response to determining that the receive circuit device is to transition to the low power mode and after receiving the sleep signal, control the PHY circuit device to operate according to a quiet / refresh cycle of the low power mode to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window, within which the receive circuit device of the PHY circuit device is powered to receive the refresh signal from the link partner to facilitate maintaining synchronization of the receive circuit device of the PHY circuit device with the link partner, including controlling the PHY circuit device to transition to a quiet time window of the schedule immediately after transmission of the sleep signal, within which the PHY circuit device ignores transmissions from the link partner.

[0008] In another embodiment, a method for power conservation with respect to a communication link includes: operating a network interface device in a normal transmit operation mode in which the network interface device continuously receives transmission symbols from a link partner via the communication link; determining, at the network interface device, in response to receiving a sleep signal from the link partner, that a receive circuit device of the network interface device is to transition to a low power mode; in response to determining that the receive circuit device is to transition to the low power mode and after receiving the sleep signal, operating the network interface device according to a quiet / refresh cycle of the low power mode to conserve power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window within which the receive circuit device of the network interface device is to be powered on to receive the refresh signal from the link partner to facilitate maintaining synchronization of the receive circuit device of the network interface device with the link partner, including transitioning the network interface device to a quiet time window of the schedule immediately after transmission of the sleep signal, within which the network interface device ignores transmissions from the link partner.

[0009] In yet another embodiment, a network interface device includes: a PHY circuit device including a transceiver, a PHY processor configured to perform PHY functions associated with a communication link. The network interface also includes a controller. The controller is configured to: operate the PHY circuit device in a normal transmit operation mode in which the PHY circuit device continuously transmits transmission symbols to a link partner via a communication link; determine that a transmit circuit device of the PHY circuit device is to transition to a low power mode; in response to determining that the transmit circuit device is to transition to the low power mode, send a sleep signal to the link partner via the communication link to prompt the link partner to enter the low power mode; and in response to determining that the transmit circuit device is to transition to the low power mode and after sending the sleep signal, control the PHY circuit device to operate according to a quiet / refresh cycle to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window, within which the PHY circuit device will send a refresh signal to the link partner to facilitate maintaining synchronization of the link partner's receive circuit device with the PHY circuit device, including controlling the PHY circuit device to transition to a quiet time window of the schedule immediately after transmission of the sleep signal, within which the PHY circuit device silences transmissions to the link partner.

[0010] In another embodiment, a method for power conservation with respect to a communication link includes: operating a network interface device in a normal transmit operation mode, wherein the network interface device continuously transmits transmission symbols to a link partner via the communication link; determining at the network interface device that a transmit circuit device of the network interface device is to transition to a low power mode; in response to determining that the transmit circuit device is to transition to the low power mode; sending, by the network interface device, a sleep signal to the link partner via the communication link to prompt the link partner to enter the low power mode; and in response to determining that the transmit circuit device is to transition to the low power mode and after sending the sleep signal, operating the network interface device according to a quiet / refresh cycle to conserve power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window within which the network interface device is to send a refresh signal to the link partner to facilitate maintaining synchronization of the link partner's receive circuit device with the network interface device, including immediately after transmission of the sleep signal, transitioning the network interface device to a quiet time window of the schedule within which the transmit circuit device silences transmissions to the link partner. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a timing diagram of an example quiet / refresh cycle of a low power mode according to an embodiment, which achieves power savings with respect to a communication link.

[0012] Figure 2is a timing diagram of an example start of quiet / refresh cycle schedule for a low power mode according to an embodiment.

[0013] Figure 3 is a timing diagram illustrating sending sleep signals, alarm signals, and wake-up signals during an example low power mode according to one embodiment.

[0014] Figure 4 is a timing diagram illustrating sending sleep signals and wake-up signals during another example low power mode according to another embodiment.

[0015] Figure 5 is a block diagram of an example network interface device implementing a power saving mode involving quiet / refresh cycle periods according to one embodiment.

[0016] Figure 6 is a flow chart of an example method for power conservation with respect to a communication link, according to one embodiment.

[0017] Figure 7 is a flow chart of another example method for power conservation with respect to a communication link according to another embodiment.

[0018] Figure 8 is a flow chart of another example method for power conservation with respect to a communication link according to another embodiment.

[0019] Fig. 9 is a flow chart of another example method for power conservation with respect to a communication link according to another embodiment. DETAILED DESCRIPTION

[0020] According to the Institute of Electrical and Electronics Engineers (IEEE) IEEE 802.3ch TM Energy Efficient Ethernet (EEE) Mechanisms Defined by Standards, pp. 1-207, June 30, 2020 (“IEEE Std 802.3ch TM -2020”), the quiet / refresh cycle of the low power idle (LPI) mode starts with an alarm time window. Therefore, after a sleep signal from a leader device, the follower device immediately enters a quiet / refresh cycle and must keep its receiver circuit device powered on to listen for the alarm signal from the leader device. However, since the leader device turns off the transmitter circuit device after sending the sleep signal, fault and / or transient signals may be sent on the communication link after the sleep signal. Since the receiver circuit device of the follower device is powered on immediately after the sleep signal to listen for the alarm signal from the leader device, the follower device may interpret the fault and / or transient signal as an alarm signal, which may result in unpredictable behavior of the follower device and / or increased power consumption of the follower device.

[0021] In one embodiment, the timing schedule of the quiet / refresh cycle includes alternating quiet time windows and alarm time windows, wherein the quiet / refresh cycle begins with the quiet time window. As a result, after the follower device receives the sleep signal from the leader device, the follower device immediately transitions to the quiet time window, in which the follower device ignores signals received via the communication link. Since the follower device immediately transitions to the quiet time window and ignores signals received via the communication link after receiving the sleep signal ends, any faults and / or transient signals on the communication link after the sleep signal are ignored by the follower device.

[0022] Figure 1 1 is a timing diagram of an example quiet / refresh cycle period 100 of a low power mode according to one embodiment. Quiet / refresh cycle period 100 corresponds to a communication link from a leader communication device (sometimes referred to herein as a "leader") to a follower communication device (sometimes referred to herein as a "follower") and is initiated by the leader sending a sleep signal 104 to the follower. Quiet / refresh cycle period 100 is sometimes referred to herein as "leader quiet / refresh cycle period 100".

[0023] The leader quiet / refresh cycle period 100 has a suitable duration T and begins immediately after the end of the sleep signal 104 sent by the leader device. According to one embodiment, the leader quiet / refresh cycle period 100 repeats until the leader decides to transition to a normal operating mode.

[0024] The leader quiet / refresh cycle period 100 includes quiet time windows 108, alert time windows 112, and refresh time windows 116 that are ordered according to a time schedule. The quiet time windows 108 alternate in time with the alert time windows 112.

[0025] The clocks of the followers are synchronized with the clock of the leader, and the transmissions between the leader and the followers are aligned with the time slots corresponding to the forward error correction (FEC) coded codewords, i.e., each time slot corresponds to the time required to send the FEC coded codeword. A time slot is sometimes referred to herein as an FEC frame.

[0026] The leader quiet / refresh cycle period 100 has a time duration of 96 FEC frames, ie, T=96 FEC frames. In other embodiments, the leader quiet / refresh cycle period 100 has another suitable time duration.

[0027] Each of the silent time window 108, the alarm time window 112, and the refresh time window 116 starts at a FEC frame boundary and ends at a FEC frame boundary. Each of the silent time window 108 and the alarm time window 112 has a time duration of four FEC frames. In other embodiments, each of the silent time window 108 and the alarm time window 112 has another suitable time duration. The refresh time window 116 has a time duration of one FEC frame. In other embodiments, the refresh time window 116 has another suitable time duration.

[0028] During the silent time window 108, the leader silences transmissions on the communication link and is allowed to shut down at least some of the transmitting circuitry to save power. Therefore, in some embodiments, the leader shuts down at least some of the transmitting circuitry to save power during the silent time window 108. Similarly, the follower ignores transmissions on the communication link during the silent time window 108 and is allowed to shut down at least some of the receiving circuitry to save power. Therefore, in some embodiments, the follower shuts down at least some of the receiving circuitry to save power during the silent time window 108.

[0029] During the alert time window 112, when the leader decides to remain in low power mode, the leader silences transmissions on the communication link and is allowed to shut down at least some of the transmit circuitry to save power. Thus, in some embodiments, when the leader decides to remain in low power mode, the leader shuts down at least some of the transmit circuitry to save power during the silent time window 108.

[0030] On the other hand, in response to the leader's decision to exit the low power mode, the leader controls the leader's transmitting circuit device to be powered on during the next occurring alarm time window 112, and transmits a signal during the next occurring alarm time window 112, which indicates to the follower that the leader is exiting the low power mode. For example, in one embodiment, the leader transmits an alarm signal during the next occurring alarm time window 112, which alerts the follower that the leader will soon send a wake-up signal, wherein the wake-up signal is a request to exit the low power mode. Therefore, according to one embodiment, the signal indicating to the follower that the leader is exiting the low power mode includes an alarm signal. In another embodiment, the leader transmits the wake-up signal during the next occurring alarm time window 112 without first transmitting the alarm signal, i.e., without performing transmission of the alarm signal, and the leader transmits the wake-up signal during the next occurring alarm time window 112 without first transmitting the alarm signal during the next occurring alarm time window 112. Therefore, according to one embodiment, the signal indicating to the follower that the leader is exiting the low power mode includes the wake-up signal and omits the alarm signal discussed above.

[0031] During the alert time window 112, the follower is prepared to receive a signal indicating that the leader is exiting the low power mode. Therefore, the follower controls the receiving circuit device to be powered on during the alert time window 112. In an embodiment in which the leader sends an alert signal before sending a wake-up signal, according to one embodiment, the follower device keeps the receiving circuit device powered on in anticipation of receiving the wake-up signal in response to receiving the alert signal in the alert time window 112. In response to receiving the wake-up signal, the follower device exits the low power mode.

[0032] In response to i) the follower not receiving a signal during the alert time window 112 indicating that the leader is exiting the low power mode, and ii) starting the following silent time window 108, the follower ignores transmissions on the communication link during the silent time window 108 and is allowed to shut down at least some receiving circuit devices to save power, as discussed above.

[0033] The leader quiet / refresh cycle period 100 begins with a quiet time window 108-1. Therefore, both the leader and the follower transition to the quiet time window 108-1 immediately after the transmission of the sleep signal 104 ends. Since the follower is in the quiet time window 108-1, any faults and / or transient signals on the communication link after the sleep signal 104 are ignored by the follower. Therefore, the follower does not inadvertently interpret the faults and / or transient signals on the communication link as a signal indicating that the leader is exiting the low power mode, thereby avoiding unpredictable behavior caused by such inadvertent interpretation of faults and / or transient signals.

[0034] The refresh time window 116 is located within the last occurring silent time window 108-48 of the leader silent / refresh cycle period 100. In one embodiment, the last occurring silent time window 108-48 includes the first occurring FEC frame, the last occurring FEC frame, and at least two intermediate occurring FEC frames that are temporally located between the first occurring FEC frame and the last occurring FEC frame, and the refresh time window 116 is included within the at least two intermediate occurring FEC frames. In an embodiment in which the last occurring silent time window 108-48 consists of four FEC frames, the refresh time window 116 is included within the third occurring FEC frame. In another embodiment in which the last occurring silent time window 108-48 consists of four FEC frames, the refresh time window 116 is included within the second occurring FEC frame. In another embodiment, the refresh time window 116 is included within the first occurring FEC frame.

[0035] In an embodiment where the quiet / refresh cycle period 100 has a length of 96 FEC frames, the refresh time window 116 corresponds to the 91st FEC frame that occurs within the quiet / refresh cycle period 100. In another embodiment where the quiet / refresh cycle period 100 has a length of 96 FEC frames, the refresh time window 116 corresponds to the 90th FEC frame that occurs within the quiet / refresh cycle period 100.

[0036] During the silent time window 108-48, the leader silences transmission on the communication link outside the refresh time window 116, and is allowed to shut down at least some transmitting circuit devices outside the refresh time window 116 to save power. Therefore, in some embodiments, the leader shuts down at least some transmitting circuit devices outside the refresh time window 116 during the silent time window 108-48 to save power. During the refresh time window 116, the leader controls the transmitting circuit devices to power on and sends a refresh signal to the follower so that the follower can maintain clock synchronization with the leader and adapt the follower's filter (e.g., equalization filter).

[0037] Similarly, the follower ignores transmissions on the communication link during the silent time window 108-48 outside the refresh time window 116, and is allowed to shut down at least some receiving circuit devices to save power outside the refresh time window 116. Therefore, in some embodiments, the follower shuts down at least some receiving circuit devices to save power during the silent time window 108-48 outside the refresh time window 116. During the refresh time window 116, the follower controls the receiving circuit devices to be powered on and uses the refresh signal from the leader to maintain clock synchronization with the leader and adapt the follower's filters (e.g., equalization filters).

[0038] At least one FEC frame of the silent time window 108-48 follows the refresh time window 116. Therefore, both the leader and the follower transition to at least one FEC frame of the silent time window 108-48 immediately after the transmission of the refresh signal ends. Since the follower is in the silent time window 108-48 after the transmission of the refresh signal ends, any faults and / or transient signals on the communication link after the refresh signal are ignored by the follower. Therefore, the follower does not inadvertently interpret faults and / or transient signals on the communication link as a signal indicating that the leader is exiting the low power mode, thereby avoiding unpredictable behavior caused by such inadvertent interpretation of faults and / or transient signals.

[0039] When the follower decides to transition the communication link from the follower to the leader to a low power mode, the follower sends a sleep signal to the leader (not shown), and the communication link from the follower to the leader enters a low power mode. The quiet / refresh cycle period 150 corresponds to the low power mode of the communication link from the follower to the leader. The quiet / refresh cycle period 150 is sometimes referred to herein as the "follower quiet / refresh cycle period 150".

[0040] The follower quiet / refresh cycle period 150 is similar to the leader quiet / refresh cycle period 100, but is offset in time from the leader quiet / refresh cycle period 100 by about T / 2. For example, according to one embodiment, the start of the follower quiet / refresh cycle period 150 is aligned with the end of the 48th occurring FEC frame in the leader quiet / refresh cycle period 100. In other embodiments, the follower quiet / refresh cycle period 150 is offset in time from the leader quiet / refresh cycle period 100 by another suitable time offset.

[0041] The follower quiet / refresh cycle period 150 includes quiet time windows 158, alarm time windows 162, and refresh time windows 176 that are ordered according to a time schedule. The quiet time windows 158 alternate in time with the alarm time windows 162. According to one embodiment, similar to the leader quiet / refresh cycle period 100, the refresh time window 176 occurs during the last occurring quiet time window 158-48.

[0042] Silent time window 158 is aligned and coincident in time with silent time window 108, and alert time window 162 is aligned and coincident in time with alert time window 112. Refresh time window 176 is offset in time by approximately T / 2 from refresh time window 116. For example, according to one embodiment, refresh time window 176 is offset in time by 48 FEC frames from refresh time window 116.

[0043] During the silent time window 158, the follower silences transmissions on the communication link and is allowed to shut down at least some of the transmitting circuitry to save power. Therefore, in some embodiments, the follower shuts down at least some of the transmitting circuitry to save power during the silent time window 158. Similarly, the leader ignores transmissions on the communication link during the silent time window 158 and is allowed to shut down at least some of the receiving circuitry to save power. Therefore, in some embodiments, the leader shuts down at least some of the receiving circuitry to save power during the silent time window 158.

[0044] During the alert time window 162, when the follower decides to remain in low power mode, the follower silences transmissions on the communication link and is allowed to shut down at least some of the transmitting circuitry to save power. Therefore, in some embodiments, when the follower decides to remain in low power mode, the follower shuts down at least some of the transmitting circuitry to save power during the silent time window 158.

[0045] On the other hand, in response to the follower's decision to exit the low power mode, the follower controls the leader's transmitting circuit device to be powered on during the next occurring alarm time window 162, and transmits a signal to the leader indicating that the follower is exiting the low power mode during the next occurring alarm time window 162. For example, in one embodiment, the follower transmits an alarm signal during the next occurring alarm time window 162, the alarm signal alerting the leader that the follower will soon send a wake-up signal, wherein the wake-up signal is a request to exit the low power mode. Therefore, according to one embodiment, the signal indicating to the leader that the follower is exiting the low power mode includes an alarm signal. In another embodiment, the follower transmits the wake-up signal during the next occurring alarm time window 162 without first transmitting the alarm signal, i.e., without performing transmission of the alarm signal, and the follower transmits the wake-up signal during the next occurring alarm time window 162 without first transmitting the alarm signal during the next occurring alarm time window 162. Therefore, according to one embodiment, the signal indicating that the follower is exiting the low power mode includes the wake-up signal and omits the alarm signal discussed above.

[0046] During the alert time window 162, the leader is prepared to receive a signal indicating that the follower is exiting the low power mode. Therefore, the leader controls the receiving circuit device to be powered on during the alert time window 162. In an embodiment in which the follower sends an alert signal before sending a wake-up signal, according to one embodiment, the leader keeps the receiving circuit device powered on in anticipation of receiving the wake-up signal in response to receiving the alert signal in the alert time window 162. In response to receiving the wake-up signal, the leader exits the low power mode.

[0047] In response to i) the leader not receiving a signal during the alert time window 162 indicating that the follower is exiting the low power mode, and ii) starting the follower silent time window 158, the leader ignores transmissions on the communication link during the silent time window 158 and is enabled to shut down at least some receiving circuit devices to save power, as discussed above.

[0048] Both the leader and the follower transition to the silent time window 158 immediately after the transmission of the sleep signal (not shown) ends. Since the leader is in the silent time window 158, the leader ignores any faults and / or transient signals on the communication link after the sleep signal. Therefore, the leader does not inadvertently interpret faults and / or transient signals on the communication link as a signal indicating that the follower is exiting the low power mode, thereby avoiding unpredictable behavior caused by such inadvertent interpretation of faults and / or transient signals.

[0049] The refresh time window 176 is located within the last occurring silent time window 158-48 of the follower silent / refresh cycle period 150. In one embodiment, the last occurring silent time window 158-48 includes the first occurring FEC frame, the last occurring FEC frame, and at least two intermediate occurring FEC frames that are temporally located between the first occurring FEC frame and the last occurring FEC frame, and the refresh time window 176 is included within the at least two intermediate occurring FEC frames. In an embodiment in which the last occurring silent time window 158-48 consists of four FEC frames, the refresh time window 176 is included within the third occurring FEC frame. In another embodiment in which the last occurring silent time window 158-48 consists of four FEC frames, the refresh time window 176 is included within the second occurring FEC frame. In another embodiment, the refresh time window 176 is included within the first occurring FEC frame.

[0050] During the silent time window 158-48, the follower silences transmission on the communication link outside the refresh time window 176, and is allowed to shut down at least some of the transmission circuit devices outside the refresh time window 176 to save power. Therefore, in some embodiments, the follower shuts down at least some of the transmission circuit devices during the silent time window 158-48 outside the refresh time window 176 to save power. During the refresh time window 176, the follower controls the transmission circuit device to power on and sends a refresh signal to the leader so that the follower can maintain clock synchronization with the leader and adapt the leader's filter (e.g., equalization filter).

[0051] Similarly, the leader ignores transmissions on the communication link during the silent time window 158-48 outside the refresh time window 176, and is allowed to shut down at least some receiving circuit devices to save power outside the refresh time window 176. Therefore, in some embodiments, the leader shuts down at least some receiving circuit devices to save power during the silent time window 158-48 outside the refresh time window 176. During the refresh time window 176, the leader controls the receiving circuit devices to power on and uses the refresh signal from the follower to adapt the leader's filter (e.g., equalization filter).

[0052] At least one FEC frame of the silent time window 158-48 follows the refresh time window 176. Therefore, both the leader and the follower transition to at least one FEC frame of the silent time window 158-48 immediately after the end of the transmission of the refresh signal. Since the leader is in the silent time window 158-48 after the end of the transmission of the refresh signal, any faults and / or transient signals on the communication link after the refresh signal are ignored by the leader. Therefore, the leader does not inadvertently interpret faults and / or transient signals on the communication link as a signal indicating that the follower is exiting the low power mode, thereby avoiding unpredictable behavior caused by such inadvertent interpretation of faults and / or transient signals.

[0053] In some embodiments, transmissions between leaders and followers are aligned with time slots corresponding to a group of multiple FEC frames, and such time slots are referred to herein as FEC superframes. Each group of multiple FEC frames includes a predetermined number of FEC frames. For example, according to one embodiment, each FEC superframe includes a group of eight FEC frames. In other embodiments, each FEC superframe includes another suitable number of FEC frames. In some embodiments, when data is being sent in normal transmission mode, data from multiple FEC codewords within the group of multiple FEC frames are interleaved within the FEC superframe.

[0054] In some embodiments, where transmissions between a leader and a follower are aligned with a FEC superframe, both the leader quiet / refresh period period 100 and the follower quiet / refresh period period 150 begin on a FEC superframe boundary.

[0055] Figure 2 is a timing diagram of the start of an example leader quiet / refresh cycle period schedule 200 for low power mode according to an embodiment. The end of the sleep signal is aligned with a FEC superframe boundary consisting of eight FEC frames, and the start of the leader quiet / refresh cycle period is aligned with a FEC superframe boundary.

[0056] The start of each quiet time window 108 is aligned in time with the start of the corresponding superframe, and the end of each alert time window 112 is aligned in time with the end of the corresponding superframe. Thus, in one embodiment, each superframe within the leader quiet / refresh period starts with a quiet time window 108 and ends with an alert time window 112.

[0057] In one embodiment, the time schedule of the corresponding follower quiet / refresh cycle period has a similar structure. For example, the start of the follower quiet / refresh cycle period is aligned in time with the FEC superframe boundary. In addition, the start of the follower quiet / quiet time window is aligned in time with the start of the corresponding superframe, and the end of each alert time window is aligned in time with the end of the corresponding superframe. Therefore, in one embodiment, each superframe within the follower quiet / refresh cycle starts with a quiet time window and ends with an alert time window.

[0058] In some embodiments, the start of the sleep signal and the end of the sleep signal are aligned with a FEC superframe boundary, and additionally or alternatively, the start of the wakeup signal and the end of the wakeup signal are aligned with a FEC superframe boundary.

[0059] Figure 3 3 is a timing diagram illustrating the transmission of a sleep signal 304, an alarm signal 308, and a wake-up signal 312 according to one embodiment. According to one embodiment, the sleep signal 304 has a duration of two FEC superframes. In other embodiments, the sleep signal 304 has another suitable duration. The start of the sleep signal 304 is aligned with the FEC superframe boundary, and the end of the sleep signal 304 is aligned with the FEC superframe boundary.

[0060] According to one embodiment, the alarm signal 308 has a duration of half of a FEC superframe (e.g., four FEC frames). In other embodiments, the alarm signal 308 has another suitable duration. The start of the alarm signal 308 is not aligned with a FEC superframe boundary and starts at the fifth occurring FEC frame within a FEC superframe. The end of the alarm signal 308 is aligned with a FEC superframe boundary.

[0061] According to one embodiment, the wake-up signal 312 has a duration of two FEC superframes. In other embodiments, the wake-up signal 312 has another suitable duration. The start of the wake-up signal 312 coincides with the end of the alarm signal 308. The start of the wake-up signal 312 is aligned with the FEC superframe boundary, and the end of the wake-up signal 312 is aligned with the FEC superframe boundary.

[0062] In one embodiment, the end of the sleep signal 304 and the start of the wake-up signal are separated in time by an integer number of FEC superframes. In one embodiment, the end of the sleep signal 304 and the start of the wake-up signal are separated in time by an integer number of FEC superframes of at least 1.

[0063] Figure 4 is a timing diagram illustrating the transmission of the sleep signal 304 and the wake-up signal 404 according to another embodiment. Figure 3 The embodiments are different. Figure 4In the embodiment of the present invention, the alarm signal is not sent before the wake-up signal. Instead, the wake-up signal 404 is sent without first sending the alarm signal.

[0064] The start of the wake-up signal 404 is not aligned with the FEC superframe boundary and starts at the fifth occurring FEC frame within the FEC superframe. According to one embodiment, the wake-up signal 404 has a duration of 2.5 FEC superframes. In other embodiments, the wake-up signal 404 has another suitable duration. The end of the wake-up signal 404 is aligned with the FEC superframe boundary.

[0065] In one embodiment, the end of the sleep signal 304 and the start of the wake-up signal 404 are separated in time by at least 0.5 FEC superframes plus 0, 1, 2, ... FEC superframes.

[0066] Figure 5 is a block diagram of an example network interface device 500 implementing the power saving techniques described above according to one embodiment. In some embodiments, the network interface device 500 is configured to operate as a leader. In other embodiments, the network interface device 500 is configured to operate as a leader. In some embodiments, the network interface device 500 can be reconfigured to operate as a leader in some scenarios and as a follower in other scenarios.

[0067] The network interface device 500 includes at least a media access control (MAC) processing device 510 and a physical layer (PHY) circuit device 520. In some embodiments, the MAC processing device 510 and the PHY circuit device 520 are configured to operate according to a communication protocol, such as the IEEE 802.3 Ethernet standard, a future iteration of the IEEE 802.3 Ethernet standard, or another suitable communication protocol.

[0068] The MAC processing device 510 is configured to perform MAC layer functions associated with a communication protocol, such as a communication protocol defined by the IEEE 802.3 Ethernet standard, a future iteration of the IEEE 802.3 Ethernet standard, or another suitable communication protocol. Similarly, the PHY circuit device 520 is configured to perform PHY functions associated with a communication protocol, such as a communication protocol defined by the IEEE 802.3 Ethernet standard, a future iteration of the IEEE 802.3 Ethernet standard, or another suitable communication protocol.

[0069] In one embodiment, the MAC processing device 510 includes a processor (not shown) and a memory (not shown) coupled to the processor, wherein the processor is configured to execute machine-readable instructions stored in the memory. In one embodiment, the memory stores machine-readable instructions that, when executed by the processor, cause the processor to perform MAC layer functions associated with a communication protocol (such as a communication protocol defined by the IEEE 802.3 Ethernet standard, a future iteration of the IEEE 802.3 Ethernet standard, or another suitable communication protocol).

[0070] In another embodiment, the MAC processing device 510 additionally or alternatively includes a hardware state machine (not shown) that is configured to perform MAC layer functions associated with a communication protocol (such as a communication protocol defined by the IEEE 802.3 Ethernet standard, a future iteration of the IEEE 802.3 Ethernet standard, or another suitable communication protocol).

[0071] The MAC processing device 510 is communicatively coupled to the PHY circuit device 520 via a communication interface 530, such as a 10 Gigabit Media Independent Interface (XGMII). In other embodiments, the MAC processing device 410 is communicatively coupled to the PHY processing device 520 via another suitable communication interface, such as a 10 Gigabit Attachment Unit Interface (XAUI), an XFI interface for a Small Form Factor Pluggable (XFP), an SFI interface for a Small Form Factor Pluggable Plus (SFP+), a Universal Serial Gigabit Media Independent Interface (USXGMII), a Reduced Media Independent Interface (RMII), a Gigabit Media Independent Interface (GMII), a Reduced Gigabit Media Independent Interface (RGMII), a Serial Gigabit Media Independent Interface (SGMII), a High Serial Gigabit Media Independent Interface (HSGMII), a Quad Serial Gigabit Media Independent Interface (QSGMII), etc., according to some embodiments.

[0072] In one embodiment, MAC processing device 510 provides data for transmission to PHY circuit device 520 via interface 530. In response to receiving data from MAC processing device 510, PHY circuit device 520 encodes, scrambles, and modulates the data to generate a transmission signal for sending the data via a suitable communication medium (such as a wired, optical, or wireless communication medium).

[0073] In one embodiment, the PHY circuit device 520 also receives a receive signal via the communication medium, and demodulates, descrambles, and decodes the data in the receive signal to generate receive data. In addition, the PHY circuit device 520 provides at least some of the receive data to the MAC processing device 510 via the interface 5430. In various embodiments, according to one embodiment, as part of generating the transmit signal, the PHY circuit device 520 includes one or more encoder devices (not shown), a scrambler device (not shown) for encoding and scrambling the data. According to one embodiment, as part of generating the receive data, the PHY circuit device 520 also includes a descrambler device (not shown) and one or more decoder devices (not shown) for descrambling and decoding the data.

[0074] PHY circuitry 520 includes physical medium attachment (PMA) sublayer circuitry 540 configured to perform PMA sublayer functions defined by the communication protocol. PMA sublayer circuitry 540 includes a transceiver 544 configured to transmit and receive signals via the communication medium.

[0075] According to one embodiment, as part of generating a transmit signal, the PMA sublayer circuit device 540 includes a modulator (not shown) that modulates data. According to one embodiment, as part of generating receive data, the PMA sublayer circuit device 540 also includes a demodulator (not shown) that demodulates information bits from the receive signal.

[0076] In some embodiments, the PMA sublayer circuit device 540 further includes an analog-to-digital converter (hereinafter “ADC”, not shown) that converts an analog signal received via the communication medium into a digital signal. In some embodiments, the PMA sublayer circuit device 440 further includes a digital-to-analog converter (hereinafter “DAC”, not shown) that converts a digital signal into an analog signal for transmission via the communication medium.

[0077] In some embodiments, the PHY circuit device 520 also includes a digital signal processing circuit device (hereinafter "DSP", not shown), which processes the digital signal to generate a signal corresponding to the modulation symbol, which is then demodulated by a demodulator (not shown). In some embodiments, at least some functions of the PMA sublayer circuit device 540 are performed by the DSP.

[0078] The PHY circuit device 520 includes a clock 550, which is used to determine the timing of the transmission operation and the reception operation. According to one embodiment, when operating as a leader, the clock 550 is a free running clock. According to one embodiment, when operating as a follower, the PHY circuit device 420 recovers the leader clock from the signal received from the leader via the communication medium and synchronizes the clock 550 to the leader clock.

[0079] The PHY circuit device 520 includes a sleep signal generator 554, which is configured to generate a sleep signal defined by the communication protocol. The sleep signal is configured to prompt the link partner to enter a low power operation mode as described above when it is sent to the link partner via the communication medium. For example, according to various embodiments, the sleep signal generator 554 generates Figure 1-Figure 2 The sleep signal 104 and / or Figure 3-Figure 4 The sleep signal 304 is received.

[0080] The PHY circuit device 520 also includes a wake-up signal generator 558, which is configured to generate a wake-up signal defined by the communication protocol. The wake-up signal is configured to prompt the link partner to exit the low power operation mode as described above when it is sent to the link partner via the communication medium. For example, according to various embodiments, the wake-up signal generator 558 generates Figure 3 The wake-up signal 312 and / or Figure 4 The wake-up signal 404. .

[0081] The PHY circuit device 520 also includes an alarm signal generator 562, which is configured to generate an alarm signal defined by the communication protocol. The alarm signal is configured to, when sent to the link partner via the communication medium, warn the link partner that a wake-up signal as described above will be sent. For example, according to one embodiment, the alarm signal generator 562 generates Figure 3 The alarm signal 308. In some embodiments, the alarm signal generator 562 is omitted.

[0082] The PHY circuit device 520 also includes a refresh signal generator 566, which is configured to generate a refresh signal defined by the communication protocol. The refresh signal is configured to, when sent to the link partner via the communication medium, facilitate the link partner to adapt the link partner's filter (e.g., equalization filter), and if the link partner is a follower, facilitate the follower to maintain clock synchronization with the leader.

[0083] The PHY circuit device 520 also includes a sleep signal detector 570, which is configured to detect a wake-up signal received from a link partner via the communication medium. The PHY circuit device 520 also includes a wake-up signal detector 574, which is configured to detect a wake-up signal received from a link partner via the communication medium. The PHY circuit device 520 also includes an alarm signal detector 578, which is configured to detect an alarm signal received from a link partner via the communication medium. In some embodiments, the alarm signal detector 578 is omitted.

[0084] The PHY circuit device 520 includes or is coupled to a low power mode controller 590, which is configured to control the operation of the PHY circuit device 520 according to the low power mode timing schedule and according to various operating states and / or modes, and to control transitions between operating states and / or modes. For example, according to one embodiment, the controller 590 is configured to respond to receiving a sleep signal and immediately after the sleep signal ends to transition to a mode in which the PHY circuit device 520 ignores any received signals during the silent period. As another example, according to one embodiment, the controller 590 is configured to immediately transition to a mode in which the PHY circuit device 520 silences transmissions for a period of time after sending the sleep signal, even if the controller 590 determines within the period that the PHY circuit device 520 will exit the low power mode.

[0085] As another example, according to one embodiment, the controller 590 is configured to immediately transition to a mode in which the PHY circuit device 520 ignores any received signals during the silent period at the end of the reception of the refresh signal. As another example, according to one embodiment, the controller 590 is configured to immediately transition to a mode in which the PHY circuit device 520 silences transmissions for a period of time after sending the refresh signal.

[0086] In one embodiment, controller 590 includes a hardware state machine, wherein at least some states of the hardware state machine generally correspond to at least some of the various operating states and / or modes of PHY circuitry 520. The hardware state machine is configured to generate control signals that control operation of PHY circuitry 520 according to the various operating states and / or modes, and to transition between states of the hardware state machine in response to received signals and / or according to a timing schedule.

[0087] In another embodiment, controller 590 includes a processor that executes machine-readable instructions that cause the processor to implement a state machine similar to the hardware state machine described above.

[0088] Figure 6 is a flow chart of an example method 600 for power conservation in a communication device including a network interface device according to one embodiment. According to one embodiment, the method 600 is composed of Figure 5 The network interface device 500 is implemented, and for ease of explanation, reference is made to Figure 5 Method 600 is described. In other embodiments, method 600 is implemented by another suitable network interface device. In addition, in some embodiments, network interface device 500 does not implement method 600 and / or implements another suitable power saving method different from method 600. In some embodiments, method 600 is related to the above referenced Figure 1-Figure 4and for ease of explanation, refer to the Quiet / Refresh Cycle Schedule described in any of Figure 1-Figure 4 Method 600 is described. In other embodiments, method 600 involves the same method as above with reference to Figure 1-Figure 4 The described quiet / refresh cycle timing schedules are different from the appropriate quiet / refresh cycle timing schedules.

[0089] At block 604, the network interface device is operated in a normal operation mode in which the network interface device continuously sends transmission symbols via the communication link. For example, the controller 590 controls the PHY circuit device 520 to operate in a normal operation mode in which the PHY circuit device 520 continuously sends transmission symbols via the communication link.

[0090] At block 608, the network interface determines that the network interface device will transition to a low power mode in which the network interface device will not transmit to save power. In one embodiment, the low power mode includes transmitting according to the quiet / refresh cycle 100 ( Figure 1 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 150 ( Figure 1 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 200 ( Figure 2 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 300 ( Figure 3 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 400 ( Figure 4 ) to operate. In one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a low power mode. For example, according to one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a low power mode in response to receiving a signal from the MAC processor 510 instructing the PHY circuit device 520 to transition to a low power mode. For example, the MAC processor 510 sends a signal to the PHY processor 520 via the communication interface 530, and the low power mode controller 590 interprets the signal as an instruction to transition to a low power mode. In various other embodiments, determining that the network interface device will transition to a low power mode is based on one or more of the following: i) determining that the network interface device has no data to send, ii) determining that the power consumption of the network interface device is to be reduced, and the like.

[0091] At block 612, in response to determining that the network interface device will transition to a low power mode at block 608, the network interface sends a sleep signal to the link partner. For example, the controller 590 controls the PHY circuit device 520 to send the sleep signal. In some embodiments, sending the sleep signal at block 612 includes sending the sleep signal as described above with reference to Figure 1-Figure 2In some embodiments, sending the sleep signal at block 612 includes sending the sleep signal as described above. Figure 3-Figure 4 In one embodiment, sending the sleep signal at block 612 includes ending transmission of the sleep signal at an FEC superframe boundary. In another embodiment, sending the sleep signal at block 612 includes starting transmission of the sleep signal at a first FEC superframe boundary and ending transmission of the sleep signal at a second FEC superframe boundary. In one embodiment, the sleep signal generator 554 generates the sleep signal.

[0092] At block 616, also in response to determining that the network interface device will transition to a low power mode at block 608 and associated with the end of transmission of the sleep signal at block 612, the network interface device operates according to a quiet / refresh period time schedule, the time schedule including i) a quiet time window immediately following the sleep signal and ii) a refresh time window. As an example, the controller 590 controls the PHY circuit device 520 to operate according to the quiet / refresh period time schedule. According to one embodiment, operating according to the quiet / refresh period at block 616 includes silencing transmission during the quiet time period and transmitting a refresh signal during the refresh time window. In one embodiment, the refresh signal generator 566 generates the refresh signal. Operating according to the quiet / refresh period time schedule at block 616 includes transitioning to a quiet window at a FEC superframe boundary coinciding with the end of transmission of the sleep signal at block 612.

[0093] In one embodiment, operating according to the quiet / refresh cycle schedule at block 616 includes operating according to the quiet / refresh cycle schedule, the schedule including i) a plurality of quiet time windows, and ii) a plurality of alert time windows, wherein the alert time windows alternate in time with the quiet time windows. According to one embodiment, the link partner maintains power on the receiving circuitry to be ready to receive a signal from the network interface device to exit the low power mode. Sending the refresh signal at block 616 includes sending the refresh signal during a refresh time window within a last occurring quiet time window in the schedule,

[0094] In one embodiment, the network interface device and the link partner are synchronized according to FEC frame time periods; the last occurring quiet time window corresponds to at least four FEC frame time periods, the at least four FEC frame time periods including a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; and sending the refresh signal at block 616 includes sending the refresh signal during a refresh time window that overlaps at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period. In one embodiment, the at least two intermediate occurring FEC frame time periods include a second occurring FEC frame time period and a third occurring FEC frame time period; the last occurring FEC frame time period is a fourth occurring FEC frame time period; and sending the refresh signal at block 616 includes sending the refresh signal during a refresh time window that overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period.

[0095] In some embodiments, operating according to the quiet / refresh cycle schedule at block 616 includes operating according to the above reference Figure 1 In other embodiments, operating according to the quiet / refresh cycle schedule at block 616 includes operating according to the above reference Figure 2 In other embodiments, operating according to the quiet / refresh cycle schedule at block 616 includes operating according to the above reference Figure 3 In other embodiments, operating according to the quiet / refresh cycle schedule at block 616 includes operating according to the above reference Figure 4 The quiet / refresh cycle described here operates.

[0096] Figure 7 is a flow chart of another example method 700 for power conservation in a communication device including a network interface device according to one embodiment. According to one embodiment, the method 700 is composed of Figure 5 The network interface device 500 is implemented, and for ease of explanation, reference is made to Figure 5 Method 700 is described. In other embodiments, method 700 is implemented by another suitable network interface device. In addition, in some embodiments, network interface device 500 does not implement method 700 and / or implements another suitable power saving method different from method 700. In some embodiments, method 700 is related to the above referenced Figure 1-Figure 4 and for ease of explanation, refer to the Quiet / Refresh Cycle Schedule described in any of Figure 1-Figure 4Method 700 is described. In other embodiments, method 700 involves the above reference Figure 1-Figure 4 The quiet / refresh cycle timing schedules described above are different from suitable quiet / refresh cycle timing schedules.

[0097] At block 704, the network interface device is operated in a normal operation mode in which the network interface device continuously receives transmission symbols from the link partner via the communication link. For example, the controller 590 controls the PHY circuit device 520 to operate in a normal operation mode in which the PHY circuit device 520 continuously receives transmission symbols from the link partner via the communication link.

[0098] At block 708, the network interface determines that the network interface device will transition to a low power mode in which the link partner does not transmit during the quiet period to save power. In one embodiment, the low power mode includes a quiet / refresh cycle 100 ( Figure 1 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 150 ( Figure 1 In another embodiment, the low power mode includes operating according to the quiet / refresh cycle 200 ( Figure 2 ) to operate. In another embodiment, the low power mode includes operating according to the quiet / refresh cycle period 300 ( Figure 3 ) to operate. In another embodiment, the low power mode includes operating according to the quiet / refresh cycle period 400 ( Figure 4 In one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a low power mode.

[0099] Determining at block 708 that the network interface device will transition to a low power mode includes determining that the network interface device will transition to a low power mode in response to receiving a sleep signal from a link partner. For example, according to one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a low power mode in response to the PHY circuit device 520 receiving a sleep signal from the link partner via a communication link. In one embodiment, the sleep signal detector 570 detects a sleep signal from the link partner and notifies the low power mode controller 590 that the sleep signal is detected; the low power mode controller 590 determines that the PHY circuit device 520 will transition to a low power mode in response to being notified by the sleep signal detector 570 that the sleep signal from the link partner is detected.

[0100] In some embodiments, receiving the sleep signal at block 708 includes receiving the sleep signal as described above. Figure 1-Figure 2 In some embodiments, receiving the sleep signal at block 708 includes receiving the sleep signal 104 described above with reference to Figure 3-Figure 4In one embodiment, receiving the sleep signal at block 708 includes receiving the sleep signal starting on an FEC superframe boundary. In another embodiment, receiving the sleep signal at block 708 includes receiving the sleep signal starting on a first FEC superframe boundary and ending on a second FEC superframe boundary.

[0101] At block 712, in response to determining that the network interface device will transition to a low power mode at block 708 and associated with the end of reception of the sleep signal, the network interface device operates according to a quiet / refresh cycle schedule, the schedule comprising i) a quiet time window immediately following the sleep signal and ii) a refresh time window. As an example, the controller 590 controls the PHY circuit device 520 to operate according to the quiet / refresh cycle schedule. According to one embodiment, operating according to the quiet / refresh cycle at block 712 includes ignoring transmissions from the link partner during the quiet time period and operating the receiving circuit device in a powered state during the refresh time window to receive the refresh signal during the refresh time window. According to one embodiment, operating according to the quiet / refresh cycle at block 712 includes powering off at least some of the receiving circuit devices during the quiet time period.

[0102] Operating according to the quiet / refresh period schedule at block 712 includes transitioning to a quiet window at an FEC superframe boundary coinciding with the end of transmission of the sleep signal at block 708 .

[0103] In one embodiment, according to one embodiment, operating according to the quiet / refresh cycle time schedule at block 712 includes operating according to the quiet / refresh cycle time schedule, the time schedule including i) a plurality of quiet time windows, and ii) a plurality of alert time windows, wherein the alert time windows alternate in time with the quiet time windows; ignoring transmissions from the link partner during the quiet time windows; and keeping the receiving circuit device powered on during the alert windows to be ready to receive a signal from the link partner to exit the low power mode. According to one embodiment, operating according to the quiet / refresh cycle time schedule at block 712 includes receiving a refresh signal during a refresh time window within the last occurring quiet time window in the time schedule, and immediately transitioning back to the remainder of the last occurring quiet time window after the reception of the refresh signal is terminated. According to one embodiment, operating according to the quiet / refresh cycle time schedule at block 712 includes receiving a refresh signal during a refresh time window within the last occurring quiet time window in the time schedule, and ignoring transmissions from the link partner during the remainder of the last occurring quiet time window immediately after the reception of the refresh signal is terminated. According to one embodiment, operating according to the silent / refresh cycle schedule at block 712 includes receiving a refresh signal during a refresh time window within a last occurring silent time window in the schedule, and controlling at least some receiving circuit devices to be in a powered-off state during a remainder of the last occurring silent time window immediately after the reception of the refresh signal is terminated.

[0104] In one embodiment, the network interface device and the link partner are synchronized according to FEC frame time periods; the last occurring quiet time window corresponds to at least four FEC frame time periods, the at least four FEC frame time periods including a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; and receiving the refresh signal at block 712 includes receiving the refresh signal during a refresh time window that overlaps at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period. In one embodiment, the at least two intermediate occurring FEC frame time periods include a second occurring FEC frame time period and a third occurring FEC frame time period; the last occurring FEC frame time period is a fourth occurring FEC frame time period; and receiving the refresh signal at block 712 includes receiving the refresh signal during a refresh time window that overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period.

[0105] According to one embodiment, operating according to the quiet / refresh period timing schedule at block 712 includes receiving a refresh signal during a third occurrence of the FEC frame time period and transitioning back to the remainder of the last occurrence of the quiet time window of the fourth occurrence of the FEC frame time period. According to one embodiment, operating according to the quiet / refresh period timing schedule at block 712 includes receiving a refresh signal during a third occurrence of the FEC frame time period and ignoring transmissions of the link partner during a fourth occurrence of the FEC frame time period. According to one embodiment, operating according to the quiet / refresh period timing schedule at block 712 includes receiving a refresh signal during a third occurrence of the FEC frame time period and controlling at least some of the receiving circuitry to be in a powered-off state during a fourth occurrence of the FEC frame time period.

[0106] In some embodiments, operating according to the quiet / refresh cycle schedule at block 712 includes operating according to the above reference Figure 1 In other embodiments, operating according to the quiet / refresh cycle schedule at block 712 includes operating according to the above reference Figure 2 In other embodiments, operating according to the quiet / refresh cycle schedule at block 712 includes operating according to the above reference Figure 3 In other embodiments, operating according to the quiet / refresh cycle schedule at block 712 includes operating according to the above reference Figure 4 The quiet / refresh cycle described here operates.

[0107] Figure 8 is a flow chart of another example method 800 for power conservation in a communication device including a network interface device according to another embodiment. According to one embodiment, the method 800 is composed of Figure 5 The network interface device 500 is implemented, and for ease of explanation, reference is made to Figure 5 Method 800 is described. In other embodiments, method 800 is implemented by another suitable network interface device. In addition, in some embodiments, network interface device 500 does not implement method 800 and / or implements another suitable power saving method different from method 800. In some embodiments, method 800 is related to the above referenced Figure 1-Figure 4 and for ease of explanation, refer to the Quiet / Refresh Cycle Schedule described in any of Figure 1-Figure 4 Method 800 is described. In other embodiments, method 800 involves the above reference Figure 1-Figure 4 The quiet / refresh cycle timing schedules described above are different from suitable quiet / refresh cycle timing schedules.

[0108] Method 800 includes Figure 6 For example, method 800 includes method flow blocks 604, 608, and 612, and for the sake of brevity, these elements will not be described in detail. Figure 6 Method flow block 616 in is replaced by method flow block 816, and additional method flow blocks 820, 824 and 828 related to transitioning back to normal operating mode are added.

[0109] At block 816, also in response to determining that the network interface device will transition to a low power mode at block 608 and associated with the end of transmission of the sleep signal at block 612, the network interface device operates according to a quiet / refresh period time schedule, the time schedule including i) a quiet time window immediately following the sleep signal and ii) a refresh time window. As an example, the controller 590 controls the PHY circuit device 520 to operate according to the quiet / refresh period time schedule. According to one embodiment, operating according to the quiet / refresh period at block 816 includes silencing transmission during the quiet time period, and if the power saving mode is still in the refresh time window, sending a refresh signal during the refresh time window. According to one embodiment, operating according to the quiet / refresh period time schedule at block 816 includes transitioning to a quiet window at an FEC superframe boundary coinciding with the end of transmission of the sleep signal at block 612.

[0110] In one embodiment, operating according to the quiet / refresh cycle schedule at block 816 includes operating according to a quiet / refresh cycle schedule that includes i) a plurality of quiet time windows, and ii) a plurality of alert time windows, wherein the alert time windows alternate in time with the quiet time windows. According to one embodiment, the link partner keeps the receiving circuitry powered on during the alert windows to be ready to receive a signal from the network interface device associated with exiting the low power mode.

[0111] At block 820, the network interface determines that the network interface device will transition to a normal operating mode. In one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a normal operating mode. For example, according to one embodiment, the low power mode controller 590 determines that the PHY circuit device 520 will transition to a normal operating mode in response to receiving a signal from the MAC processor 510 instructing the PHY circuit device 520 to transition to a normal operating mode. For example, the MAC processor 510 sends a signal to the PHY processor 520 via the communication interface 530, and the low power mode controller 590 interprets the signal as an instruction to transition to a normal operating mode. In various other embodiments, determining that the network interface device transitions to a normal operating mode is based on one or more of the following: i) determining that the network interface device has data to send, ii) determining that the power consumption of the network interface device can be increased, and the like.

[0112] In some embodiments, determining at block 820 that the network interface device is transitioning to the normal operating mode includes determining that the network device is to transition to the normal operating mode when the sleep signal is sent at block 612 .

[0113] At block 824, in response to determining that the network interface device will transition to the normal operation mode at block 820, the network interface sends an alarm signal to the link partner during the alarm window. For example, the controller 590 controls the PHY circuit device 520 to send the alarm signal. In some embodiments, sending the alarm signal at block 824 includes sending the alarm signal as described above. Figure 1-Figure 2 In some embodiments, sending the alarm signal at block 824 includes sending the alarm signal described above. Figure 3 The alarm signal 308 described above. In one embodiment, sending the alarm signal at block 824 includes ending transmission of the alarm signal at an FEC superframe boundary. In another embodiment, sending the alarm signal at block 824 includes starting transmission of the alarm signal at the fourth occurring FEC frame within the FEC superframe and ending transmission of the alarm signal at an ending boundary of the FEC superframe. In one embodiment, the alarm signal generator 562 generates the alarm signal.

[0114] At block 828, in response to determining that the network interface device will transition to the normal operation mode at block 820 and after sending the alarm signal at block 824, the network interface sends a wake-up signal to the link partner to instruct the link partner to exit the low power mode. For example, the controller 590 controls the PHY circuit device 520 to send the wake-up signal. In some embodiments, sending the wake-up signal at block 828 includes sending the above referenced Figure 1-Figure 2 In some embodiments, sending the wake-up signal at block 828 includes sending the wake-up signal described above. Figure 3In one embodiment, sending the wake-up signal at block 828 includes ending transmission of the wake-up signal at an FEC superframe boundary. In another embodiment, sending the wake-up signal at block 828 includes starting transmission of the wake-up signal at a first FEC superframe boundary and ending transmission of the wake-up signal at a second FEC superframe boundary. In one embodiment, the wake-up signal generator 558 generates the wake-up signal.

[0115] In some embodiments, if the network interface device determines that the network device will transition to a normal operating mode when sending the sleep signal at block 612, the network interface device: continues to transition to a low power mode at block 820, sends an alarm signal at the first occurring alarm window at block 824, and sends a wake-up signal at block 828. In some such embodiments, the end of transmission of the sleep signal is required to occur at a first FEC superframe boundary; and sending the wake-up signal at block 828 includes starting transmission of the wake-up signal at a second FEC superframe boundary and ending transmission of the wake-up signal at a third FEC superframe boundary.

[0116] In some embodiments, sending the alarm signal at block 824 is omitted; and sending the wake-up signal at block 828 after sending the alarm signal is not performed. For example, sending the wake-up signal at block 828 is performed according to the above reference Figure 4 was implemented based on the discussion.

[0117] The method 800 also includes the network interface device transitioning to the normal operation mode after sending the wake-up signal at block 828. For example, the controller 590 controls the PHY circuit device 520 to transition to the normal operation mode.

[0118] Fig. 9 is a flow chart of another example method 900 for saving power in a communication device including a network interface device according to another embodiment. According to one embodiment, the method 900 is Figure 5 The network interface device 500 is implemented, and for ease of explanation, reference is made to Figure 5 Method 900 is described. In other embodiments, method 900 is implemented by another suitable network interface device. In addition, in some embodiments, network interface device 500 does not implement method 900 and / or implements another suitable power saving method different from method 900. In some embodiments, method 900 is related to the above referenced Figure 1-Figure 4 and for ease of explanation, refer to the Quiet / Refresh Cycle Schedule described in any of Figure 1-Figure 4 Method 900 is described. In other embodiments, method 900 involves the above reference Figure 1-Figure 4 The quiet / refresh cycle timing schedules described above are different from suitable quiet / refresh cycle timing schedules.

[0119] Method 900 includes Figure 7 For example, method 900 includes method flow blocks 704 and 708, and for the sake of brevity, these elements will not be described in detail. Figure 7 Method flow block 712 is replaced by method flow block 912, and additional method flow blocks 916, 920 and 924 related to transitioning back to normal operating mode are added.

[0120] At block 912, in response to determining that the network interface device will transition to a low power mode at block 708 and associated with the end of receiving the sleep signal, the network interface device operates according to a quiet / refresh period schedule, the schedule including i) a quiet time window immediately following the sleep signal and ii) a refresh time window. As an example, the controller 590 controls the PHY circuit device 520 to operate according to the quiet / refresh period schedule. According to one embodiment, operating according to the quiet / refresh period at block 912 includes ignoring transmissions from the link partner during the quiet time period, and if still in the power saving mode when the refresh time window occurs, controlling the receiving circuit device to power on to receive the refresh signal during the refresh time window. According to one embodiment, operating according to the quiet / refresh period schedule at block 912 includes transitioning to the quiet window at the FEC superframe boundary coinciding with the end of receiving the sleep signal.

[0121] In one embodiment, operating according to the quiet / refresh cycle schedule at block 912 includes operating according to the quiet / refresh cycle schedule, the schedule comprising i) a plurality of quiet time windows, and ii) a plurality of alarm time windows, wherein the alarm time windows alternate in time with the quiet time windows. According to one embodiment, the network interface device keeps the receiving circuitry powered on during the alarm windows to be ready to receive a signal from the network interface device associated with exiting the low power mode.

[0122] At block 916, the network interface device controls the receiving circuit device to be powered on during the alarm window and receives the alarm signal during the alarm window. For example, the controller 590 controls the PHY circuit device 520 to be powered on during the alarm time window, and the alarm signal detector 578 detects the alarm signal during the alarm time window. In some embodiments, receiving the alarm signal at block 916 includes receiving the alarm signal described above with reference to Figure 1-Figure 2 In some embodiments, receiving the alarm signal at block 916 includes receiving the alarm signal described above. Figure 3308 described above. In one embodiment, receiving the alarm signal at block 916 includes receiving the alarm signal ending in relation to an FEC superframe boundary. In another embodiment, receiving the alarm signal at block 916 includes controlling the receiving circuitry of the network interface device to be powered on beginning during a fourth occurring FEC frame within the FEC superframe.

[0123] At block 920, in response to receiving the alarm signal at block 916, the network interface device controls the receiving circuit device to remain powered on after the alarm window in anticipation of receiving the wake-up signal, and the network interface device receives the wake-up signal after receiving the alarm signal at block 916. For example, the controller 590 controls the PHY circuit device 520 to be powered on during the alarm time window, and the alarm signal detector 578 detects the alarm signal during the alarm time window. In some embodiments, receiving the wake-up signal at block 920 includes receiving the above referenced Figure 1-Figure 2 In some embodiments, receiving the wake-up signal at block 920 includes receiving the wake-up signal described above. Figure 3 The wake-up signal 312 described above. In one embodiment, receiving the wake-up signal at block 920 includes ending the reception of the wake-up signal in relation to an FEC superframe boundary. In another embodiment, receiving the wake-up signal at block 828 includes starting the reception of the wake-up signal on a first FEC superframe boundary and ending the reception of the wake-up signal on a second FEC superframe boundary.

[0124] In some embodiments, receiving the alarm signal at block 916 is omitted; and receiving the wake-up signal at block 920 after receiving the alarm signal is not performed. For example, receiving the wake-up signal at block 920 is as described above with reference to Figure 4 was implemented based on the discussion.

[0125] At block 924, the network interface device transitions to the normal operation mode in response to receiving the wake-up signal at block 920. For example, the controller 590 controls the PHY circuit device 520 to transition to the normal operation mode in response to receiving the wake-up signal.

[0126] Embodiment 1: A network interface device, comprising: a physical layer (PHY) circuit device including a transceiver, the PHY processor configured to perform PHY functions associated with a communication link; and a controller. The controller is configured to: operate the PHY circuit device in a normal receive operation mode in which the PHY circuit device continuously receives transmission symbols from a link partner via a communication link; determine that a receive circuit device of the PHY circuit device is to transition to a low power mode in response to receiving a sleep signal from the link partner; and in response to determining that the receive circuit device is to transition to the low power mode and after receiving the sleep signal, control the PHY circuit device to operate according to a quiet / refresh cycle of the low power mode to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window, within which the receive circuit device of the PHY circuit device is to be powered on to receive the refresh signal from the link partner to facilitate keeping the receive circuit device of the PHY circuit device synchronized with the link partner, including controlling the PHY circuit device to transition to a quiet time window of the schedule immediately after transmission of the sleep signal, within which the PHY circuit device ignores transmissions from the link partner.

[0127] Embodiment 2: A network device according to embodiment 1, wherein: the refresh time window is located within the last occurring silent time window in the time schedule; and the controller is configured to control the PHY circuit device to be powered on to receive a refresh signal during the refresh time window within the last occurring silent time window, and ignore transmission from the link partner during the remaining time after the refresh time window of the last occurring silent time window.

[0128] Embodiment 3: A network device according to embodiment 2, wherein: the PHY circuit device is configured to synchronize with the link partner according to a forward error correction (FEC) frame time period; the last occurring silent time window corresponds to at least four FEC frame time periods, and the at least four FEC frame time periods include a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; the refresh time window overlaps with at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period; and the controller is configured to control the PHY circuit device to: be powered on to receive a refresh signal during at least one of the at least two intermediate occurring FEC frame time periods, and ignore transmissions from the link partner during the last occurring FEC frame time period.

[0129] Embodiment 4: A network device according to embodiment 3, wherein: at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; the last FEC frame time period is a fourth FEC frame time period; the refresh time window overlaps with the third FEC frame time period, does not overlap with the second FEC frame time period, and does not overlap with the fourth FEC frame time period; and the controller is configured to control the PHY circuit device to: power on the receiving circuit device to receive a refresh signal during the third FEC frame time period, and ignore the transmission from the link partner during the fourth FEC frame time period.

[0130] Embodiment 5: A network device according to any one of embodiments 1-4, wherein: the PHY circuit device is configured to synchronize with the link partner according to a forward error correction (FEC) superframe time period, each FEC superframe time period corresponds to a predetermined number of FEC frame time periods; and the controller is configured to control the PHY circuit device to transition to a silent time window at a FEC superframe boundary coinciding with the end of reception of a sleep signal.

[0131] Embodiment 6: A method for power saving with respect to a communication link, the method comprising: operating a network interface device in a normal transmission operation mode, in which the network interface device continuously receives transmission symbols from a link partner via the communication link; at the network interface device, determining that a receiving circuit device of the network interface device will transition to a low power mode in response to receiving a sleep signal from the link partner; in response to determining that the receiving circuit device will transition to the low power mode and after receiving the sleep signal, operating the network interface device according to a quiet / refresh cycle of the low power mode to save power, the quiet / refresh cycle corresponding to a time schedule, the time schedule including a refresh time window, within which the receiving circuit device of the network interface device will be powered on to receive a refresh signal from the link partner to facilitate keeping the receiving circuit device of the network interface device synchronized with the link partner, including transitioning the network interface device to a quiet time window of the time schedule immediately after transmission of the sleep signal, within which the network interface device ignores transmissions from the link partner.

[0132] Embodiment 7: A method for power saving according to embodiment 6, wherein: the refresh time window is within the last occurring silent time window in the time schedule; and the method further comprises: during the refresh time window within the last occurring silent time window, powering on the receiving circuit device to receive a refresh signal, and ignoring transmissions from the link partner during the remaining time after the refresh time window of the last occurring silent time window.

[0133] Embodiment 8: The method for power saving according to embodiment 7 further includes: a network interface device controls reception via a communication link according to a forward error correction (FEC) frame time period; wherein a last occurring silent time window corresponds to at least four FEC frame time periods, the at least four FEC frame time periods including a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; wherein a refresh time window overlaps with at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period; and wherein the method further includes: powering a receiving circuit device to receive a refresh signal during at least one of the at least two intermediate occurring FEC frame time periods, and the network interface device ignores transmissions from a link partner during a last occurring FEC frame time period.

[0134] Embodiment 9: A method for power saving according to embodiment 8, wherein: at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; the last FEC frame time period is a fourth FEC frame time period; the refresh time window overlaps with the third FEC frame time period, does not overlap with the second FEC frame time period, and does not overlap with the fourth FEC frame time period; and the method further includes: powering on the receiving circuit device to receive a refresh signal during the third FEC frame time period, and ignoring the transmission from the link partner by the network interface device during the fourth FEC frame time period.

[0135] Embodiment 10: The method for power saving according to any one of Embodiments 6-9 further includes: a network interface device controlling reception via a communication link according to a forward error correction (FEC) superframe time period, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; and the network interface device transitioning to a silent time window at a FEC superframe boundary coinciding with the end of reception of a sleep signal.

[0136] Embodiment 11: A network interface device, comprising: a physical layer (PHY) circuit device including a transceiver, a PHY processor configured to perform PHY functions associated with a communication link; and a controller. The controller is configured to: operate the PHY circuit device in a normal transmit operation mode in which the PHY circuit device continuously transmits transmission symbols to a link partner via a communication link; determine that a transmit circuit device of the PHY circuit device is to transition to a low power mode; in response to determining that the transmit circuit device is to transition to the low power mode, send a sleep signal to the link partner via the communication link to prompt the link partner to enter the low power mode; and in response to determining that the transmit circuit device is to transition to the low power mode and after sending the sleep signal, control the PHY circuit device to operate according to a quiet / refresh cycle to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window during which the PHY circuit device will send a refresh signal to the link partner to facilitate maintaining synchronization of the link partner's receive circuit device with the PHY circuit device, including controlling the PHY circuit device to transition to a quiet time window of the schedule immediately after transmission of the sleep signal, during which the PHY circuit device silences transmissions to the link partner.

[0137] Embodiment 12: A network device according to embodiment 11, wherein: the refresh time window is located within the last occurring silent time window in the time schedule; and the controller is configured to control the PHY circuit device to send a refresh signal during the refresh time window within the last occurring silent time window.

[0138] Embodiment 13: A network device according to embodiment 12, wherein: the PHY circuit device is configured to synchronize with the link partner according to a forward error correction (FEC) frame time period; the last occurring silent time window corresponds to at least four FEC frame time periods, including the first occurring FEC frame time period, the last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; the refresh time window overlaps with at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period; and the controller is configured to control the PHY circuit device to send a refresh signal during at least one of the at least two intermediate occurring FEC frame time periods.

[0139] Embodiment 14: A network device according to Embodiment 13, wherein: at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; the last FEC frame time period is a fourth FEC frame time period; the refresh time window overlaps with the third FEC frame time period, does not overlap with the second FEC frame time period, and does not overlap with the fourth FEC frame time period; and the controller is configured to control the PHY circuit device to send a refresh signal during the third FEC frame time period.

[0140] Embodiment 15: A network device according to any one of embodiments 11-14, wherein: the PHY circuit device is configured to synchronize with the link partner according to a forward error correction (FEC) superframe time period, each FEC superframe time period corresponds to a predetermined number of FEC frame time periods; and the controller is configured to control the PHY circuit device to: control the PHY to end the transmission of the sleep signal at the FEC superframe boundary, and transition to the silent time window at the FEC superframe boundary.

[0141] Embodiment 16: A method for power saving with respect to a communication link, the method comprising: operating a network interface device in a normal transmission operation mode, in which the network interface device continuously transmits transmission symbols to a link partner via a communication link; determining at the network interface device that a transmission circuit device of the network interface device will transition to a low power mode; in response to determining that the transmission circuit device will transition to a low power mode; sending a sleep signal by the network interface device to the link partner via the communication link to prompt the link partner to enter the low power mode; and in response to determining that the transmission circuit device will transition to the low power mode and after sending the sleep signal, operating the network interface device according to a quiet / refresh cycle to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window, within which the network interface device will send a refresh signal to the link partner to facilitate keeping the link partner's receiving circuit device synchronized with the network interface device, including immediately transitioning the network interface device to a quiet time window of the schedule after transmission of the sleep signal, within which the transmission circuit device silences transmissions to the link partner.

[0142] Embodiment 17: A method for power saving according to embodiment 16, wherein: the refresh time window is located within the last occurring silent time window in the time schedule; and the method further comprises the network interface device sending a refresh signal during the refresh time window within the last occurring silent time window.

[0143] Embodiment 18: The method for power saving according to embodiment 17 further includes: a network interface device controls transmission via a communication link according to a forward error correction (FEC) frame time period; wherein a last occurring silent time window corresponds to at least four FEC frame time periods, the at least four FEC frame time periods including a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; wherein a refresh time window overlaps with at least one of the at least two intermediate occurring FEC frame time periods, does not overlap with the first occurring FEC frame time period, and does not overlap with the last occurring FEC frame time period; and wherein the method further includes the network interface device sending a refresh signal during at least one of the at least two intermediate occurring FEC frame time periods.

[0144] Embodiment 19: A method for power saving according to embodiment 18, wherein: at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; the last FEC frame time period is the fourth FEC frame time period; the refresh time window overlaps with the third FEC frame time period, does not overlap with the second FEC frame time period, and does not overlap with the fourth FEC frame time period; and the method also includes sending a refresh signal by the network interface device during the third FEC frame time period.

[0145] Embodiment 20: The method for power saving according to any one of Embodiments 16-19 further includes: a network interface device controlling transmission via a communication link according to a forward error correction (FEC) superframe time period, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; the network interface device ending transmission of a sleep signal at an FEC superframe boundary; and the network interface device transitioning to a silent time window at the FEC superframe boundary.

[0146] At least some of the various blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any computer-readable memory coupled to the processor, such as RAM, ROM, flash memory, etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions.

[0147] When implemented in hardware, the hardware may include one or more discrete components, integrated circuit devices, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0148] Although the present invention has been described with reference to specific examples, these examples are intended to be illustrative only and not limiting, and modifications, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the present invention.

Claims

1. A network interface device, comprising: a physical layer (PHY) circuit arrangement including a transceiver, the PHY processor being configured to perform PHY functions associated with a communication link; as well as The controller is configured as: operating the PHY circuitry in a normal receive mode of operation in which the PHY circuitry continuously receives transmission symbols from a link partner via the communication link, determining that the receiving circuitry of the PHY circuitry is to transition to a low power mode in response to receiving a sleep signal from the link partner, and In response to determining that the receiving circuit device is to transition to the low power mode and after receiving the sleep signal, controlling the PHY circuit device to operate according to a quiet / refresh cycle of the low power mode to save power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window, within which the receiving circuit device of the PHY circuit device is powered to receive the refresh signal from the link partner to facilitate maintaining the receiving circuit device of the PHY circuit device synchronized with the link partner, including controlling the PHY circuit device to transition to a quiet time window of the schedule immediately after transmission of the sleep signal, during which the PHY circuit device ignores transmissions from the link partner.

2. The network device according to claim 1, wherein: The refresh time window is located within the last occurring silent time window in the time schedule; as well as The controller is configured to control the PHY circuit device to be powered on to receive the refresh signal during the refresh time window within the last occurring silent time window and ignore transmission from the link partner during a remaining time after the refresh time window of the last occurring silent time window.

3. The network device according to claim 2, wherein: The PHY circuitry is configured to synchronize with the link partner according to a forward error correction (FEC) frame period; The last occurring silent time window corresponds to at least four FEC frame time periods, wherein the at least four FEC frame time periods include a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; The refresh time window overlaps with at least one of the at least two intermediate FEC frame time periods, does not overlap with the first FEC frame time period, and does not overlap with the last FEC frame time period; and The controller is configured to control the PHY circuit device to: is powered on to receive the refresh signal during the at least one of the at least two intervening FEC frame time periods, and During the last occurring FEC frame period, transmissions from the link partner are ignored.

4. The network device according to claim 3, wherein: The at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; The last occurring FEC frame time period is the fourth occurring FEC frame time period; The refresh time window overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period; and The controller is configured to control the PHY circuit device to: During the third occurring FEC frame period, energizing the receiving circuit means to receive the refresh signal, and During the fourth occurring FEC frame period, transmissions from the link partner are ignored.

5. The network device according to claim 1, wherein: The PHY circuit arrangement is configured to synchronize with the link partner according to forward error correction (FEC) superframe time periods, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; as well as The controller is configured to control the PHY circuit device to transition to the silent time window at an FEC superframe boundary coinciding with an end of reception of the sleep signal.

6. A method for power conservation with respect to a communication link, the method comprising: operating the network interface device in a normal transmit mode of operation in which the network interface device continuously receives transmission symbols from a link partner via the communications link; at the network interface device, determining, in response to receiving a sleep signal from the link partner, that receive circuitry of the network interface device is to transition to a low power mode; In response to determining that the receiving circuitry is to transition to the low power mode and after receiving the sleep signal, operating the network interface device according to a quiet / refresh period of the low power mode to conserve power, the quiet / refresh period corresponding to a schedule, the schedule including a refresh time window within which the receiving circuitry of the network interface device is powered on to receive the refresh signal from the link partner to facilitate maintaining synchronization of the receiving circuitry of the network interface device with the link partner, including immediately following transmission of the sleep signal, transitioning the network interface device to a quiet time window of the schedule within which the network interface device ignores transmissions from the link partner.

7. The method for power saving according to claim 6, wherein: The refresh time window is located within the last occurring silent time window in the time schedule; as well as The method further comprises: During the refresh time window within the last occurring quiet time window, energizing the receiving circuit means to receive the refresh signal, and During a remaining time after the refresh time window of the last occurring silence time window, transmissions from the link partner are ignored.

8. The method for power saving according to claim 7, further comprising: controlling, by the network interface device, reception via the communication link according to a forward error correction (FEC) frame period; wherein the last occurring silent time window corresponds to at least four FEC frame time periods, and the at least four FEC frame time periods include a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; wherein the refresh time window overlaps with at least one of the at least two intermediate FEC frame time periods, does not overlap with the first FEC frame time period, and does not overlap with the last FEC frame time period; as well as The method further comprises: energizing the receiving circuitry to receive the refresh signal during the at least one of the at least two intervening FEC frame time periods, and Transmissions from the link partner during the last occurring FEC frame time period are ignored by the network interface device.

9. The method for power saving according to claim 8, wherein: The at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; The last occurring FEC frame time period is the fourth occurring FEC frame time period; The refresh time window overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period; as well as The method further comprises: During the third occurring FEC frame period, energizing the receiving circuit means to receive the refresh signal, and Transmissions from the link partner are ignored by the network interface device during the fourth occurring FEC frame time period.

10. The method for power saving according to claim 6, further comprising: controlling, by the network interface device, reception via the communication link according to forward error correction (FEC) superframe time periods, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; as well as The network interface device transitions to the silent time window at an FEC superframe boundary coinciding with an end of reception of the sleep signal.

11. A network interface device, comprising: a physical layer (PHY) circuit arrangement comprising a transceiver, the PHY processor being configured to perform PHY functions associated with a communication link; as well as The controller is configured as: operating the PHY circuitry in a normal transmit mode of operation in which the PHY circuitry continuously transmits transmission symbols to a link partner via the communication link, determining that the transmit circuitry of the PHY circuitry is to transition to a low power mode, In response to determining that the transmitting circuit device will transition to the low power mode, sending a sleep signal to the link partner via the communication link to prompt the link partner to enter the low power mode, and In response to determining that the transmitting circuit device is to transition to the low power mode and after transmitting the sleep signal, controlling the PHY circuit device to operate according to a quiet / refresh cycle to save power, the quiet / refresh cycle corresponding to a time schedule, the time schedule including a refresh time window, within which the PHY circuit device is to send a refresh signal to the link partner to facilitate maintaining synchronization between the receiving circuit device of the link partner and the PHY circuit device, including controlling the PHY circuit device to transition to a quiet time window of the time schedule immediately after transmission of the sleep signal, within which the PHY circuit device silences transmissions to the link partner.

12. The network device according to claim 11, wherein: The refresh time window is located within the last occurring silent time window in the time schedule; as well as The controller is configured to control the PHY circuit device to send the refresh signal during the refresh time window within the last occurring silent time window.

13. The network device according to claim 12, wherein: The PHY circuitry is configured to synchronize with the link partner according to a forward error correction (FEC) frame period; The last occurring silent time window corresponds to at least four FEC frame time periods, wherein the at least four FEC frame time periods include a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; The refresh time window overlaps with at least one of the at least two intermediate FEC frame time periods, does not overlap with the first FEC frame time period, and does not overlap with the last FEC frame time period; as well as The controller is configured to control the PHY circuitry to transmit the refresh signal during the at least one intervening FEC frame period of the at least two intervening FEC frame periods.

14. The network device according to claim 13, wherein: The at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; The last occurring FEC frame time period is the fourth occurring FEC frame time period; The refresh time window overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period; and The controller is configured to control the PHY circuit device to send the refresh signal during the third occurring FEC frame time period.

15. The network device according to claim 11, wherein: The PHY circuitry is configured to synchronize with the link partner according to forward error correction (FEC) superframe time periods, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; and The controller is configured to control the PHY circuit device to: controlling the PHY to end transmission of the sleep signal at an FEC superframe boundary, and A transition to the silence time window is made at the FEC superframe boundary.

16. A method for power conservation with respect to a communication link, the method comprising: operating the network interface device in a normal transmit mode of operation in which the network interface device continuously transmits transmission symbols to a link partner via the communications link; determining, at the network interface device, that transmit circuitry of the network interface device is to transition to a low power mode; In response to determining that the transmitting circuit device will transition to the low power mode; the network interface device sends a sleep signal to the link partner via the communication link to prompt the link partner to enter the low power mode; and In response to determining that the transmitting circuit device is to transition to the low power mode and after transmitting the sleep signal, operating the network interface device according to a quiet / refresh cycle to conserve power, the quiet / refresh cycle corresponding to a schedule, the schedule including a refresh time window within which the network interface device is to transmit a refresh signal to the link partner to facilitate maintaining synchronization between the receiving circuit device of the link partner and the network interface device, including immediately following transmission of the sleep signal, transitioning the network interface device to a quiet time window of the schedule within which the transmitting circuit device silences transmissions to the link partner.

17. The method for power saving according to claim 16, wherein: The refresh time window is located within the last occurring silent time window in the time schedule; and The method also includes sending, by the network interface device, the refresh signal during the refresh time window within the last occurring silence time window.

18. The method for power saving according to claim 17, further comprising: controlling, by the network interface device, transmission via the communication link according to a forward error correction (FEC) frame time period; wherein the last occurring silent time window corresponds to at least four FEC frame time periods, and the at least four FEC frame time periods include a first occurring FEC frame time period, a last occurring FEC frame time period, and at least two intermediate occurring FEC frame time periods; wherein the refresh time window overlaps with at least one of the at least two intermediate FEC frame time periods, does not overlap with the first FEC frame time period, and does not overlap with the last FEC frame time period; and The method further comprises sending, by the network interface device, the refresh signal during the at least one of the at least two intervening FEC frame time periods.

19. The method for power conservation according to claim 18, wherein: The at least two intermediate FEC frame time periods include a second FEC frame time period and a third FEC frame time period; The last occurring FEC frame time period is the fourth occurring FEC frame time period; The refresh time window overlaps with the third occurring FEC frame time period, does not overlap with the second occurring FEC frame time period, and does not overlap with the fourth occurring FEC frame time period; and The method also includes sending, by the network interface device, the refresh signal during the third occurring FEC frame time period.

20. The method for power conservation according to claim 16, further comprising: controlling, by the network interface device, transmission via the communication link according to forward error correction (FEC) superframe time periods, each FEC superframe time period corresponding to a predetermined number of FEC frame time periods; The network interface device ends the transmission of the sleep signal at the FEC superframe boundary; as well as The network interface device is configured to transition to the silent time window at the FEC superframe boundary.

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