Array substrate, display panel and display device

Abstract

An array substrate, a display panel, and a display device are disclosed. The array substrate includes: a plurality of first active patterns (C11) located in a display area (AA); the first active patterns (C11) include: a first portion (CA) extending along a first direction, and a second portion (CB) extending from one end of the first portion (CA); a plurality of first metal lines (M11) extending along the first direction; a plurality of conductive portions (D11) located in the display area (AA); at least one of the conductive portions (D11) has its orthographic projection on a substrate (11) located between the orthographic projections of adjacent first metal lines (M11) on the substrate (11); and a second conductive layer (D2) including: The first electrode (D21) is located in the display area (AA); wherein the first metal line (M11) on both sides of the conductive part (D11) includes a first sub-metal line (MA) and a second sub-metal line (MB); wherein the first sub-metal line (MA) is electrically connected to the second part (CB); the first part (CA) is electrically connected to the first electrode (D21) through the conductive part (D11); the distance between the orthographic projection of the conductive part (D11) on the substrate (11) and the orthographic projection of the first sub-metal line (MA) on the substrate (11) is greater than the distance between the orthographic projection of the second sub-metal line (MB) on the substrate (11).

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Virtual reality (VR) technology is a new technology that seamlessly integrates real-world and virtual-world information. The most significant characteristic of VR display products compared to conventional displays is their ultra-high resolution. Currently, the optimal solution for ultra-high PPI is Liquid Crystal Display (LCD) technology because the pixel area circuit in an LCD display structure has only one switching transistor (Thin Film Transistor, TFT), which is highly conducive to achieving high PPI. Summary of the Invention

[0003] This disclosure provides an array substrate, a display panel, and a display device. The array substrate has a display area and a non-display area located around the display area, wherein it includes:

[0004] Substrate;

[0005] A first active layer, located on one side of the substrate, includes: a plurality of first active patterns located in the display area; the first active pattern includes: a first portion extending along a first direction, and a second portion extending from one end of the first portion;

[0006] The first metal layer includes: a plurality of first metal lines extending along a first direction; the orthographic projection of the first portion on the substrate is located between the orthographic projections of adjacent first metal lines on the substrate, and the portion of the second portion projected onto the substrate overlaps with the portion of the first metal line projected onto the substrate.

[0007] The first conductive layer includes: a plurality of conductive portions located in the display area; at least one of the plurality of conductive portions, in its orthographic projection on the substrate, is located between the orthographic projections of adjacent first metal lines on the substrate.

[0008] The second conductive layer includes: a plurality of first electrodes located in the display area;

[0009] The first metal line on both sides adjacent to the conductive portion includes a first sub-metal line and a second sub-metal line; wherein the first sub-metal line is electrically connected to the second portion; the first portion is electrically connected to the first electrode through the conductive portion; the distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second sub-metal line on the substrate.

[0010] In one possible implementation, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0011] 15% ≤ b / a ≤ 75%, where a represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal line on the substrate, and b represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0012] In one possible implementation, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0013] 3% ≤ (ab) / c ≤ 15%, where c represents the minimum spacing between adjacent first and second sub-metal lines.

[0014] In one possible implementation, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0015] 60% ≤ d / c ≤ 95%, where d represents the length of the conductive part in the direction perpendicular to the first direction.

[0016] In one possible implementation, the first portion has a first axis of symmetry extending along the first direction, and the conductive portion has a second axis of symmetry extending along the first direction.

[0017] The second axis of symmetry is located on the side of the first axis of symmetry away from the first sub-metal wire.

[0018] In one possible implementation, the first electrode has a first outer edge extending along the first direction; between two adjacent first metal lines, the portion of the first outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate away from the first sub-metal line.

[0019] The conductive portion has a second outer edge extending along the first direction; between two adjacent first metal lines, the portion of the second outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate away from the first sub-metal line.

[0020] Between two adjacent first metal lines, the portion of the second outer edge projected onto the substrate is located on the side of the first outer edge that is away from the first sub-metal line.

[0021] In one possible implementation, the first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line.

[0022] The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal lines, the portion of the fourth outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line.

[0023] Between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate is located on the side of the fourth outer edge projected onto the substrate away from the first sub-metal line.

[0024] In one possible implementation, the first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line.

[0025] The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal lines, the portion of the fourth outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line.

[0026] Between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate coincides with the portion of the fourth outer edge projected onto the substrate.

[0027] In one possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal lines extending along a second direction;

[0028] The first part includes: a first sub-part, a second sub-part, and a third sub-part distributed sequentially along the first direction; wherein the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second metal line on the substrate; the first sub-part is located on the side of the second sub-part facing the second part, and the third sub-part is located on the side of the second sub-part away from the second part;

[0029] The orthographic projection of the first sub-part onto the substrate overlaps with the orthographic projection of the conductive part onto the substrate.

[0030] In one possible implementation, the array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal lines extending along a second direction; the second portion including: a fourth sub-portion connected to the first portion and extending along a third direction, and a fifth sub-portion connected to the fourth sub-portion, the first metal lines being electrically connected to the fifth sub-portion; the second direction intersects the first direction, and the third direction intersects the first direction;

[0031] The conductive portion includes: a fifth outer edge extending along the second direction and toward the fifth sub-portion;

[0032] The orthographic projection of the second metal line onto the substrate covers the orthographic projection of the fifth outer edge onto the substrate.

[0033] In one possible implementation, the distance between the orthographic projection of the sixth outer edge onto the substrate and the orthographic projection of the fifth outer edge onto the substrate in the first direction is one-fifth to four-fifths of the length of the orthographic projection of the second metal line onto the substrate in the first direction.

[0034] In one possible implementation, the second metal wire has a sixth outer edge extending along the second direction and toward the fifth sub-part;

[0035] The orthographic projection of the sixth outer edge onto the substrate is located on the side where the orthographic projection of the fifth outer edge onto the substrate faces the orthographic projection of the fifth sub-part onto the substrate.

[0036] In one possible implementation, the first conductive layer is located on the side of the first active layer that is away from the substrate;

[0037] The array substrate further includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via penetrating the first insulating layer, wherein the conductive portion is electrically connected to the first portion through the first via;

[0038] Between two adjacent first metal lines, the minimum distance between the center of the first via in the orthographic projection of the substrate and the minimum distance between the first sub-metal line in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate is greater than the minimum distance between the first via and the second sub-metal line in the orthographic projection of the substrate.

[0039] In one possible implementation, the first electrode is located on the side of the first conductive layer opposite to the substrate;

[0040] The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via;

[0041] Between two adjacent first metal lines, the minimum distance between the center of the second via in the orthographic projection of the substrate and the minimum distance between the first sub-metal line in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate is greater than the minimum distance between the second via and the second sub-metal line in the orthographic projection of the substrate.

[0042] In one possible implementation, at least a portion of the orthographic projection of the first via on the substrate does not overlap with at least a portion of the orthographic projection of the second via on the substrate.

[0043] In one possible implementation, the first insulating layer comprises one or a combination of the following:

[0044] First gate insulating layer;

[0045] First interlayer dielectric layer;

[0046] Second interlayer dielectric layer.

[0047] In one possible implementation, the thickness of at least one of the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer is greater than [missing information].

[0048] In one possible implementation, the array substrate further includes a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes a plurality of third metal lines extending along the second direction, the orthogonal projection of the third metal lines on the substrate covering the orthogonal projection of the second metal lines on the substrate.

[0049] In one possible implementation, the array substrate includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of rows of pixel light-transmitting areas extending along the first direction and arranged along the second direction; at least one of the plurality of rows of pixel light-transmitting areas includes: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; the wavelength range of light emitted from the third pixel light-transmitting area is smaller than the wavelength range of light emitted from the first pixel light-transmitting area and smaller than the wavelength range of light emitted from the second pixel light-transmitting area;

[0050] The third metal line includes: a main portion of the third metal line extending along the second direction, and a first shielding structure connected to the main portion of the third metal line; the maximum length of the first shielding structure in the first direction is greater than the maximum length of the main portion of the third metal line in the first direction; the orthographic projection of the first shielding structure onto the substrate is located in the gap between at least two adjacent orthographic projections of the third pixel light-transmitting areas onto the substrate in the first direction.

[0051] In one possible implementation, the array substrate further includes: a spacer; the orthographic projection of the first shielding structure onto the substrate covers the orthographic projection of the spacer onto the substrate.

[0052] In one possible implementation, the third metal wire further includes: a second shielding structure connected to the main portion of the third metal wire; the maximum length of the second shielding structure in the first direction is greater than the maximum length of the main portion of the third metal wire in the first direction, and less than the maximum length of the first shielding structure in the first direction.

[0053] The orthographic projection of the second shielding structure onto the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas onto the substrate in the second direction, and the orthographic projection of the second shielding structure onto the substrate does not overlap with the orthographic projection of the first shielding structure onto the substrate.

[0054] In one possible implementation, the array substrate further includes, in the non-display area: a second active layer located on the side of the first active layer facing the substrate, a driving source drain located on the side of the second active layer facing away from the substrate, and a driving gate.

[0055] In one possible implementation, the material of the first active layer includes a metal oxide; the material of the second active layer includes low-temperature polycrystalline silicon.

[0056] In one possible implementation, the second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; and the driving source drain is located in the first metal layer.

[0057] In one possible implementation, the second active layer is located between the third metal layer and the first active layer; the drive source drain is located in the second metal layer; and the drive gate is located in the third metal layer.

[0058] In one possible implementation, the array substrate further includes a third conductive layer located on the side of the second conductive layer opposite to the substrate, the third conductive layer including a plurality of cutouts, the portion of the cutouts projecting onto the substrate overlapping the portion of the first electrode on the substrate.

[0059] In one possible implementation, the array substrate further includes a fourth metal layer located on the side of the third conductive layer facing the substrate and in contact with the third conductive layer;

[0060] The fourth metal layer includes a fourth metal line extending along the first direction, wherein the orthographic projection of the fourth metal line onto the substrate covers the orthographic projection of the first metal line onto the substrate.

[0061] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate.

[0062] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0063] Figure 1A One of the schematic diagrams illustrating crosstalk issues in a display panel;

[0064] Figure 1B The second illustration shows a crosstalk problem in the display panel;

[0065] Figure 1C The third illustration shows a display panel experiencing crosstalk issues.

[0066] Figure 1D The fourth illustration shows a display panel experiencing crosstalk issues.

[0067] Figure 2A This is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0068] Figure 2B for Figure 2A A schematic diagram of a single film layer of the third metal layer in the middle;

[0069] Figure 2C for Figure 2A Schematic diagram of the single-film layer of the first active layer in the middle;

[0070] Figure 2D for Figure 2A Schematic diagram of a single film layer of the second metal layer in the middle;

[0071] Figure 2E for Figure 2A A schematic diagram of a single film layer of the first metal layer in the middle;

[0072] Figure 2F for Figure 2A A schematic diagram of a single film layer of the first conductive layer in the middle;

[0073] Figure 2G for Figure 2A A schematic diagram of a single film layer of the second conductive layer in the middle;

[0074] Figure 3 for Figure 2A A schematic diagram of the cross-section at the dashed line A1A2;

[0075] Figure 4A for Figure 2A One of the schematic diagrams showing only a portion of the membrane layer;

[0076] Figure 4B for Figure 2A Schematic diagram of only part of the film layer (Part 2);

[0077] Figure 5A This is a schematic diagram of the self-pixel electrode and associated structure provided in an embodiment of the present disclosure;

[0078] Figure 5B This is a schematic diagram of the first metal wire M11 and its associated structure provided in an embodiment of this disclosure;

[0079] Figure 5C This is a schematic diagram of adjacent pixel electrodes and associated structures provided in an embodiment of this disclosure;

[0080] Figure 5D for Figure 5A The corresponding first coupling capacitor C dp1 A schematic diagram of its structure;

[0081] Figure 5E for Figure 5A The corresponding second coupling capacitor C dp2 A schematic diagram of its structure;

[0082] Figure 6 This is a second top view of the array substrate provided in the embodiments of this disclosure;

[0083] Figure 7A This is the third top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0084] Figure 7B for Figure 7A The corresponding first coupling capacitor C dp1 A schematic diagram of its structure;

[0085] Figure 7C for Figure 7B The corresponding second coupling capacitor C dp2 A schematic diagram of its structure;

[0086] Figure 8 for Figure 7A A schematic diagram showing only a portion of the film layers stacked together;

[0087] Figure 9 This is the fourth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0088] Figure 10A Fifth top view of the array substrate provided in the embodiments of this disclosure;

[0089] Figure 10B It can be Figure 10A A schematic diagram of a single film layer of the third metal wire M31 in the middle;

[0090] Figure 10C for Figure 10B A larger-scale diagram;

[0091] Figure 11 One of the cross-sectional schematic diagrams of the array substrate provided in the embodiments of this disclosure;

[0092] Figure 12 This is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of this disclosure;

[0093] Figure 13A This is the sixth top view schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0094] Figure 13B for Figure 13A A schematic diagram of a single film layer of the third conductive layer in the middle;

[0095] Figure 13C for Figure 13B A schematic diagram of a larger area;

[0096] Figure 14 This is a schematic diagram of the display panel structure provided in an embodiment of the present disclosure. Detailed Implementation

[0097] Different forms may be used to implement this disclosure. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited solely to the content described in the following embodiments. Without conflict, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0098] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0099] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure can include two or more quantities.

[0100] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0101] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0102] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0103] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0104] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0105] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0106] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0107] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0108] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "roughly the same" can mean that the values ​​differ by no more than 10%.

[0109] Virtual Reality (VR) and Augmented Reality (AR) head-mounted display panels utilize LTPO (Low Temperature Polycrystalline Oxide) technology. LTPO technology integrates two types of TFTs (Thin Film Transistors): LTPS (Low Temperature Poly-Silicon) and oxide. Specifically, the display area uses oxide TFTs, while the peripheral non-display areas use LTPS TFTs.

[0110] In AR and VR display panels, see Figure 1A As shown, there is a first coupling capacitance C between the data line and its own pixel electrode (which can be understood as the pixel electrode electrically connected to the data line) inside the pixel. dp1 And the second coupling capacitor C of the adjacent pixel electrode (the pixel electrode not electrically connected to the data line). dp2 When C dp1 >C dp2 Furthermore, when the differences are significant, common crosstalk problems arise, such as during display. Figure 1B When the image shown is white in the middle and black at the edges, a phenomenon will appear where the top is bright and the bottom is dark, with the middle as the boundary. Figure 1C As shown. Specifically, as... Figure 1B , Figure 1C and Figure 1D As shown, pixels A1 and A2 are two pixels at different positions on the same data line, pixels B1 and B2 are two pixels at different positions on the same data line, pixels B1 and A1 are two pixels in the same row on adjacent data lines, and pixels B2 and A2 are two pixels in the same row on adjacent data lines; when the pixel itself is coupled (the first coupling capacitance C... dp1 ) and mutual coupling effect (second coupling capacitance C) dp2 When the voltages are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, thus increasing the voltage difference between pixel A1 and the common electrode voltage (Vcom), resulting in a bright display. The charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, thus decreasing the voltage difference between pixel A2 and the common electrode voltage (Vcom), resulting in a dark display. This is the defective phenomenon of the top being bright and the bottom being dark in the Crosstalk screen.

[0111] In view of this, see Figures 2A-2G , Figure 3 and Figure 4A As shown, where, Figure 2B for Figure 2A A schematic diagram of a single film layer of the third metal layer in the middle. Figure 2C for Figure 2A A schematic diagram of the first active layer in the middle. Figure 2D for Figure 2A A schematic diagram of a single film layer of the second metal layer in the middle. Figure 2E for Figure 2A A schematic diagram of the single-film layer of the first metal layer in the middle. Figure 2F for Figure 2A A schematic diagram of the single-film layer of the first conductive layer in the middle. Figure 2G for Figure 2A A schematic diagram of a single film layer of the second conductive layer in the middle. Figure 3 for Figure 2A A cross-sectional view at the dashed line A1A2. Figure 4A for Figure 2A A schematic diagram showing only a portion of the film layers is shown. This disclosure provides an array substrate having a display area AA and a non-display area BB located around the display area AA, comprising:

[0112] Substrate 11;

[0113] The first active layer C1 is located on one side of the substrate 11 and includes: a plurality of first active patterns C11 located in the display area AA; the first active pattern C11 includes: a first part CA extending along the first direction X, and a second part CB extending from one end of the first part CA.

[0114] The first metal layer M1 includes: multiple first metal lines M11 extending along a first direction X; a first part CA projected onto the substrate 11, located between the projected projections of adjacent first metal lines M11 onto the substrate; and a second part CB projected onto the substrate 11, overlapping with the projected projections of the first metal lines M11 onto the substrate 11. Specifically, the first metal lines M11 can be data lines; specifically, the display area AA can have multiple first transistors; the second part CB at the position overlapping with the first metal lines M11 can serve as the first electrode of the first transistor; the second part CB at the position overlapping with the first metal lines M11 can be conductive, realizing the electrical connection between the first transistor and the data lines.

[0115] The first conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; at least one of the conductive portions D11 has its orthographic projection onto the substrate 11 located between the orthographic projections of adjacent first metal lines M11 onto the substrate 11; specifically, the first conductive layer D1 can be a transparent conductive layer, and the conductive portion D11 can serve as the second electrode of a first transistor, connecting the first active pattern C11 to the first electrode D21; specifically, the orthographic projection shape of the conductive portion D11 onto the substrate 11 can be rectangular, and the length of the conductive portion D11 in the first direction X can be greater than its length in the second direction Y; specifically, the length of the conductive portion D11 in the first direction X can also be equal to its length in the second direction Y.

[0116] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 can be a transparent conductive layer, and the material of the second conductive layer D2 can be the same as the material of the first conductive layer D1; specifically, the first electrodes D21 can be pixel electrodes; specifically, the orthographic projection of the first electrodes D21 onto the substrate 11 can be located between the orthographic projections of adjacent first metal lines M11 onto the substrate 11; specifically, the orthographic projection shape of the first electrodes D21 onto the substrate 11 can be rectangular; the length of the first electrodes D21 in the first direction X is greater than the length in the second direction Y.

[0117] The first metal line M11 on both sides adjacent to the conductive part D11 includes a first sub-metal line MA and a second sub-metal line MB. The first sub-metal line MA is electrically connected to the second part CB, that is, the first metal line M11 electrically connected to the second part CB is regarded as the first type of metal line MA. The first part CA is electrically connected to the first electrode D21 through the conductive part D11. The distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11.

[0118] The first metal line M11 and its associated structure can form a first coupling capacitor C with its own pixel electrode and associated structure.dp1 The first metal line M11 and its associated structure can form a second coupling capacitor C with the adjacent pixel electrode and its associated structure. dp2 Among them, the self-pixel electrode and associated structure can be as follows: Figure 5A The area shown in the dashed box can specifically include: the first electrode D21 (e.g. Figure 5A As shown in the dashed box S1), and the conductive part D11 (as shown in the image) connected to the first electrode D21 through the second via K2. Figure 5A As shown in the dashed box S2), and the portion of the first active pattern C11 connected to the conductive part D11 through the first via K1 located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S2), and the portion of the first active pattern C11 located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S2). Figure 5A As shown in the dashed box S3, that is, the portion of the first active pattern C11 located below the second metal line M21, since the on time of each row of pixels is very short during the display frame, it can be considered that the gate of the first transistor in the pixel is off most of the time. The part of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator; the first metal line M11 and the associated structure can be as follows Figure 5B The area shown in the dashed box may specifically include: the first metal wire M11 (e.g. Figure 5B As shown in the dashed box S4), and the portion of the first active pattern C11, which is electrically connected to the first metal line M11 through the third via K3, located on the side of the second metal line M21 in the first direction X closer to the second metal line M21 (as shown in the dashed box S4), and the portion of the first active pattern C11 located on the side of the second metal line M21 closer to the second metal line M21 in the first direction X. Figure 5B As shown in the dashed box S5, that is, the portion of the first active pattern C11 located above the second metal line M21; adjacent pixel electrodes and associated structures can be as follows Figure 5C The area shown in the dashed box can specifically include: the adjacent first electrode D21 (e.g. Figure 5C As shown in the dashed box S6), and the adjacent conductive part D11 connected to the adjacent first electrode D21 through the second via K2 (as ... S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 S6 Figure 5C As shown in the dashed box S7), and the portion of the adjacent first active pattern C11 connected to the adjacent conductive portion D11 through the first via K1 located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S7), and the portion of the adjacent first active pattern C11 located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S7). Figure 5C As shown in the dashed box S8, that is, the portion of the first active pattern C11 located below the second metal line M21; the first coupling capacitor C dp1 The composition can be as follows Figure 5D As shown, the second coupling capacitor C dp2 The composition can be as follows Figure 5E As shown;

[0119] Based on the research conducted by the inventors of this application, the first coupling capacitance C is caused... dp1 The second coupling capacitor C dp2The main reason for the difference is the asymmetry in the design of the first active pattern C11, and the thinner film between the first active layer C1 and the first conductive layer D1, and the thinner first coupling capacitor C. dp1 The first active pattern C11 and the conductive part D11 overlap vertically (e.g.) Figure 5D The region shown in the thick solid line box S has a larger capacitance, while the second coupling capacitor C... dp2 Without this overlap, the first coupling capacitor C is formed. dp1 The second coupling capacitor C dp2 The main part that produces the difference (in addition, although the first coupling capacitor C) dp1 In the first active pattern C11, the overlap area between the first active pattern C11 and the first electrode D21 is larger than the overlap area between the first active pattern C11 and the conductive part D11. However, due to the thicker film layer between the first active pattern C11 and the first electrode D21, the overlap capacitance is very small and the difference can be ignored. Meanwhile, since there is only one film layer between the first metal line M11 and the conductive part D11, the lateral capacitance formed by the first metal line M11 and the conductive part D11 is significantly reduced in the second coupling capacitance C11. dp2 China dominates.

[0120] In this embodiment, the distance *a* between the orthographic projection of the conductive portion D11 onto the substrate 11 and the orthographic projection *MA* of the first sub-metal line MA onto the substrate 11 is greater than the distance *b* between the orthographic projection *MA* of the second sub-metal line MB onto the substrate 11. This increases the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C. dp2 And due to the first coupling capacitor C dp1 In the middle, the first active pattern C11 and the conductive part D11 overlap with a capacitor (such as... Figure 5D The area shown in the thick solid line frame S occupies the main part, and the distance between the conductive part D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C. dp1 This has a significant impact, thereby reducing the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The difference in these characteristics improves the vertical crosstalk problem.

[0121] It should be noted that when the outer edge of the orthographic projection of the conductive part D11 onto the substrate 11 is straight, the distance 'a' between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11 can be the minimum distance 'a' between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11. When the outer edge of the orthographic projection of the conductive part D11 onto the substrate 11 is not straight (e.g., due to manufacturing process, the edge has some unevenness) or when the orthographic projection of the conductive part D11 onto the substrate 11 is not rectangular, the distance 'a' between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11 can be the average distance 'a' between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11. Similarly, when the outer edge of the orthographic projection of the conductive part D11 onto the substrate 11 is straight, the distance b between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the second sub-metal line MB onto the substrate 11 can be the minimum distance b between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the second sub-metal line MB onto the substrate 11; when the outer edge of the orthographic projection of the conductive part D11 onto the substrate 11 is not straight (for example, due to the manufacturing process, the edge is partially uneven) or when the orthographic projection of the conductive part D11 onto the substrate 11 is not rectangular, the distance b between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the second sub-metal line MB onto the substrate 11 can be the average distance between the orthographic projection of the conductive part D11 onto the substrate 11 and the orthographic projection of the second sub-metal line MB onto the substrate 11.

[0122] It should be noted that the first sub-metal line MA is electrically connected to the second part CB, which can be understood as the first sub-metal line MA being electrically connected to the second part CB through the first transistor; when the orthographic projection of the conductive part D11 on the substrate 11 is rectangular, the minimum distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be the distance between the left edge of the conductive part D11 and the right edge of the first sub-metal line MA; the minimum distance b between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be the distance between the right edge of the conductive part D11 and the left edge of the second sub-metal line MB.

[0123] In one possible implementation, combined with Figure 2A or Figure 4A As shown, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy the following relationship:

[0124] 15% ≤ b / a ≤ 75%, where a represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and b represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11.

[0125] In one possible implementation, combined with Figure 2A or Figure 4A As shown, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy the following relationship:

[0126] 3% ≤ (ab) / c ≤ 15%, where c represents the minimum spacing between adjacent first sub-metal line MA and second sub-metal line MB.

[0127] Specifically, in combination Figure 4A As shown, the minimum spacing c between adjacent first sub-metal line MA and second sub-metal line MB can be the spacing between the right edge of the first sub-metal line MA and the left edge of the second sub-metal line MB.

[0128] In one possible implementation, combined with Figure 2A or Figure 4A As shown, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy the following relationship:

[0129] 60% ≤ d / c ≤ 95%, where d represents the length of the conductive part D11 in the direction perpendicular to the first direction X.

[0130] In one possible implementation, the conductive portion D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: 70% ≤ d / c ≤ 90%; in one possible implementation, the conductive portion D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: 75% ≤ d / c ≤ 85%; in one possible implementation, the conductive portion D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: 78% ≤ d / c ≤ 85%; in one possible implementation, the conductive portion D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: d / c =78%; In one possible embodiment, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: d / c = 79%; In one possible embodiment, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: d / c = 79.64%; In one possible embodiment, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: d / c = 80%; In one possible embodiment, the conductive part D11, the first sub-metal line MA, and the second sub-metal line MB satisfy: d / c = 81%.

[0131] In one possible implementation, the minimum distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be 0.35μm to 1.15μm; the minimum distance b between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be 0.05μm to 0.85μm.

[0132] In one possible implementation, the minimum distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be 0.3 μm to 1.5 μm; the minimum distance b between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be 0.2 μm to 1 μm.

[0133] In one possible implementation, the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB can be 2 μm to 10 μm; in one possible implementation, the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB can be 4 μm to 8 μm; in one possible implementation, the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB can be 5 μm to 6 μm; in one possible implementation, the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB can be 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm, 5.6 μm, 5.7 μm, 5.8 μm, 5.8 μm, or 6.0 μm; in one possible implementation, the minimum spacing c between adjacent first sub-metal lines MA and second sub-metal lines MB can be 5.65 μm.

[0134] In one possible implementation, the length d of the conductive portion D11 perpendicular to the first direction X can be 2μm to 8μm; in one possible implementation, the length d of the conductive portion D11 perpendicular to the first direction X can be 3μm to 6μm; in one possible implementation, the length d of the conductive portion D11 perpendicular to the first direction X can be 4μm to 5μm; in one possible implementation, the length d of the conductive portion D11 perpendicular to the first direction X can be 4.1μm, 4.2μm, 4.3μm, 4.4μm, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm, or 5.0μm.

[0135] In one possible implementation, the length d of the conductive portion D11 in the direction perpendicular to the first direction X can be 4.5 μm; the minimum spacing c between adjacent first sub-metal line MA and second sub-metal line MB can be 5.65 μm.

[0136] In one possible implementation, combined with Figure 2A, Figure 2C and Figure 2F As shown, the first part CA has a first axis of symmetry e1 extending along the first direction X, and the first part CA is symmetrical about the first axis of symmetry e1; the conductive part D11 has a second axis of symmetry e2 extending along the first direction X, and the conductive part D11 is symmetrical about the second axis of symmetry e2; the second axis of symmetry e2 is located on the side of the first axis of symmetry e1 away from the first sub-metal line MA.

[0137] In one possible implementation, combined with Figure 2A , Figure 2F and Figure 2G As shown, the first electrode D21 has a first outer edge f1 extending along the first direction X; between two adjacent first metal lines M11, the portion of the first outer edge f1 projected onto the substrate 11 is located on the side of the first part CA projected onto the substrate 11 away from the first sub-metal line MA; specifically, as... Figure 2F As shown, the first outer edge f1 can be the right edge of the first electrode D21; the conductive portion D11 has a second outer edge f2 extending along the first direction X; between two adjacent first metal lines M11, the portion of the second outer edge f2 projected onto the substrate 11 is located on the side of the first portion CA projected onto the substrate 11 away from the first sub-metal line MA; specifically, as... Figure 2G As shown, the second outer edge f2 can be the right edge of the conductive part D11; between two adjacent first metal lines M11, the portion of the second outer edge f2 projected onto the substrate 11 is located on the side of the first outer edge f1 away from the first sub-metal line MA.

[0138] In one possible implementation, combined with Figure 2A , Figure 2F and Figure 2G As shown, the first electrode D21 has a third outer edge f3 extending along the first direction X; between two adjacent first metal lines M11, the portion of the third outer edge f3 projected onto the substrate 11 is located on the side of the first part CA projected onto the substrate 11 closer to the first sub-metal line MA; specifically, as... Figure 2F As shown, the third outer edge f3 can be the left edge of the first electrode D21; the conductive portion D11 has a fourth outer edge f4 extending along the first direction X; between two adjacent first metal lines M11, the portion of the fourth outer edge f4 projected onto the substrate 11 is located on the side of the first portion CA projected onto the substrate 11 closer to the first sub-metal line MA; specifically, as... Figure 2GAs shown, the fourth outer edge f4 can be the left edge of the conductive portion D11; between two adjacent first metal lines M11, the portion of the fourth outer edge f4 projected onto the substrate 11 is located on the side of the third outer edge f3 projected onto the substrate 11 away from the first sub-metal line MA. In this embodiment, by moving the conductive portion D11 away from the first sub-metal line MA, the second coupling capacitance C is increased. dp2 This reduces the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The difference in these characteristics improves the vertical crosstalk problem.

[0139] In specific implementation, combined with Figure 2A As shown, the second coupling capacitance C can be increased by moving the conductive part D11 away from the first sub-metal line MA. dp2 In another possible implementation, see Figure 6 As shown, the conductive part D11 can also be moved without moving it. Instead, by moving the edge of the conductive part D11 away from the first sub-metal line MA to the side away from the first sub-metal line MA, that is, increasing the width of D11 along the second direction Y, and decreasing the minimum distance b between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11, the second coupling capacitance C can also be increased. dp2 .

[0140] Specifically, such as Figure 6 As shown, the first electrode D21 has a third outer edge f3 extending along the first direction X; between two adjacent first metal lines M11, the portion of the third outer edge f3 projected onto the substrate 11 is located on the side of the first part CA projected onto the substrate 11 closer to the first sub-metal line MA; specifically, as... Figure 6 As shown, the third outer edge f3 can be the left edge of the first electrode D21; the conductive portion D11 has a fourth outer edge f4 extending along the first direction X; between two adjacent first metal lines M11, the portion of the fourth outer edge f4 projected onto the substrate 11 is located on the side of the first portion CA projected onto the substrate 11 closer to the first sub-metal line MA; specifically, as... Figure 6 As shown, the fourth outer edge f4 can be the left edge of the conductive portion D11; between two adjacent first metal lines M11, the portion of the third outer edge f3 projected onto the substrate 11 coincides with the portion of the fourth outer edge f4 projected onto the substrate 11. In this embodiment, by moving the edge of the conductive portion D11 away from the first sub-metal line MA to the side away from the first sub-metal line MA, the second coupling capacitance C is increased. dp2 This reduces the second coupling capacitance C. dp2 With the first coupling capacitor C dp1The difference in these characteristics improves the vertical crosstalk problem.

[0141] It should be noted that, in order to clearly illustrate the positional relationship of the various structures in the embodiments of this disclosure, Figures 2A-9 The first electrode D21 in the second row is marked with respect to the edges and positional relationships of the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB. In specific implementation, the first electrode D21 in each row also satisfies the relevant edge and positional relationships with the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB corresponding to the current row. This disclosure is not limited to these.

[0142] Additionally, it should be noted that, for example, Figure 2G The first electrode D21 in the second row from top to bottom is shown only in part due to the limited area of ​​the illustration. The complete pattern of the first electrode D21 can be shown as the first electrode D21 in the first row from top to bottom. This embodiment is not limited to this.

[0143] In one possible implementation, combined with Figure 2C and Figure 4B As shown, the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1, the second metal layer M2 including: a plurality of second metal lines M21 extending along the second direction Y;

[0144] The first part CA includes: a first sub-part CA1, a second sub-part CA2, and a third sub-part CA3 distributed sequentially along the first direction X; wherein, the orthographic projection of the second sub-part CA2 onto the substrate overlaps with the orthographic projection of the second metal line M21 onto the substrate 11; the first sub-part CA1 is located on the side of the second sub-part CA2 facing the second part CB, and the third sub-part CA3 is located on the side of the second sub-part CA2 away from the second part CB; that is, the portion of the first part CA that overlaps with the projection of the second metal line M21 is taken as the second sub-part CA2;

[0145] The orthographic projection of the first sub-part CA1 onto the substrate 11 overlaps with the orthographic projection of the conductive part D11 onto the substrate 11. Specifically, the overlapping area between the orthographic projection of the first sub-part CA1 onto the substrate 11 and the orthographic projection of the conductive part D11 onto the substrate 11 can be as follows: Figure 4B The frame S is shown as a medium-thick solid line.

[0146] In one possible implementation, combined with Figure 2A , Figure 3 , Figure 7A and Figure 8 As shown, where Figure 8 for Figure 7AA schematic diagram of the stacked film layers in the middle section shows that the array substrate also includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1, the second metal layer M2 including: multiple second metal lines M21 extending along the second direction Y; the second part CB including: a fourth sub-part CB1 connected to the first part CA and extending along the third direction, and a fifth sub-part CB2 connected to the fourth sub-part CB1, the first metal lines M11 being electrically connected to the fifth sub-part CB2; the second direction Y intersects the first direction X, and the third direction Z intersects the first direction X; the conductive part D11 includes: a fifth outer edge f5 extending along the second direction Y and toward the fifth sub-part CB2, specifically, as shown in the diagram. Figure 7A As shown, the fifth outer edge f5 can be the upper edge of the conductive part D11; the second metal line M21 has a sixth outer edge f6 extending along the second direction Y and toward the fifth sub-part CB2, specifically, as... Figure 7A As shown, the sixth outer edge f6 can be the upper edge of the second metal line M21; the orthographic projection of the sixth outer edge f6 onto the substrate 11 is located on the side where the orthographic projection of the fifth outer edge f5 onto the substrate 11 faces the orthographic projection of the fifth sub-part CB2 onto the substrate 11.

[0147] In this embodiment, the second metal line M21 has a sixth outer edge f6 extending along the second direction Y and toward the fifth sub-part CB2. That is, when the second metal line M21 is moved upward (after the second metal line M21 is moved upward, the first coupling capacitor C... dp1 The composition can be as follows Figure 7B As shown, the second coupling capacitor C dp2 The composition can be as follows Figure 7C As shown), the second metal line M21 can shield the overlapping capacitance between the first active pattern C11 and the conductive part D11 (that is, it can shield the capacitance of...). Figure 5D (The capacitance of the region shown in the thick solid line frame S) can thus reduce the first coupling capacitance C. dp1 The overlapping capacitor, which accounts for a relatively large proportion, reduces the first coupling capacitor C. dp1 The second metal line M21 moves upward, which affects the lateral capacitance between the first metal line M11 and the conductive part D11 (forming the second coupling capacitor C). dp2 The main part (of the system) has a relatively small impact, which can reduce the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The difference in these characteristics improves the vertical crosstalk problem.

[0148] Specifically, the second metal line M21 can be a gate line.

[0149] Specifically, the second direction Y can be perpendicular to the first direction X; the angle between the third direction Z and the first direction X can be 0 to 90°; specifically, the angle between the third direction Z and the first direction X can be 30° to 60°; specifically, the angle between the third direction Z and the first direction X can be 45°.

[0150] In one possible implementation, combined with Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the length g1 of the orthogonal projection of the first electrode D21 onto the substrate 11 along the second direction Y can be equal to the length g2 of the orthogonal projection of the conductive portion D11 onto the substrate 11 along the second direction Y. The length g1 of the orthogonal projection of the first electrode D21 onto the substrate 11 along the second direction Y can be less than the minimum spacing c between adjacent first sub-metal lines MA and MB. In one possible embodiment, combined with... Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the length g4 of the orthogonal projection of the first electrode D21 onto the substrate 11 along the first direction X can be greater than the length g5 of the orthogonal projection of the conductive portion D11 onto the substrate 11 along the first direction X. In one possible embodiment, combined with Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the length g5 of the orthogonal projection of the conductive portion D11 onto the substrate 11 along the first direction X can be one-fifth to four-fifths of the length g4 of the orthogonal projection of the first electrode D21 onto the substrate 11 along the first direction X; in one possible embodiment, the length g5 of the orthogonal projection of the conductive portion D11 onto the substrate 11 along the first direction X can be one-half of the length g4 of the orthogonal projection of the first electrode D21 onto the substrate 11 along the first direction X.

[0151] In one possible implementation, combined with Figure 2A As shown, the orthographic projection of the conductive portion D11 onto the substrate 11 can cover the orthographic projection of the gap between two adjacent first electrodes D21 in the first direction X onto the substrate 11. In one possible embodiment, combined with Figure 2A As shown, the overlapping area of ​​the orthographic projection of the conductive portion D11 onto the substrate 11 and the orthographic projection of the first electrode D21 onto the substrate 11 can occupy one-fifth to four-fifths of the orthographic projection area of ​​the conductive portion D11 onto the substrate 11; in one possible embodiment, combined with Figure 2A As shown, the overlapping area of ​​the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 can account for one-third of the orthographic projection area of ​​the conductive part D11 on the substrate 11.

[0152] In one possible implementation, combined with Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the spacing g6 between two adjacent first electrodes D21 in the first direction X can be one-fifth to four-fifths of the length g5 of the conductive portion D11 projected onto the substrate 11 in the first direction X; in one possible embodiment, combined with Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the distance g6 between two adjacent first electrodes D21 in the first direction X can be one-third of the length g5 of the conductive part D11 projected onto the substrate 11 in the first direction X.

[0153] In one possible implementation, combined with Figure 2A , Figure 2C , Figure 2F and Figure 2G As shown, the maximum length g3 of the orthographic projection of the first part CA1 of the first active pattern C11 onto the substrate 11 along the second direction Y can be less than the length g2 of the orthographic projection of the conductive part D11 onto the substrate 11 along the second direction Y.

[0154] In one possible implementation, combined with Figure 2C As shown, the maximum length g7 of the orthographic projection of the first part CA1 of the first active pattern C11 onto the substrate 11 along the first direction X can be one-third to three-thirds of the maximum length g8 of the orthographic projection of the first part CA1 of the first active pattern C11 onto the substrate 11 along the first direction X; in one possible implementation, combined with Figure 2C As shown, the maximum length g7 of the orthographic projection of the first part CA1 of the first active pattern C11 onto the substrate 11 along the first direction X can be half of the maximum length g8 of the orthographic projection of the first part CA1 of the first active pattern C11 onto the substrate 11 along the first direction X.

[0155] In one possible implementation, combined with Figure 2C As shown, the maximum length g9 of the orthographic projection of the fourth sub-part CB1 of the first active pattern C11 onto the substrate 11 along the first direction X can be one-third to three-thirds of the maximum length g10 of the orthographic projection of the second sub-part CB of the first active pattern C11 onto the substrate 11 along the first direction X; in one possible implementation, combined with Figure 2CAs shown, the maximum length g9 of the orthographic projection of the fourth sub-part CB1 of the first active pattern C11 onto the substrate 11 along the first direction X can be half of the maximum length g10 of the orthographic projection of the second sub-part CB of the first active pattern C11 onto the substrate 11 along the first direction X; the maximum length g11 of the orthographic projection of the fifth sub-part CB2 of the first active pattern C11 onto the substrate 11 along the first direction X can be half of the maximum length g10 of the orthographic projection of the second sub-part CB of the first active pattern C11 onto the substrate 11 along the first direction X.

[0156] In one possible implementation, combined with Figure 2C As shown, the maximum length g12 of the orthographic projection of the fifth sub-part CB2 of the first active pattern C11 onto the substrate 11 along the second direction Y can be equal to the maximum length g3 of the orthographic projection of the first part CA of the first active pattern C11 onto the substrate 11 along the second direction Y; in one possible implementation, combined with Figure 2C As shown, the maximum length g12 of the orthographic projection of the fifth sub-part CB2 of the first active pattern C11 onto the substrate 11 along the second direction Y can be greater than the length g13 of the orthographic projection of the fourth sub-part CB1 of the first active pattern C11 onto the substrate 11 along the second direction Y.

[0157] In one possible implementation, combined with Figure 7A and Figure 8 As shown, the distance d1 between the orthographic projection of the sixth outer edge f6 onto the substrate 11 and the orthographic projection of the fifth outer edge f5 onto the substrate 11 in the first direction X is one-fifth to four-fifths of the length d2 of the orthographic projection of the second metal line M21 onto the substrate 11 in the first direction X.

[0158] In one possible implementation, combined with Figure 7A and Figure 8 As shown, the orthographic projection of the second metal line M21 onto the substrate 11 covers the orthographic projection of the fifth outer edge f5 onto the substrate 11. That is, the maximum upward movement of the second metal line M21 does not exceed the upper edge of the conductive portion D11.

[0159] In one possible implementation, the distance d1 between the orthographic projection of the sixth outer edge f6 onto the substrate 11 and the orthographic projection of the fifth outer edge f5 onto the substrate 11 in the first direction X is 1 μm to 3 μm. In another possible implementation, the distance d1 between the orthographic projection of the sixth outer edge f6 onto the substrate 11 and the orthographic projection of the fifth outer edge f5 onto the substrate 11 in the first direction X is 1.5 μm.

[0160] In specific implementation, such as Figure 2AAs shown, the second coupling capacitance C can be reduced simply by making the minimum distance a between the orthographic projection of the conductive part D11 on the substrate 11 and the minimum distance b between the orthographic projection of the first sub-metal line MA on the substrate 11 and the first sub-metal line MA on the substrate 11 greater than the minimum distance b between the orthographic projection of the second sub-metal line MB on the substrate 11 (i.e., shifting the conductive part D11 to the right). dp2 With the first coupling capacitor C dp1 Differences; or, as Figure 7A and Figure 8 As shown, the second coupling capacitance C is reduced by making the orthographic projection of the sixth outer edge f6 onto the substrate 11 located on the side where the orthographic projection of the fifth outer edge f5 onto the substrate 11 faces the orthographic projection of the fifth sub-part CB2 onto the substrate 11 (that is, by moving the second metal line M21 upward). dp2 With the first coupling capacitor C dp1 Differences; or, as Figure 9 As shown, the minimum distance 'a' between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection 'a' of the first sub-metal line MA on the substrate 11 is greater than the minimum distance 'b' between the orthographic projection 'a' of the second sub-metal line MB on the substrate 11 (i.e., the conductive part D11 is shifted to the right). Simultaneously, the orthographic projection of the sixth outer edge f6 on the substrate 11 is positioned on the side where the orthographic projection of the fifth outer edge f5 on the substrate 11 faces the orthographic projection of the fifth sub-part CB2 on the substrate 11 (i.e., the second metal line M21 is moved upwards), thereby reducing the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The differences.

[0161] In one possible implementation, combined with Figure 2A and Figure 3 As shown, the first conductive layer D1 is located on the side of the first active layer C1 facing away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 penetrating the first insulating layer F1. The conductive part D11 is electrically connected to the first part CA through the first via K1; between two adjacent first metal lines M11, the minimum distance d3 between the center O1 of the first via K1 projected onto the substrate 11 and the first sub-metal line MA projected onto the substrate 11 is greater than the minimum distance d4 between the first via K1 and the second sub-metal line MB projected onto the substrate 11. In this embodiment, when the conductive part D11 is moved to the right, the first via K1 that connects the conductive part D11 and the first active pattern C11 is also moved to the right, to avoid affecting the conduction effect between the conductive part D11 and the first active pattern C11 when the conductive part D11 is moved to the right but the first via K1 is not moved to the right.

[0162] In one possible implementation, combined with Figure 2A and Figure 3As shown, the first electrode D21 is located on the side of the first conductive layer D1 facing away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 penetrating the second insulating layer F2; the first electrode D21 is electrically connected to the conductive part D11 of K2 through the second via; between two adjacent first metal lines M11, the minimum distance d5 between the center O2 of the second via K2 projected onto the substrate 11 and the minimum distance d6 between the second via K2 and the first sub-metal line MA projected onto the substrate 11 is greater than the minimum distance d6 between the second sub-metal line MB projected onto the substrate 11. In this embodiment, when the conductive part D11 is moved to the right, the second via K2 that connects the first electrode D21 and the conductive part D11 is also moved to the right, to avoid affecting the conduction effect between the first electrode D21 and the conductive part D11 when the conductive part D11 is moved to the right but the second via K2 is not moved to the right.

[0163] In one possible implementation, at least a portion of the orthographic projection of the first via K1 onto the substrate 11 does not overlap with at least a portion of the orthographic projection of the second via K2 onto the substrate 11. In one possible implementation, combined with... Figure 2A and Figure 3 As shown, the entire orthographic projection of the first via K1 onto the substrate 11 does not overlap with the entire orthographic projection of the second via K2 onto the substrate 11.

[0164] In one possible implementation, the first insulating layer F1 comprises one or a combination of the following:

[0165] First gate insulating layer 15;

[0166] First interlayer dielectric layer 16;

[0167] Second interlayer dielectric layer 17.

[0168] Specifically, in combination Figure 3 As shown, the first interlayer dielectric layer 16 may be located on the side of the first gate insulating layer 15 away from the substrate 11; the second interlayer dielectric layer 17 may be located on the side of the first interlayer dielectric layer 16 away from the substrate 11.

[0169] In one possible implementation, combined with Figure 3 As shown, the first insulating layer F1 includes: a first gate insulating layer 15, a first interlayer dielectric layer 16, and a second interlayer dielectric layer 17.

[0170] In one possible implementation, 2A and Figure 3 As shown, the array substrate also includes a third via K3 that penetrates the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17, and the first metal line M11 is electrically connected to the second part CB of the first active pattern C11 through the third via K3.

[0171] In one possible implementation, combined with Figure 2A As shown, the orthographic projection of the third metal line M31 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11; specifically, the orthographic projection of the second metal line M21 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11. In one possible embodiment, the orthographic projection of the second via K2 onto the substrate 11 is located at the overlapping area of ​​the first electrode D21 and the conductive portion D11 on the substrate 11, thereby achieving electrical connection between the first electrode D21 and the conductive portion D11 at the overlapping area through the second via K2.

[0172] In one possible implementation, the orthographic projection of the third metal line M31 onto the substrate 11 covers a portion of the orthographic projection of the first via K1 onto the substrate 11. The orthographic projection of the first metal line M11 onto the substrate 11 covers the orthographic projection of the third via K3 onto the substrate 11. In another possible implementation, the orthographic projection of the first via K1 onto the substrate 11 is located at the overlapping region of the orthographic projections of the first part CA of the first active pattern C11 and the conductive part D11 onto the substrate 11, thereby achieving electrical connection between the first part CA and the conductive part D11 at the overlapping region through the first via K1.

[0173] In one possible implementation, the orthographic projection of the first metal line M11 onto the substrate 11 covers the orthographic projection of the third via K3 onto the substrate 11. Specifically, the orthographic projection of the third via K3 onto the substrate 11 is located at the overlapping area of ​​the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 onto the substrate 11, thereby achieving electrical connection between the first metal line M11 and the second portion CB of the first active pattern C11 through the third via K3.

[0174] In one possible implementation, the orthographic projections of the first via K1 and the second via K2 onto the substrate 11 are both located between the orthographic projections of the first sub-metal line MA and the second sub-metal line MB onto the substrate 11. In another possible implementation, the orthographic projections of the first via K1 and the second via K2 onto the substrate 11 have a gap in the first direction X. Specifically, the length of the gap between the first via K1 and the second via K2 in the first direction X can be one-quarter to three-quarters of the length of the conductive portion D11 in the first direction X.

[0175] In one possible implementation, the third via K3 has a third via symmetry axis e3 extending along the second direction Y; the first electrode D21 has a first electrode outer edge f7 extending along the second direction Y and facing the side of the electrically connected conductive portion D11; the distance between the third via symmetry axis e3 and the first electrode outer edge f7 in the first direction X can be one-quarter to three-quarters of the length of the first electrode D21 along the first direction X; in one possible implementation, the distance between the third via symmetry axis e3 and the first electrode outer edge f7 in the first direction X can be one-half of the length of the first electrode D21 along the first direction X, and the third via symmetry axis e3 is located at half the length of the first electrode D21 along the first direction X.

[0176] In practical implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17. Combined with rightward shifting of the conductive portion D11 and / or upward shifting of the second metal trace M21, precise capacitance difference control can be achieved, reducing the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The differences.

[0177] In one possible implementation, combined with Figure 3 As shown, the thickness of at least one of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17 is greater than [a certain value].

[0178] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0179] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0180] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0181] In one possible implementation, combined with Figure 3 As shown, the array substrate further includes a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes multiple third metal lines M31 extending along the second direction Y, the orthographic projection of the third metal lines M31 onto the substrate 11 covering the orthographic projection of the second metal lines M21 onto the substrate 11. Specifically, the third metal lines M31 can be used to block at least a portion of the first active pattern C11 of the first transistor to avoid the illumination effect of ambient light on the first active pattern C11, thereby affecting the characteristics of the first transistor.

[0182] In one possible implementation, combined with Figure 2A As shown, the orthogonal projection of the third metal line M31 onto the substrate 11 can cover the orthogonal projection of the gap between two adjacent first electrodes D21 in the first direction X onto the substrate 11. In one possible implementation, combined with Figure 2AAs shown, the orthographic projection of the third metal line M31 onto the substrate 11 can cover the portion of the first part CA of the first active pattern C11 projected onto the substrate 11, and also cover the portion of the fourth sub-part CB1 of the first active pattern C11 projected onto the substrate 11. The orthographic projection of the third metal line M31 onto the substrate 11 can also cover the portion of the conductive part D11 projected onto the substrate 11.

[0183] In one possible implementation, combined with Figure 2A As shown, the orthographic projection of the third metal line M31 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11. In this embodiment of the present disclosure, the orthographic projection of the third metal line M31 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11. That is, by using the third metal line M31 of the array substrate to cover the second via K2, the risk of light leakage from the second via K2 on the array substrate can be reduced.

[0184] Because Virtual Reality (VR) headsets are near-eye displays, and the images displayed on the LCD screen need to be magnified many times by the imaging system before reaching the human eye, even though current VR display resolutions have reached over 1000 PPI, a screen-door effect due to the light-blocking structure is still visible in the overall display. Therefore, in one possible implementation, see... Figure 10A , Figure 10B and Figure 10C As shown, where, Figure 10B It can be Figure 10A A schematic diagram of a single film layer of the third metal wire M31 in the middle. Figure 10B It can also be Figure 10C A partial schematic diagram of the area within the dashed box J1. Figure 10C It can be Figure 10BA larger schematic diagram shows that the array substrate includes: multiple pixel light-transmitting areas P, each pixel light-transmitting area P comprising: multiple rows H of pixel light-transmitting areas extending along a first direction X and arranged along a second direction Y; at least one row H of the multiple pixel light-transmitting areas includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the wavelength range of light emitted from the third pixel light-transmitting area P3 is smaller than the wavelength range of light emitted from the first pixel light-transmitting area P1 and smaller than the wavelength range of light emitted from the second pixel light-transmitting area P2; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area emitting red light, the second pixel... The light-transmitting area P2 can be a pixel light-transmitting area that emits green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area that emits blue light; the third metal line M31 includes: a third metal line main part M310 extending along the second direction Y, and a first blocking structure Z1 connected to the third metal line main part M310; the maximum length h1 of the first blocking structure Z1 in the first direction X is greater than the maximum length h3 of the third metal line main part M310 in the first direction X; the orthographic projection of the first blocking structure Z1 onto the substrate 11 is located in the gap between at least partially adjacent third pixel light-transmitting areas P3 onto the substrate 11 in the first direction X.

[0185] Specifically, the array substrate also includes: spacers (not shown in the figure, the specific shape and position of which can be determined by the orthographic projection onto the substrate 11 as follows). Figure 10C As shown, the orthographic projection of the spacer on the substrate 11 can be octagonal, and can be located in the gap between at least two adjacent third pixel light-transmitting areas P3 in the first direction X (as shown in the orthographic projection of the spacer on the substrate 11); the orthographic projection of the first blocking structure Z1 on the substrate 11 covers the orthographic projection of the spacer on the substrate 11. That is, the orthographic projection of the spacer on the substrate 11 is located in the gap between at least two adjacent third pixel light-transmitting areas P3 in the first direction X (as shown in the orthographic projection of the spacer on the substrate 11).

[0186] In this embodiment of the disclosure, the spacer is placed in the gap between the light-transmitting areas of adjacent blue pixels, which effectively reduces the human eye’s sensitivity to compensation from the occlusion of the spacer (e.g., a black matrix). (Blue pixels are less bright than green and red pixels, so placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels results in a smaller difference in brightness for the human eye than placing it on green and red pixels.)

[0187] In one possible implementation, see Figure 10A , Figure 10B and Figure 10CAs shown, the third metal line M31 further includes: a second shielding structure Z2 connected to the main part of the third metal line M310; the maximum length h2 of the second shielding structure Z2 in the first direction X is greater than the maximum length h3 of the main part of the third metal line M310 in the first direction X, and less than the maximum length h1 of the first shielding structure Z1 in the first direction X; the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting P3 areas in the second direction Y on the substrate 11, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11.

[0188] In this embodiment, the orthographic projection of the second occlusion structure Z1 onto the substrate 11 is located in the gap between the orthographic projections of two adjacent light-transmitting P3 areas of the third pixel onto the substrate 11 in the second direction Y. Furthermore, the orthographic projection of the second occlusion structure Z2 onto the substrate 11 does not overlap with the orthographic projection of the first occlusion structure Z1 onto the substrate 11. In other words, the second occlusion structure Z1 can be set at a position without spacers between adjacent blue pixels, reducing the brightness difference between positions with and without spacers for blue pixels, making the brightness distribution more uniform throughout the pixel area, thereby reducing the screen door effect and improving the visual effect.

[0189] In one possible implementation, the length m3 of the third pixel light-transmitting area P3 in the first direction X is smaller than the length m1 of the first pixel light-transmitting area P1 in the first direction X, and smaller than the length m2 of the second pixel light-transmitting area P2 in the first direction X.

[0190] Specifically, the light-transmitting area P of a pixel can be understood as the effective display area of ​​the pixel. It can be the area within the pixel region that is not obstructed by obstructing structures (such as light-shielding layers, grid lines, data lines, black matrices, etc.). Specifically, in one possible implementation, such as... Figure 10C In the diagram, the light-transmitting area P of a pixel can be represented as a white area.

[0191] In one possible implementation, the length m1 of the first pixel light-transmitting area P1 in the first direction X is equal to the length m2 of the second pixel light-transmitting area P2 in the first direction X. In this embodiment, by setting the length m3 of the third pixel light-transmitting area P3 in the first direction X to be shorter, a second blocking structure Z2 is set. Moreover, compared with the first pixel light-transmitting area P1 and the second pixel light-transmitting area P2, which have a longer emitted light wavelength range, the third pixel light-transmitting area P3, which has a smaller emitted light wavelength range, has a lower brightness. This can effectively reduce the sensitivity of the human eye to the second blocking structure Z2 and reduce the brightness difference between the positions with and without spacers in the third pixel light-transmitting area P3, making the brightness distribution more uniform throughout the pixel area, thereby reducing the screen door effect and improving the visual effect.

[0192] In this embodiment, the spacer can be placed in the gap between the light-transmitting areas of adjacent blue pixels, effectively reducing the human eye's sensitivity to compensation from occlusions (such as black matrices) caused by the spacer (blue pixels are brighter than green and red pixels, so placing the spacer in the gap between the light-transmitting areas of adjacent blue pixels results in a smaller visual difference in brightness compared to placing it on green and red pixels). Furthermore, a second occlusion structure Z2 can be provided in the location between adjacent blue pixels without the spacer, reducing the brightness difference between the locations with and without the spacer, making the brightness distribution more uniform across the entire pixel area, thereby reducing the screen-door effect and improving the visual effect.

[0193] In one possible implementation, the wavelength range of light emitted from the third pixel light-transmitting area P3 can be greater than the wavelength range of light emitted from the first pixel light-transmitting area P1, and also greater than the wavelength range of light emitted from the second pixel light-transmitting area P2. Specifically, the third pixel light-transmitting area P3 can be a red pixel light-transmitting area, the first pixel light-transmitting area P1 can be a blue pixel light-transmitting area, and the second pixel light-transmitting area P2 can be a green pixel light-transmitting area. That is, a second blocking structure Z2 can be provided in the gap between at least some of the adjacent two red pixel light-transmitting areas, and a spacer can be placed in the gap between the adjacent two red pixel light-transmitting areas.

[0194] In one possible implementation, combined with Figure 10C As shown, the first blocking structure Z1 and the second blocking structure Z2 are alternately distributed along the first direction X in the orthographic projection of the substrate 11. Specifically, the first blocking structure Z1 and the second blocking structure Z2 can be located in the same column upwards, such as both being located in the column upwards where the light-transmitting area P3 of the third pixel is located.

[0195] In one possible implementation, the orthographic projection shape of the first shielding structure Z1 onto the substrate 11 can be the same as the orthographic projection shape of the spacer onto the substrate 11. For example, the orthographic projection shape of the spacer onto the substrate 11 can be hexagonal, octagonal, circular, or elliptical; the orthographic projection shape of the first shielding structure Z1 onto the substrate 11 can also be hexagonal, octagonal, circular, or elliptical.

[0196] Specifically, the orthographic projection shape of the second shielding structure Z2 onto the substrate 11 can be rectangular. The maximum length of the second shielding structure Z2 in the first direction X can be greater than the maximum length in the second direction Y.

[0197] Specifically, the ratio of the maximum length h2 of the second blocking structure Z2 in the first direction X to the maximum length h1 of the first blocking structure Z1 in the first direction X is greater than or equal to 0.78.

[0198] Specifically, the orthographic projection of the second shielding structure Z2 onto the substrate 11 is a rectangle, and the maximum length h2 of the second shielding structure Z2 in the first direction X can be the length of the vertical side of the rectangle along the first direction X; the orthographic projection of the first shielding structure Z1 onto the substrate 11 is an octagon, and the maximum length h1 of the first shielding structure Z1 in the first direction X can be the distance between two opposite sides of the octagon that are parallel to the second direction Y.

[0199] In one possible implementation, see Figure 10C As shown, in the row H of the pixel light-transmitting area, the first pixel light-transmitting area P1, the second pixel light-transmitting area P2, and the third pixel light-transmitting area P3 are arranged sequentially along the second direction Y; the pixel light-transmitting areas P with the same emitted light wavelength range are located on the same first direction X, that is, the first pixel light-transmitting area P1 is located in the same column, the second pixel light-transmitting area P2 is located in the same column, and the third pixel light-transmitting area P3 is located in the same column.

[0200] In one possible implementation, the maximum length h2 of the second shielding structure Z2 in the first direction X can be in the range of 8μm to 12μm, specifically, for example, 8μm, 9μm, 10μm, 10.5μm, 11μm, 12μm; the maximum length h1 of the first shielding structure Z1 in the first direction X can be in the range of 10μm to 15μm, specifically, for example, 10μm, 11μm, 12μm, 13μm, 13.5μm, 14μm, 15μm; the maximum length h3 of the third metal wire main portion M310 in the first direction X can be in the range of 5μm to 10μm, specifically, for example, 5μm, 6μm, 7μm, 7.5μm, 8μm, 9μm, 10μm.

[0201] In one possible implementation, see Figure 11 and Figure 12As shown, the array substrate also includes a second active layer C2 located on the side of the first active layer C1 facing the substrate 11, a driving source drain (including driving source MQ2 and driving drain MQ3) located on the side of the second active layer C2 away from the substrate 11, and a driving gate MQ1. Specifically, the array substrate may include a gate driving circuit for the non-display area BB. The gate driving circuit board includes a plurality of second transistors, each of which may include a second active layer C2, a driving source drain (including driving source MQ2 and driving drain MQ3), and a driving gate MQ1. In this embodiment, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology to integrate both LTPS (Low Temperature Poly-Silicon) and Oxide (oxide) TFTs (Thin Film Transistors), enabling AR and VR products to have high resolution (PPI, Pixel Per Inch), high aperture ratio, and high transmittance.

[0202] In one possible implementation, see Figure 11 and Figure 12 As shown, the array substrate also includes the following located in the non-display area BB: a first driving electrode MD1, a second driving electrode MD2, a third driving electrode MD3, and a fourth driving electrode MD4, wherein the first driving electrode MD1 is electrically connected to the second driving electrode MD2, and the third driving electrode MD3 is electrically connected to the fourth driving electrode MD4. Specifically, the first driving electrode MD1 can serve as a first signal line, and the third driving electrode MD3 can serve as a second signal line. The first signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer; the second signal line may include a signal line electrically connected to the gate driving circuit, and / or a signal line electrically connected to a multiplexer. The first signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line. The second signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light emission control line.

[0203] In one possible implementation, see Figure 11As shown, the second active layer C2 is located between the third metal layer M3 and the substrate 11; the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the first metal layer M1. In this embodiment, the driving gate MQ1 is located in the third metal layer M3, and the driving source and drain are located in the first metal layer M1. This allows for the simultaneous formation of the third metal layer M3 and the first metal layer M1 in the display area AA, as well as the corresponding driving gate MQ1 and driving source and drain in the non-display area, simplifying the manufacturing process of the display panel.

[0204] In one possible implementation, see Figure 11 As shown, the first driving electrode MD1 and the third driving electrode MD3 can be located in the first metal layer M1; the second driving electrode MD2 can be located in the third metal layer M3; and the fourth driving electrode MD4 can be located in the second metal layer M2. Thus, while forming the first metal layer M1 of the display area AA, the corresponding first driving electrode MD1 and the third driving electrode MD3 of the non-display area can be formed; while forming the second metal layer M2 of the display area AA, the corresponding fourth driving electrode MD4 of the non-display area can be formed; and while forming the third metal layer M3 of the display area AA, the corresponding second driving electrode MD2 of the non-display area can be formed, which can simplify the manufacturing process of the display panel.

[0205] In one possible implementation, at least a portion of the traces of the second metal layer M2 and at least a portion of the traces of the third metal layer M3 can be electrically connected in the non-display area BB. For example, the second metal line M21 and the third metal line M31 can be electrically connected in the non-display area BB to enable the transistors in the display area AA to form a dual-gate structure.

[0206] In one possible implementation, see Figure 12 As shown, the second active layer C2 is located between the third metal layer M3 and the first active layer C1; the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the second metal layer M2; and the driving gate MQ1 is located in the third metal layer M3. In this embodiment, the driving source and drain are located in the second metal layer M2, and the driving gate MQ1 is located in the third metal layer M3. This allows for the simultaneous formation of the third metal layer M3 and the second metal layer M2 in the display area AA, as well as the corresponding driving gate MQ1 and driving source / drain in the non-display area, simplifying the manufacturing process of the display panel.

[0207] In one possible implementation, see Figure 12As shown, the first driving electrode MD1 can be located in the first metal layer M1; the second driving electrode MD2 can be located in the second metal layer M2; and the third driving electrode MD3 can be located in the third metal layer M3. Thus, while forming the first metal layer M1 of the display area AA, the corresponding first driving electrode MD1 of the non-display area can be formed; while forming the second metal layer M2 of the display area AA, the corresponding second driving electrode MD2 of the non-display area can be formed; and while forming the third metal layer M3 of the display area AA, the corresponding third driving electrode MD3 of the non-display area can be formed, which can simplify the manufacturing process of the display panel.

[0208] In one possible implementation, combined with Figure 11 , Figures 13A-13C As shown, where, Figure 13B for Figure 13A The corresponding pattern of the third conductive layer, Figure 13B It can also be Figure 13C A partial schematic diagram of the area within the dashed box, namely... Figure 13C for Figure 13B In a larger schematic diagram, the array substrate further includes a third conductive layer D3 located on the side of the second conductive layer D2 facing away from the substrate. The third conductive layer D3 includes multiple cutouts L, the portion of which, when projected onto the substrate 11, overlaps with a portion of the first electrode D21 on the substrate 11. In this embodiment, the array substrate further includes a third conductive layer D3, which includes multiple cutouts L. The portion of which, when projected onto the substrate 11, overlaps with a portion of the first electrode D21 on the substrate 11, allowing the first electrode D21 and the third conductive layer D3 to form an edge electric field at the cutouts L, thereby driving the liquid crystal deflection. In this embodiment, the driving mode of the display panel can be a novel Fringe Field Switching (FFS) mode, or an Advanced Super Dimension Switching (ADS) mode.

[0209] It should be noted that, Figure 13A To clearly illustrate the various film layers, only the hollowed-out L-shape of the third conductive layer D3 is shown. The complete pattern of the third conductive layer D3 can be seen as follows: Figure 13B As shown, Figure 13B Larger areas of patterns can be like Figure 13C As shown.

[0210] Specifically, the third conductive layer D3 can be a common electrode layer, forming an electric field with the first electrode D21, thereby driving the liquid crystal molecules between the array substrate and the opposing substrate.

[0211] In one possible implementation, the third conductive layer D3 may include: a plurality of hollow rows extending along a first direction X and arranged along a second direction Y; the hollow rows include: a plurality of hollows L arranged sequentially along the first direction X. In one possible implementation, combined with Figures 13A-13C As shown, the hollowed-out L can correspond one-to-one with the first electrode D21.

[0212] In one possible implementation, the portion of the cutout L projected onto the substrate 11 overlaps with the portion of the first metal line M11 projected onto the substrate 11; in one possible implementation, the portion of the cutout L projected onto the substrate 11 overlaps with the portion of the third metal line M31 projected onto the substrate 11; in one possible implementation, the portion of the cutout L projected onto the substrate 11 overlaps with the portion of the third metal line M31 projected onto the substrate 11.

[0213] In one possible implementation, the orthographic projection of the second metal line M21 onto the substrate 11 covers the orthographic projection of the gap between two adjacent cutout rows onto the substrate 11.

[0214] In one possible implementation, see Figure 11 and Figure 12 As shown, the array substrate further includes a fourth metal layer M4 located on the side of the third conductive layer D3 facing the substrate 11 and in contact with the third conductive layer D3; the fourth metal layer M4 includes a plurality of fourth metal lines M41 extending along the first direction X, the orthographic projection of the fourth metal lines M41 on the substrate 11 covering the orthographic projection of the first metal lines M11 on the substrate 11.

[0215] Specifically, the conductivity of the fourth metal layer M4 can be superior to that of the third conductive layer D3. Multiple fourth metal lines M41 on the array substrate that contact the third conductive layer D3 can reduce the resistance of the third conductive layer D3.

[0216] In one possible implementation, see Figure 11 As shown, the display panel may also include at least one of the following:

[0217] A buffer layer 12 is located between the substrate 11 and the second active layer C2;

[0218] The second gate insulating layer 13 is located between the second active layer C2 and the third metal layer M3;

[0219] The third interlayer dielectric layer 14 is located between the third metal layer M3 and the first active layer C1;

[0220] The first gate insulating layer 15 is located between the first active layer C1 and the second metal layer M2;

[0221] A first interlayer dielectric layer 16 is located between the second metal layer M2 and the first metal layer M1;

[0222] The second interlayer dielectric layer 17 is located between the first metal layer M1 and the first conductive layer D1;

[0223] A first planarization layer 18 located between the first conductive layer D1 and the second conductive layer D2;

[0224] The second planarization layer 19 is located between the second conductive layer D2 and the fourth metal layer M4.

[0225] In some examples, at least one of the buffer layer 12, the second gate insulating layer 13, the third interlayer dielectric layer 14, the first gate insulating layer 15, the first interlayer dielectric layer 16, the second interlayer dielectric layer 17, the first planarization layer 18, and the second planarization layer 19 can be an inorganic insulating layer, for example, it can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer.

[0226] In one possible implementation, the material of the first active layer C1 includes a rare-earth element-doped metal oxide. Specifically, the material of the first active layer C1 is a metal oxide semiconductor material, which may include any one or more of the following: amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare-earth element-doped metal oxides (RE-OS). The rare-earth element-doped metal oxide may include lanthanide-doped metal oxides (Ln-OS). The crystallization state of the active layer material can be amorphous, partially crystalline, or polycrystalline. In this embodiment, the material of the first active layer C1 is a rare-earth element-doped metal oxide. The first active layer C1 can maintain stable performance even when exposed to light, thus eliminating the need for a light-shielding layer in the light-transmitting area P and further improving the aperture ratio of the display panel. In this embodiment of the disclosure, the first active layer C1 of the display area transistor can be an oxide active layer, that is, thin film transistors with oxide active layers have advantages such as low leakage current.

[0227] In one possible implementation, the material of the second active layer C2 includes low-temperature polysilicon. That is, considering that the current high-migration oxide gate drive circuit design is not mature enough, which would result in large transistor sizes in the gate drive circuit and excessively large bezels, in this embodiment, a low-temperature polysilicon transistor design can be used in the gate drive circuit of the non-display area.

[0228] In this embodiment, the first active layer C1 of the first transistor in the display area can be an oxide active layer, and the second active layer C2 of the second transistor in the non-display area can be a polycrystalline silicon active layer. Since oxide thin-film transistors have advantages such as low leakage current, and low-temperature polycrystalline silicon thin-film transistors have advantages such as high mobility and fast charging, integrating low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors onto a single display panel forms a low-temperature polycrystalline oxide display panel. Utilizing the advantages of both, high resolution (Pixels Per Inch, PPI) and low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved. For example, the array substrate provided in this embodiment combines the high mobility and narrow bezel of the second transistor using polycrystalline silicon as the second active layer C2 with the high transmittance of the first transistor using metal oxide semiconductor material as the first active layer C1. When this array substrate is used in a display panel, the display effect of virtual reality can be further improved.

[0229] In one possible implementation, the first active layer C1 and the second active layer C2 can also be the same layer and made of the same material. Specifically, both the first active layer C1 and the second active layer C2 can be oxide active layers. For example, the materials of the first active layer C1 and the second active layer C2 can include: amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO). In this embodiment, when both the active layers of the transistors in the display area and the non-display area are oxide active layers, the second transistor in the non-display area and the first transistor in the display area can both adopt an oxide double-gate structure, and the bottom gate size of the second transistor in the non-display area is larger than the top gate size (the single-sided wrapping size can be 0.5μm to 2μm), which can effectively improve the on-state current and device stability of the second transistor in the non-display area. For the first transistor in the display area, the bottom gate size can be smaller than the top gate size (the bottom gate is 0.3μm to 0.6μm smaller on one side than the top gate), which can avoid the influence on the aperture ratio.

[0230] In one possible implementation, the material of the first conductive layer D1 may include: metal oxides (e.g., indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0231] In one possible implementation, the material of the second conductive layer D2 may include: metal oxides (e.g., indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0232] In one possible implementation, the material of the third conductive layer D3 may include: metal oxides (e.g., indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0233] In one possible implementation, at least two of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 are made of the same material. In another possible implementation, the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 may also be made of different materials.

[0234] In one possible implementation, at least one of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may be made of any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0235] In one possible implementation, at least two of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are made of the same material. In another possible implementation, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may also be made of different materials.

[0236] In some examples, the substrate 11 can be a flexible substrate or a rigid substrate. For example, a rigid substrate may include a glass substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si). However, the embodiments disclosed herein are not limited in this respect.

[0237] Based on the same inventive concept, this disclosure also provides a display panel, which includes an array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate.

[0238] In one possible implementation, the opposing substrate may include an opposing substrate, a black matrix located on one side of the opposing substrate, and an optical adhesive layer located on the side of the black rectangle opposite to the opposing substrate.

[0239] In one possible implementation, the display panel further includes a color filter layer; the color filter layer may be located on an opposing substrate, or the color filter layer may be located on an array substrate.

[0240] Figure 14 This is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure. In some examples, such as... Figure 14 As shown, the display panel may include a timing controller 20, a data driver 40, a gate driving circuit, and a sub-pixel array 10. The gate driving circuit may include at least one driver, such as a scan driver 30. The timing controller 20, the data driver 40, and the gate driving circuit may be located in a non-display area surrounding the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of regularly arranged sub-pixels PX. The scan driver 30 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 40 may be configured to provide data signals to the sub-pixels PX along data lines; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0241] In some examples, timing controller 20 can provide grayscale values ​​and control signals of specifications suitable for data driver 40 to data driver 40; timing controller 20 can provide clock signals, initial signals, etc., of specifications suitable for scan driver 30 to scan driver 30. Data driver 40 can use the grayscale values ​​and control signals received from timing controller 20 to generate data voltages to be provided to data lines D1 to Dn. For example, data driver 40 can sample grayscale values ​​using a clock signal and apply data signals corresponding to grayscale values ​​to data lines D1 to Dn on a sub-pixel line basis. Scan driver 30 can use clock signals, initial signals, etc., received from timing controller 20 to generate scan signals to be provided to scan lines G1 to Gm. For example, scan driver 30 can sequentially provide scan signals with on-level pulses to scan lines. In some examples, scan driver 30 may include a shift register that can generate scan signals by sequentially transmitting scan initial signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. Here, n and m are both natural numbers.

[0242] In some examples, the gate driver circuitry can be directly disposed on the substrate. For example, the gate driver can be disposed in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel during the sub-pixel formation process. However, this embodiment does not limit the location or formation method of the gate driver. In some examples, the gate driver can be disposed on a separate chip or printed circuit board to connect to pads or solder pads formed on the substrate.

[0243] In some examples, the data driver 40 may be disposed on a separate chip or printed circuit board to connect to the sub-pixel PX via signal access pins disposed on the substrate. For example, the data driver 40 may be formed using a chip-on-glass, chip-on-plastic, or chip-on-film configuration to connect to signal access pins on the substrate. The timing controller 20 may be disposed separately from or integrated with the data driver 40. However, this embodiment is not limited to this.

[0244] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0245] In this embodiment, the minimum distance a between the orthographic projection of the conductive portion D11 onto the substrate 11 and the minimum distance b between the orthographic projection of the first sub-metal line MA onto the substrate 11 and the first sub-metal line MB onto the substrate 11 is greater than the minimum distance b between the orthographic projection of MA onto the second sub-metal line MB onto the substrate 11. This increases the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C. dp2 And due to the first coupling capacitor C dp1 In the middle, the first active pattern C11 and the conductive part D11 overlap with a capacitor (such as... Figure 5D The area shown in the thick solid line frame S occupies the main part, and the distance between the conductive part D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C. dp1 This has a significant impact, thereby reducing the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The difference in these characteristics improves the vertical crosstalk problem.

[0246] It should be noted that, in this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0247] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0248] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate having a display area and a non-display area located around the periphery of the display area, wherein, include: Substrate; A first active layer, located on one side of the substrate, includes: a plurality of first active patterns located in the display area; the first active pattern includes: a first portion extending along a first direction, and a second portion extending from one end of the first portion; The first metal layer includes: a plurality of first metal lines extending along a first direction; the orthographic projection of the first portion on the substrate is located between the orthographic projections of adjacent first metal lines on the substrate, and the portion of the second portion projected onto the substrate overlaps with the portion of the first metal line projected onto the substrate. The first conductive layer includes: a plurality of conductive portions located in the display area; at least one of the plurality of conductive portions, in its orthographic projection on the substrate, is located between the orthographic projections of adjacent first metal lines on the substrate. The second conductive layer includes: a plurality of first electrodes located in the display area; The first metal line on both sides adjacent to the conductive portion includes a first sub-metal line and a second sub-metal line; wherein the first sub-metal line is electrically connected to the second portion; the first portion is electrically connected to the first electrode through the conductive portion; the distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second sub-metal line on the substrate.

2. The array substrate as claimed in claim 1, wherein, The conductive part, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 15%≤b / a≤75%, where a represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal line on the substrate, and b represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the second sub-metal line on the substrate.

3. The array substrate as described in claim 2, wherein, The conductive part, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 3%≤(ab) / c≤15%, where c represents the minimum spacing between adjacent first and second sub-metal lines.

4. The array substrate as claimed in claim 3, wherein, The conductive part, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 60%≤d / c≤95%, where d represents the length of the conductive part in the direction perpendicular to the first direction.

5. The array substrate according to any one of claims 1-4, wherein, The first part has a first axis of symmetry extending along the first direction, and the conductive part has a second axis of symmetry extending along the first direction. The second axis of symmetry is located on the side of the first axis of symmetry away from the first sub-metal wire.

6. The array substrate according to any one of claims 1-4, wherein, The first electrode has a first outer edge extending along the first direction; between two adjacent first metal lines, the portion of the first outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate away from the first sub-metal line. The conductive portion has a second outer edge extending along the first direction; between two adjacent first metal lines, the portion of the second outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate away from the first sub-metal line. Between two adjacent first metal lines, the portion of the second outer edge projected onto the substrate is located on the side of the first outer edge that is away from the first sub-metal line.

7. The array substrate as claimed in claim 6, wherein, The first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line. The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal lines, the portion of the fourth outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line. Between two adjacent first metal lines, the portion of the fourth outer edge projected onto the substrate is located on the side of the third outer edge projected onto the substrate away from the first sub-metal line.

8. The array substrate as claimed in claim 6, wherein, The first electrode has a third outer edge extending along the first direction; between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line. The conductive portion has a fourth outer edge extending along the first direction; between two adjacent first metal lines, the portion of the fourth outer edge projected onto the substrate is located on the side of the first portion projected onto the substrate closer to the first sub-metal line. Between two adjacent first metal lines, the portion of the third outer edge projected onto the substrate coincides with the portion of the fourth outer edge projected onto the substrate.

9. The array substrate according to any one of claims 1-4, wherein, The array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal lines extending along a second direction; The first part includes: a first sub-part, a second sub-part, and a third sub-part distributed sequentially along the first direction; wherein the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the second metal line on the substrate; the first sub-part is located on the side of the second sub-part facing the second part, and the third sub-part is located on the side of the second sub-part away from the second part; The orthographic projection of the first sub-part onto the substrate overlaps with the orthographic projection of the conductive part onto the substrate.

10. The array substrate according to any one of claims 1-4, wherein, The array substrate further includes: a second metal layer located between the first active layer and the first conductive layer, the second metal layer including: a plurality of second metal lines extending along a second direction; the second part including: a fourth sub-part connected to the first part and extending along a third direction, and a fifth sub-part connected to the fourth sub-part, the first metal lines being electrically connected to the fifth sub-part; the second direction intersects the first direction, and the third direction intersects the first direction; The conductive portion includes: a fifth outer edge extending along the second direction and toward the fifth sub-portion; The orthographic projection of the second metal line onto the substrate covers the orthographic projection of the fifth outer edge onto the substrate.

11. The array substrate as claimed in claim 10, wherein, The second metal wire has a sixth outer edge extending along the second direction and toward the fifth sub-part; the distance between the orthographic projection of the sixth outer edge onto the substrate and the orthographic projection of the fifth outer edge onto the substrate in the first direction is one-fifth to four-fifths of the length of the orthographic projection of the second metal wire onto the substrate in the first direction.

12. The array substrate as claimed in claim 10, wherein, The second metal wire has a sixth outer edge extending along the second direction and toward the fifth sub-part; The orthographic projection of the sixth outer edge onto the substrate is located on the side where the orthographic projection of the fifth outer edge onto the substrate faces the orthographic projection of the fifth sub-part onto the substrate.

13. The array substrate according to any one of claims 1-4, wherein, The first conductive layer is located on the side of the first active layer that is away from the substrate; The array substrate further includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via penetrating the first insulating layer, wherein the conductive portion is electrically connected to the first portion through the first via; Between two adjacent first metal lines, the minimum distance between the center of the first via in the orthographic projection of the substrate and the minimum distance between the first sub-metal line in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate is greater than the minimum distance between the first via and the second sub-metal line in the orthographic projection of the substrate.

14. The array substrate as claimed in claim 13, wherein, The first electrode is located on the side of the first conductive layer that faces away from the substrate; The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via; Between two adjacent first metal lines, the minimum distance between the center of the second via in the orthographic projection of the substrate and the minimum distance between the first sub-metal line in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate is greater than the minimum distance between the second via and the second sub-metal line in the orthographic projection of the substrate.

15. The array substrate as claimed in claim 14, wherein, At least a portion of the orthographic projection of the first via on the substrate does not overlap with at least a portion of the orthographic projection of the second via on the substrate.

16. The array substrate as claimed in claim 13, wherein, The first insulating layer comprises one or a combination of the following: First gate insulating layer; First interlayer dielectric layer; Second interlayer dielectric layer.

17. The array substrate as claimed in claim 16, wherein, The thickness of at least one of the first gate insulating layer, the first interlayer dielectric layer, and the second interlayer dielectric layer is greater than 3000 Å.

18. The array substrate as claimed in claim 9, wherein, The array substrate further includes a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes a plurality of third metal lines extending along the second direction, the orthogonal projection of the third metal lines on the substrate covering the orthogonal projection of the second metal lines on the substrate.

19. The array substrate as claimed in claim 18, wherein, The array substrate includes: a plurality of pixel light-transmitting areas, the plurality of pixel light-transmitting areas including: a plurality of rows of pixel light-transmitting areas extending along the first direction and arranged along the second direction; at least one of the plurality of rows of pixel light-transmitting areas includes: a first pixel light-transmitting area, a second pixel light-transmitting area, and a third pixel light-transmitting area; the wavelength range of light emitted from the third pixel light-transmitting area is smaller than the wavelength range of light emitted from the first pixel light-transmitting area and smaller than the wavelength range of light emitted from the second pixel light-transmitting area; The third metal line includes: a main portion of the third metal line extending along the second direction, and a first shielding structure connected to the main portion of the third metal line; the maximum length of the first shielding structure in the first direction is greater than the maximum length of the main portion of the third metal line in the first direction; the orthographic projection of the first shielding structure onto the substrate is located in the gap between at least two adjacent orthographic projections of the third pixel light-transmitting areas onto the substrate in the first direction.

20. The array substrate as claimed in claim 19, wherein, The array substrate further includes: a spacer; the orthographic projection of the first shielding structure onto the substrate covers the orthographic projection of the spacer onto the substrate.

21. The array substrate as claimed in claim 19, wherein, The third metal wire further includes: a second shielding structure connected to the main part of the third metal wire; the maximum length of the second shielding structure in the first direction is greater than the maximum length of the main part of the third metal wire in the first direction, and less than the maximum length of the first shielding structure in the first direction; The orthographic projection of the second shielding structure onto the substrate is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas onto the substrate in the second direction, and the orthographic projection of the second shielding structure onto the substrate does not overlap with the orthographic projection of the first shielding structure onto the substrate.

22. The array substrate as claimed in claim 18, wherein, The array substrate further includes, in the non-display area: a second active layer located on the side of the first active layer facing the substrate, a driving source drain located on the side of the second active layer away from the substrate, and a driving gate.

23. The array substrate as claimed in claim 22, wherein, The material of the first active layer includes: metal oxide; the material of the second active layer includes: low-temperature polycrystalline silicon.

24. The array substrate as claimed in claim 22 or 23, wherein, The second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; and the driving source drain is located in the first metal layer.

25. The array substrate as claimed in claim 24, wherein, The second active layer is located between the third metal layer and the first active layer; the driving source drain is located in the second metal layer; and the driving gate is located in the third metal layer.

26. The array substrate according to any one of claims 1-4, wherein, The array substrate further includes a third conductive layer located on the side of the second conductive layer opposite to the substrate. The third conductive layer includes a plurality of cutouts, and the portion of the cutouts projecting onto the substrate overlaps with the portion of the first electrode on the substrate.

27. The array substrate as claimed in claim 26, wherein, The array substrate further includes: a fourth metal layer located on the side of the third conductive layer facing the substrate and in contact with the third conductive layer; The fourth metal layer includes a fourth metal line extending along the first direction, wherein the orthographic projection of the fourth metal line onto the substrate covers the orthographic projection of the first metal line onto the substrate.

28. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-27, and further includes a counter substrate disposed opposite to the array substrate.

29. A display device, wherein, Includes the display panel as described in claim 28.

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