Multi-modular redundancy computer synchronization circuit and method based on TTE bus

Abstract

The invention relates to a multi-modular redundancy computer synchronization circuit and method based on a TTE bus. A local crystal oscillator provides basic frequency information P0 for a timer function module; the timer function module receives basic frequency information sent by the local crystal oscillator, and outputs a periodic synchronization signal L1 after frequency division processing; the TTE end node receives the TTE network synchronization instruction L0, converts the TTE network synchronization instruction L0 into a periodic synchronization signal L2 and outputs the periodic synchronization signal L2; the precision identification function module receives the L1 and the L2, judges the precision of the L2 by taking P0 provided by a local crystal oscillator as a reference source, and determines which path of periodic synchronization signal is output as an identified periodic synchronization signal L3 according to a preset strategy; and the synchronous two-out-of-three redundancy discrimination function module receives a periodic synchronization signal L3 output by the precision discrimination function module and synchronization signals L4 and L5 sent by an external redundancy CPU synchronization circuit, performs two-out-of-three voting on three paths of signals L3, L4 and L5, and outputs a final synchronization signal L6 to the CPU1 as a task periodic synchronization signal.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated design of control systems for manned launch vehicles, and relates to a multi-mode redundant computer synchronization circuit and method based on a TTE bus. Background Art

[0002] The launch vehicle control system mainly realizes the navigation, guidance and control of the rocket during flight, as well as related timing output control, tank pressurization control, propellant utilization control, engine thrust regulation control and power supply and distribution management functions.

[0003] Reliability is one of the primary design principles that a launch vehicle control system must consider. The onboard equipment of the control system usually solves the problem of reliable operation in the event of a single failure by configuring redundant configurations of the same functions, such as dual / triple redundant configurations of the system bus and triple redundant configurations of the equipment information processing module, which are all effective measures to improve system reliability.

[0004] While the use of triple redundant information processing modules improves system reliability, it also introduces new problems. That is, the triple redundant information processing modules need to perform information exchange and real-time calculations based on the same time base and the same beat, and shield the system abnormalities caused by the failure of a single information processing module through three-out-of-two redundancy or fault absorption. If the difference in the command operation of the three redundant information processing modules (hereinafter referred to as three machines) in the same control cycle is too large, it will affect the data exchange and other operations of the three machines. Therefore, how to achieve the synchronization of the redundant information processing modules in the device becomes the key to the normal operation of the redundancy mechanism.

[0005] The computer task cycle Tc is also called the control cycle. The computer task cycle refers to the time it takes for the computer module to complete a calculation and control output in a control system device that adopts a periodic control method. The computer task cycle is the difference between the start time t0 of the current computing task and the start time t1 of the next computer task cycle, that is, Tc = t1-t0.

[0006] The task cycle deviation δTc refers to the deviation value of the starting time of running the same computing task between multi-module computers. That is, if the starting time of running computing task A of computer module 1 is t0A1, and the starting time of running computing task A of computer module 2 is t0A2, the task cycle deviation δTc between the two is |t0A1-t0A2|.

[0007] The computer synchronization period Ts refers to the time interval between two synchronization signals received by a computer module when there are multiple groups of computer modules in the control system device or between devices that simultaneously perform calculations and control outputs.

[0008] By setting a reasonable computer synchronization period Ts and synchronization method, the task cycle deviation δTc can be reduced or eliminated as much as possible, which can effectively improve the synchronization of the redundant information processing module of the control system.

[0009] The launch vehicle control system usually achieves synchronization of data processing and output control between multiple redundant CPUs of the redundant information processing module (usually the onboard computer) in the following ways:

[0010] 1) Existing technical solution 1: Public external clock synchronization

[0011] All redundant computer CPU modules share a common clock source. Since all computer CPU modules are based on this clock source, each CPU is naturally synchronized.

[0012] This solution has simple configuration, high synchronization accuracy, and good consistency in phase and frequency. However, the synchronization source is often an external single point, so each CPU may fail due to a common cause of CPU synchronization caused by failure of the external synchronization source, affecting system reliability.

[0013] The use of public external clock synchronization has been applied in traditional launch vehicle models. Generally, control system equipment such as inertial groups are used as external frequency standards. The external frequency standard sends high-precision clock information to the three CPU modules of the onboard computer of the redundant rocket machine at the same time. The three CPUs all generate periodic interrupts based on the clock information as the starting point of the single-machine control cycle. Since the same clock source is used, the three machines can naturally achieve synchronization of information processing. However, this synchronization method is more dependent on the reliability of the external frequency standard. After the external frequency standard fails, the equipment cannot operate normally, which will have catastrophic consequences. At the same time, in order to ensure the accuracy after the external frequency standard is introduced, there are relatively strict restrictions on the cable type and transmission distance between the synchronization source and the equipment receiving the synchronization source. Generally, only a small number of devices are required to introduce the frequency source information, usually only the onboard computer. Therefore, this solution is limited to the scope of application in the launch vehicle control system.

[0014] 2) Existing technical solution 2: independent operation, limited system clock synchronization

[0015] All redundant computer CPUs use their own clock sources. Since each CPU clock is independent of each other, the frequency consistency and phase error are random.

[0016] Even if the redundant computer CPUs can be triggered and synchronized a limited number of times through system integration design methods, they can only maintain synchronization for a short time due to the frequency stability of different clock sources. The accumulated error of clock drift will eventually cause loss of synchronization, which will seriously affect the control system function.

[0017] At present, in the launch vehicle control system, except for the case of introducing an inertial device external frequency standard into the onboard computer in the existing technical solution 1, the clocks of different devices are operated independently. In order to avoid the influence of clock drift, the application software of each device needs to design a special data transmission asynchronous processing logic, which objectively increases the complexity of the system.

[0018] 3) Existing technical solution 3: local voting independent clock

[0019] All redundant computer CPUs have their own clock sources, but each CPU module votes on each other's clock sources to adjust the drift of a single clock source and finally obtain the clock used for the CPU module.

[0020] This synchronization solution can provide long-term clock synchronization between various CPU modules. The software design is relatively simple, and there is no need to consider redundancy management issues too much. However, synchronization circuits and synchronization voting circuits are configured in each single machine, and the function implementation is relatively complex. At the same time, in order to avoid external influences, synchronization circuits and synchronization voting circuits can often only be set inside a single machine, which is difficult to apply to multiple control system single machine devices, which also limits its application in situations where synchronization is required between multiple devices.

[0021] Currently, this synchronization solution is generally used between multiple CPU modules of onboard computers with redundant functions in launch vehicles. Summary of the invention

[0022] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to propose a multi-mode redundant computer synchronization circuit and method based on the TTE bus, and to improve the overall synchronization accuracy and reliability of the long-term operation between the equipment of the entire control system of the launch vehicle and within the TTE network equipment by introducing the TTE bus clock into each network device including the computer module (information processing module) of the launch vehicle control system as a global reference clock.

[0023] The solution to the technical problem of the present invention is: a multi-mode redundant computer synchronization circuit based on a TTE bus, wherein the multi-mode redundant computer has three CPU1 synchronization circuits, CPU2 synchronization circuits, and CPU3 synchronization circuits with the same structure, each of which includes a local crystal oscillator, a timer function module, a TTE end node, an accuracy identification function module, and a synchronization three-out-of-two redundancy discrimination function module;

[0025] The local crystal oscillator provides basic frequency information P0 for the timer function module;

[0026] The timer function module receives the basic frequency information sent by the local crystal oscillator, and outputs the periodic synchronization signal L1 after frequency division processing;

[0027] The TTE end node receives the TTE network synchronization instruction L0 and converts it into a periodic synchronization signal L2 for output;

[0028] The precision identification function module receives the periodic synchronization signals L1 and L2, uses the basic frequency information P0 provided by the local crystal oscillator as the reference source, determines the precision of the periodic synchronization signal L2, and determines which periodic synchronization signal to output as the identified periodic synchronization signal L3 according to the preset strategy;

[0029] The synchronous three-out-of-two redundant discrimination function module receives the periodic synchronization signal L3 output by the accuracy identification function module, and the synchronization signals L4 and L5 sent by the external redundant CPU synchronization circuit. After performing a two-out-of-three vote on the three signals L3, L4, and L5, it outputs the final synchronization signal L6 to CPU1 as the task periodic synchronization signal.

[0030] Furthermore, the periodic synchronization signal L3 output by the CPU1 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_1, L32_1, and L33_1, L31_1 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_1 and L33_1 are respectively used as input signals of the external CPU2 and CPU3 synchronization circuits;

[0031] The synchronization signal L4 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_3 output by the CPU3 synchronization circuit precision identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_2 output by the CPU2 synchronization circuit precision identification function module;

[0032] The periodic synchronization signal L3 output by the CPU2 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_2, L32_2, and L33_2. L31_2 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_2 and L33_2 are respectively used as input signals of the external CPU1 and CPU3 synchronization circuits;

[0033] The synchronization signal L4 sent by the external redundant CPU synchronization circuit received by the CPU2 synchronization circuit is the periodic synchronization signal L32_1 output by the CPU1 synchronization circuit precision identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit received by the CPU2 synchronization circuit is the periodic synchronization signal L33_3 output by the CPU3 synchronization circuit precision identification function module;

[0034] The periodic synchronization signal L3 output by the CPU3 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_3, L32_3, and L33_3. L31_3 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_3 and L33_3 are respectively used as input signals of the external CPU1 and CPU2 synchronization circuits;

[0035] The synchronization signal L4 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_2 output by the CPU2 synchronization circuit accuracy identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_1 output by the CPU1 synchronization circuit accuracy identification function module.

[0036] A multi-mode redundant computer synchronization method based on a TTE bus, comprising steps of a multi-mode redundant CPU synchronization method inside a TTE network device and steps of a synchronization signal source selection method inside a TTE network device;

[0037] The method for synchronizing a multi-mode redundant CPU in a TTE network device includes the following steps:

[0038] 1) Setting the synchronization cycle: The synchronization cycle of the three redundant CPUs of the network equipment is consistent with the task cycle, which is recorded as Ts. The control system completes a network data interaction once per task cycle, and the TTE bus network synchronization instruction sending cycle is set to be consistent with the task cycle, that is, Tb = Ts;

[0039] 2) After the device is powered on or reset, each CPU function is initialized, the local crystal oscillator in the synchronization circuit starts working, and outputs the basic frequency information P0;

[0040] 3) The timer module randomly defines the zero time ti, and according to the basic frequency information sent by the local crystal oscillator, when the timing reaches the time ti+10ms, it outputs the synchronization signal L1 consistent with the task cycle;

[0041] 4) The precision identification function module directly outputs the input synchronization signal L1, and the output end synchronization signal is defined as L3. L3 is divided into three paths L31_i, L32_i, and L33_i, i∈{1, 2, 3}, which are output to the local and other two groups of CPU synchronization circuit synchronization three-out-of-two redundant identification function modules respectively;

[0042] 5) Define the synchronization signals independently input by the two groups of external input information processing modules as L4 and L5. The synchronization three-out-of-two redundant discrimination function module performs a three-out-of-two vote on the synchronization signal after receiving the local synchronization signal L31_i and the external synchronization signals L4 and L5, and uses the voting result L6 as the CPU1 task cycle synchronization signal. After receiving L6, CPU1 starts the calculation output of this cycle;

[0043] 6) At the same time, the L6 signal is sent back to the timer function module, and the timer function module redefines the time when L6 is received as ti, and starts the next synchronization timing;

[0044] The method for selecting a synchronization signal source inside a TTE network device comprises the following steps:

[0045] After CPU1 is initially powered on, according to the TTE network device internal multi-mode redundant CPU synchronization method, the synchronization signal L6 after two-out-of-three voting of the local crystal oscillator is used as the synchronization source;

[0046] After the TTE bus network is powered on, the TTE bus continuously sends the network synchronization signal L0 to the TTE end node at a theoretical period Tb. The TTE end node converts L0 into an L2 synchronization signal and sends it to the accuracy identification module.

[0047] The host computer in the TTE network sends a synchronization source switching instruction to network devices including multi-mode redundant computers through the TTE network. After CPU1 receives the instruction, the accuracy identification module starts the long-cycle timing. Within the long-cycle timing time range, the accuracy identification module continues to judge the accuracy of L0;

[0048] After the long period timing ends, if CPU1 switches L2 as the local synchronization signal L3 output, the synchronization signal source accuracy monitoring and dynamic switching operations are continuously performed;

[0049] When each CPU receives the synchronization source switching instruction and switches to select the local TTE synchronization source, it continuously monitors the TTE synchronization source accuracy. If the number of times the TTE synchronization source signal L2 is monitored within a 1s period is less than the preset value, or the number of times the TTE synchronization source signal L2 accuracy deviation is monitored within a 1s period exceeds the preset percentage, it switches to the synchronization source L1 generated by the local timer as the input for redundant judgment, and no longer uses the synchronization signal input by the TTE end node. Otherwise, it continues to use the network synchronization signal L2 as the synchronization signal L3 output.

[0050] Furthermore, in addition to being used to generate a periodic synchronization signal, the basic frequency information P0 is also used as a clock signal for various circuits of the CPU including a precision identification function.

[0051] Furthermore, the method of performing two-out-of-three voting of synchronization signals is as follows:

[0052] A) define the initial timeout parameter Td, the value of which is consistent with the synchronization period;

[0053] B) When any of the three synchronization signal input channels of the synchronization three-out-of-two redundant discrimination function module receives a synchronization signal, the built-in synchronization timer Tick is started, and the channel is recorded as channelA. At this time, the synchronization three-out-of-two redundant discrimination function module does not output;

[0054] C) If the synchronization signal from any of the two channels except channelA is received before the Tick timer value is less than the timeout parameter Td, it is considered that the synchronization three-out-of-two redundancy judgment condition is met, and this time is recorded as tss. The synchronization signal input is shielded, and the voting synchronization signal L6 is output at time tss. The built-in synchronization timer is reset. After the reset is successful, the shielding of the synchronization signal input is cancelled;

[0055] D) If no synchronization signal is received from any channel input except channelA before the Tick timer reaches the timeout parameter Td, then when the timer reaches Td, L6 is directly output without voting.

[0056] Furthermore, the long-cycle timing time Ts'=100Ts is set.

[0057] Furthermore, the accuracy identification module continuously determines the accuracy of L0, and the determination method is as follows:

[0058] Initialize parameters p=0, q=0;

[0059] The precision identification module records the time t0 when the network synchronization signal L2 is first received after receiving the synchronization source switching instruction;

[0060] Before the long-period timing ends, the accuracy identification module records the time t1, t2, ..., t2 of each time the network synchronization signal L2 is received. j+1 , and calculate the time interval Δt = t j+1 -t j ; If Δt∈[Ts-0.1ms,Ts+0.1ms], then the p value increases by 1. Then the q value increases by 1;

[0061] After the long period timing ends, stop counting p and q;

[0062] Determine the q count value: if q=0, and p>preset value, the precision identification module closes the L1 synchronization signal path, opens the L2 synchronization signal path, and completes the selection and switching of the synchronization source input; if q>0, the input L1 synchronization signal is maintained as the local synchronization signal L3 output;

[0063] After the long-cycle timing ends, if the CPU maintains the synchronization signal L1 as the local synchronization signal L3 output, the dynamic switching operation of the synchronization signal source will no longer be performed; if the CPU switches L2 as the local synchronization signal L3 output, the synchronization signal source accuracy monitoring and dynamic switching operation will continue to be performed.

[0064] Furthermore, the synchronization method is applicable to computers with non-redundant configurations. In this case, the two-out-of-three redundant discrimination function module is cancelled, and the multi-mode synchronization signal sent by the redundant CPU is no longer received, and the synchronization output signal generated by the local computer is no longer sent to other redundant CPUs. After the local accuracy identification module performs accuracy identification on the TTE network signal, the local crystal oscillator synchronization signal L1 or the TTE network synchronization signal L2 is directly output as the final synchronization signal L3.

[0065] The beneficial effects of the present invention compared with the prior art are:

[0066] The present invention utilizes the TTE bus network clock as a unified synchronization source for the network devices of the entire system, which is beneficial to reducing the requirements for the crystal oscillator indicators of the single-machine device itself, thereby reducing the design cost. At the same time, it can make use of the high-precision, low-jitter effect of the TTE bus network clock to improve the system-level synchronization accuracy of the control system, and realize control signal acquisition, navigation, guidance and control calculation, and output execution under unified time scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 Synchronize circuit composition and information flow for a single CPU;

[0068] Figure 2 Synchronize information flow for triple redundant CPU synchronization circuits;

[0069] Figure 3 A two-out-of-three voting method for synchronization signals of the precision identification function module;

[0070] Figure 4 Switch the synchronization source input to TTE network synchronization;

[0071] Figure 5 The synchronization source application situation when the information processing module 3 does not meet the synchronization source switching to the TTE network synchronization condition;

[0072] Figure 6 This is a schematic diagram of the whole network synchronization of the control system;

[0073] Figure 7 This is a schematic diagram of the whole network synchronization of the control system;

[0074] Figure 8 Switch the synchronization source input to TTE network synchronization for non-redundant devices. DETAILED DESCRIPTION

[0075] As a type of distributed time-triggered network, the TTE bus is designed with a high-precision clock synchronization mechanism to ensure the deterministic transmission of TT (time triggered) messages. This ensures that all network nodes are unified in the global clock, thereby reducing the transmission jitter of TT messages. Clock synchronization enables network end nodes to have a unified communication system time. TTE network nodes can perform time-triggered communication based on this unified time to ensure communication determinism. TTE end nodes maintain a periodic local counter, i.e., a local clock, based on the clock crystal oscillator. The power-on time of the nodes is inconsistent, resulting in the local clock being in a discrete state. The TTE clock synchronization mechanism can make the local clocks in the discrete state converge, realize the local clock synchronization of the end nodes, and correct the clock deviation caused by the crystal oscillator deviation during the communication process, so as to maintain the local clock deviation of any two nodes within the accuracy range, thus meeting the requirements of time-triggered communication. That is, the TTE network adopts a distributed clock synchronization method, transmits clock information between nodes through the interaction of synchronization frames, and runs a clock synchronization strategy in the nodes, so that the local clocks of all network nodes are established and maintained with high-precision synchronization.

[0076] Therefore, when TTE is used as a system bus, the clock synchronization mechanism of TTE itself can be used to use this network global clock as the system clock of the multi-machine redundant configuration, to achieve the synchronization of single-machine multi-mode redundant equipment and control system level equipment, and to integrate the advantages of high synchronization accuracy, simple implementation method, and long-term synchronization, thereby improving the clock synchronization accuracy and reliability of the entire control system and the purpose of long-term working robustness.

[0077] The present invention first designs a multi-mode redundant computer synchronization circuit based on TTE bus. The independent CPU (information processing module) synchronization circuit function module comprises: A: local crystal oscillator, B: timer function module; C: TTE end node; D: precision identification function module, E: synchronization three out of two redundant judgment function module, such as Figure 1 shown.

[0078] Among the components of the above synchronization circuit functional modules, A: local crystal oscillator and C: TTE end node are both implemented by independent chips or hardware circuits; the remaining modules can be implemented by independent hardware circuits or in FPGA logic.

[0079] in:

[0080] A: The local crystal oscillator provides basic frequency information P0 for the timer function module;

[0081] B: The timer function module receives the basic frequency information sent by the local crystal oscillator, and outputs the periodic synchronization signal L1 after frequency division processing;

[0082] C: The TTE end node receives the TTE network synchronization instruction L0 and converts it into a periodic synchronization signal L2 for output;

[0083] D: The precision identification function module receives the periodic synchronization signals L1 and L2, uses the basic frequency information P0 provided by the local crystal oscillator as the reference source, determines the precision of the periodic synchronization signal L2, and determines which periodic synchronization signal to output as the identified periodic synchronization signal L3 according to the preset strategy;

[0084] E: The synchronous three-out-of-two redundant discrimination function module receives the periodic synchronization signal L3 output by the accuracy identification function module, as well as the synchronization signals L4 and L5 sent by the external redundant CPU synchronization circuit. After performing a two-out-of-three vote on the three signals L3, L4, and L5, it outputs the final synchronization signal L6 to the CPU (information processing module) as the task periodic synchronization signal.

[0085] Design the synchronization information flow of three redundant CPUs as follows: The synchronization circuit is designed to be universal, and the synchronization circuits of CPU1 to 3 are completely consistent, such as Figure 2 shown.

[0086] in:

[0087] The periodic synchronization signal L3 output by the CPU1 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_1, L32_1, and L33_1. L31_1 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_1 and L33_1 are respectively used as input signals of the external CPU2 and CPU3 synchronization circuits;

[0088] The synchronization signal L4 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_3 output by the CPU3 synchronization circuit accuracy identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_2 output by the CPU2 synchronization circuit accuracy identification function module.

[0089] The periodic synchronization signal L3 output by the CPU2 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_2, L32_2, and L33_2. L31_2 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_2 and L33_2 are respectively used as input signals of the external CPU1 and CPU3 synchronization circuits;

[0090] The synchronization signal L4 sent by the external redundant CPU synchronization circuit and received by the CPU2 synchronization circuit is the periodic synchronization signal L32_1 output by the CPU1 synchronization circuit accuracy identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit and received by the CPU2 synchronization circuit is the periodic synchronization signal L33_3 output by the CPU3 synchronization circuit accuracy identification function module.

[0091] The periodic synchronization signal L3 output by the CPU3 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_3, L32_3, and L33_3. L31_3 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_3 and L33_3 are respectively used as input signals of the external CPU1 and CPU2 synchronization circuits;

[0092] The synchronization signal L4 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_2 output by the CPU2 synchronization circuit accuracy identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_1 output by the CPU1 synchronization circuit accuracy identification function module.

[0093] Based on the multi-mode redundant computer synchronization circuit designed above, a multi-mode redundant computer synchronization method of TTE bus is proposed, including the steps of multi-mode redundant CPU synchronization method inside TTE network equipment and the steps of synchronization signal source selection method inside TTE network equipment;

[0094] (I) Internal multi-mode redundant CPU synchronization method of TTE network equipment

[0095] The internal CPU synchronization of TTE network equipment refers to the method of using a local crystal oscillator to achieve device CPU synchronization before the TTE bus participates in synchronization. After the equipment is powered on or reset, the timers of each redundant information processing module start working. If the timer of each machine reaches the synchronization cycle time point, it will send out the local timing synchronization signal and output the signal to the three machines at the same time. Each machine will vote on the synchronization signal generated by itself and the synchronization signal information from the other two machines, and generate a synchronization interrupt for the local machine. After the interruption occurs, the local timer is reset and restarts the timing, and the cycle synchronization is completed in this way.

[0096] Taking the control system network equipment task cycle Tc = 10ms and the use of triple redundant mode (corresponding to independent CPU1, CPU2, CPU3) as an example, the multi-mode CPU synchronization method in the device is specifically described as follows:

[0097] 1) Set the synchronization cycle: To ensure the consistency of the calculation output time of each CPU 1 to 3, clock synchronization is performed once in each task cycle, that is, the synchronization cycle of the three redundant CPUs of the network device is consistent with the task cycle, which is Ts = 10ms. The control system completes a network data interaction once in each task cycle, and sets the TTE bus network synchronization instruction sending cycle to be consistent with the task cycle, which is Tb = 10ms.

[0098] 2) Taking CPU1 (information processing module 1) as an example, the multi-mode redundant computer performs the following synchronization process:

[0099] ① After the device is powered on or reset, the functions of each CPU (information processing module) are initialized, and the local crystal oscillator in the synchronization circuit starts to work and outputs the basic frequency information P0. In addition to generating a periodic synchronization signal, P0 is also used as a clock signal for each circuit of the information processing module, including the accuracy identification function.

[0100] ② The timer module randomly defines the zero time ti, and according to the basic frequency information sent by the local crystal oscillator, when the timing reaches the time ti+10ms, it outputs the synchronization signal L1 with a period of 10ms consistent with the task cycle.

[0101] ③ The precision identification function module directly outputs the input synchronization signal L1, and the output synchronization signal is defined as L3. L3 is divided into three paths L31_1, L32_1, and L33_1, which are output to the synchronization three-out-of-two redundant identification function modules of the local and other two groups of information processing module synchronization circuits respectively.

[0102] ④ Define the two groups of external input information processing modules, and the independent input synchronization signals are L4 and L5 respectively. The synchronization three-out-of-two redundant judgment function module performs a three-out-of-two voting on the synchronization signal after receiving the local synchronization signal L31_1 and the external synchronization signals L4 and L5, and uses the voting result L6 as the CPU1 task cycle synchronization signal. After receiving L6, CPU1 starts the calculation output of this cycle.

[0103] ⑤At the same time, the L6 signal is sent back to the timer function module, and the timer function module redefines the time when L6 is received as ti and starts the next synchronous timing.

[0104] Among them, in step ④, the synchronization signal three-out-of-two voting method performed by the synchronization three-out-of-two redundancy judgment function module is:

[0105] A) Define the initial timeout parameter Td, which is consistent with the synchronization period and is 10ms.

[0106] B) Synchronous three-out-of-two redundant discrimination function module When any of the three synchronization signal input channels receives a synchronization signal, the built-in synchronization timer Tick is started, and the channel is recorded as channel A. At this time, the synchronous three-out-of-two redundant discrimination function module does not output.

[0107] C) If the synchronization signal from any of the two channels except channelA is received before the Tick timer value is less than the timeout parameter Td, it is considered that the synchronization three-out-of-two redundancy judgment condition is met, and this time is recorded as tss. The synchronization signal input is shielded, and the voting synchronization signal L6 is output at time tss, and the built-in synchronization timer is reset. After the reset is successful, the shielding of the synchronization signal input is cancelled.

[0108] D) If no synchronization signal is received from any channel input except channelA before the Tick timer reaches the timeout parameter Td, then when the timer reaches Td, L6 is directly output without voting.

[0109] Taking CPU1 (information processing module 1) as an example, the synchronization signal three-out-of-two voting method executed by the synchronization three-out-of-two redundant judgment function module is as follows: Figure 3 shown.

[0110] (II) Method for selecting internal synchronization signal source of TTE network equipment:

[0111] After the TTE network starts running, each TTE end node first synchronizes the entire network time. After the end node enters the synchronization mode, the end node continuously outputs the bus network synchronization signal to the information processing module. After receiving the "synchronization source switching instruction" sent by the system, each machine begins to judge the accuracy of the bus network synchronization signal output by the TTE end node to determine whether to use the bus network synchronization signal instead of the local synchronization signal as the synchronization interrupt source. If the accuracy meets 10ms±0.1ms within a continuous 1s period, the 10ms output by the TTE end node is used as the interrupt source; after the three machines synchronize the 10ms signal by voting two out of three, the synchronized 10ms is used as the synchronization interrupt source for this machine.

[0112] Taking CPU1 (information processing module 1) as an example, the method for selecting a synchronization signal source by a single-mode information processing module is as follows:

[0113] 1) Method for selecting the synchronization signal source after receiving the "synchronization source switching instruction":

[0114] A) CPU1 (information processing module 1) is an independent TTE bus network device. After initial power-on, according to the internal multi-mode redundant CPU synchronization method of the TTE network device, the synchronization signal L6 after two-out-of-three voting of the local crystal oscillator is used as the synchronization source.

[0115] B) After the TTE bus network is powered on, the TTE bus continuously sends the network synchronization signal L0 to the TTE end node at a theoretical period Tb. The TTE end node converts L0 into an L2 synchronization signal and sends it to the accuracy identification module.

[0116] C) The host computer A in the TTE network (usually the ground test and launch control computer) sends a "synchronous source switching instruction" to network devices including multi-mode redundant computers through the TTE network. After CPU1 (information processing module 1) receives the instruction, the accuracy identification module starts the long-cycle timing, and the long-cycle timing duration Ts'=1000ms. Within the long-cycle timing time range, the accuracy identification module continues to judge the accuracy of L0.

[0117] The accuracy determination method continuously performed by the accuracy identification module is as follows:

[0118] ①Initialize parameters p=0, q=0.

[0119] ② The accuracy identification module records the time t0 when the network synchronization signal L2 is first received after receiving the "synchronization source switching instruction".

[0120] ③ Before the long-period timing ends, the accuracy identification module records the time t1, t2, ... t2 of each time the network synchronization signal L2 is received. j+1 , and calculate the time interval Δt = t j+1 -t j ; If Δt∈[10-0.1(ms),10+0.1(ms)], then p=p+1; if Then q=q+1.

[0121] ④After the long period timing ends, stop counting p and q.

[0122] ⑤ Determine the q count value: If q = 0 and p> 900, the precision identification module closes the L1 synchronization signal path and opens the L2 synchronization signal path to complete the selection and switching of the synchronization source input; Figure 4 As shown; if q>0, the input L1 synchronization signal is maintained and output as the local synchronization signal L3.

[0123] ⑥ If after the long-cycle timing Ts' ends, if the information processing module maintains the synchronization signal L1 as the local synchronization signal L3 output, the dynamic switching operation of the synchronization signal source will no longer be performed; if the information processing module switches L2 as the local synchronization signal L3 output, the synchronization signal source accuracy monitoring and dynamic switching operation will continue to be performed.

[0124] After the long period timing Ts' ends, information processing modules 1 and 2 use L2 as the local synchronization signal output, and information processing module 3 does not meet the synchronization source input condition switching condition and maintains the input L1 synchronization signal as the local synchronization signal L3 output as an example to illustrate the actual synchronization source usage in this case. Figure 5 shown.

[0125] 2) Synchronous signal source accuracy monitoring and dynamic switching method:

[0126] After the long period timing Ts' ends, if the information processing module switches L2 to output as the local synchronization signal L3, the synchronization signal source accuracy monitoring and dynamic switching operations are continuously performed.

[0127] When each information processing module receives the "synchronization source switching instruction" and switches to select the local TTE synchronization source, it continuously monitors the accuracy of the TTE synchronization source. If the number of times the TTE synchronization source signal L2 is monitored within a 1s period is less than 900, or the number of times the TTE synchronization source signal L2 accuracy deviation exceeds 10ms±0.1ms within a 1s period exceeds 30%, the synchronization source L1 generated by the local timer is switched as the input for redundant judgment, and the synchronization signal 10ms input by the TTE end node is no longer used. Otherwise, the network synchronization signal L2 continues to be used as the synchronization signal L3 output.

[0128] Still taking the example that CPU1 (information processing module 1) has output L2 as the local synchronization signal L3, the method of dynamically switching the synchronization signal source is described:

[0129] A) Initialize the structure

[0130] Struct Check

[0131] {

[0132] Time t;

[0133] Scales;

[0134] }

[0135] As well as the current variable tc and the rationality count values ​​sc1, sc2, and the sequence number k.

[0136] The element Time t in the structure Check is the moment when the precision identification module detects the TTE synchronization source L2, and Scale s is the result of the precision identification module judging whether the TTE synchronization source L2 meets the preset precision range at that moment.

[0137] ① Initialize the rationality count values ​​sc1 = 0, sc2 = 0. From the time the information processing module switches L2 as the local synchronization signal L3 output, the accuracy identification module performs the following statistical calculations:

[0138] ② The time when the precision identification module first receives the network synchronization signal L2 is tc0, and the structure array element Check[0].t=tc0, Check[0].s=1 is assigned.

[0139] cs1=cs1+Check[0].s, cs2=cs2+(1-Check[0].s). k=0, tc=Check[k].t.

[0140] ③ When the precision identification module receives the network synchronization signal L2 again at time tc1, it assigns the structure array element Check[1].t=tc1. If Check[1].t-Check[0].t∈[10-0.1(ms),10+0.1(ms)], then Check[1].s=1, otherwise Check[0].s=0.

[0141] cs1=cs1+Check[1].s, cs2=cs2+(1-Check[1].s).

[0142] ④ Similarly, if the accuracy identification module receives the network synchronization signal L2 for the i-th time at tci, the structure array element Check[i].t=tci is assigned. If Check[i].t-Check[i-1].t∈[10-0.1(ms),10+0.1(ms)], then Check[i].s=1, otherwise Check[i].s=0.

[0143] cs1=cs1+Check[i].s, cs2=cs2+(1-Check[i].s).

[0144] ⑤If Check[i].t-tc>1000ms, perform the following operations:

[0145] If any of the following situations occurs, the synchronization source L1 generated by the local timer is switched to be used as the synchronization signal L3 output, and the synchronization signal 10ms input by the TTE end node is no longer used. Otherwise, the network synchronization signal L2 continues to be used as the synchronization signal L3 output.

[0146] Case 1: Too many TTE synchronization source L2 losses are detected: cs1+cs2<90;

[0147] Case 2: Too many low-precision times of TTE synchronization source L2 are detected: cs2 / (cs1+cs2)>30%.

[0148] Otherwise, perform the following 1000ms sliding window operation:

[0149] Step 1: cs1 = cs1 - Check[k].s + Check[i].s, cs2 = cs2 - (1 - Check[k].s) + (1 - Check[i].s); k = k + 1, tc = Check[k].t; Execute step 2:

[0150] Step 2: Determine whether Check[i].t-tc>1000ms is true at this time. If not, repeat ④. If true, execute step 3:

[0151] Step 3: cs1=cs1-Check[k].s, cs2=cs2-(1-Check[k].s); k=k+1, tc=Check[k].t, execute step 2.

[0152] (III) Synchronization between control system devices:

[0153] The control system devices are interconnected through redundant TTE switches. When dual redundant links are used for full network synchronization, the connection relationship between the three redundant devices is as follows: Figure 6 The device side synchronizes each machine CPU to a unified network-wide TTE clock by performing a two-out-of-three redundant vote on the TTE end node synchronization signal, as shown below Figure 7 shown.

[0154] The present invention will be further described below in conjunction with the embodiments.

[0155] Example 1

[0156] Taking the network devices in the control system as the onboard computer (configured with three redundant information processing modules), the integrated controller (configured with three redundant information processing modules), the inertial group (configured with a single-mode non-redundant information processing module), and the servo mechanism (configured with three redundant information processing modules) as an example, the control system device synchronization method based on the TTE bus is explained as follows:

[0157] 1) When the control system equipment is powered on, each device starts to use the local crystal oscillator to provide basic frequency information P0ij to the timer function module; the timer function module receives the basic frequency information sent by the local crystal oscillator, and outputs the periodic synchronization signal L1ij after frequency division processing, and the precision identification module directly uses L1ij as the local synchronization signal output L3ij. Among them, i is the device number, and this system defines the onboard computer i=1, the integrated controller i=2, the inertial group i=3, and the servo mechanism i=4; j is the extension number of this device, for redundant equipment, j=1~3; for non-redundant equipment, j is fixed to 1, and the subscript j can be ignored.

[0158] 2) For the onboard computer, integrated controller, servo mechanism and other equipment configured with three redundant information processing modules, the information processing module needs to perform two-out-of-three redundant voting on the L3ij output by the local machine and the synchronization signals L4ij and L5ij output by the other two machines, and then use them as the actual CPU synchronization source L6i to achieve synchronization of the three machines; for the inertial group configured with non-redundant information processing modules, directly use the L3i output by the local machine as the CPU synchronization source L6i. At this time, different devices use their own crystal oscillators as the time reference, and different devices operate asynchronously.

[0159] 3) After the TTE network runs stably, it starts to periodically send the global TTE network synchronization source signal L0ij to each network device end node. After each end node detects L0ij, it outputs L2ij with the same frequency, but all network devices still run asynchronously with their own crystal oscillator as the time base.

[0160] 4) The host computer sends a "synchronization source switching instruction" to all network devices. After each device detects the signal, the accuracy identification module of each information processing module begins to detect the accuracy of L2ij within 1000ms. If the accuracy meets the requirements within the specified time, L2ij replaces L1ij as the local L3ij output, that is, the interrupt source switching from the local time base to the TTE network synchronization signal is completed; if L2ij does not meet the accuracy requirements, L1ij continues to be used as the local L3ij output. In this process, for the onboard computer, integrated controller, servo mechanism and other equipment equipped with three redundant information processing modules, the information processing module needs to perform a two-out-of-three redundant vote on the local output L3ij and the synchronization signals L4ij and L5ij output by the other two machines as the actual CPU synchronization source L6i to achieve synchronization of the three machines.

[0161] 5) For the information processing module that has switched to TTE network synchronization interruption, the accuracy of L2ij is continuously judged using a 1000ms sliding window range. Once the accuracy does not meet the specified value, the interrupt source generated by the local time base is restored, and L1ij replaces L2ij as the local L3ij output, and before receiving a new "synchronization source switching instruction", the operation of replacing L1ij with L2ij as the local L3ij output is no longer executed.

[0162] Example 2

[0163] Computer products with non-redundant configurations can also use this method to use the TTE network global clock as a high-precision external synchronization signal.

[0164] Compared with triple redundant equipment, the information processing module of non-redundant computer products cancels the synchronization three-out-of-two redundant identification module, no longer receives the multi-mode synchronization signal sent by the redundant information processing module, and no longer sends the synchronization output signal generated by the local machine to other redundant information processing modules. After the local precision identification module performs precision identification on the TTE network signal, it can directly output the local crystal oscillator synchronization signal L1 or the TTE network synchronization signal L2 as the final synchronization signal L3 according to the above conditions, such as Figure 8 shown.

[0165] In summary, the multi-mode redundant computer synchronization method based on TTE bus is applied to the launch vehicle control system, and the system synchronization scheme is optimized:

[0166] (1) By using the redundant TTE network global clock as a unified external synchronization signal for the control system's online devices, all the control system's online devices can be unified under the same synchronization clock reference, extending the scope of control system device synchronization and facilitating the realization of time determinism for system calculations and execution behaviors.

[0167] (2) The TTE network global clock is used as a unified external synchronization signal for the equipment, which simplifies the synchronization circuit design of the equipment's multi-machine redundant information processing module.

[0168] (3) The TTE network global clock is used as an external synchronization signal, which is coordinated with the synchronization circuit inside the device to form a redundant configuration mode of heterogeneous synchronization sources, thereby improving the reliability of the device. Even in the case of a complete failure of the internal synchronization circuit of the device, the CPU synchronization signal can still be reliably issued.

[0169] (4) Using the TTE network global clock as a high-precision external synchronization signal reduces the accuracy requirements for the frequency standard circuit in the equipment, objectively and effectively reducing the cost of equipment components. On the other hand, the TTE network global clock itself has a high accuracy, which helps to improve the final synchronization accuracy of each device in the control system.

[0170] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0171] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A multi-mode redundant computer synchronization circuit based on TTE bus, characterized in that: The multi-mode redundant computer has three identically structured CPU1 synchronization circuits, CPU2 synchronization circuits, and CPU3 synchronization circuits, each of which includes a local crystal oscillator, a timer function module, a TTE end node, an accuracy identification function module, and a synchronization three-out-of-two redundancy discrimination function module; The local crystal oscillator provides basic frequency information P0 for the timer function module; The timer function module receives the basic frequency information sent by the local crystal oscillator, and outputs the periodic synchronization signal L1 after frequency division processing; The TTE end node receives the TTE network synchronization instruction L0 and converts it into a periodic synchronization signal L2 for output; The precision identification function module receives the periodic synchronization signals L1 and L2, uses the basic frequency information P0 provided by the local crystal oscillator as the reference source, determines the precision of the periodic synchronization signal L2, and determines which periodic synchronization signal to output as the identified periodic synchronization signal L3 according to the preset strategy; The synchronous three-out-of-two redundant discrimination function module receives the periodic synchronization signal L3 output by the accuracy identification function module, and the synchronization signals L4 and L5 sent by the external redundant CPU synchronization circuit. After performing a two-out-of-three vote on the three signals L3, L4, and L5, it outputs the final synchronization signal L6 to CPU1 as the task periodic synchronization signal.

2. The multi-mode redundant computer synchronization circuit based on TTE bus according to claim 1, characterized in that: The periodic synchronization signal L3 output by the CPU1 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_1, L32_1, and L33_1. L31_1 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_1 and L33_1 are respectively used as input signals of the external CPU2 and CPU3 synchronization circuits; The synchronization signal L4 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_3 output by the CPU3 synchronization circuit precision identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit received by the CPU1 synchronization circuit is the periodic synchronization signal L32_2 output by the CPU2 synchronization circuit precision identification function module; The periodic synchronization signal L3 output by the CPU2 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_2, L32_2, and L33_2. L31_2 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_2 and L33_2 are respectively used as input signals of the external CPU1 and CPU3 synchronization circuits; The synchronization signal L4 sent by the external redundant CPU synchronization circuit received by the CPU2 synchronization circuit is the periodic synchronization signal L32_1 output by the CPU1 synchronization circuit precision identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit received by the CPU2 synchronization circuit is the periodic synchronization signal L33_3 output by the CPU3 synchronization circuit precision identification function module; The periodic synchronization signal L3 output by the CPU3 synchronization circuit accuracy identification function module is divided into three homologous synchronization signals L31_3, L32_3, and L33_3. L31_3 is input to the local synchronization three-out-of-two redundancy identification function module, and L32_3 and L33_3 are respectively used as input signals of the external CPU1 and CPU2 synchronization circuits; The synchronization signal L4 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_2 output by the CPU2 synchronization circuit accuracy identification function module; the synchronization signal L5 sent by the external redundant CPU synchronization circuit and received by the CPU3 synchronization circuit is the periodic synchronization signal L33_1 output by the CPU1 synchronization circuit accuracy identification function module.

3. A TTE bus-based multi-mode redundant computer synchronization method based on the circuit of any one of claims 1 to 2, characterized in that: The method comprises the steps of a method for synchronizing a multi-mode redundant CPU inside a TTE network device and the steps of a method for selecting a synchronization signal source inside a TTE network device; The method for synchronizing a multi-mode redundant CPU in a TTE network device includes the following steps: 1) Setting the synchronization cycle: The synchronization cycle of the three redundant CPUs of the network equipment is consistent with the task cycle, which is recorded as Ts. The control system completes a network data interaction once per task cycle, and the TTE bus network synchronization instruction sending cycle is set to be consistent with the task cycle, that is, Tb = Ts; 2) After the device is powered on or reset, each CPU function is initialized, the local crystal oscillator in the synchronization circuit starts working, and outputs the basic frequency information P0; 3) The timer module randomly defines the zero time ti, and according to the basic frequency information sent by the local crystal oscillator, when the timing reaches the time ti+10ms, it outputs the synchronization signal L1 consistent with the task cycle; 4) The precision identification function module directly outputs the input synchronization signal L1, and the output end synchronization signal is defined as L3. L3 is divided into three paths L31_i, L32_i, and L33_i, i∈{1, 2, 3}, which are output to the local and other two groups of CPU synchronization circuit synchronization three-out-of-two redundant identification function modules respectively; 5) Define the synchronization signals independently input by the two groups of external input information processing modules as L4 and L5. The synchronization three-out-of-two redundant discrimination function module performs a three-out-of-two vote on the synchronization signal after receiving the local synchronization signal L31_i and the external synchronization signals L4 and L5, and uses the voting result L6 as the CPU1 task cycle synchronization signal. After receiving L6, CPU1 starts the calculation output of this cycle; 6) At the same time, the L6 signal is sent back to the timer function module, and the timer function module redefines the time when L6 is received as ti, and starts the next synchronization timing; The method for selecting a synchronization signal source inside a TTE network device comprises the following steps: After CPU1 is initially powered on, according to the TTE network device internal multi-mode redundant CPU synchronization method, the synchronization signal L6 after two-out-of-three voting of the local crystal oscillator is used as the synchronization source; After the TTE bus network is powered on, the TTE bus continuously sends the network synchronization signal L0 to the TTE end node at a theoretical period Tb. The TTE end node converts L0 into an L2 synchronization signal and sends it to the accuracy identification module. The host computer in the TTE network sends a synchronization source switching instruction to network devices including multi-mode redundant computers through the TTE network. After CPU1 receives the instruction, the accuracy identification module starts the long-cycle timing. Within the long-cycle timing time range, the accuracy identification module continues to judge the accuracy of L0; After the long period timing ends, if CPU1 switches L2 as the local synchronization signal L3 output, the synchronization signal source accuracy monitoring and dynamic switching operations are continuously performed; When each CPU receives the synchronization source switching instruction and switches to select the local TTE synchronization source, it continuously monitors the TTE synchronization source accuracy. If the number of times the TTE synchronization source signal L2 is monitored within a 1s period is less than the preset value, or the number of times the TTE synchronization source signal L2 accuracy deviation is monitored within a 1s period exceeds the preset percentage, it switches to the synchronization source L1 generated by the local timer as the input for redundant judgment, and no longer uses the synchronization signal input by the TTE end node. Otherwise, it continues to use the network synchronization signal L2 as the synchronization signal L3 output.

4. A multi-mode redundant computer synchronization method based on TTE bus according to claim 3, characterized in that: In addition to being used to generate a periodic synchronization signal, the basic frequency information P0 is also used as a clock signal for various circuits of the CPU including the accuracy identification function.

5. A multi-mode redundant computer synchronization method based on TTE bus according to claim 3, characterized in that: The method of performing two-out-of-three voting of synchronization signals is as follows: A) define the initial timeout parameter Td, the value of which is consistent with the synchronization period; B) When any of the three synchronization signal input channels of the synchronization three-out-of-two redundant discrimination function module receives a synchronization signal, the built-in synchronization timer Tick is started, and the channel is recorded as channelA. At this time, the synchronization three-out-of-two redundant discrimination function module does not output; C) If the synchronization signal from any of the two channels except channelA is received before the Tick timer value is less than the timeout parameter Td, it is considered that the synchronization three-out-of-two redundancy judgment condition is met, and this time is recorded as tss. The synchronization signal input is shielded, and the voting synchronization signal L6 is output at time tss. The built-in synchronization timer is reset. After the reset is successful, the shielding of the synchronization signal input is cancelled; D) If no synchronization signal is received from any channel input except channelA before the Tick timer reaches the timeout parameter Td, then when the timer reaches Td, L6 is directly output without voting.

6. A multi-mode redundant computer synchronization method based on TTE bus according to claim 3, characterized in that: Set the long period timing time Ts'=100Ts.

7. A TTE bus-based multi-mode redundant computer synchronization method according to claim 3, characterized in that: The accuracy identification module continuously judges the accuracy of L0, and the judgment method is as follows: Initialize parameters p=0, q=0; The precision identification module records the time t0 when the network synchronization signal L2 is first received after receiving the synchronization source switching instruction; Before the long-period timing ends, the accuracy identification module records the time t1, t2, ..., t2 of each time the network synchronization signal L2 is received. j+1 , and calculate the time interval Δt = t j+1 -t j ; If Δt∈[Ts-0.1ms,Ts+0.1ms], then the p value increases by 1. Then the q value increases by 1; After the long period timing ends, stop counting p and q; Determine the q count value: if q=0, and p>preset value, the precision identification module closes the L1 synchronization signal path, opens the L2 synchronization signal path, and completes the selection and switching of the synchronization source input; if q>0, the input L1 synchronization signal is maintained as the local synchronization signal L3 output; After the long-cycle timing ends, if the CPU maintains the synchronization signal L1 as the local synchronization signal L3 output, the dynamic switching operation of the synchronization signal source will no longer be performed; if the CPU switches L2 as the local synchronization signal L3 output, the synchronization signal source accuracy monitoring and dynamic switching operation will continue to be performed.

8. A TTE bus-based multi-mode redundant computer synchronization method according to claim 3, characterized in that: The synchronization method is applicable to computers with non-redundant configurations. In this case, the synchronization two-out-of-three redundant discrimination function module is canceled, and the multi-mode synchronization signal sent by the redundant CPU is no longer received, and the synchronization output signal generated by the local computer is no longer sent to other redundant CPUs. After the local accuracy identification module performs accuracy identification on the TTE network signal, the local crystal oscillator synchronization signal L1 or the TTE network synchronization signal L2 is directly output as the final synchronization signal L3.

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