Chip detection system and method

Abstract

The invention provides a chip detection system and method.The chip detection system comprises an upper computer and a lower computer, the upper computer and the lower computer establish communication connection, and the lower computer is connected with a chip to be detected through a built-in interface unit of the lower computer; the upper computer is used for receiving a configuration file input by a user, generating a data packet based on the configuration file and sending the data packet to the lower computer, and the configuration file is written by adopting a description language; analyzing the packaged detection data sent by the lower computer to generate a test report; the lower computer is used for sending the data packet to the to-be-tested chip so as to control software in the to-be-tested chip to run; in the software running process of the to-be-tested chip, the level state of the pin in the to-be-tested chip is collected, the level state is converted into detection data to be packaged, and the packaged detection data is transmitted to an upper computer. According to the embodiment of the invention, the input of manpower and material resources in a design function verification stage can be reduced to a great extent, and various costs in a test process are greatly reduced.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing system and method. Background Art

[0002] Microcontroller Unit (MCU) chip testing can perform complete functional verification and performance testing on chips in the tape-out stage, thereby ensuring the batch listing and mass production of chips. In this process, the following test contents are usually required: Interface function test: This part of the content is the most basic test type for MCU chips. The purpose is to verify whether the various functional modules or interfaces of the MCU work according to the expected functions, such as whether the general I / O input and output, communication interface protocol is correct, whether AD / DA can collect or output normally, whether the timer is on time and continuous, etc.; Electrical parameter test: This part of the test is mainly used to verify the electrical parameters of the MCU after tape-out, including but not limited to power supply voltage, dynamic / static power consumption, operating frequency, temperature range, etc.; Software operation test: As a programming control device, the MCU chip, software program operation test is also an indispensable core project, and its purpose is to verify the stable operation status of the chip core and the normal function of the bus.

[0003] At present, in view of the rapid development of the MCU chip industry, the related technologies include the following three main testing methods for MCU chips: 1. Mature ATE products: This equipment can automatically complete all chip-related test items in batches and issue detailed test reports; 2. Self-developed automated testing equipment: To a certain extent, it covers test items such as interface functions, software operation, and some electrical performance; 3. Manual testing by testers: Since the functions of MCU chips are relatively less complex, all software development and performance testing can be performed for the design.

[0004] The above existing MCU chip testing methods also have various shortcomings to a certain extent. 1. Self-programming test: This method consumes relatively more manpower and time costs. At the same time, due to personnel capacity issues, it is easy to ignore or miss some test items, and the final result is uncontrollable. At the same time, due to the large number of interfaces, different types of debugging equipment need to be purchased, and the complexity is relatively high; 2. Mature ATE equipment: There are many types of ATE equipment on the market, but due to its high cost, the cost of a single unit is too high, and the size is large. At the same time, in order to ensure the functional reuse of the MCU, such equipment also needs to invest a lot of energy in software design, which is not suitable for early development; 3. Self-developed equipment: Use self-developed boards to communicate with the target MCU to complete functional verification, but due to the limitations of the equipment itself, all interface functions cannot be customized, which will lead to some imperfect tests. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a chip detection system and method, which can greatly reduce the manpower and material resources investment in the design function verification stage. All operations in the system are controlled by descriptive configuration files and host computer interfaces, avoiding repeated programming of multiple interfaces and avoiding human subjective loopholes. Compared with other products or designs on the market, the system provides more distinct versatility and portability, and due to the convenient operability defined by the host computer protocol, it can also perform tests on various complex custom timing interfaces, greatly reducing various costs in the process and providing reliable guarantees for subsequent processes.

[0006] In the first aspect, the present application provides a chip testing system, which includes: an upper computer and a lower computer, the upper computer and the lower computer establish a communication connection, the lower computer is connected to the chip to be tested through its built-in interface unit; the upper computer is used to receive a configuration file input by a user, generate a data packet based on the configuration file, and send the data packet to the lower computer, the configuration file is written in a description language; the packaged detection data sent by the lower computer is analyzed to generate a test report; the lower computer is used to send the data packet to the chip to be tested to control the software running in the chip to be tested; during the software running of the chip to be tested, the level state of the pins in the chip to be tested is collected, and the level state is converted into detection data for packaging, and the packaged detection data is transmitted to the upper computer.

[0007] In the second aspect, the present application provides a chip testing method, which is applied to a chip detection system, the system comprising: a host computer and a slave computer, the host computer and the slave computer establish a communication connection, the slave computer is connected to the chip to be tested through its built-in interface unit; the method comprises: using the host computer to receive a configuration file input by the user, generating a data packet based on the configuration file, and sending the data packet to the slave computer, the configuration file being written in a description language; using the slave computer to send the data packet to the chip to be tested to control the software running in the chip to be tested; during the software running of the chip to be tested, the level state of the pins in the chip to be tested is collected, and the level state is converted into detection data for packaging, and the packaged detection data is transmitted to the host computer; using the host computer to receive the packaged detection data sent by the slave computer, and analyzing it to generate a test report.

[0008] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages:

[0009] An embodiment of the present application provides a chip testing system, which includes: an upper computer and a lower computer, the upper computer and the lower computer establish a communication connection, the lower computer is connected to the chip to be tested through its built-in interface unit; the upper computer is used to receive a configuration file input by a user, generate a data packet based on the configuration file, and send the data packet to the lower computer, the configuration file is written in a description language; the packaged detection data sent by the lower computer is analyzed to generate a test report; the lower computer is used to send the data packet to the chip to be tested to control the software running in the chip to be tested; during the software running of the chip to be tested, the level state of the pins in the chip to be tested is collected, and the level state is converted into detection data for packaging, and the packaged detection data is transmitted to the upper computer.

[0010] The chip detection system provided in the embodiment of the present application has the following advantages:

[0011] 1. The chip under test does not need to be repeatedly programmed and debugged. It only needs to realize the general read and write functions and transplant the protocol stack. The logic process is adjusted and controlled by the host computer.

[0012] 2. The host computer configures global logic and control through descriptive files, which is easier to understand and use than code programming.

[0013] 3. The interface unit in the lower computer does not need to implement complex interface logic functions. It only needs to collect the interface level of the chip under test at high frequency. The upper computer analyzes the collected waveform and determines the correctness and integrity of the peripheral function, which can avoid the need to redesign the FPGA logic function after MCUIO reuse or peripheral upgrade.

[0014] 4. The interface between MCU and test board is multiplexed. By setting the power area, clock area, MCU pin area and other areas, various types of MCUs with different pin numbers, different main frequencies and different power supplies can be tested.

[0015] The embodiments of the present application can greatly reduce the human and material investment in the design function verification stage. All operations in the system are controlled by descriptive configuration files and host computer interfaces, avoiding repeated programming of multiple interfaces and subjective human loopholes. Compared with other products or designs on the market, the system provides more distinct versatility and portability, and because of the convenient operability defined by the host computer protocol, it can also perform testing of various complex custom timing interfaces, greatly reducing various costs in the process and providing reliable guarantees for subsequent processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic diagram of the structure of a chip detection system provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of the lower computer provided in the embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of an interface unit in a lower computer provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a waveform display interface of a host computer provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of a chip detection method provided in an embodiment of the present application;

[0023] Figure 6 A schematic flow chart of another chip detection method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0025] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0026] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0027] It should be noted that the concepts such as "first" and "second" mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0028] It should be noted that the modifications of "one" and "plurality" mentioned in the present application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0029] The chip detection system provided by the present application is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] Figure 1 FIG. 1 is a schematic diagram of a chip detection system in an embodiment of the present application. This embodiment can be applied to the case of detecting chip performance, such as Figure 1 As shown, the chip detection system 10 provided in the embodiment of the present application mainly includes a host computer 11 and a slave computer 12, and the host computer 11 and the slave computer 12 establish a communication connection. The slave computer 12 is connected to the chip to be tested 13 through its built-in interface unit.

[0031] The upper computer 11 is used to receive the configuration file input by the user, generate a data packet based on the configuration file, and send the data packet to the lower computer 12; analyze the packaged detection data sent by the lower computer 12 to generate a test report. The lower computer 12 is used to send the data packet to the chip under test 13 to control the software running in the chip under test; during the software running of the chip under test 13, the level state of the pins in the chip under test 13 is collected, and the level state is converted into detection data for packaging, and the packaged detection data is transmitted to the upper computer 11.

[0032] The host computer 11 generally refers to a computer system responsible for overall test process control, data collection and analysis. The host computer 11 runs specially designed test software, which can be a graphical user interface (GUI) to allow operators to configure test files, start test processes, and monitor test progress. The host computer is also responsible for saving the test results to a database or file for subsequent analysis. Optionally, the host computer 11 can include electronic devices such as notebook computers, desktop computers, and laptops that deploy computer operating systems.

[0033] The lower computer 12 generally refers to a test device or instrument directly connected to the chip to be tested. The lower computer 12 may be a specialized tester, a signal generator, a power supply, or other hardware capable of generating an excitation signal and measuring a response. The lower computer receives data packets from the upper computer to set the test conditions, and then collects the operating status of the chip during the operation of the chip, and transmits the collected data back to the upper computer.

[0034] The chip under test refers to an integrated circuit (IC) or other type of semiconductor device whose performance, function or reliability needs to be evaluated during the test process. Optionally, in the embodiment of the present application, the chip under test is an MCU chip as an example for explanation.

[0035] The following is a detailed description of the lower computer and the upper computer in the embodiment of the present application.

[0036] The communication connection between the host computer 11 and the slave computer 12 can be established through a variety of interfaces, such as General Purpose Interface Bus (GPIB), Universal Serial Bus (USB), Ethernet or a proprietary communication protocol, etc. For automated chip testing, it is very important to ensure efficient and stable communication between the host computer and the slave computer, because this directly affects the speed and accuracy of the test.

[0037] Optionally, the upper computer 11 and the lower computer 12 establish a communication connection via USB. USB communication generally supports plug-and-play function, and when the lower computer is connected to the upper computer via USB, the operating system of the upper computer can automatically identify the new hardware and install the necessary driver without additional configuration.

[0038] The upper computer is used to receive the configuration file input by the user, generate a data packet based on the configuration file, and send the data packet to the lower computer. The configuration file is written in a description language.

[0039] Configuration files are files used to define and control various settings and parameters during chip testing. They ensure that the lower computer and the chip under test can run in the predetermined manner and can flexibly adapt to different types of chips under test.

[0040] The above configuration files are used as input for the host computer and are all written in description language. Compared with programming language, this file provides a simpler explanation method and you can get started with it with just a simple understanding.

[0041] A descriptive language is a language that is defined for describing states or beginnings and endings in detail. It is a language that allows the generation of new description schemes and descriptors. Descriptive languages ​​can be text-based or graphical. For example, text-based descriptive languages ​​can include XML, JSON, YAML, etc., and graphical-based descriptive languages ​​can include UML, etc.

[0042] In an embodiment of the present application, a format of a configuration file is provided, and the format of the configuration file includes at least one of the following operation instructions: a delay instruction, a read operation instruction, a write operation instruction, a register address, a judgment instruction, and a judgment condition.

[0043] The operation instructions contained in the configuration file are used to define specific behaviors and logic during the test or operation process to control hardware devices, execute test sequences, or manage data flows.

[0044] Among them, the function of the delay instruction is to specify a period of time to wait before executing the next step, which is mainly used to ensure that certain operations (such as power supply stability and signal propagation) have enough time to complete. The function of the read operation instruction is to read data from a specified location (such as a register, a memory address), mainly used to obtain sensor values, status information or data from other external devices. The function of the write operation instruction is to write data to the specified location (such as a register, a memory address) of the chip under test, which is mainly used to set parameters, initialize hardware or send commands to the chip under test. The function of the register address is to identify the specific register location to be accessed. It is mainly used to specify which register needs to be read or written when interacting with the chip under test. The function of the judgment instruction is to decide whether to perform subsequent operations based on certain conditions, and is mainly used to implement branch logic, such as selecting different processing paths based on test results. The function of the judgment condition is to define the specific conditional expression used in the judgment instruction, which is mainly used as part of the judgment instruction to determine the direction of the program flow.

[0045] The configuration file includes the instruction set for controlling the MCU. Users can use the interactive interface of the host computer to customize the logical sequence between various operation instructions to build the control sequence of the MCU. It is similar to "building blocks" in programming, that is, using pre-defined operation instructions to build complex program logic.

[0046] The configuration file input by the user includes the operation instructions that the user needs to use according to the test items of the MCU, the dependencies between the various operation instructions, and the control objects of the various description language operation instructions.

[0047] Dependency refers to the order in which operation instructions are executed. The dependency can be represented in the form of a directed acyclic graph (DAG), which helps the operation instructions to be executed correctly according to their dependencies and ensures that an instruction is executed only after all preconditions are met.

[0048] For each operation instruction, specify the specific object controlled by the operation instruction. For example, a "write" instruction may be for setting the state of a GPIO pin, while a "read" instruction may be for obtaining sensor data from an ADC (analog-to-digital converter).

[0049] After receiving the configuration file input by the user, the host computer parses the configuration file according to the data protocol stack to obtain its corresponding data packet.

[0050] Among them, the structure of the data protocol stack includes: frame header, data packet length, instruction type, payload data and CRC check; pillow, used to store characters indicating the start of the data packet; data packet length, used to store characters indicating the length of the data packet; instruction type, used to store the operation instructions of the data packet; payload data, used to store the control object corresponding to the operation instructions of the data packet; CRC check, used to store the check code of the data packet.

[0051] The process of parsing the configuration file to generate a data packet mainly includes: identifying the control objects in the configuration file, for example, extracting all register addresses, peripheral identifiers, etc. from the configuration file. Parsing the operation instructions in the configuration file: understanding the meaning of each instruction, such as delay, read and write operations, etc. Constructing the dependency relationship between each operation instruction in the configuration file: establishing a dependency graph between operation instructions based on the information in the configuration file to ensure the correct execution order.

[0052] Based on the results of the analysis, a data model is constructed in the memory of the upper computer. The model should contain all necessary information, such as the state of the control object, the instruction queue, the conditional judgment rules, etc. The data model is converted into a data packet that is actually transmitted to the lower computer. Specifically, the process of generating a data packet mainly includes: Serializing instructions: Serializing instructions into a format suitable for transmission according to dependencies and execution order. Encapsulating data packets: Encapsulating serialized instructions and other necessary information (such as checksums, command headers, etc.) into a complete data packet according to the format of the data protocol stack. Furthermore, the data packet can be optimized and compressed to minimize the amount of data and improve transmission efficiency.

[0053] After the upper computer generates a data packet, it transmits the data packet to the lower computer through the USB connection between the upper computer and the lower computer. The lower computer is specifically used to read the type of the operation instruction in the data packet, and when the operation instruction type is the first setting type, forward the data packet to the device under test, and when the operation instruction type is the second setting type, convert the level state into detection data for packaging, and transmit the packaged detection data to the upper computer; the first setting type refers to the operation instruction for controlling the chip under test, and the second setting type refers to the operation instruction for controlling the lower computer.

[0054] like Figure 2As shown, the lower computer provided in the embodiment of the present application also includes: a field programmable gate array (FPGA) unit, a power supply unit, a frequency control unit and an analog control unit; the FPGA unit is used to receive a data packet, parse the data packet, obtain the instruction in the data packet, and forward the data packet to the chip to be tested when the instruction in the data packet is a forwarding instruction; when the instruction in the data packet is an encapsulation instruction, the collected level state is converted into detection data for encapsulation, and the encapsulated detection data is transmitted to the upper computer; the power supply unit is used to power the lower computer and provide a power signal matching the model of the chip to be tested to the chip to be tested; the frequency control unit is used to provide a clock signal to the chip to be tested under the control of the FPGA unit; the analog unit is used to provide an analog level to the chip to be tested under the control of the FPGA unit, and collect the level state output by the analog module in the chip to be tested.

[0055] FPGA is an integrated circuit that can be programmed and configured by the user. It consists of a large number of logic blocks (LogicBlocks), input / output blocks (IOBs) and programmable interconnection resources. After manufacturing, these components can redefine their functions and interconnection relationships through configuration data loaded by the user.

[0056] FPGA can realize different circuit functions by updating configuration files without changing the hardware, which provides great flexibility. Since FPGA is composed of many independent logic units, it can naturally support highly parallel data processing, which is conducive to improving throughput.

[0057] In one possible implementation, the lower computer is specifically used to read the type of operation instruction in the data packet, and when the operation instruction type is a first setting type, forward the data packet to the device under test; when the operation instruction type is a second setting type, convert the level state into detection data for packaging, and transmit the packaged detection data to the upper computer; the first setting type refers to the operation instruction used to control the chip under test, and the second setting type refers to the operation instruction used to control the lower computer.

[0058] FPGA can receive data packets transmitted by the host computer from the USB communication unit, parse the received data packets, extract the operation instructions, and respond according to the parsed operation instructions. For example, when a forwarding instruction is detected, it is ready to send the data packet to the chip under test.

[0059] The same data protocol stack as that of the host computer is deployed in the FPGA unit, and the FPGA unit parses the data packet based on the data protocol station.

[0060] During the test process, the lower computer prepares to start measurement according to the control instructions of the first stage, waits for the chip to be tested to be ready, starts high-frequency logic level acquisition of all pins of the chip to be tested, and encapsulates the data stream for real-time transmission to the upper computer.

[0061] The above-mentioned encapsulation instruction refers to converting the collected electrical levels into electrical digital signals, and then encapsulating the point digital signals and feeding them back to the host computer through the USB interface.

[0062] The power supply unit plays a vital role in the test system. It is mainly used to provide stable power modules or circuits for the entire lower computer and all its components. Ensure that all devices connected to the lower computer - including microcontrollers (MCUs), sensors, communication interfaces, memory, and other peripherals - can obtain the correct voltage and current they need to work properly.

[0063] In addition, the power supply unit can provide different levels of voltage for different types of chips to be tested: for example, it can provide any level of voltage such as 1.2V, 3.3V, 5V, 12V, etc., so that the lower computer can adapt to various types of MCU chip tests.

[0064] The frequency control unit is mainly used to provide accurate clock signals for the chip under test. The clock signal is the heartbeat of the digital circuit and determines the time base for all synchronous operations. The frequency control unit can generate multiple clock signals of different frequencies at the same time to adapt to different chips under test. Each clock signal in the frequency control unit can be independently configured to meet the requirements of specific applications.

[0065] The frequency control unit provides 1kHz-200MHz multi-channel output with a wide frequency range, which can cover various application scenarios from low-speed sensor reading to high-speed data processing, so as to be suitable for situations where the MCU performance at different operating frequencies needs to be tested and verified.

[0066] In addition, to ensure accuracy and reliability, the frequency control unit provides a high-precision and stable clock signal. The frequency control unit uses a crystal oscillator (Crystal Oscillator), a temperature-compensated crystal oscillator (TCXO), a voltage-controlled crystal oscillator (VCXO), or a higher-level constant-temperature controlled crystal oscillator (OCXO) to generate the clock signal.

[0067] The analog unit is mainly used to provide accurate analog levels for the chip under test and perform analog data acquisition to verify the performance of the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) in the chip under test.

[0068] In one possible implementation, the lower computer also includes: a temperature unit and a power consumption monitoring unit; the temperature unit is used to monitor the temperature of the lower computer and different positions of the chip to be tested; the ambient temperature is controlled to be a set temperature; the power consumption monitoring unit is used to obtain the dynamic power consumption parameters and static power consumption parameters of the chip to be tested during the test process.

[0069] The host computer provides fixed test monitoring instructions such as temperature and power consumption, and can provide cold and hot start and other types of experimental investigation and various indicators monitoring functions. The temperature unit is mainly used to collect the temperature of each detection point in the lower computer and the chip to be tested, and control the ambient temperature to the set temperature to achieve the test of the chip to be tested in different environments.

[0070] The power consumption monitoring unit is used to obtain the dynamic power consumption parameters and static power consumption parameters of the chip under test during the test process.

[0071] In one possible implementation, Figure 3 As shown, the interface unit 30 includes an input / output pin area 31, which includes multiple input / output pins. The input / output pins are configured through software to implement one or more of the following functions: general input / output, serial communication interface, two-wire serial bus, serial peripheral interface, timer, counter, controller area network, and universal serial bus.

[0072] General Purpose Input / Output (GPIO) is a basic I / O function that allows each pin to be individually configured as input or output mode. It is mainly used for simple digital signal transmission, such as switch status detection, LED control, etc.

[0073] The Serial Communication Interface (SCI) provides full-duplex asynchronous serial communication. It is mainly used for UART (Universal Asynchronous Receiver / Transmitter), supports standard protocols such as RS-232 and RS-485, and is suitable for low-speed data exchange.

[0074] The two-wire serial bus (I2C, Inter-Integrated Circuit) is a half-duplex synchronous serial communication protocol that uses two lines for data transmission (SDA-data line and SCL-clock line). It is mainly used to connect low-speed peripheral devices such as sensors, EEPROM, etc.

[0075] Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that uses a four-wire system (MOSI, MISO, SCK, SS / CS) to achieve high-speed full-duplex communication. It is mainly used for fast data transmission tasks, such as the connection of peripherals such as ADC / DAC and memory.

[0076] The interface unit includes: a power pin area 32, a reset pin area 36, ​​a clock pin area 35, a digital ground pin area 33 and an analog pin ground area 34; the power pin area includes multiple power signal pins; the reset pin area includes multiple reset signal pins; the clock pin area includes multiple clock signal pins; the digital ground pin area includes multiple pins for digital signal ground lines; and the analog ground pin area includes multiple pins for analog signal ground lines.

[0077] The pins in the power pin area are used to connect to the power supply unit to provide the required voltage level for the chip under test. The power pin area includes multiple power pins with different voltage levels to meet the needs of different modules inside the chip (such as core voltage, I / O voltage, etc.).

[0078] The pins in the reset pin area are used to receive reset signals to initialize or restart the state of the chip under test. They can be high level active or low level active, depending on the actual situation of the chip under test.

[0079] The pins in the clock pin area are used to receive the clock signal from the frequency control unit as the time reference for synchronizing all internal operations. Multiple clock pins can be included to support different clock sources or divided clock signals.

[0080] The pins in the digital ground pin area are mainly used to provide a common reference point for all digital signals to ensure consistency and stability of signal levels.

[0081] The pins in the analog ground pin area are mainly used to provide an independent ground path for the analog circuit part of the chip under test to avoid the influence of digital noise on sensitive analog signals.

[0082] The lower computer prepares to start measurement according to the control instructions of the first stage, waits for the chip to be tested to be ready, starts to collect high-frequency logic levels of all pins of the chip to be tested, and encapsulates the data stream for real-time transmission to the upper computer. The upper computer starts to display the real-time waveform of the data stream and analyze the data interface protocol, and finally displays the results (taking the jtag waveform as an example, as follows Figure 4 ), and finally log the test results.

[0083] Furthermore, after all the detection processes are completed, the host computer will automatically generate a test report based on the test results and the customized test report format.

[0084] In the embodiment of the present application, the lower computer does not communicate with the chip to be tested through the interface protocol, and all analysis is performed by the upper computer. The upper computer can customize any interface protocol by hand-drawing waveforms, avoiding the need for the acquisition board to synchronously design different detection codes for different chips to be tested, greatly improving the versatility and compatibility.

[0085] The embodiments of the present application can greatly reduce the human and material investment in the design function verification stage. All operations in the system are controlled by descriptive configuration files and host computer interfaces, avoiding repeated programming of multiple interfaces and subjective human loopholes. Compared with other products or designs on the market, the system provides more distinct versatility and portability, and because of the convenient operability defined by the host computer protocol, it can also perform testing of various complex custom timing interfaces, greatly reducing various costs in the process and providing reliable guarantees for subsequent processes.

[0086] Based on the above embodiments, an embodiment of the present application provides a chip detection method, which is applied to a chip detection system. The system includes: a host computer and a slave computer, the host computer and the slave computer establish a communication connection, and the slave computer is connected to the chip to be tested through its built-in interface unit.

[0087] like Figure 5 As shown, the chip detection method provided in the embodiment of the present application includes S101-S104.

[0088] S101, using a host computer to receive a configuration file input by a user, generating a data packet based on the configuration file, and sending the data packet to a lower computer, wherein the configuration file is written in a description language.

[0089] S102: Using the lower computer to send the data packet to the chip under test, so as to control the software running in the chip under test.

[0090] S103, during the software running of the chip under test, collecting the level status of the pins in the chip under test, converting the level status into detection data for packaging, and transmitting the packaged detection data to the host computer.

[0091] S104: using the upper computer to receive the packaged test data sent by the lower computer, and analyze it to generate a test report.

[0092] The chip detection method provided in the embodiment of the present application is executed by the chip detection system in the above embodiment, and has the same beneficial effects as the above chip detection system.

[0093] Further, such as Figure 6 As shown, the host computer includes two specific processes. The first part is the instruction control stage. In this stage, the host computer parses the configuration file, reads the configuration instructions in the configuration file, generates corresponding data packets according to the data protocol stack, and then transmits them to the lower computer through the USB interface, and then transmits them to the chip to be tested through the lower computer to control the internal software operation of the chip to be tested. The second part is the test process stage. In this stage, the lower computer prepares to start measurement according to the control instructions of the first stage, waits for the preparation of the chip to be tested, starts to collect high-frequency logic levels of all pins of the chip to be tested, and encapsulates the data stream for real-time transmission to the host computer. The host computer starts to display the real-time waveform of this data stream and analyze the data interface protocol, and finally logs the test results. At the same time, the host computer provides fixed test monitoring instructions such as temperature and power consumption, and can provide functions such as cold and hot start and other partial type experiments and various indicators monitoring. After all processes are completed, the test report will be automatically generated according to the test results and the custom test report format.

[0094] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip detection system, characterized in that: The system comprises: an upper computer and a lower computer, wherein the upper computer and the lower computer establish a communication connection, and the lower computer is connected to the chip to be tested through its built-in interface unit; The upper computer is used to receive a configuration file input by a user, generate a data packet based on the configuration file, and send the data packet to the lower computer, wherein the configuration file is written in a description language; analyze the packaged detection data sent by the lower computer and generate a test report; The lower computer is used to send the data packet to the chip to be tested to control the software running in the chip to be tested; during the software running process of the chip to be tested, the level status of the pins in the chip to be tested is collected, and the level status is converted into the detection data for packaging, and the packaged detection data is transmitted to the upper computer.

2. The chip detection system according to claim 1, characterized in that: The interface unit includes an input / output pin area, which includes multiple input / output pins. The input / output pins can realize one or more of the following functions through software configuration: general input / output, serial communication interface, two-wire serial bus, and serial peripheral interface.

3. The chip detection system according to claim 2, characterized in that: The interface unit further comprises: a power pin area, a reset pin area, a clock pin area, a digital ground pin area and an analog pin ground area; The power pin area includes a plurality of power signal pins; The reset pin area includes a plurality of reset signal pins; The clock pin area includes a plurality of clock signal pins; The digital ground pin area includes a plurality of pins of digital signal ground lines; The analog ground pin area includes a plurality of pins of analog signal ground lines.

4. The chip detection system according to any one of claims 1 to 3, characterized in that: The lower computer also includes: a field programmable logic gate array FPGA unit, a power supply unit, a frequency control unit and an analog control unit; The FPGA unit is used to receive the data packet, parse the data packet, obtain the operation instruction in the data packet, and forward the data packet to the chip to be tested when the operation instruction in the data packet is a forwarding instruction; when the instruction in the data packet is a packaging instruction, convert the collected level state into detection data for packaging, and transmit the packaged detection data to the host computer; A power supply unit, used to supply power to the lower computer and provide a power signal matching the model of the chip to be tested to the chip to be tested; A frequency control unit, used for providing a clock signal for the chip under test; The analog unit is used to provide an analog level for the chip under test and collect the level status of the analog module output in the chip under test.

5. The chip detection system according to claim 4, characterized in that: The lower computer also includes: a temperature unit and a power consumption monitoring unit; A temperature unit is used to monitor the temperature of the lower computer and the temperature of different positions of the chip to be tested; and to control the temperature of the environment to be tested to be a set temperature; The power consumption monitoring unit is used to obtain the dynamic power consumption parameters and static power consumption parameters of the chip under test during the test process.

6. The chip detection system according to claim 1, characterized in that: The format of the configuration file includes at least one of the following operation instructions: delay instruction, read operation instruction, write operation instruction, register address, judgment instruction and judgment condition; the configuration file includes: the dependency relationship between each of the operation instructions, and the control object of each of the operation instructions.

7. The chip detection system according to claim 6, characterized in that: The host computer, the slave computer and the chip to be tested are all equipped with a data protocol stack, wherein the structure of the data protocol stack includes: a frame header, a data packet length, an instruction type, load data and a CRC check; The pillow is used to store a character indicating the beginning of the data packet; The data packet length is used to store characters indicating the length of the data packet; The instruction type is used to store operation instructions; The load data is used to store the control object corresponding to the operation instruction; The CRC check is used to store the check code.

8. The chip detection system according to claim 7, characterized in that: The upper computer and the lower computer establish a communication connection via a universal serial bus USB.

9. A chip detection method, characterized in that: The method is applied to a chip detection system, the system comprising: a host computer and a slave computer, the host computer and the slave computer establish a communication connection, and the slave computer is connected to the chip to be tested through its built-in interface unit; the method comprises: The upper computer receives a configuration file input by a user, generates a data packet based on the configuration file, and sends the data packet to the lower computer, wherein the configuration file is written in a description language; Using the lower computer to send the data packet to the chip under test to control the software running in the chip under test; During the software running of the chip to be tested, the level state of the pins in the chip to be tested is collected, and the level state is converted into detection data for packaging, and the packaged detection data is transmitted to the host computer; The upper computer receives the packaged test data sent by the lower computer, analyzes the data, and generates a test report.

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