IO model generation system and method in HIL test

Abstract

The invention discloses an IO model generation system and method in HIL testing, and relates to the field of HIL testing, and the system comprises an IO signal list generation tool which is used for generating an IO signal list; the signal verification module is used for configuring E2E verification information in the signal group; the first interface setting module is used for setting a fault injection interface; the IO model generation tool is used for generating an IO model; the IO model comprises an E2E verification model, wherein the E2E verification model comprises a first fault injection interface and a second fault injection interface; completing fault injection of the counter signal processing model through the first fault injection interface; completing fault injection of the verification calculation model through a second fault injection interface; and respectively calculating a counter signal calculation value and a verification signal calculation value corresponding to the next frame of message according to the current value of the back-mining counter signal to complete signal verification. According to the invention, automatic generation of IO models under different systems is realized, and E2E verification and fault injection thereof are realized.

Description

Technical Field

[0001] The present invention relates to the field of HIL testing, and in particular to an IO model generation system, method and IO model structure in HIL testing. Background Art

[0002] In order to test automotive electronic controllers under different working conditions, HIL (Hardware in the Loop) testing has gradually become a common testing method. The existing HIL test system supports loading load models and has realized the simulation of the real control object of the load controller. In order to realize the interaction between the load model signal and the controller's IO signal, it is necessary to call different model interfaces according to the current test software system, manually build the signal IO model, and perform signal mapping between the model interface and the corresponding board signal interface in the HIL test software.

[0003] There are many deficiencies when building models manually. For example, when the controller communication matrix changes, the model needs to be modified manually; signal mapping needs to be implemented manually, which is time-consuming, labor-intensive and error-prone; when the IO model needs to communicate with the load model, manually adding signal interfaces will result in poor model readability; for the relationship between the bus signals of different ECUs and the load model signals, the signal calculation module needs to be manually added or modified, which is error-prone and difficult to modify. In addition, in the current HIL system, scripts need to be manually written to implement the bus signal Counter and CheckSum calculations. When the communication matrix changes, the code needs to be modified and debugged, and real-time fault injection and fault recovery of counters and fault values ​​cannot be achieved. Summary of the invention

[0004] The present invention provides an IO model generation system and method in HIL testing, which are used to overcome at least one technical problem existing in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides an IO model generation system in a HIL test, comprising:

[0006] Input module, used to input tool configuration files;

[0007] An IO signal list generation tool, used to generate an IO signal list; the IO signal list includes a plurality of signal groups, and the signal groups include counter signals and check signals;

[0008] A signal verification module, used to configure E2E verification information in the signal group to obtain a configured signal group;

[0009] A first interface setting module, configured to set a fault injection interface based on the configuration signal group;

[0010] An IO model generation tool, used for parsing the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface;

[0011] Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model;

[0012] By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

[0013] Optionally, the tool configuration file includes a node name of the controller under test, a counter signal matching field and a check signal matching field; wherein,

[0014] The node name of the controller under test is used to match the node under test in the dbc file and the ldf file;

[0015] The counter signal matching field is used to identify the counter signal defined in the dbc file and the ldf file;

[0016] The check signal matching field is used to identify the check signals defined in the dbc file and the ldf file.

[0017] Optionally, the IO signal list generation tool includes a configuration module, a parsing module and a generation button;

[0018] The configuration module is used to configure the dbc file path, the ldf file path and the hard-wire signal list path; the configuration module is also used to configure the target HIL system and the loading tool configuration file;

[0019] The parsing module is used to parse the ldf file, dbc file and hard-line signal list;

[0020] The Generate button is used to generate a mapping file; the Generate button is also used to generate an IO signal list according to the type of the target HIL system.

[0021] Optionally, the target HIL system includes a first system and a second system;

[0022] When the target HIL system is the first system, the counter signal processing model and the verification calculation model are lower computer callback functions, including a msg.h header file and a callback function .c script, and the callback function .c script is used to complete the calculation of the counter signal acquisition, the counter signal calculation value and the verification signal calculation value;

[0023] When the target HIL system is the second system, the counter signal processing model and the verification calculation model are module structures, and the E2E verification model at least includes a sampling module, a counter signal processing module, and a verification calculation module; the sampling module is used to retrieve the current value of the counter signal and send it to the counter signal processing module; the counter signal processing module is used to calculate the corresponding counter signal calculation value in the next frame message; the verification calculation module is used to calculate the verification signal calculation value.

[0024] Optionally, the module structure further includes a bus module, a check signal group module, a counter signal group module, a counter signal interface and at least one general signal group module;

[0025] The verification signal group module is used to send the start bit of the verification signal in the message data field and the length of the signal itself to the bus module;

[0026] The counter signal interface is used to receive the counter signal calculation value;

[0027] The counter signal group module is used to receive the counter signal calculation value, and combine the counter signal calculation value with the signal length and signal start bit in the counter signal group module and send the result to the bus module;

[0028] The general signal group module is used to combine the value of the general signal in the signal group with the signal length and signal start bit in the general signal group module and send the result to the bus module;

[0029] The bus module is used to package the values, start bits and signal lengths of all received signals and send them to the verification calculation module.

[0030] Optionally, it also includes a second interface setting module;

[0031] The second interface setting module is used to set the module custom interface so that the IO model includes the module custom interface;

[0032] The module custom interface is used to call the custom model.

[0033] On the other hand, the present invention also provides a method for generating an IO model in a HIL test, comprising:

[0034] Input tool configuration file;

[0035] Generate an IO signal list, the IO signal list includes a plurality of signal groups, the signal groups include a counter signal and a check signal;

[0036] Configuring E2E verification information in the signal group to obtain a configured signal group;

[0037] Based on the configuration signal group, setting a fault injection interface;

[0038] Parsing the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface;

[0039] Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model;

[0040] By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

[0041] Optionally, generate an IO signal list, specifically:

[0042] Configure the dbc file path, ldf file path and hard-wired signal list path;

[0043] Configure the target HIL system;

[0044] Load tool configuration file;

[0045] Parse the ldf file, dbc file and hard-wired signal list respectively to generate mapping files;

[0046] According to the type of the target HIL system, an IO signal list is generated.

[0047] Optionally, by retrieving the current value of the counter signal, the corresponding counter signal calculation value and the check signal calculation value in the next frame message are calculated respectively, specifically:

[0048] Send the start bit of the check signal in the message data field and the length of the signal itself to the bus module;

[0049] Retrieve the current value of the counter signal and send it to the counter signal processing module;

[0050] Calculate the corresponding counter signal calculation value in the next frame message according to the current value of the counter signal, and send the counter signal calculation value to the counter signal interface and the counter signal group module respectively;

[0051] The counter signal calculation value is combined with the signal length and signal start bit in the counter signal group module and then sent to the bus module;

[0052] The value of the general signal in the signal group is combined with the signal length and the signal start bit in the general signal group module and then sent to the bus module;

[0053] Packing the values, start bits and signal lengths of all received signals through the bus module and sending them to the verification calculation module;

[0054] Calculating a verification signal calculation value using the verification calculation module;

[0055] Signal verification is performed by using the counter signal calculation value at the counter signal interface and the verification signal calculation value.

[0056] Optionally, it further includes: setting a module custom interface so that the IO model includes the module custom interface;

[0057] The module custom interface is used to call the custom model.

[0058] The innovative features of the embodiments of the present invention include:

[0059] 1. In this embodiment, the automatic generation of IO models and related configuration files under different systems is realized, and by adding E2E verification information to the IO signal list, the generated IO model includes the E2E verification model. The counter signal and the verification signal are calculated using the E2E verification model to complete the verification of the IO model, which is one of the innovations of the embodiment of the present invention.

[0060] 2. In this embodiment, a fault injection interface is set through the first interface setting module, so that when an E2E verification model is generated, a first fault injection interface is generated in the counter signal processing model, and a second fault injection interface is generated in the verification calculation model. In this way, the information of the counter signal processing model can be modified through the first fault injection interface to complete the fault injection of the counter signal processing model; the information of the verification calculation model can be modified through the second fault injection interface to complete the fault injection of the verification calculation model, thereby realizing fault injection, which is one of the innovations of the embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 A schematic diagram of the structure of an IO model generation system provided by an embodiment of the present invention;

[0063] Figure 2 A schematic diagram of the structure of an IO model provided in an embodiment of the present invention;

[0064] Figure 3 A schematic diagram of the structure of an IO signal list generation tool provided in an embodiment of the present invention;

[0065] Figure 4 A structural diagram of a function call interface under the first system;

[0066] Figure 5 It is a structural schematic diagram of an E2E verification model under the second system;

[0067] Figure 6 A schematic diagram of the structure of a counter signal processing module provided in an embodiment of the present invention;

[0068] Figure 7 A schematic diagram of the structure of a verification calculation module provided in an embodiment of the present invention;

[0069] Figure 8 Another structural schematic diagram of the IO model generation system provided by an embodiment of the present invention;

[0070] Fig. 9 A schematic diagram of building a user-defined module provided in an embodiment of the present invention;

[0071] Fig.10 A schematic diagram of a user reference module call provided by an embodiment of the present invention;

[0072] Fig.11 A flow chart of an IO model generation method provided by an embodiment of the present invention;

[0073] Fig.12 A flow chart for generating an IO signal list provided by an embodiment of the present invention;

[0074] Fig.13 Another flow chart of the IO model generation method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0076] It should be noted that the terms "including" and "having" and any variations thereof in the embodiments of the present invention and the accompanying drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0077] The embodiment of the present invention discloses an IO model generation system, method and IO model structure in HIL test, which are described in detail below.

[0078] Figure 1 A schematic diagram of the structure of an IO model generation system provided by an embodiment of the present invention, Figure 2 For a structural diagram of an IO model provided in an embodiment of the present invention, please refer to Figure 1 and Figure 2 , an IO model generation system in HIL test provided by an embodiment of the present invention includes:

[0079] Input module, used to input tool configuration files;

[0080] IO signal list generation tool, used to generate IO signal list; IO signal list includes multiple signal groups, signal groups include counter signals and check signals;

[0081] A signal verification module, used to configure E2E verification information in a signal group to obtain a configured signal group;

[0082] A first interface setting module, used to set a fault injection interface based on a configuration signal group;

[0083] An IO model generation tool is used to parse the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface;

[0084] Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model;

[0085] By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

[0086] Specifically, please refer to Figure 1 An IO model generation system in HIL test provided by an embodiment of the present invention includes an input module, a tool configuration file is input through the input module, and a node name of a controller under test, a counter signal matching field, and a check signal matching field are configured through the tool configuration file. The node name of the controller under test is used to match the node under test in the dbc file and the ldf file, the counter signal matching field is used to identify the counter signal defined in the dbc file and the ldf file, and the check signal matching field is used to identify the check signal defined in the dbc file and the ldf file.

[0087] It should be noted that the counter signal matching field and the check signal matching field support regular expressions. In addition, DBC (Data base Container) files and LDF (Log Data File) files are two different file formats used in CAN bus communication. DBC files are database files that contain all communication information, including CAN ID, signal name, signal length, signal period and other information. LDF files are log files that are used to record all CAN bus communication data, including CAN frames, signals and other information, for subsequent analysis and debugging.

[0088] Please refer to Figure 1 The IO model generation system in the HIL test provided by the present invention also includes an IO signal list generation tool, which is an exe file compiled and generated by python, and a UI interface is built based on the graphical user interface toolkit wxpython of the Python programming language.

[0089] Figure 3 A schematic diagram of the structure of the IO signal list generation tool provided in the embodiment of the present invention, please refer to Figure 3, the IO signal list generation tool includes a configuration module, a parsing module and a generate button. In actual use, the dbc file path, ldf file path, hard-wired signal list path, target HIL system and tool configuration file are configured through the configuration module. Then the parsing module is used to parse the ldf file and dbc file based on python's ldfParser and canTool tools, and to parse the hard-wired signal list based on pandas. Click the generate button to generate a mapping file and an IO signal list based on openpyxl. The mapping file can be directly added to the corresponding HIL test software, and the IO signal list contains the basic information of all IO signals of the current controller.

[0090] It should be noted that the generated IO signal list is an Excel file, which is used to describe the information related to CAN / LIN bus signals and hard-wire signals. Figure 2 In order to verify the IO model, the IO model generated by the present invention includes an E2E (end to end) verification module, and the calculation of the counter signal and the verification signal and the fault injection are realized through the E2E verification module, so as to verify the IO model.

[0091] In order to make the generated IO model include the E2E verification module, the present invention adds content to the IO signal list through the signal verification module. When adding content, first divide it into multiple signal groups according to information attributes, such as counter signals and verification signals. Then, for each signal group, add E2E verification information to obtain a configuration signal group.

[0092] In the signal list, there are two pages, ECU and para. The ECU page includes Channel, Msg, MsgID, SignalGroup, DataID, Signal, If_Live Counter, If_Check, TxorRx, Startbit, SigLen, Initialvalue, Minimum, Maximum, Factor, Offset, SendType, checkType, Function and other columns.

[0093] Among them, Channel, Msg, MsgID, SignalGroup, Signal, Startbit, SigLen, Initialvalue, Minimum, Maximum, Factor, Offset, and SendType are the channel name, message name, message ID, signal group name, signal name, signal start bit, signal length, initial value, maximum value, minimum value, precision, offset, and signal serialization type, respectively, which are obtained by parsing dbc. TxorRx is used to show that the signal is an ECU send signal or an ECU receive signal. If_Live counter and If_check are used to show whether the current signal is a counter signal and a check signal, which is identified here by the matching field between the counter signal and the check signal. DataID is the CRC prefix calculation value in the E2E check, which needs to be filled in manually and is 0 by default.

[0094] After adding the E2E verification information, it is necessary to complete the end-to-end information transmission through the interface to verify the signal. Therefore, the present invention also sets a fault injection interface through the first interface setting module, so that fault injection can be implemented through the fault injection interface, that is, the fault value of the counter signal or the verification signal is modified through the fault injection interface.

[0095] After setting up the fault injection interface, the IO model can be generated. In this embodiment, the IO model generation tool is used to parse the IO signal list and the configuration signal group, and the IO model is generated according to the information in the table. Here, the IO model generation tool can be, for example, a built-in function of Matlab. Since the E2E verification information is added to the table, the generated IO model includes not only the HIL model but also the E2E verification model.

[0096] When verifying information, it is necessary to calculate the counter signal and the check signal separately. Therefore, the signal group in the present invention includes at least the counter signal and the check signal. Thus, the E2E check model generated after adding the E2E check information to the signal group includes a counter (counter) signal processing model and a check (CheckSum) calculation model. The counter signal processing model can realize the calculation of the counter signal, and the check calculation model can realize the calculation of the check signal.

[0097] Since faults need to be injected into the counter signal or the check signal separately, the fault injection interface should be set up for the counter signal processing model and the check calculation model respectively. Figure 2 In this embodiment, a first fault injection interface is set on the counter signal processing model, and a second fault injection interface is set on the verification calculation model.

[0098] After the fault injection interfaces are set up for the two models respectively, the information of the counter signal processing model can be modified through the first fault injection interface to complete the fault injection of the counter signal processing model; the information of the verification calculation model can be modified through the second fault injection interface to complete the fault injection of the verification calculation model.

[0099] It should be noted that in the present invention, the target HIL system includes a first system and a second system. When configured as different target HIL systems, the generated E2E models are not completely the same. The first system may be, for example, a CC system, and the second system may be, for example, a NI system. The NI system refers to the system provided by Natianol Instrument, and the CC system refers to the system provided by concurrent.

[0100] For example, when the target HIL system is the first system, the counter signal processing model and the verification calculation model are lower-level computer callback functions, including the msg.h header file and the callback function .c script. Among them, the msg.h file stores the ECU's channel name, message ID, message dlc, signal group name, signal name, verification algorithm flag and other information in the format of a structure. In the .c script, according to the currently configured system, the counter signal is retrieved to obtain the current value of the counter signal, and then the current value is used to calculate the corresponding counter signal calculation value and verification signal calculation value in the next frame message. The data can be verified through the counter signal calculation value and the verification signal calculation value.

[0101] Figure 4 This is a structural diagram of the function call interface under the first system, refer to Figure 4 The value of the signal interface can be referenced in the callback function. The maximum value, minimum value and step length of the counter are used to create errors in the maximum value, minimum value and step length of the counter; the counter fault switch and fault value are used to implement the fixed value fault of the counter; the check fault switch and fault value are used to implement the fixed value fault of the check.

[0102] When the target HIL system is the second system, the counter signal processing model and verification calculation model in the E2E model are module structures. Please refer to Figure 5 , Figure 5 This is a structural diagram of an E2E verification model under the second system. At this time, the E2E verification model includes a collection module, a counter signal processing module, a verification calculation module, a bus module, a verification signal group module, a counter signal group module, a counter signal interface and at least one general signal group module.

[0103] When the E2E verification model calculates the counter signal and the verification signal, a verification signal group module is created for the verification signal. This module passes the start bit of the verification signal in the message data field and the length of the signal itself to the bus module, such as Figure 5 The dotted box in the figure represents the bus module. For the counter signal, the sampling module will sample the current value of the current counter signal and send it to the counter signal processing module, which will calculate and process the received counter signal to obtain the corresponding counter signal calculation value in the next frame message.

[0104] After obtaining the corresponding counter signal calculation value in the next frame message, it is sent to the counter signal interface and the counter signal group module respectively. The counter signal group module combines the counter signal calculation value with the signal length and signal start bit in the counter signal group module and sends it to the bus module.

[0105] In addition to counter signals and check signals, a signal group also contains one or more general signals. Figure 5 , the values ​​of these signals are combined with the signal length and start bit in the corresponding general signal module through the signal reference tag and passed to the bus module. The bus module packages the values, start bits and signal lengths of all received signals and sends them to the verification calculation module, which calculates the verification signal value. After obtaining the verification signal value, the data can be verified by processing and comparing the verification signal value with the counter signal calculation value received by the counter signal interface.

[0106] Figure 6 For a structural diagram of a counter signal processing module provided in an embodiment of the present invention, please refer to Figure 6 The maximum and minimum values ​​in this module are obtained through the parameter page in the IO signal list. The counter range is different under different specifications. Normally, the step length defaults to 1. When you want to create a step length fault, you can modify the value of the step length interface. The default value of the error value is -1. When the error value is greater than or equal to 0, the counter signal will be set to the error value, that is, the injected fault value, and remain unchanged.

[0107] CRC8, CRC16, and byte XOR algorithms are often used for E2E verification. Figure 7 For a schematic diagram of a structure of a verification calculation module provided in an embodiment of the present invention, please refer to Figure 7 Interface 1 will pass in the packaged signal value, signal length and signal initial value. The signal serialization type is configured in the IO signal list, including Intel and motorala signal types. The function module restores the signal group data field in the script based on these two inputs.

[0108] The IO model generation system provided by the present invention can configure the algorithm type supported by the ECU in the IO signal table. When the algorithm used is byte XOR, DataId, initial XOR value, end XOR value, and CRC table are all 0 and will not be used in the verification calculation module; when configured as CRC verification, DataId, initial XOR value, and end XOR value will be written according to the configuration in the IO signal list, and the value in the CRC table will be calculated according to the polynomial coefficients configured in the IO signal list.

[0109] Then, according to the data field and algorithm-related information, the corresponding check signal value can be calculated. The error value interface of the check calculation module defaults to -1. When the error value is greater than or equal to 0, the check signal will be set to the error value, that is, the injected fault value, and remain unchanged.

[0110] Optionally, Figure 8 Another structural diagram of the IO model generation system provided by the embodiment of the present invention is shown in FIG. Figure 8 An IO model generation system in a HIL test provided by an embodiment of the present invention also includes a second interface setting module; the second interface setting module is used to set a module custom interface so that the IO model includes a module custom interface; the module custom interface is used to call a custom model.

[0111] Specifically, please refer to Figure 8 In order to meet the different functional requirements of users, the IO model generation system provided by the present invention also includes a second interface setting module. When generating the IO model, the module custom interface is set using the second interface setting module. In this way, the generated IO model includes the module custom interface. When the user needs to configure some other functions, he can build a model of the corresponding function and then call the custom model through the module custom interface to meet different user needs.

[0112] This embodiment builds a user-defined model in the Function.mdl model. After the model is built, it is also necessary to set a user reference variable for the user-defined model. The writing method of the user reference variable can be, for example, FUN_variable name. Fig. 9 A schematic diagram of building a user-defined module provided in an embodiment of the present invention, wherein OffSet, Factor and tag are user-defined reference variables.

[0113] The present invention adds a user reference description in the Function cell of the corresponding signal in the IO signal list, and each signal can call one or more user-defined modules, and can assign values ​​to user-defined variables in the cell, for example: UserBlock_1: Factor = 100, OffSet = 5, tag = aimSignal. Among them, UserBlock_1 represents the user-defined module name 1, and OffSet, Factor and tag represent user reference variables respectively.

[0114] Fig.10 This is a schematic diagram of a user reference module call provided by an embodiment of the present invention. From this diagram, it can be seen that the three user reference variables OffSet, Factor and tag in the user-defined module are set to the values ​​in the cell.

[0115] Based on the same inventive concept, the present invention also provides a method for generating an IO model in a HIL test. Fig.11 A flow chart of an IO model generation method provided in an embodiment of the present invention. The IO model generation method in a HIL test provided in an embodiment of the present invention includes:

[0116] Step 1: Enter the tool configuration file;

[0117] Step 2: Generate an IO signal list, the IO signal list includes multiple signal groups, and the signal group includes a counter signal and a check signal;

[0118] Step 3: Configure E2E verification information in the signal group to obtain a configured signal group;

[0119] Step 4: Set the fault injection interface based on the configured signal group;

[0120] Step 5: Parse the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface;

[0121] Step 6: Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model;

[0122] Step 7: By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

[0123] Specifically, please refer to Fig.11In an embodiment of the present invention, a method for generating an IO model in a HIL test is provided. In step 1, a tool configuration file is input, and the node name of the controller under test, the counter signal matching field, and the check signal matching field are configured through the tool configuration file. The node name of the controller under test is used to match the node under test in the dbc file and the ldf file, the counter signal matching field is used to identify the counter signal defined in the dbc file and the ldf file, and the check signal matching field is used to identify the check signal defined in the dbc file and the ldf file.

[0124] It should be noted that the counter signal match field and the check signal match field support regular expressions. In addition, DBC files and LDF files are two different file formats used in CAN bus communication. DBC files are database files that contain all communication information, including CAN ID, signal name, signal length, signal period, and other information. LDF files are log files that are used to record all CAN bus communication data, including CAN frames, signals, and other information, for subsequent analysis and debugging.

[0125] In step 2, the IO signal list generation tool is used to configure the system. The tool is an exe file compiled by Python, and the UI interface is built based on the graphical user interface toolkit wxpython of the Python programming language.

[0126] The IO signal list generation tool includes a configuration module, a parsing module, and a generate button. In actual use, the dbc file path, ldf file path, hard-wired signal list path, target HIL system, and tool configuration file are configured through the configuration module. Then the parsing module uses the ldfParser and canTool tools of python to parse the ldf file and dbc file, and uses pandas to parse the hard-wired signal list. Click the generate button to generate a mapping file and an IO signal list based on openpyxl. The mapping file can be directly added to the corresponding HIL test software, and the IO signal list contains the basic information of all IO signals of the current controller.

[0127] It should be noted that the generated IO signal list is an Excel file, which is used to describe the information related to CAN / LIN bus signals and hard-wire signals. Figure 2 In order to verify the IO model, the IO model generated by the present invention includes an E2E (end to end) verification module, and the calculation of the counter signal and the verification signal and the fault injection are realized through the E2E verification module, so as to verify the IO model.

[0128] In order to make the generated IO model include the E2E verification module, the present invention adds content to the IO signal list through step 3. When adding content, first divide it into multiple signal groups according to information attributes, such as counter signals and verification signals. Then, for each signal group, add E2E verification information to obtain a configuration signal group.

[0129] After adding the E2E verification information, it is necessary to complete the end-to-end information transmission through the interface to verify the signal. Therefore, the present invention also sets a fault injection interface through step 4, so that fault injection can be implemented through the fault injection interface, that is, the fault value of the counter signal or the verification signal is modified through the fault injection interface.

[0130] After setting up the fault injection interface, the IO model can be generated through step 5. In this embodiment, the IO signal list and the configuration signal group are parsed using an IO model generation tool, and the IO model is generated according to the information in the table. Here, the IO model generation tool can be, for example, a built-in function of MATLAB. Since the E2E verification information is added to the table, the generated IO model includes not only the HIL model but also the E2E verification model.

[0131] When verifying information, it is necessary to calculate the counter signal and the check signal separately. Therefore, the signal group in the present invention includes at least the counter signal and the check signal. In this way, the E2E check model generated after adding the E2E check information to the signal group includes a counter (counter) signal processing model and a check (CheckSum) calculation model. The counter signal processing model can realize the calculation of the counter signal, and the check calculation model can realize the calculation of the check signal. By processing and comparing the counter signal and the check signal, information verification can be realized.

[0132] Since faults need to be injected into the counter signal or the check signal separately, the fault injection interface should be set for the counter signal processing model and the check calculation model respectively. Figure 2 In this embodiment, a first fault injection interface is set on the counter signal processing model, and a second fault injection interface is set on the verification calculation model.

[0133] After the fault injection interfaces of the two models are set up respectively, in step 6, the information of the counter signal processing model can be modified through the first fault injection interface to complete the fault injection of the counter signal processing model; the information of the verification calculation model can be modified through the second fault injection interface to complete the fault injection of the verification calculation model.

[0134] It should be noted that, in the present invention, the target HIL system includes a first system and a second system. When configured as different target HIL systems, the generated E2E models are not completely the same.

[0135] For example, when the target HIL system is the first system, the counter signal processing model and the verification calculation model are lower-level computer callback functions, including the msg.h header file and the callback function .c script. Among them, the msg.h file stores the ECU's channel name, message ID, message dlc, signal group name, signal name, verification algorithm flag and other information in the format of a structure. In the .c script, according to the currently configured system, the counter signal is retrieved to obtain the current value of the counter signal, and then the current value is used to calculate the corresponding counter signal calculation value and verification signal calculation value in the next frame message. The data can be verified through the counter signal calculation value and the verification signal calculation value.

[0136] When the target HIL system is the second system, the counter signal processing model and the verification calculation model in the E2E model are module structures. At this time, the E2E verification model includes a sampling module, a counter signal processing module, a verification calculation module, a bus module, a verification signal group module, a counter signal group module, a counter signal interface and at least one general signal group module.

[0137] When the E2E verification model calculates the counter signal and the verification signal, a verification signal group module will be created for the verification signal, which will pass the start bit of the verification signal in the message data field and the length of the signal itself to the bus module. For the counter signal, the sampling module will sample the current value of the current counter signal and send it to the counter signal processing module, which will calculate and process the received counter signal to obtain the corresponding counter signal calculation value in the next frame message.

[0138] After obtaining the corresponding counter signal calculation value in the next frame message, it is sent to the counter signal interface and the counter signal group module respectively. The counter signal group module combines the counter signal calculation value with the signal length and signal start bit in the counter signal group module and sends it to the bus module.

[0139] In addition to counter signals and check signals, a signal group also contains one or more general signals. Figure 5, the values ​​of these signals are combined with the signal length and start bit in the corresponding general signal module through the signal reference tag and passed to the bus module. The bus module packages the values, start bits and signal lengths of all received signals and sends them to the verification calculation module, which calculates the verification signal value. After obtaining the verification signal value, the data can be verified by processing and comparing the verification signal value with the counter signal calculation value received by the counter signal interface.

[0140] Optionally, Fig.12 For a flow chart of generating an IO signal list provided by an embodiment of the present invention, please refer to Fig.12 , generate an IO signal list, specifically: Step 21: configure the dbc file path, ldf file path and hard-wire signal list path; Step 22: configure the target HIL system; Step 23: load the tool configuration file; Step 24: parse the ldf file, dbc file and hard-wire signal list respectively to generate a mapping file; Step 25: generate an IO signal list according to the type of the target HIL system.

[0141] Specifically, please refer to Fig.12 In this embodiment, an IO signal list generation tool is used to generate an IO signal list. The IO signal list generation tool includes a configuration module, a parsing module, and a generation button. In actual use, first in step 21, the dbc file path, the ldf file path, and the hard-wired signal list path are configured through the configuration module. Then in step 22, the target HIL system, such as the first system or the second system, is configured. After the configuration is completed, in step 23, the tool configuration file is loaded.

[0142] In step 24, the parsing module is used to parse the ldf file and dbc file based on the ldfParser and canTool tools of python, and the hard-wired signal list is parsed based on pandas. After the parsing is completed, click the Generate button to generate a mapping file based on openpyxl, which can be directly added to the corresponding HIL test software. After obtaining the target HIL system, in step 25, an IO signal list can be generated according to the type of the target HIL system. The IO signal list contains the basic information of all IO signals of the current controller.

[0143] Optionally, Fig.13 For another flow chart of the IO model generation method provided by the embodiment of the present invention, please refer to Fig.13 The IO model generation method provided in this embodiment also includes: Step 04, setting a module custom interface so that the IO model includes the module custom interface; the module custom interface is used to call the custom model.

[0144] Specifically, please refer to Fig.13 In order to meet the different functional requirements of users, the IO model generation method provided by the present invention also sets the module custom interface through step 04, so that the module custom interface can be automatically generated when the IO model is generated. When the user needs to configure some other functions, he can build a model of the corresponding function and then call the custom model through the module custom interface to meet different user needs.

[0145] Those skilled in the art can understand that the accompanying drawings are only schematic diagrams of an embodiment, and the modules or processes in the accompanying drawings are not necessarily required to implement the present invention.

[0146] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description of the embodiment, or can be changed accordingly and located in one or more devices different from the embodiment. The modules in the above embodiment can be combined into one module, or can be further divided into multiple sub-modules.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system for generating IO models in HIL testing, characterized in that: include: Input module, used to input tool configuration files; An IO signal list generation tool, used to generate an IO signal list; the IO signal list includes a plurality of signal groups, and the signal groups include counter signals and check signals; A signal verification module, used to configure E2E verification information in the signal group to obtain a configured signal group; A first interface setting module, configured to set a fault injection interface based on the configuration signal group; An IO model generation tool, used for parsing the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface; Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; Modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model; By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

2. The IO model generation system in HIL test according to claim 1, characterized in that: The tool configuration file includes the node name of the controller under test, a counter signal matching field and a check signal matching field; wherein, The node name of the controller under test is used to match the node under test in the dbc file and the ldf file; The counter signal matching field is used to identify the counter signal defined in the dbc file and the ldf file; The check signal matching field is used to identify the check signals defined in the dbc file and the ldf file.

3. The IO model generation system in HIL test according to claim 1, characterized in that: The IO signal list generation tool includes a configuration module, a parsing module and a generation button; The configuration module is used to configure the dbc file path, the ldf file path and the hard-wire signal list path; the configuration module is also used to configure the target HIL system and the loading tool configuration file; The parsing module is used to parse the ldf file, dbc file and hard-line signal list; The Generate button is used to generate a mapping file; the Generate button is also used to generate an IO signal list according to the type of the target HIL system.

4. The IO model generation system in HIL test according to claim 3, characterized in that: The target HIL system includes a first system and a second system; When the target HIL system is the first system, the counter signal processing model and the verification calculation model are lower computer callback functions, including a msg.h header file and a callback function .c script, and the callback function .c script is used to complete the calculation of the counter signal acquisition, the counter signal calculation value and the verification signal calculation value; When the target HIL system is the second system, the counter signal processing model and the verification calculation model are module structures, and the E2E verification model at least includes a sampling module, a counter signal processing module, and a verification calculation module; the sampling module is used to sample the current value of the counter signal and send it to the counter signal processing module; the counter signal processing module is used to calculate the corresponding counter signal calculation value in the next frame message; The verification calculation module is used to calculate the verification signal calculation value.

5. The IO model generation system in HIL test according to claim 4, characterized in that: The module structure also includes a bus module, a check signal group module, a counter signal group module, a counter signal interface and at least one general signal group module; The verification signal group module is used to send the start bit of the verification signal in the message data field and the length of the signal itself to the bus module; The counter signal interface is used to receive the counter signal calculation value; The counter signal group module is used to receive the counter signal calculation value, and combine the counter signal calculation value with the signal length and signal start bit in the counter signal group module and send the result to the bus module; The general signal group module is used to combine the value of the general signal in the signal group with the signal length and signal start bit in the general signal group module and send the result to the bus module; The bus module is used to package the values, start bits and signal lengths of all received signals and send them to the verification calculation module.

6. The IO model generation system in HIL testing according to claim 1, characterized in that: Also includes a second interface setting module; The second interface setting module is used to set the module custom interface so that the IO model includes the module custom interface; The module custom interface is used to call the custom model.

7. A method for generating an IO model in a HIL test, characterized in that: include: Input tool configuration file; Generate an IO signal list, the IO signal list includes a plurality of signal groups, the signal groups include a counter signal and a check signal; Configuring E2E verification information in the signal group to obtain a configured signal group; Based on the configuration signal group, setting a fault injection interface; Parsing the IO signal list and the configuration signal group to generate an IO model; the IO model includes a HIL model and an E2E verification model, the E2E verification model includes a counter signal processing model and a verification calculation model, the counter signal processing model includes a first fault injection interface, and the verification calculation model includes a second fault injection interface; Modify the information of the counter signal processing model through the first fault injection interface to complete the fault injection of the counter signal processing model; Modify the information of the verification calculation model through the second fault injection interface to complete the fault injection of the verification calculation model; By collecting the current value of the counter signal, the corresponding counter signal calculation value and verification signal calculation value in the next frame message are calculated respectively to complete the signal verification.

8. The method for generating an IO model in a HIL test according to claim 7, characterized in that: Generate an IO signal list, specifically: Configure the dbc file path, ldf file path and hard-wired signal list path; Configure the target HIL system; Load tool configuration file; Parse the ldf file, dbc file and hard-wired signal list respectively to generate mapping files; According to the type of the target HIL system, an IO signal list is generated.

9. The method for generating an IO model in a HIL test according to claim 7, characterized in that: By collecting the current value of the counter signal, the corresponding counter signal calculation value and check signal calculation value in the next frame message are calculated respectively, specifically: Send the start bit of the check signal in the message data field and the length of the signal itself to the bus module; Retrieve the current value of the counter signal and send it to the counter signal processing module; Calculate the corresponding counter signal calculation value in the next frame message according to the current value of the counter signal, and send the counter signal calculation value to the counter signal interface and the counter signal group module respectively; The counter signal calculation value is combined with the signal length and signal start bit in the counter signal group module and then sent to the bus module; The value of the general signal in the signal group is combined with the signal length and the signal start bit in the general signal group module and then sent to the bus module; Packing the values, start bits and signal lengths of all received signals through the bus module and sending them to the verification calculation module; Calculating a verification signal calculation value using the verification calculation module; Signal verification is performed by using the counter signal calculation value at the counter signal interface and the verification signal calculation value.

10. The method for generating an IO model in a HIL test according to claim 7, characterized in that: Also includes: Setting a module custom interface so that the IO model includes the module custom interface; The module custom interface is used to call the custom model.

Images